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aa11e38c DA |
1 | /* |
2 | * Copyright (C) 2002 Motorola GSG-China | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * as published by the Free Software Foundation; either version 2 | |
7 | * of the License, or (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, | |
17 | * USA. | |
18 | * | |
19 | * Author: | |
20 | * Darius Augulis, Teltonika Inc. | |
21 | * | |
22 | * Desc.: | |
23 | * Implementation of I2C Adapter/Algorithm Driver | |
24 | * for I2C Bus integrated in Freescale i.MX/MXC processors | |
25 | * | |
26 | * Derived from Motorola GSG China I2C example driver | |
27 | * | |
28 | * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de | |
29 | * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de | |
30 | * Copyright (C) 2007 RightHand Technologies, Inc. | |
31 | * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt> | |
32 | * | |
d533f049 JL |
33 | * Copyright 2013 Freescale Semiconductor, Inc. |
34 | * | |
aa11e38c DA |
35 | */ |
36 | ||
37 | /** Includes ******************************************************************* | |
38 | *******************************************************************************/ | |
39 | ||
40 | #include <linux/init.h> | |
41 | #include <linux/kernel.h> | |
42 | #include <linux/module.h> | |
43 | #include <linux/errno.h> | |
44 | #include <linux/err.h> | |
45 | #include <linux/interrupt.h> | |
46 | #include <linux/delay.h> | |
47 | #include <linux/i2c.h> | |
48 | #include <linux/io.h> | |
49 | #include <linux/sched.h> | |
50 | #include <linux/platform_device.h> | |
51 | #include <linux/clk.h> | |
5a0e3ad6 | 52 | #include <linux/slab.h> |
dfcd04b1 SG |
53 | #include <linux/of.h> |
54 | #include <linux/of_device.h> | |
82906b13 | 55 | #include <linux/platform_data/i2c-imx.h> |
aa11e38c DA |
56 | |
57 | /** Defines ******************************************************************** | |
58 | *******************************************************************************/ | |
59 | ||
60 | /* This will be the driver name the kernel reports */ | |
61 | #define DRIVER_NAME "imx-i2c" | |
62 | ||
63 | /* Default value */ | |
64 | #define IMX_I2C_BIT_RATE 100000 /* 100kHz */ | |
65 | ||
8cc7331f JL |
66 | /* IMX I2C registers: |
67 | * the I2C register offset is different between SoCs, | |
68 | * to provid support for all these chips, split the | |
69 | * register offset into a fixed base address and a | |
70 | * variable shift value, then the full register offset | |
71 | * will be calculated by | |
72 | * reg_off = ( reg_base_addr << reg_shift) | |
73 | */ | |
aa11e38c | 74 | #define IMX_I2C_IADR 0x00 /* i2c slave address */ |
8cc7331f JL |
75 | #define IMX_I2C_IFDR 0x01 /* i2c frequency divider */ |
76 | #define IMX_I2C_I2CR 0x02 /* i2c control */ | |
77 | #define IMX_I2C_I2SR 0x03 /* i2c status */ | |
78 | #define IMX_I2C_I2DR 0x04 /* i2c transfer data */ | |
79 | ||
80 | #define IMX_I2C_REGSHIFT 2 | |
ad90efae | 81 | #define VF610_I2C_REGSHIFT 0 |
aa11e38c DA |
82 | |
83 | /* Bits of IMX I2C registers */ | |
84 | #define I2SR_RXAK 0x01 | |
85 | #define I2SR_IIF 0x02 | |
86 | #define I2SR_SRW 0x04 | |
87 | #define I2SR_IAL 0x10 | |
88 | #define I2SR_IBB 0x20 | |
89 | #define I2SR_IAAS 0x40 | |
90 | #define I2SR_ICF 0x80 | |
91 | #define I2CR_RSTA 0x04 | |
92 | #define I2CR_TXAK 0x08 | |
93 | #define I2CR_MTX 0x10 | |
94 | #define I2CR_MSTA 0x20 | |
95 | #define I2CR_IIEN 0x40 | |
96 | #define I2CR_IEN 0x80 | |
97 | ||
171408c2 JL |
98 | /* register bits different operating codes definition: |
99 | * 1) I2SR: Interrupt flags clear operation differ between SoCs: | |
100 | * - write zero to clear(w0c) INT flag on i.MX, | |
101 | * - but write one to clear(w1c) INT flag on Vybrid. | |
102 | * 2) I2CR: I2C module enable operation also differ between SoCs: | |
103 | * - set I2CR_IEN bit enable the module on i.MX, | |
104 | * - but clear I2CR_IEN bit enable the module on Vybrid. | |
105 | */ | |
106 | #define I2SR_CLR_OPCODE_W0C 0x0 | |
107 | #define I2SR_CLR_OPCODE_W1C (I2SR_IAL | I2SR_IIF) | |
108 | #define I2CR_IEN_OPCODE_0 0x0 | |
109 | #define I2CR_IEN_OPCODE_1 I2CR_IEN | |
110 | ||
aa11e38c DA |
111 | /** Variables ****************************************************************** |
112 | *******************************************************************************/ | |
113 | ||
aa11e38c DA |
114 | /* |
115 | * sorted list of clock divider, register value pairs | |
116 | * taken from table 26-5, p.26-9, Freescale i.MX | |
117 | * Integrated Portable System Processor Reference Manual | |
118 | * Document Number: MC9328MXLRM, Rev. 5.1, 06/2007 | |
119 | * | |
120 | * Duplicated divider values removed from list | |
121 | */ | |
d533f049 JL |
122 | struct imx_i2c_clk_pair { |
123 | u16 div; | |
124 | u16 val; | |
125 | }; | |
aa11e38c | 126 | |
4b775022 | 127 | static struct imx_i2c_clk_pair imx_i2c_clk_div[] = { |
aa11e38c DA |
128 | { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 }, |
129 | { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 }, | |
130 | { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 }, | |
131 | { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B }, | |
132 | { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A }, | |
133 | { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 }, | |
134 | { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 }, | |
135 | { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 }, | |
136 | { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 }, | |
137 | { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B }, | |
138 | { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E }, | |
139 | { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D }, | |
140 | { 3072, 0x1E }, { 3840, 0x1F } | |
141 | }; | |
142 | ||
ad90efae JL |
143 | /* Vybrid VF610 clock divider, register value pairs */ |
144 | static struct imx_i2c_clk_pair vf610_i2c_clk_div[] = { | |
145 | { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 }, | |
146 | { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 }, | |
147 | { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D }, | |
148 | { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 }, | |
149 | { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 }, | |
150 | { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 }, | |
151 | { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 }, | |
152 | { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 }, | |
153 | { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 }, | |
154 | { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B }, | |
155 | { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 }, | |
156 | { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 }, | |
157 | { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B }, | |
158 | { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A }, | |
159 | { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E }, | |
160 | }; | |
161 | ||
5bdfba29 SG |
162 | enum imx_i2c_type { |
163 | IMX1_I2C, | |
164 | IMX21_I2C, | |
ad90efae | 165 | VF610_I2C, |
5bdfba29 SG |
166 | }; |
167 | ||
4b775022 JL |
168 | struct imx_i2c_hwdata { |
169 | enum imx_i2c_type devtype; | |
170 | unsigned regshift; | |
171 | struct imx_i2c_clk_pair *clk_div; | |
172 | unsigned ndivs; | |
173 | unsigned i2sr_clr_opcode; | |
174 | unsigned i2cr_ien_opcode; | |
175 | }; | |
176 | ||
aa11e38c DA |
177 | struct imx_i2c_struct { |
178 | struct i2c_adapter adapter; | |
aa11e38c DA |
179 | struct clk *clk; |
180 | void __iomem *base; | |
aa11e38c DA |
181 | wait_queue_head_t queue; |
182 | unsigned long i2csr; | |
65de394d | 183 | unsigned int disable_delay; |
43309f3b | 184 | int stopped; |
db3a3d4e | 185 | unsigned int ifdr; /* IMX_I2C_IFDR */ |
9b2a6da3 FD |
186 | unsigned int cur_clk; |
187 | unsigned int bitrate; | |
4b775022 JL |
188 | const struct imx_i2c_hwdata *hwdata; |
189 | }; | |
190 | ||
191 | static const struct imx_i2c_hwdata imx1_i2c_hwdata = { | |
192 | .devtype = IMX1_I2C, | |
193 | .regshift = IMX_I2C_REGSHIFT, | |
194 | .clk_div = imx_i2c_clk_div, | |
195 | .ndivs = ARRAY_SIZE(imx_i2c_clk_div), | |
196 | .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C, | |
197 | .i2cr_ien_opcode = I2CR_IEN_OPCODE_1, | |
198 | ||
199 | }; | |
200 | ||
201 | static const struct imx_i2c_hwdata imx21_i2c_hwdata = { | |
202 | .devtype = IMX21_I2C, | |
203 | .regshift = IMX_I2C_REGSHIFT, | |
204 | .clk_div = imx_i2c_clk_div, | |
205 | .ndivs = ARRAY_SIZE(imx_i2c_clk_div), | |
206 | .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C, | |
207 | .i2cr_ien_opcode = I2CR_IEN_OPCODE_1, | |
208 | ||
5bdfba29 SG |
209 | }; |
210 | ||
ad90efae JL |
211 | static struct imx_i2c_hwdata vf610_i2c_hwdata = { |
212 | .devtype = VF610_I2C, | |
213 | .regshift = VF610_I2C_REGSHIFT, | |
214 | .clk_div = vf610_i2c_clk_div, | |
215 | .ndivs = ARRAY_SIZE(vf610_i2c_clk_div), | |
216 | .i2sr_clr_opcode = I2SR_CLR_OPCODE_W1C, | |
217 | .i2cr_ien_opcode = I2CR_IEN_OPCODE_0, | |
218 | ||
219 | }; | |
220 | ||
5bdfba29 SG |
221 | static struct platform_device_id imx_i2c_devtype[] = { |
222 | { | |
223 | .name = "imx1-i2c", | |
4b775022 | 224 | .driver_data = (kernel_ulong_t)&imx1_i2c_hwdata, |
5bdfba29 SG |
225 | }, { |
226 | .name = "imx21-i2c", | |
4b775022 | 227 | .driver_data = (kernel_ulong_t)&imx21_i2c_hwdata, |
5bdfba29 SG |
228 | }, { |
229 | /* sentinel */ | |
230 | } | |
aa11e38c | 231 | }; |
5bdfba29 | 232 | MODULE_DEVICE_TABLE(platform, imx_i2c_devtype); |
aa11e38c | 233 | |
dfcd04b1 | 234 | static const struct of_device_id i2c_imx_dt_ids[] = { |
4b775022 JL |
235 | { .compatible = "fsl,imx1-i2c", .data = &imx1_i2c_hwdata, }, |
236 | { .compatible = "fsl,imx21-i2c", .data = &imx21_i2c_hwdata, }, | |
ad90efae | 237 | { .compatible = "fsl,vf610-i2c", .data = &vf610_i2c_hwdata, }, |
dfcd04b1 SG |
238 | { /* sentinel */ } |
239 | }; | |
2f641a8b | 240 | MODULE_DEVICE_TABLE(of, i2c_imx_dt_ids); |
dfcd04b1 | 241 | |
5bdfba29 SG |
242 | static inline int is_imx1_i2c(struct imx_i2c_struct *i2c_imx) |
243 | { | |
4b775022 | 244 | return i2c_imx->hwdata->devtype == IMX1_I2C; |
5bdfba29 SG |
245 | } |
246 | ||
1d5ef2a8 JL |
247 | static inline void imx_i2c_write_reg(unsigned int val, |
248 | struct imx_i2c_struct *i2c_imx, unsigned int reg) | |
249 | { | |
4b775022 | 250 | writeb(val, i2c_imx->base + (reg << i2c_imx->hwdata->regshift)); |
1d5ef2a8 JL |
251 | } |
252 | ||
253 | static inline unsigned char imx_i2c_read_reg(struct imx_i2c_struct *i2c_imx, | |
254 | unsigned int reg) | |
255 | { | |
4b775022 | 256 | return readb(i2c_imx->base + (reg << i2c_imx->hwdata->regshift)); |
1d5ef2a8 JL |
257 | } |
258 | ||
aa11e38c DA |
259 | /** Functions for IMX I2C adapter driver *************************************** |
260 | *******************************************************************************/ | |
261 | ||
43309f3b | 262 | static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy) |
aa11e38c DA |
263 | { |
264 | unsigned long orig_jiffies = jiffies; | |
43309f3b | 265 | unsigned int temp; |
aa11e38c DA |
266 | |
267 | dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); | |
268 | ||
43309f3b | 269 | while (1) { |
1d5ef2a8 | 270 | temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); |
43309f3b RZ |
271 | if (for_busy && (temp & I2SR_IBB)) |
272 | break; | |
273 | if (!for_busy && !(temp & I2SR_IBB)) | |
274 | break; | |
da9c99fc | 275 | if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) { |
aa11e38c DA |
276 | dev_dbg(&i2c_imx->adapter.dev, |
277 | "<%s> I2C bus is busy\n", __func__); | |
da9c99fc | 278 | return -ETIMEDOUT; |
aa11e38c DA |
279 | } |
280 | schedule(); | |
281 | } | |
282 | ||
283 | return 0; | |
284 | } | |
285 | ||
286 | static int i2c_imx_trx_complete(struct imx_i2c_struct *i2c_imx) | |
287 | { | |
e39428d5 | 288 | wait_event_timeout(i2c_imx->queue, i2c_imx->i2csr & I2SR_IIF, HZ / 10); |
aa11e38c | 289 | |
e39428d5 | 290 | if (unlikely(!(i2c_imx->i2csr & I2SR_IIF))) { |
aa11e38c DA |
291 | dev_dbg(&i2c_imx->adapter.dev, "<%s> Timeout\n", __func__); |
292 | return -ETIMEDOUT; | |
293 | } | |
294 | dev_dbg(&i2c_imx->adapter.dev, "<%s> TRX complete\n", __func__); | |
295 | i2c_imx->i2csr = 0; | |
296 | return 0; | |
297 | } | |
298 | ||
299 | static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx) | |
300 | { | |
1d5ef2a8 | 301 | if (imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR) & I2SR_RXAK) { |
aa11e38c DA |
302 | dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__); |
303 | return -EIO; /* No ACK */ | |
304 | } | |
305 | ||
306 | dev_dbg(&i2c_imx->adapter.dev, "<%s> ACK received\n", __func__); | |
307 | return 0; | |
308 | } | |
309 | ||
9b2a6da3 FD |
310 | static void i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx) |
311 | { | |
312 | struct imx_i2c_clk_pair *i2c_clk_div = i2c_imx->hwdata->clk_div; | |
313 | unsigned int i2c_clk_rate; | |
314 | unsigned int div; | |
315 | int i; | |
316 | ||
317 | /* Divider value calculation */ | |
318 | i2c_clk_rate = clk_get_rate(i2c_imx->clk); | |
319 | if (i2c_imx->cur_clk == i2c_clk_rate) | |
320 | return; | |
321 | else | |
322 | i2c_imx->cur_clk = i2c_clk_rate; | |
323 | ||
324 | div = (i2c_clk_rate + i2c_imx->bitrate - 1) / i2c_imx->bitrate; | |
325 | if (div < i2c_clk_div[0].div) | |
326 | i = 0; | |
327 | else if (div > i2c_clk_div[i2c_imx->hwdata->ndivs - 1].div) | |
328 | i = i2c_imx->hwdata->ndivs - 1; | |
329 | else | |
330 | for (i = 0; i2c_clk_div[i].div < div; i++); | |
331 | ||
332 | /* Store divider value */ | |
333 | i2c_imx->ifdr = i2c_clk_div[i].val; | |
334 | ||
335 | /* | |
336 | * There dummy delay is calculated. | |
337 | * It should be about one I2C clock period long. | |
338 | * This delay is used in I2C bus disable function | |
339 | * to fix chip hardware bug. | |
340 | */ | |
341 | i2c_imx->disable_delay = (500000U * i2c_clk_div[i].div | |
342 | + (i2c_clk_rate / 2) - 1) / (i2c_clk_rate / 2); | |
343 | ||
344 | #ifdef CONFIG_I2C_DEBUG_BUS | |
345 | dev_dbg(&i2c_imx->adapter.dev, "I2C_CLK=%d, REQ DIV=%d\n", | |
346 | i2c_clk_rate, div); | |
347 | dev_dbg(&i2c_imx->adapter.dev, "IFDR[IC]=0x%x, REAL DIV=%d\n", | |
348 | i2c_clk_div[i].val, i2c_clk_div[i].div); | |
349 | #endif | |
350 | } | |
351 | ||
43309f3b | 352 | static int i2c_imx_start(struct imx_i2c_struct *i2c_imx) |
aa11e38c DA |
353 | { |
354 | unsigned int temp = 0; | |
43309f3b | 355 | int result; |
aa11e38c DA |
356 | |
357 | dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); | |
358 | ||
9b2a6da3 FD |
359 | i2c_imx_set_clk(i2c_imx); |
360 | ||
e5bf216a FE |
361 | result = clk_prepare_enable(i2c_imx->clk); |
362 | if (result) | |
363 | return result; | |
1d5ef2a8 | 364 | imx_i2c_write_reg(i2c_imx->ifdr, i2c_imx, IMX_I2C_IFDR); |
aa11e38c | 365 | /* Enable I2C controller */ |
4b775022 JL |
366 | imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR); |
367 | imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode, i2c_imx, IMX_I2C_I2CR); | |
43309f3b RZ |
368 | |
369 | /* Wait controller to be stable */ | |
370 | udelay(50); | |
371 | ||
aa11e38c | 372 | /* Start I2C transaction */ |
1d5ef2a8 | 373 | temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); |
aa11e38c | 374 | temp |= I2CR_MSTA; |
1d5ef2a8 | 375 | imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); |
43309f3b RZ |
376 | result = i2c_imx_bus_busy(i2c_imx, 1); |
377 | if (result) | |
378 | return result; | |
379 | i2c_imx->stopped = 0; | |
380 | ||
aa11e38c | 381 | temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK; |
1d5ef2a8 | 382 | imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); |
43309f3b | 383 | return result; |
aa11e38c DA |
384 | } |
385 | ||
386 | static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx) | |
387 | { | |
388 | unsigned int temp = 0; | |
389 | ||
43309f3b RZ |
390 | if (!i2c_imx->stopped) { |
391 | /* Stop I2C transaction */ | |
392 | dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); | |
1d5ef2a8 | 393 | temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); |
43309f3b | 394 | temp &= ~(I2CR_MSTA | I2CR_MTX); |
1d5ef2a8 | 395 | imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); |
43309f3b | 396 | } |
5bdfba29 | 397 | if (is_imx1_i2c(i2c_imx)) { |
a4094a76 RZ |
398 | /* |
399 | * This delay caused by an i.MXL hardware bug. | |
400 | * If no (or too short) delay, no "STOP" bit will be generated. | |
401 | */ | |
402 | udelay(i2c_imx->disable_delay); | |
403 | } | |
43309f3b | 404 | |
a1ee06b7 | 405 | if (!i2c_imx->stopped) { |
43309f3b | 406 | i2c_imx_bus_busy(i2c_imx, 0); |
a1ee06b7 VL |
407 | i2c_imx->stopped = 1; |
408 | } | |
43309f3b | 409 | |
aa11e38c | 410 | /* Disable I2C controller */ |
4b775022 JL |
411 | temp = i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN, |
412 | imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); | |
83914337 | 413 | clk_disable_unprepare(i2c_imx->clk); |
aa11e38c DA |
414 | } |
415 | ||
aa11e38c DA |
416 | static irqreturn_t i2c_imx_isr(int irq, void *dev_id) |
417 | { | |
418 | struct imx_i2c_struct *i2c_imx = dev_id; | |
419 | unsigned int temp; | |
420 | ||
1d5ef2a8 | 421 | temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); |
aa11e38c DA |
422 | if (temp & I2SR_IIF) { |
423 | /* save status register */ | |
424 | i2c_imx->i2csr = temp; | |
425 | temp &= ~I2SR_IIF; | |
4b775022 | 426 | temp |= (i2c_imx->hwdata->i2sr_clr_opcode & I2SR_IIF); |
1d5ef2a8 | 427 | imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR); |
e39428d5 | 428 | wake_up(&i2c_imx->queue); |
aa11e38c DA |
429 | return IRQ_HANDLED; |
430 | } | |
431 | ||
432 | return IRQ_NONE; | |
433 | } | |
434 | ||
435 | static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs) | |
436 | { | |
437 | int i, result; | |
438 | ||
439 | dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n", | |
440 | __func__, msgs->addr << 1); | |
441 | ||
442 | /* write slave address */ | |
1d5ef2a8 | 443 | imx_i2c_write_reg(msgs->addr << 1, i2c_imx, IMX_I2C_I2DR); |
aa11e38c DA |
444 | result = i2c_imx_trx_complete(i2c_imx); |
445 | if (result) | |
446 | return result; | |
447 | result = i2c_imx_acked(i2c_imx); | |
448 | if (result) | |
449 | return result; | |
450 | dev_dbg(&i2c_imx->adapter.dev, "<%s> write data\n", __func__); | |
451 | ||
452 | /* write data */ | |
453 | for (i = 0; i < msgs->len; i++) { | |
454 | dev_dbg(&i2c_imx->adapter.dev, | |
455 | "<%s> write byte: B%d=0x%X\n", | |
456 | __func__, i, msgs->buf[i]); | |
1d5ef2a8 | 457 | imx_i2c_write_reg(msgs->buf[i], i2c_imx, IMX_I2C_I2DR); |
aa11e38c DA |
458 | result = i2c_imx_trx_complete(i2c_imx); |
459 | if (result) | |
460 | return result; | |
461 | result = i2c_imx_acked(i2c_imx); | |
462 | if (result) | |
463 | return result; | |
464 | } | |
465 | return 0; | |
466 | } | |
467 | ||
054b62d9 | 468 | static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs, bool is_lastmsg) |
aa11e38c DA |
469 | { |
470 | int i, result; | |
471 | unsigned int temp; | |
8e8782c7 | 472 | int block_data = msgs->flags & I2C_M_RECV_LEN; |
aa11e38c DA |
473 | |
474 | dev_dbg(&i2c_imx->adapter.dev, | |
475 | "<%s> write slave address: addr=0x%x\n", | |
476 | __func__, (msgs->addr << 1) | 0x01); | |
477 | ||
478 | /* write slave address */ | |
1d5ef2a8 | 479 | imx_i2c_write_reg((msgs->addr << 1) | 0x01, i2c_imx, IMX_I2C_I2DR); |
aa11e38c DA |
480 | result = i2c_imx_trx_complete(i2c_imx); |
481 | if (result) | |
482 | return result; | |
483 | result = i2c_imx_acked(i2c_imx); | |
484 | if (result) | |
485 | return result; | |
486 | ||
487 | dev_dbg(&i2c_imx->adapter.dev, "<%s> setup bus\n", __func__); | |
488 | ||
489 | /* setup bus to read data */ | |
1d5ef2a8 | 490 | temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); |
aa11e38c | 491 | temp &= ~I2CR_MTX; |
8e8782c7 KB |
492 | |
493 | /* | |
494 | * Reset the I2CR_TXAK flag initially for SMBus block read since the | |
495 | * length is unknown | |
496 | */ | |
497 | if ((msgs->len - 1) || block_data) | |
aa11e38c | 498 | temp &= ~I2CR_TXAK; |
1d5ef2a8 JL |
499 | imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); |
500 | imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); /* dummy read */ | |
aa11e38c DA |
501 | |
502 | dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__); | |
503 | ||
504 | /* read data */ | |
505 | for (i = 0; i < msgs->len; i++) { | |
8e8782c7 | 506 | u8 len = 0; |
aa11e38c DA |
507 | result = i2c_imx_trx_complete(i2c_imx); |
508 | if (result) | |
509 | return result; | |
8e8782c7 KB |
510 | /* |
511 | * First byte is the length of remaining packet | |
512 | * in the SMBus block data read. Add it to | |
513 | * msgs->len. | |
514 | */ | |
515 | if ((!i) && block_data) { | |
516 | len = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); | |
517 | if ((len == 0) || (len > I2C_SMBUS_BLOCK_MAX)) | |
518 | return -EPROTO; | |
519 | dev_dbg(&i2c_imx->adapter.dev, | |
520 | "<%s> read length: 0x%X\n", | |
521 | __func__, len); | |
522 | msgs->len += len; | |
523 | } | |
aa11e38c | 524 | if (i == (msgs->len - 1)) { |
054b62d9 FD |
525 | if (is_lastmsg) { |
526 | /* | |
527 | * It must generate STOP before read I2DR to prevent | |
528 | * controller from generating another clock cycle | |
529 | */ | |
530 | dev_dbg(&i2c_imx->adapter.dev, | |
531 | "<%s> clear MSTA\n", __func__); | |
532 | temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); | |
533 | temp &= ~(I2CR_MSTA | I2CR_MTX); | |
534 | imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); | |
535 | i2c_imx_bus_busy(i2c_imx, 0); | |
536 | i2c_imx->stopped = 1; | |
537 | } else { | |
538 | /* | |
539 | * For i2c master receiver repeat restart operation like: | |
540 | * read -> repeat MSTA -> read/write | |
541 | * The controller must set MTX before read the last byte in | |
542 | * the first read operation, otherwise the first read cost | |
543 | * one extra clock cycle. | |
544 | */ | |
545 | temp = readb(i2c_imx->base + IMX_I2C_I2CR); | |
546 | temp |= I2CR_MTX; | |
547 | writeb(temp, i2c_imx->base + IMX_I2C_I2CR); | |
548 | } | |
aa11e38c DA |
549 | } else if (i == (msgs->len - 2)) { |
550 | dev_dbg(&i2c_imx->adapter.dev, | |
551 | "<%s> set TXAK\n", __func__); | |
1d5ef2a8 | 552 | temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); |
aa11e38c | 553 | temp |= I2CR_TXAK; |
1d5ef2a8 | 554 | imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); |
aa11e38c | 555 | } |
8e8782c7 KB |
556 | if ((!i) && block_data) |
557 | msgs->buf[0] = len; | |
558 | else | |
559 | msgs->buf[i] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); | |
aa11e38c DA |
560 | dev_dbg(&i2c_imx->adapter.dev, |
561 | "<%s> read byte: B%d=0x%X\n", | |
562 | __func__, i, msgs->buf[i]); | |
563 | } | |
564 | return 0; | |
565 | } | |
566 | ||
567 | static int i2c_imx_xfer(struct i2c_adapter *adapter, | |
568 | struct i2c_msg *msgs, int num) | |
569 | { | |
570 | unsigned int i, temp; | |
571 | int result; | |
054b62d9 | 572 | bool is_lastmsg = false; |
aa11e38c DA |
573 | struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter); |
574 | ||
575 | dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); | |
576 | ||
43309f3b RZ |
577 | /* Start I2C transfer */ |
578 | result = i2c_imx_start(i2c_imx); | |
aa11e38c DA |
579 | if (result) |
580 | goto fail0; | |
581 | ||
aa11e38c DA |
582 | /* read/write data */ |
583 | for (i = 0; i < num; i++) { | |
054b62d9 FD |
584 | if (i == num - 1) |
585 | is_lastmsg = true; | |
586 | ||
aa11e38c DA |
587 | if (i) { |
588 | dev_dbg(&i2c_imx->adapter.dev, | |
589 | "<%s> repeated start\n", __func__); | |
1d5ef2a8 | 590 | temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); |
aa11e38c | 591 | temp |= I2CR_RSTA; |
1d5ef2a8 | 592 | imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); |
43309f3b RZ |
593 | result = i2c_imx_bus_busy(i2c_imx, 1); |
594 | if (result) | |
595 | goto fail0; | |
aa11e38c DA |
596 | } |
597 | dev_dbg(&i2c_imx->adapter.dev, | |
598 | "<%s> transfer message: %d\n", __func__, i); | |
599 | /* write/read data */ | |
600 | #ifdef CONFIG_I2C_DEBUG_BUS | |
1d5ef2a8 | 601 | temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); |
aa11e38c DA |
602 | dev_dbg(&i2c_imx->adapter.dev, "<%s> CONTROL: IEN=%d, IIEN=%d, " |
603 | "MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n", __func__, | |
604 | (temp & I2CR_IEN ? 1 : 0), (temp & I2CR_IIEN ? 1 : 0), | |
605 | (temp & I2CR_MSTA ? 1 : 0), (temp & I2CR_MTX ? 1 : 0), | |
606 | (temp & I2CR_TXAK ? 1 : 0), (temp & I2CR_RSTA ? 1 : 0)); | |
1d5ef2a8 | 607 | temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); |
aa11e38c DA |
608 | dev_dbg(&i2c_imx->adapter.dev, |
609 | "<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, " | |
610 | "IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n", __func__, | |
611 | (temp & I2SR_ICF ? 1 : 0), (temp & I2SR_IAAS ? 1 : 0), | |
612 | (temp & I2SR_IBB ? 1 : 0), (temp & I2SR_IAL ? 1 : 0), | |
613 | (temp & I2SR_SRW ? 1 : 0), (temp & I2SR_IIF ? 1 : 0), | |
614 | (temp & I2SR_RXAK ? 1 : 0)); | |
615 | #endif | |
616 | if (msgs[i].flags & I2C_M_RD) | |
054b62d9 | 617 | result = i2c_imx_read(i2c_imx, &msgs[i], is_lastmsg); |
aa11e38c DA |
618 | else |
619 | result = i2c_imx_write(i2c_imx, &msgs[i]); | |
da9c99fc AP |
620 | if (result) |
621 | goto fail0; | |
aa11e38c DA |
622 | } |
623 | ||
624 | fail0: | |
625 | /* Stop I2C transfer */ | |
626 | i2c_imx_stop(i2c_imx); | |
627 | ||
628 | dev_dbg(&i2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__, | |
629 | (result < 0) ? "error" : "success msg", | |
630 | (result < 0) ? result : num); | |
631 | return (result < 0) ? result : num; | |
632 | } | |
633 | ||
634 | static u32 i2c_imx_func(struct i2c_adapter *adapter) | |
635 | { | |
8e8782c7 KB |
636 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
637 | | I2C_FUNC_SMBUS_READ_BLOCK_DATA; | |
aa11e38c DA |
638 | } |
639 | ||
640 | static struct i2c_algorithm i2c_imx_algo = { | |
641 | .master_xfer = i2c_imx_xfer, | |
642 | .functionality = i2c_imx_func, | |
643 | }; | |
644 | ||
3611431c | 645 | static int i2c_imx_probe(struct platform_device *pdev) |
aa11e38c | 646 | { |
5bdfba29 SG |
647 | const struct of_device_id *of_id = of_match_device(i2c_imx_dt_ids, |
648 | &pdev->dev); | |
aa11e38c DA |
649 | struct imx_i2c_struct *i2c_imx; |
650 | struct resource *res; | |
6d4028c6 | 651 | struct imxi2c_platform_data *pdata = dev_get_platdata(&pdev->dev); |
aa11e38c | 652 | void __iomem *base; |
8c88ab04 | 653 | int irq, ret; |
aa11e38c DA |
654 | |
655 | dev_dbg(&pdev->dev, "<%s>\n", __func__); | |
656 | ||
aa11e38c DA |
657 | irq = platform_get_irq(pdev, 0); |
658 | if (irq < 0) { | |
659 | dev_err(&pdev->dev, "can't get irq number\n"); | |
a8763f33 | 660 | return irq; |
aa11e38c DA |
661 | } |
662 | ||
3cc2d009 | 663 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
84dbf809 TR |
664 | base = devm_ioremap_resource(&pdev->dev, res); |
665 | if (IS_ERR(base)) | |
666 | return PTR_ERR(base); | |
aa11e38c | 667 | |
9f8a3e7f RZ |
668 | i2c_imx = devm_kzalloc(&pdev->dev, sizeof(struct imx_i2c_struct), |
669 | GFP_KERNEL); | |
aa11e38c DA |
670 | if (!i2c_imx) { |
671 | dev_err(&pdev->dev, "can't allocate interface\n"); | |
9f8a3e7f | 672 | return -ENOMEM; |
309c18d2 DA |
673 | } |
674 | ||
5bdfba29 | 675 | if (of_id) |
4b775022 | 676 | i2c_imx->hwdata = of_id->data; |
0fc1347a | 677 | else |
4b775022 JL |
678 | i2c_imx->hwdata = (struct imx_i2c_hwdata *) |
679 | platform_get_device_id(pdev)->driver_data; | |
5bdfba29 | 680 | |
aa11e38c | 681 | /* Setup i2c_imx driver structure */ |
973c5ed4 | 682 | strlcpy(i2c_imx->adapter.name, pdev->name, sizeof(i2c_imx->adapter.name)); |
aa11e38c DA |
683 | i2c_imx->adapter.owner = THIS_MODULE; |
684 | i2c_imx->adapter.algo = &i2c_imx_algo; | |
685 | i2c_imx->adapter.dev.parent = &pdev->dev; | |
686 | i2c_imx->adapter.nr = pdev->id; | |
dfcd04b1 | 687 | i2c_imx->adapter.dev.of_node = pdev->dev.of_node; |
aa11e38c | 688 | i2c_imx->base = base; |
aa11e38c DA |
689 | |
690 | /* Get I2C clock */ | |
1f09c672 | 691 | i2c_imx->clk = devm_clk_get(&pdev->dev, NULL); |
aa11e38c | 692 | if (IS_ERR(i2c_imx->clk)) { |
aa11e38c | 693 | dev_err(&pdev->dev, "can't get I2C clock\n"); |
9f8a3e7f | 694 | return PTR_ERR(i2c_imx->clk); |
aa11e38c | 695 | } |
aa11e38c | 696 | |
46f2832b JL |
697 | ret = clk_prepare_enable(i2c_imx->clk); |
698 | if (ret) { | |
699 | dev_err(&pdev->dev, "can't enable I2C clock\n"); | |
700 | return ret; | |
701 | } | |
aa11e38c | 702 | /* Request IRQ */ |
9f8a3e7f RZ |
703 | ret = devm_request_irq(&pdev->dev, irq, i2c_imx_isr, 0, |
704 | pdev->name, i2c_imx); | |
aa11e38c | 705 | if (ret) { |
9f8a3e7f RZ |
706 | dev_err(&pdev->dev, "can't claim irq %d\n", irq); |
707 | return ret; | |
aa11e38c DA |
708 | } |
709 | ||
710 | /* Init queue */ | |
711 | init_waitqueue_head(&i2c_imx->queue); | |
712 | ||
713 | /* Set up adapter data */ | |
714 | i2c_set_adapdata(&i2c_imx->adapter, i2c_imx); | |
715 | ||
716 | /* Set up clock divider */ | |
9b2a6da3 | 717 | i2c_imx->bitrate = IMX_I2C_BIT_RATE; |
dfcd04b1 | 718 | ret = of_property_read_u32(pdev->dev.of_node, |
9b2a6da3 | 719 | "clock-frequency", &i2c_imx->bitrate); |
dfcd04b1 | 720 | if (ret < 0 && pdata && pdata->bitrate) |
9b2a6da3 | 721 | i2c_imx->bitrate = pdata->bitrate; |
aa11e38c DA |
722 | |
723 | /* Set up chip registers to defaults */ | |
4b775022 JL |
724 | imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN, |
725 | i2c_imx, IMX_I2C_I2CR); | |
726 | imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR); | |
aa11e38c DA |
727 | |
728 | /* Add I2C adapter */ | |
729 | ret = i2c_add_numbered_adapter(&i2c_imx->adapter); | |
730 | if (ret < 0) { | |
731 | dev_err(&pdev->dev, "registration failed\n"); | |
9f8a3e7f | 732 | return ret; |
aa11e38c DA |
733 | } |
734 | ||
735 | /* Set up platform driver data */ | |
736 | platform_set_drvdata(pdev, i2c_imx); | |
46f2832b | 737 | clk_disable_unprepare(i2c_imx->clk); |
aa11e38c | 738 | |
9f8a3e7f | 739 | dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n", irq); |
aa11e38c | 740 | dev_dbg(&i2c_imx->adapter.dev, "device resources from 0x%x to 0x%x\n", |
9f8a3e7f RZ |
741 | res->start, res->end); |
742 | dev_dbg(&i2c_imx->adapter.dev, "allocated %d bytes at 0x%x\n", | |
743 | resource_size(res), res->start); | |
aa11e38c DA |
744 | dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n", |
745 | i2c_imx->adapter.name); | |
06d141e9 | 746 | dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n"); |
aa11e38c DA |
747 | |
748 | return 0; /* Return OK */ | |
aa11e38c DA |
749 | } |
750 | ||
3611431c | 751 | static int i2c_imx_remove(struct platform_device *pdev) |
aa11e38c DA |
752 | { |
753 | struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev); | |
aa11e38c DA |
754 | |
755 | /* remove adapter */ | |
756 | dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n"); | |
757 | i2c_del_adapter(&i2c_imx->adapter); | |
aa11e38c | 758 | |
aa11e38c | 759 | /* setup chip registers to defaults */ |
1d5ef2a8 JL |
760 | imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR); |
761 | imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IFDR); | |
762 | imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2CR); | |
763 | imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2SR); | |
aa11e38c | 764 | |
aa11e38c DA |
765 | return 0; |
766 | } | |
767 | ||
768 | static struct platform_driver i2c_imx_driver = { | |
3611431c WS |
769 | .probe = i2c_imx_probe, |
770 | .remove = i2c_imx_remove, | |
aa11e38c DA |
771 | .driver = { |
772 | .name = DRIVER_NAME, | |
773 | .owner = THIS_MODULE, | |
dfcd04b1 | 774 | .of_match_table = i2c_imx_dt_ids, |
5bdfba29 SG |
775 | }, |
776 | .id_table = imx_i2c_devtype, | |
aa11e38c DA |
777 | }; |
778 | ||
779 | static int __init i2c_adap_imx_init(void) | |
780 | { | |
3611431c | 781 | return platform_driver_register(&i2c_imx_driver); |
aa11e38c | 782 | } |
5d3f3331 | 783 | subsys_initcall(i2c_adap_imx_init); |
aa11e38c DA |
784 | |
785 | static void __exit i2c_adap_imx_exit(void) | |
786 | { | |
787 | platform_driver_unregister(&i2c_imx_driver); | |
788 | } | |
aa11e38c DA |
789 | module_exit(i2c_adap_imx_exit); |
790 | ||
791 | MODULE_LICENSE("GPL"); | |
792 | MODULE_AUTHOR("Darius Augulis"); | |
793 | MODULE_DESCRIPTION("I2C adapter driver for IMX I2C bus"); | |
794 | MODULE_ALIAS("platform:" DRIVER_NAME); |