[deliverable/linux.git] / drivers / i2c / busses / i2c-iop3xx.c

/* ------------------------------------------------------------------------- */
/* i2c-iop3xx.c i2c driver algorithms for Intel XScale IOP3xx & IXP46x       */
/* ------------------------------------------------------------------------- */
/* Copyright (C) 2003 Peter Milne, D-TACQ Solutions Ltd
 *                    <Peter dot Milne at D hyphen TACQ dot com>
 *
 * With acknowledgements to i2c-algo-ibm_ocp.c by 
 * Ian DaSilva, MontaVista Software, Inc. idasilva@mvista.com
 *
 * And i2c-algo-pcf.c, which was created by Simon G. Vogl and Hans Berglund:
 *
 * Copyright (C) 1995-1997 Simon G. Vogl, 1998-2000 Hans Berglund
 *  
 * And which acknowledged Kyösti Mälkki <kmalkki@cc.hut.fi>,
 * Frodo Looijaard <frodol@dds.nl>, Martin Bailey<mbailey@littlefeet-inc.com>
 *
 * Major cleanup by Deepak Saxena <dsaxena@plexity.net>, 01/2005:
 *
 * - Use driver model to pass per-chip info instead of hardcoding and #ifdefs
 * - Use ioremap/__raw_readl/__raw_writel instead of direct dereference
 * - Make it work with IXP46x chips
 * - Cleanup function names, coding style, etc
 *
 * - writing to slave address causes latchup on iop331.
 *	fix: driver refuses to address self.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, version 2.
 */

#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/slab.h>
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/sched.h>
#include <linux/platform_device.h>
#include <linux/i2c.h>

#include <asm/io.h>

#include "i2c-iop3xx.h"

/* global unit counter */
static int i2c_id;

static inline unsigned char 
iic_cook_addr(struct i2c_msg *msg) 
{
	unsigned char addr;

	addr = (msg->addr << 1);

	if (msg->flags & I2C_M_RD)
		addr |= 1;

	/*
	 * Read or Write?
	 */
	if (msg->flags & I2C_M_REV_DIR_ADDR)
		addr ^= 1;

	return addr;   
}

static void 
iop3xx_i2c_reset(struct i2c_algo_iop3xx_data *iop3xx_adap)
{
	/* Follows devman 9.3 */
	__raw_writel(IOP3XX_ICR_UNIT_RESET, iop3xx_adap->ioaddr + CR_OFFSET);
	__raw_writel(IOP3XX_ISR_CLEARBITS, iop3xx_adap->ioaddr + SR_OFFSET);
	__raw_writel(0, iop3xx_adap->ioaddr + CR_OFFSET);
} 

static void 
iop3xx_i2c_enable(struct i2c_algo_iop3xx_data *iop3xx_adap)
{
	u32 cr = IOP3XX_ICR_GCD | IOP3XX_ICR_SCLEN | IOP3XX_ICR_UE;

	/* 
	 * Every time unit enable is asserted, GPOD needs to be cleared
	 * on IOP321 to avoid data corruption on the bus.
	 */
#ifdef CONFIG_ARCH_IOP321
#define IOP321_GPOD_I2C0    0x00c0  /* clear these bits to enable ch0 */
#define IOP321_GPOD_I2C1    0x0030  /* clear these bits to enable ch1 */

	*IOP321_GPOD &= (iop3xx_adap->id == 0) ? ~IOP321_GPOD_I2C0 : 
		~IOP321_GPOD_I2C1;
#endif
	/* NB SR bits not same position as CR IE bits :-( */
	iop3xx_adap->SR_enabled = 
		IOP3XX_ISR_ALD | IOP3XX_ISR_BERRD |
		IOP3XX_ISR_RXFULL | IOP3XX_ISR_TXEMPTY;

	cr |= IOP3XX_ICR_ALD_IE | IOP3XX_ICR_BERR_IE |
		IOP3XX_ICR_RXFULL_IE | IOP3XX_ICR_TXEMPTY_IE;

	__raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
}

static void 
iop3xx_i2c_transaction_cleanup(struct i2c_algo_iop3xx_data *iop3xx_adap)
{
	unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
	
	cr &= ~(IOP3XX_ICR_MSTART | IOP3XX_ICR_TBYTE | 
		IOP3XX_ICR_MSTOP | IOP3XX_ICR_SCLEN);

	__raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
}

/* 
 * NB: the handler has to clear the source of the interrupt! 
 * Then it passes the SR flags of interest to BH via adap data
 */
static irqreturn_t 
iop3xx_i2c_irq_handler(int this_irq, void *dev_id, struct pt_regs *regs) 
{
	struct i2c_algo_iop3xx_data *iop3xx_adap = dev_id;
	u32 sr = __raw_readl(iop3xx_adap->ioaddr + SR_OFFSET);

	if ((sr &= iop3xx_adap->SR_enabled)) {
		__raw_writel(sr, iop3xx_adap->ioaddr + SR_OFFSET);
		iop3xx_adap->SR_received |= sr;
		wake_up_interruptible(&iop3xx_adap->waitq);
	}
	return IRQ_HANDLED;
}

/* check all error conditions, clear them , report most important */
static int 
iop3xx_i2c_error(u32 sr)
{
	int rc = 0;

	if ((sr & IOP3XX_ISR_BERRD)) {
		if ( !rc ) rc = -I2C_ERR_BERR;
	}
	if ((sr & IOP3XX_ISR_ALD)) {
		if ( !rc ) rc = -I2C_ERR_ALD;		
	}
	return rc;	
}

static inline u32 
iop3xx_i2c_get_srstat(struct i2c_algo_iop3xx_data *iop3xx_adap)
{
	unsigned long flags;
	u32 sr;

	spin_lock_irqsave(&iop3xx_adap->lock, flags);
	sr = iop3xx_adap->SR_received;
	iop3xx_adap->SR_received = 0;
	spin_unlock_irqrestore(&iop3xx_adap->lock, flags);

	return sr;
}

/*
 * sleep until interrupted, then recover and analyse the SR
 * saved by handler
 */
typedef int (* compare_func)(unsigned test, unsigned mask);
/* returns 1 on correct comparison */

static int 
iop3xx_i2c_wait_event(struct i2c_algo_iop3xx_data *iop3xx_adap, 
			  unsigned flags, unsigned* status,
			  compare_func compare)
{
	unsigned sr = 0;
	int interrupted;
	int done;
	int rc = 0;

	do {
		interrupted = wait_event_interruptible_timeout (
			iop3xx_adap->waitq,
			(done = compare( sr = iop3xx_i2c_get_srstat(iop3xx_adap) ,flags )),
			1 * HZ;
			);
		if ((rc = iop3xx_i2c_error(sr)) < 0) {
			*status = sr;
			return rc;
		} else if (!interrupted) {
			*status = sr;
			return -ETIMEDOUT;
		}
	} while(!done);

	*status = sr;

	return 0;
}

/*
 * Concrete compare_funcs 
 */
static int 
all_bits_clear(unsigned test, unsigned mask)
{
	return (test & mask) == 0;
}

static int 
any_bits_set(unsigned test, unsigned mask)
{
	return (test & mask) != 0;
}

static int 
iop3xx_i2c_wait_tx_done(struct i2c_algo_iop3xx_data *iop3xx_adap, int *status)
{
	return iop3xx_i2c_wait_event( 
		iop3xx_adap, 
	        IOP3XX_ISR_TXEMPTY | IOP3XX_ISR_ALD | IOP3XX_ISR_BERRD,
		status, any_bits_set);
}

static int 
iop3xx_i2c_wait_rx_done(struct i2c_algo_iop3xx_data *iop3xx_adap, int *status)
{
	return iop3xx_i2c_wait_event( 
		iop3xx_adap, 
		IOP3XX_ISR_RXFULL | IOP3XX_ISR_ALD | IOP3XX_ISR_BERRD,
		status,	any_bits_set);
}

static int 
iop3xx_i2c_wait_idle(struct i2c_algo_iop3xx_data *iop3xx_adap, int *status)
{
	return iop3xx_i2c_wait_event( 
		iop3xx_adap, IOP3XX_ISR_UNITBUSY, status, all_bits_clear);
}

static int 
iop3xx_i2c_send_target_addr(struct i2c_algo_iop3xx_data *iop3xx_adap, 
				struct i2c_msg* msg)
{
	unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
	int status;
	int rc;

	/* avoid writing to my slave address (hangs on 80331),
	 * forbidden in Intel developer manual
	 */
	if (msg->addr == MYSAR) {
		return -EBUSY;
	}

	__raw_writel(iic_cook_addr(msg), iop3xx_adap->ioaddr + DBR_OFFSET);
	
	cr &= ~(IOP3XX_ICR_MSTOP | IOP3XX_ICR_NACK);
	cr |= IOP3XX_ICR_MSTART | IOP3XX_ICR_TBYTE;

	__raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
	rc = iop3xx_i2c_wait_tx_done(iop3xx_adap, &status);

	return rc;
}

static int 
iop3xx_i2c_write_byte(struct i2c_algo_iop3xx_data *iop3xx_adap, char byte, 
				int stop)
{
	unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
	int status;
	int rc = 0;

	__raw_writel(byte, iop3xx_adap->ioaddr + DBR_OFFSET);
	cr &= ~IOP3XX_ICR_MSTART;
	if (stop) {
		cr |= IOP3XX_ICR_MSTOP;
	} else {
		cr &= ~IOP3XX_ICR_MSTOP;
	}
	cr |= IOP3XX_ICR_TBYTE;
	__raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
	rc = iop3xx_i2c_wait_tx_done(iop3xx_adap, &status);

	return rc;
} 

static int 
iop3xx_i2c_read_byte(struct i2c_algo_iop3xx_data *iop3xx_adap, char* byte, 
				int stop)
{
	unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
	int status;
	int rc = 0;

	cr &= ~IOP3XX_ICR_MSTART;

	if (stop) {
		cr |= IOP3XX_ICR_MSTOP | IOP3XX_ICR_NACK;
	} else {
		cr &= ~(IOP3XX_ICR_MSTOP | IOP3XX_ICR_NACK);
	}
	cr |= IOP3XX_ICR_TBYTE;
	__raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);

	rc = iop3xx_i2c_wait_rx_done(iop3xx_adap, &status);

	*byte = __raw_readl(iop3xx_adap->ioaddr + DBR_OFFSET);

	return rc;
}

static int 
iop3xx_i2c_writebytes(struct i2c_adapter *i2c_adap, const char *buf, int count)
{
	struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
	int ii;
	int rc = 0;

	for (ii = 0; rc == 0 && ii != count; ++ii) 
		rc = iop3xx_i2c_write_byte(iop3xx_adap, buf[ii], ii==count-1);
	return rc;
}

static int 
iop3xx_i2c_readbytes(struct i2c_adapter *i2c_adap, char *buf, int count)
{
	struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
	int ii;
	int rc = 0;

	for (ii = 0; rc == 0 && ii != count; ++ii)
		rc = iop3xx_i2c_read_byte(iop3xx_adap, &buf[ii], ii==count-1);
	
	return rc;
}

/*
 * Description:  This function implements combined transactions.  Combined
 * transactions consist of combinations of reading and writing blocks of data.
 * FROM THE SAME ADDRESS
 * Each transfer (i.e. a read or a write) is separated by a repeated start
 * condition.
 */
static int 
iop3xx_i2c_handle_msg(struct i2c_adapter *i2c_adap, struct i2c_msg* pmsg) 
{
	struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
	int rc;

	rc = iop3xx_i2c_send_target_addr(iop3xx_adap, pmsg);
	if (rc < 0) {
		return rc;
	}

	if ((pmsg->flags&I2C_M_RD)) {
		return iop3xx_i2c_readbytes(i2c_adap, pmsg->buf, pmsg->len);
	} else {
		return iop3xx_i2c_writebytes(i2c_adap, pmsg->buf, pmsg->len);
	}
}

/*
 * master_xfer() - main read/write entry
 */
static int 
iop3xx_i2c_master_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs, 
				int num)
{
	struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
	int im = 0;
	int ret = 0;
	int status;

	iop3xx_i2c_wait_idle(iop3xx_adap, &status);
	iop3xx_i2c_reset(iop3xx_adap);
	iop3xx_i2c_enable(iop3xx_adap);

	for (im = 0; ret == 0 && im != num; im++) {
		ret = iop3xx_i2c_handle_msg(i2c_adap, &msgs[im]);
	}

	iop3xx_i2c_transaction_cleanup(iop3xx_adap);
	
	if(ret)
		return ret;

	return im;   
}

static int 
iop3xx_i2c_algo_control(struct i2c_adapter *adapter, unsigned int cmd,
			unsigned long arg)
{
	return 0;
}

static u32 
iop3xx_i2c_func(struct i2c_adapter *adap)
{
	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
}

static struct i2c_algorithm iop3xx_i2c_algo = {
	.master_xfer	= iop3xx_i2c_master_xfer,
	.algo_control	= iop3xx_i2c_algo_control,
	.functionality	= iop3xx_i2c_func,
};

static int 
iop3xx_i2c_remove(struct platform_device *pdev)
{
	struct i2c_adapter *padapter = platform_get_drvdata(pdev);
	struct i2c_algo_iop3xx_data *adapter_data = 
		(struct i2c_algo_iop3xx_data *)padapter->algo_data;
	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	unsigned long cr = __raw_readl(adapter_data->ioaddr + CR_OFFSET);

	/*
	 * Disable the actual HW unit
	 */
	cr &= ~(IOP3XX_ICR_ALD_IE | IOP3XX_ICR_BERR_IE |
		IOP3XX_ICR_RXFULL_IE | IOP3XX_ICR_TXEMPTY_IE);
	__raw_writel(cr, adapter_data->ioaddr + CR_OFFSET);

	iounmap((void __iomem*)adapter_data->ioaddr);
	release_mem_region(res->start, IOP3XX_I2C_IO_SIZE);
	kfree(adapter_data);
	kfree(padapter);

	platform_set_drvdata(pdev, NULL);

	return 0;
}

static int 
iop3xx_i2c_probe(struct platform_device *pdev)
{
	struct resource *res;
	int ret, irq;
	struct i2c_adapter *new_adapter;
	struct i2c_algo_iop3xx_data *adapter_data;

	new_adapter = kzalloc(sizeof(struct i2c_adapter), GFP_KERNEL);
	if (!new_adapter) {
		ret = -ENOMEM;
		goto out;
	}

	adapter_data = kzalloc(sizeof(struct i2c_algo_iop3xx_data), GFP_KERNEL);
	if (!adapter_data) {
		ret = -ENOMEM;
		goto free_adapter;
	}

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res) {
		ret = -ENODEV;
		goto free_both;
	}

	if (!request_mem_region(res->start, IOP3XX_I2C_IO_SIZE, pdev->name)) {
		ret = -EBUSY;
		goto free_both;
	}

	/* set the adapter enumeration # */
	adapter_data->id = i2c_id++;

	adapter_data->ioaddr = (u32)ioremap(res->start, IOP3XX_I2C_IO_SIZE);
	if (!adapter_data->ioaddr) {
		ret = -ENOMEM;
		goto release_region;
	}

	irq = platform_get_irq(pdev, 0);
	if (irq < 0) {
		ret = -ENXIO;
		goto unmap;
	}
	ret = request_irq(irq, iop3xx_i2c_irq_handler, 0,
				pdev->name, adapter_data);

	if (ret) {
		ret = -EIO;
		goto unmap;
	}

	memcpy(new_adapter->name, pdev->name, strlen(pdev->name));
	new_adapter->id = I2C_HW_IOP3XX;
	new_adapter->owner = THIS_MODULE;
	new_adapter->dev.parent = &pdev->dev;

	/*
	 * Default values...should these come in from board code?
	 */
	new_adapter->timeout = 100;	
	new_adapter->retries = 3;
	new_adapter->algo = &iop3xx_i2c_algo;

	init_waitqueue_head(&adapter_data->waitq);
	spin_lock_init(&adapter_data->lock);

	iop3xx_i2c_reset(adapter_data);
	iop3xx_i2c_enable(adapter_data);

	platform_set_drvdata(pdev, new_adapter);
	new_adapter->algo_data = adapter_data;

	i2c_add_adapter(new_adapter);

	return 0;

unmap:
	iounmap((void __iomem*)adapter_data->ioaddr);

release_region:
	release_mem_region(res->start, IOP3XX_I2C_IO_SIZE);

free_both:
	kfree(adapter_data);

free_adapter:
	kfree(new_adapter);

out:
	return ret;
}


static struct platform_driver iop3xx_i2c_driver = {
	.probe		= iop3xx_i2c_probe,
	.remove		= iop3xx_i2c_remove,
	.driver		= {
		.owner	= THIS_MODULE,
		.name	= "IOP3xx-I2C",
	},
};

static int __init 
i2c_iop3xx_init (void)
{
	return platform_driver_register(&iop3xx_i2c_driver);
}

static void __exit 
i2c_iop3xx_exit (void)
{
	platform_driver_unregister(&iop3xx_i2c_driver);
	return;
}

module_init (i2c_iop3xx_init);
module_exit (i2c_iop3xx_exit);

MODULE_AUTHOR("D-TACQ Solutions Ltd <www.d-tacq.com>");
MODULE_DESCRIPTION("IOP3xx iic algorithm and driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4 LT	1	/* ------------------------------------------------------------------------- */
	2	/* i2c-iop3xx.c i2c driver algorithms for Intel XScale IOP3xx & IXP46x */
	3	/* ------------------------------------------------------------------------- */
	4	/* Copyright (C) 2003 Peter Milne, D-TACQ Solutions Ltd
	5	* <Peter dot Milne at D hyphen TACQ dot com>
	6	*
	7	* With acknowledgements to i2c-algo-ibm_ocp.c by
	8	* Ian DaSilva, MontaVista Software, Inc. idasilva@mvista.com
	9	*
	10	* And i2c-algo-pcf.c, which was created by Simon G. Vogl and Hans Berglund:
	11	*
	12	* Copyright (C) 1995-1997 Simon G. Vogl, 1998-2000 Hans Berglund
	13	*
fbd9a6d7	14	* And which acknowledged Kyösti Mälkki <kmalkki@cc.hut.fi>,
1da177e4 LT	15	* Frodo Looijaard <frodol@dds.nl>, Martin Bailey<mbailey@littlefeet-inc.com>
	16	*
	17	* Major cleanup by Deepak Saxena <dsaxena@plexity.net>, 01/2005:
	18	*
	19	* - Use driver model to pass per-chip info instead of hardcoding and #ifdefs
	20	* - Use ioremap/__raw_readl/__raw_writel instead of direct dereference
	21	* - Make it work with IXP46x chips
	22	* - Cleanup function names, coding style, etc
	23	*
39288e1a PM	24	* - writing to slave address causes latchup on iop331.
	25	* fix: driver refuses to address self.
	26	*
1da177e4 LT	27	* This program is free software; you can redistribute it and/or modify
	28	* it under the terms of the GNU General Public License as published by
	29	* the Free Software Foundation, version 2.
	30	*/
	31
1da177e4 LT	32	#include <linux/interrupt.h>
	33	#include <linux/kernel.h>
	34	#include <linux/module.h>
	35	#include <linux/delay.h>
	36	#include <linux/slab.h>
	37	#include <linux/init.h>
	38	#include <linux/errno.h>
	39	#include <linux/sched.h>
d052d1be	40	#include <linux/platform_device.h>
1da177e4 LT	41	#include <linux/i2c.h>
	42
	43	#include <asm/io.h>
	44
	45	#include "i2c-iop3xx.h"
	46
	47	/* global unit counter */
60507095	48	static int i2c_id;
1da177e4 LT	49
	50	static inline unsigned char
	51	iic_cook_addr(struct i2c_msg *msg)
	52	{
	53	unsigned char addr;
	54
	55	addr = (msg->addr << 1);
	56
	57	if (msg->flags & I2C_M_RD)
	58	addr \|= 1;
	59
	60	/*
	61	* Read or Write?
	62	*/
	63	if (msg->flags & I2C_M_REV_DIR_ADDR)
	64	addr ^= 1;
	65
	66	return addr;
	67	}
	68
	69	static void
	70	iop3xx_i2c_reset(struct i2c_algo_iop3xx_data *iop3xx_adap)
	71	{
	72	/* Follows devman 9.3 */
	73	__raw_writel(IOP3XX_ICR_UNIT_RESET, iop3xx_adap->ioaddr + CR_OFFSET);
	74	__raw_writel(IOP3XX_ISR_CLEARBITS, iop3xx_adap->ioaddr + SR_OFFSET);
	75	__raw_writel(0, iop3xx_adap->ioaddr + CR_OFFSET);
	76	}
	77
1da177e4 LT	78	static void
	79	iop3xx_i2c_enable(struct i2c_algo_iop3xx_data *iop3xx_adap)
	80	{
	81	u32 cr = IOP3XX_ICR_GCD \| IOP3XX_ICR_SCLEN \| IOP3XX_ICR_UE;
	82
	83	/*
44bbe87e	84	* Every time unit enable is asserted, GPOD needs to be cleared
1da177e4 LT	85	* on IOP321 to avoid data corruption on the bus.
	86	*/
	87	#ifdef CONFIG_ARCH_IOP321
	88	#define IOP321_GPOD_I2C0 0x00c0 /* clear these bits to enable ch0 */
	89	#define IOP321_GPOD_I2C1 0x0030 /* clear these bits to enable ch1 */
	90
	91	*IOP321_GPOD &= (iop3xx_adap->id == 0) ? ~IOP321_GPOD_I2C0 :
	92	~IOP321_GPOD_I2C1;
	93	#endif
	94	/* NB SR bits not same position as CR IE bits :-( */
	95	iop3xx_adap->SR_enabled =
	96	IOP3XX_ISR_ALD \| IOP3XX_ISR_BERRD \|
	97	IOP3XX_ISR_RXFULL \| IOP3XX_ISR_TXEMPTY;
	98
	99	cr \|= IOP3XX_ICR_ALD_IE \| IOP3XX_ICR_BERR_IE \|
	100	IOP3XX_ICR_RXFULL_IE \| IOP3XX_ICR_TXEMPTY_IE;
	101
	102	__raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
	103	}
	104
	105	static void
	106	iop3xx_i2c_transaction_cleanup(struct i2c_algo_iop3xx_data *iop3xx_adap)
	107	{
	108	unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
	109
	110	cr &= ~(IOP3XX_ICR_MSTART \| IOP3XX_ICR_TBYTE \|
	111	IOP3XX_ICR_MSTOP \| IOP3XX_ICR_SCLEN);
	112
	113	__raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
	114	}
	115
	116	/*
	117	* NB: the handler has to clear the source of the interrupt!
	118	* Then it passes the SR flags of interest to BH via adap data
	119	*/
	120	static irqreturn_t
	121	iop3xx_i2c_irq_handler(int this_irq, void dev_id, struct pt_regs regs)
	122	{
	123	struct i2c_algo_iop3xx_data *iop3xx_adap = dev_id;
	124	u32 sr = __raw_readl(iop3xx_adap->ioaddr + SR_OFFSET);
	125
	126	if ((sr &= iop3xx_adap->SR_enabled)) {
	127	__raw_writel(sr, iop3xx_adap->ioaddr + SR_OFFSET);
	128	iop3xx_adap->SR_received \|= sr;
	129	wake_up_interruptible(&iop3xx_adap->waitq);
	130	}
	131	return IRQ_HANDLED;
	132	}
	133
	134	/* check all error conditions, clear them , report most important */
	135	static int
	136	iop3xx_i2c_error(u32 sr)
	137	{
	138	int rc = 0;
	139
	140	if ((sr & IOP3XX_ISR_BERRD)) {
	141	if ( !rc ) rc = -I2C_ERR_BERR;
	142	}
	143	if ((sr & IOP3XX_ISR_ALD)) {
	144	if ( !rc ) rc = -I2C_ERR_ALD;
	145	}
	146	return rc;
	147	}
	148
149	static inline u32
150	iop3xx_i2c_get_srstat(struct i2c_algo_iop3xx_data *iop3xx_adap)
151	{
152	unsigned long flags;
153	u32 sr;
154
155	spin_lock_irqsave(&iop3xx_adap->lock, flags);
156	sr = iop3xx_adap->SR_received;
157	iop3xx_adap->SR_received = 0;
158	spin_unlock_irqrestore(&iop3xx_adap->lock, flags);
159
160	return sr;
161	}
162
163	/*
164	* sleep until interrupted, then recover and analyse the SR
165	* saved by handler
166	*/
167	typedef int (* compare_func)(unsigned test, unsigned mask);
168	/* returns 1 on correct comparison */
169
170	static int
171	iop3xx_i2c_wait_event(struct i2c_algo_iop3xx_data *iop3xx_adap,
172	unsigned flags, unsigned* status,
173	compare_func compare)
174	{
175	unsigned sr = 0;
176	int interrupted;
177	int done;
178	int rc = 0;
179
180	do {
181	interrupted = wait_event_interruptible_timeout (
182	iop3xx_adap->waitq,
fbd9a6d7	183	(done = compare( sr = iop3xx_i2c_get_srstat(iop3xx_adap) ,flags )),
1da177e4 LT	184	1 * HZ;
	185	);
	186	if ((rc = iop3xx_i2c_error(sr)) < 0) {
	187	*status = sr;
	188	return rc;
	189	} else if (!interrupted) {
	190	*status = sr;
	191	return -ETIMEDOUT;
	192	}
	193	} while(!done);
	194
	195	*status = sr;
	196
	197	return 0;
	198	}
	199
	200	/*
	201	* Concrete compare_funcs
	202	*/
	203	static int
	204	all_bits_clear(unsigned test, unsigned mask)
	205	{
	206	return (test & mask) == 0;
	207	}
	208
	209	static int
	210	any_bits_set(unsigned test, unsigned mask)
	211	{
	212	return (test & mask) != 0;
	213	}
	214
	215	static int
	216	iop3xx_i2c_wait_tx_done(struct i2c_algo_iop3xx_data iop3xx_adap, int status)
	217	{
	218	return iop3xx_i2c_wait_event(
	219	iop3xx_adap,
	220	IOP3XX_ISR_TXEMPTY \| IOP3XX_ISR_ALD \| IOP3XX_ISR_BERRD,
	221	status, any_bits_set);
	222	}
	223
	224	static int
	225	iop3xx_i2c_wait_rx_done(struct i2c_algo_iop3xx_data iop3xx_adap, int status)
	226	{
	227	return iop3xx_i2c_wait_event(
	228	iop3xx_adap,
	229	IOP3XX_ISR_RXFULL \| IOP3XX_ISR_ALD \| IOP3XX_ISR_BERRD,
	230	status, any_bits_set);
	231	}
	232
	233	static int
	234	iop3xx_i2c_wait_idle(struct i2c_algo_iop3xx_data iop3xx_adap, int status)
	235	{
	236	return iop3xx_i2c_wait_event(
	237	iop3xx_adap, IOP3XX_ISR_UNITBUSY, status, all_bits_clear);
	238	}
	239
	240	static int
	241	iop3xx_i2c_send_target_addr(struct i2c_algo_iop3xx_data *iop3xx_adap,
	242	struct i2c_msg* msg)
	243	{
	244	unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
	245	int status;
	246	int rc;
	247
39288e1a PM	248	/* avoid writing to my slave address (hangs on 80331),
	249	* forbidden in Intel developer manual
	250	*/
	251	if (msg->addr == MYSAR) {
	252	return -EBUSY;
	253	}
	254
1da177e4 LT	255	__raw_writel(iic_cook_addr(msg), iop3xx_adap->ioaddr + DBR_OFFSET);
	256
	257	cr &= ~(IOP3XX_ICR_MSTOP \| IOP3XX_ICR_NACK);
	258	cr \|= IOP3XX_ICR_MSTART \| IOP3XX_ICR_TBYTE;
	259
	260	__raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
	261	rc = iop3xx_i2c_wait_tx_done(iop3xx_adap, &status);
	262
	263	return rc;
	264	}
	265
	266	static int
	267	iop3xx_i2c_write_byte(struct i2c_algo_iop3xx_data *iop3xx_adap, char byte,
	268	int stop)
	269	{
	270	unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
	271	int status;
	272	int rc = 0;
	273
	274	__raw_writel(byte, iop3xx_adap->ioaddr + DBR_OFFSET);
	275	cr &= ~IOP3XX_ICR_MSTART;
	276	if (stop) {
	277	cr \|= IOP3XX_ICR_MSTOP;
	278	} else {
	279	cr &= ~IOP3XX_ICR_MSTOP;
	280	}
	281	cr \|= IOP3XX_ICR_TBYTE;
	282	__raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
	283	rc = iop3xx_i2c_wait_tx_done(iop3xx_adap, &status);
	284
	285	return rc;
	286	}
	287
	288	static int
	289	iop3xx_i2c_read_byte(struct i2c_algo_iop3xx_data iop3xx_adap, char byte,
	290	int stop)
	291	{
	292	unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
	293	int status;
	294	int rc = 0;
	295
	296	cr &= ~IOP3XX_ICR_MSTART;
	297
	298	if (stop) {
	299	cr \|= IOP3XX_ICR_MSTOP \| IOP3XX_ICR_NACK;
	300	} else {
	301	cr &= ~(IOP3XX_ICR_MSTOP \| IOP3XX_ICR_NACK);
	302	}
	303	cr \|= IOP3XX_ICR_TBYTE;
	304	__raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
	305
	306	rc = iop3xx_i2c_wait_rx_done(iop3xx_adap, &status);
	307
	308	*byte = __raw_readl(iop3xx_adap->ioaddr + DBR_OFFSET);
	309
	310	return rc;
	311	}
	312
	313	static int
	314	iop3xx_i2c_writebytes(struct i2c_adapter i2c_adap, const char buf, int count)
	315	{
	316	struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
	317	int ii;
	318	int rc = 0;
319
320	for (ii = 0; rc == 0 && ii != count; ++ii)
321	rc = iop3xx_i2c_write_byte(iop3xx_adap, buf[ii], ii==count-1);
322	return rc;
323	}
324
325	static int
326	iop3xx_i2c_readbytes(struct i2c_adapter i2c_adap, char buf, int count)
327	{
328	struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
329	int ii;
330	int rc = 0;
331
332	for (ii = 0; rc == 0 && ii != count; ++ii)
333	rc = iop3xx_i2c_read_byte(iop3xx_adap, &buf[ii], ii==count-1);
334
335	return rc;
336	}
337
338	/*
339	* Description: This function implements combined transactions. Combined
340	* transactions consist of combinations of reading and writing blocks of data.
341	* FROM THE SAME ADDRESS
342	* Each transfer (i.e. a read or a write) is separated by a repeated start
343	* condition.
344	*/
345	static int
346	iop3xx_i2c_handle_msg(struct i2c_adapter i2c_adap, struct i2c_msg pmsg)
347	{
348	struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
349	int rc;
350
351	rc = iop3xx_i2c_send_target_addr(iop3xx_adap, pmsg);
352	if (rc < 0) {
353	return rc;
354	}
355
356	if ((pmsg->flags&I2C_M_RD)) {
357	return iop3xx_i2c_readbytes(i2c_adap, pmsg->buf, pmsg->len);
358	} else {
359	return iop3xx_i2c_writebytes(i2c_adap, pmsg->buf, pmsg->len);
360	}
361	}
362
363	/*
364	* master_xfer() - main read/write entry
365	*/
366	static int
367	iop3xx_i2c_master_xfer(struct i2c_adapter i2c_adap, struct i2c_msg msgs,
368	int num)
369	{
370	struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
371	int im = 0;
372	int ret = 0;
373	int status;
374
375	iop3xx_i2c_wait_idle(iop3xx_adap, &status);
376	iop3xx_i2c_reset(iop3xx_adap);
377	iop3xx_i2c_enable(iop3xx_adap);
378
379	for (im = 0; ret == 0 && im != num; im++) {
380	ret = iop3xx_i2c_handle_msg(i2c_adap, &msgs[im]);
381	}
382
383	iop3xx_i2c_transaction_cleanup(iop3xx_adap);
384
385	if(ret)
386	return ret;
387
388	return im;
389	}
390
391	static int
392	iop3xx_i2c_algo_control(struct i2c_adapter *adapter, unsigned int cmd,
393	unsigned long arg)
394	{
395	return 0;
396	}
397
398	static u32
399	iop3xx_i2c_func(struct i2c_adapter *adap)
400	{
401	return I2C_FUNC_I2C \| I2C_FUNC_SMBUS_EMUL;
402	}
403
404	static struct i2c_algorithm iop3xx_i2c_algo = {
1da177e4 LT	405	.master_xfer = iop3xx_i2c_master_xfer,
	406	.algo_control = iop3xx_i2c_algo_control,
	407	.functionality = iop3xx_i2c_func,
	408	};
	409
	410	static int
3ae5eaec	411	iop3xx_i2c_remove(struct platform_device *pdev)
1da177e4	412	{
3ae5eaec	413	struct i2c_adapter *padapter = platform_get_drvdata(pdev);
1da177e4 LT	414	struct i2c_algo_iop3xx_data *adapter_data =
	415	(struct i2c_algo_iop3xx_data *)padapter->algo_data;
	416	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	417	unsigned long cr = __raw_readl(adapter_data->ioaddr + CR_OFFSET);
	418
	419	/*
	420	* Disable the actual HW unit
	421	*/
	422	cr &= ~(IOP3XX_ICR_ALD_IE \| IOP3XX_ICR_BERR_IE \|
	423	IOP3XX_ICR_RXFULL_IE \| IOP3XX_ICR_TXEMPTY_IE);
	424	__raw_writel(cr, adapter_data->ioaddr + CR_OFFSET);
	425
	426	iounmap((void __iomem*)adapter_data->ioaddr);
	427	release_mem_region(res->start, IOP3XX_I2C_IO_SIZE);
	428	kfree(adapter_data);
	429	kfree(padapter);
	430
3ae5eaec	431	platform_set_drvdata(pdev, NULL);
1da177e4 LT	432
	433	return 0;
	434	}
	435
	436	static int
3ae5eaec	437	iop3xx_i2c_probe(struct platform_device *pdev)
1da177e4	438	{
1da177e4	439	struct resource *res;
48944738	440	int ret, irq;
1da177e4 LT	441	struct i2c_adapter *new_adapter;
	442	struct i2c_algo_iop3xx_data *adapter_data;
	443
5263ebb5	444	new_adapter = kzalloc(sizeof(struct i2c_adapter), GFP_KERNEL);
1da177e4 LT	445	if (!new_adapter) {
	446	ret = -ENOMEM;
	447	goto out;
	448	}
1da177e4	449
5263ebb5	450	adapter_data = kzalloc(sizeof(struct i2c_algo_iop3xx_data), GFP_KERNEL);
1da177e4 LT	451	if (!adapter_data) {
	452	ret = -ENOMEM;
	453	goto free_adapter;
	454	}
1da177e4 LT	455
	456	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	457	if (!res) {
	458	ret = -ENODEV;
	459	goto free_both;
	460	}
	461
	462	if (!request_mem_region(res->start, IOP3XX_I2C_IO_SIZE, pdev->name)) {
	463	ret = -EBUSY;
	464	goto free_both;
	465	}
	466
	467	/* set the adapter enumeration # */
	468	adapter_data->id = i2c_id++;
	469
	470	adapter_data->ioaddr = (u32)ioremap(res->start, IOP3XX_I2C_IO_SIZE);
	471	if (!adapter_data->ioaddr) {
	472	ret = -ENOMEM;
	473	goto release_region;
	474	}
	475
48944738 DV	476	irq = platform_get_irq(pdev, 0);
	477	if (irq < 0) {
	478	ret = -ENXIO;
	479	goto unmap;
	480	}
	481	ret = request_irq(irq, iop3xx_i2c_irq_handler, 0,
1da177e4	482	pdev->name, adapter_data);
fbd9a6d7 DW	483
fbd9a6d7 DW	484	if (ret) {
1da177e4 LT	485	ret = -EIO;
	486	goto unmap;
	487	}
	488
	489	memcpy(new_adapter->name, pdev->name, strlen(pdev->name));
	490	new_adapter->id = I2C_HW_IOP3XX;
	491	new_adapter->owner = THIS_MODULE;
	492	new_adapter->dev.parent = &pdev->dev;
	493
	494	/*
	495	* Default values...should these come in from board code?
	496	*/
	497	new_adapter->timeout = 100;
	498	new_adapter->retries = 3;
	499	new_adapter->algo = &iop3xx_i2c_algo;
	500
	501	init_waitqueue_head(&adapter_data->waitq);
	502	spin_lock_init(&adapter_data->lock);
	503
	504	iop3xx_i2c_reset(adapter_data);
1da177e4 LT	505	iop3xx_i2c_enable(adapter_data);
1da177e4 LT	506
3ae5eaec	507	platform_set_drvdata(pdev, new_adapter);
1da177e4 LT	508	new_adapter->algo_data = adapter_data;
	509
	510	i2c_add_adapter(new_adapter);
	511
	512	return 0;
	513
	514	unmap:
	515	iounmap((void __iomem*)adapter_data->ioaddr);
	516
	517	release_region:
	518	release_mem_region(res->start, IOP3XX_I2C_IO_SIZE);
	519
	520	free_both:
	521	kfree(adapter_data);
	522
	523	free_adapter:
	524	kfree(new_adapter);
	525
	526	out:
	527	return ret;
	528	}
	529
	530
3ae5eaec	531	static struct platform_driver iop3xx_i2c_driver = {
1da177e4	532	.probe = iop3xx_i2c_probe,
3ae5eaec RK	533	.remove = iop3xx_i2c_remove,
	534	.driver = {
	535	.owner = THIS_MODULE,
	536	.name = "IOP3xx-I2C",
	537	},
1da177e4 LT	538	};
	539
	540	static int __init
	541	i2c_iop3xx_init (void)
	542	{
3ae5eaec	543	return platform_driver_register(&iop3xx_i2c_driver);
1da177e4 LT	544	}
	545
	546	static void __exit
	547	i2c_iop3xx_exit (void)
	548	{
3ae5eaec	549	platform_driver_unregister(&iop3xx_i2c_driver);
1da177e4 LT	550	return;
	551	}
	552
	553	module_init (i2c_iop3xx_init);
	554	module_exit (i2c_iop3xx_exit);
	555
	556	MODULE_AUTHOR("D-TACQ Solutions Ltd <www.d-tacq.com>");
	557	MODULE_DESCRIPTION("IOP3xx iic algorithm and driver");
	558	MODULE_LICENSE("GPL");