Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * (C) Copyright 2003-2004 | |
3 | * Humboldt Solutions Ltd, adrian@humboldt.co.uk. | |
4 | ||
5 | * This is a combined i2c adapter and algorithm driver for the | |
6 | * MPC107/Tsi107 PowerPC northbridge and processors that include | |
7 | * the same I2C unit (8240, 8245, 85xx). | |
8 | * | |
9 | * Release 0.8 | |
10 | * | |
11 | * This file is licensed under the terms of the GNU General Public | |
12 | * License version 2. This program is licensed "as is" without any | |
13 | * warranty of any kind, whether express or implied. | |
14 | */ | |
15 | ||
1da177e4 LT |
16 | #include <linux/kernel.h> |
17 | #include <linux/module.h> | |
18 | #include <linux/sched.h> | |
5af50730 RH |
19 | #include <linux/of_address.h> |
20 | #include <linux/of_irq.h> | |
0d1cde23 | 21 | #include <linux/of_platform.h> |
5a0e3ad6 | 22 | #include <linux/slab.h> |
d052d1be | 23 | |
b3bfce2b | 24 | #include <linux/clk.h> |
8101a300 | 25 | #include <linux/io.h> |
1da177e4 | 26 | #include <linux/fsl_devices.h> |
1da177e4 LT |
27 | #include <linux/i2c.h> |
28 | #include <linux/interrupt.h> | |
29 | #include <linux/delay.h> | |
30 | ||
f2bd5efe | 31 | #include <asm/mpc52xx.h> |
8ce795cb | 32 | #include <asm/mpc85xx.h> |
f2bd5efe WG |
33 | #include <sysdev/fsl_soc.h> |
34 | ||
0d1cde23 JS |
35 | #define DRV_NAME "mpc-i2c" |
36 | ||
f00d738f WG |
37 | #define MPC_I2C_CLOCK_LEGACY 0 |
38 | #define MPC_I2C_CLOCK_PRESERVE (~0U) | |
39 | ||
8101a300 WG |
40 | #define MPC_I2C_FDR 0x04 |
41 | #define MPC_I2C_CR 0x08 | |
42 | #define MPC_I2C_SR 0x0c | |
43 | #define MPC_I2C_DR 0x10 | |
1da177e4 | 44 | #define MPC_I2C_DFSRR 0x14 |
1da177e4 LT |
45 | |
46 | #define CCR_MEN 0x80 | |
47 | #define CCR_MIEN 0x40 | |
48 | #define CCR_MSTA 0x20 | |
49 | #define CCR_MTX 0x10 | |
50 | #define CCR_TXAK 0x08 | |
51 | #define CCR_RSTA 0x04 | |
52 | ||
53 | #define CSR_MCF 0x80 | |
54 | #define CSR_MAAS 0x40 | |
55 | #define CSR_MBB 0x20 | |
56 | #define CSR_MAL 0x10 | |
57 | #define CSR_SRW 0x04 | |
58 | #define CSR_MIF 0x02 | |
59 | #define CSR_RXAK 0x01 | |
60 | ||
61 | struct mpc_i2c { | |
54377cd0 | 62 | struct device *dev; |
7366d36c | 63 | void __iomem *base; |
1da177e4 LT |
64 | u32 interrupt; |
65 | wait_queue_head_t queue; | |
66 | struct i2c_adapter adap; | |
67 | int irq; | |
0c2daaaf | 68 | u32 real_clk; |
0a488c49 | 69 | #ifdef CONFIG_PM_SLEEP |
531183e5 ZC |
70 | u8 fdr, dfsrr; |
71 | #endif | |
b3bfce2b | 72 | struct clk *clk_per; |
f2bd5efe WG |
73 | }; |
74 | ||
75 | struct mpc_i2c_divider { | |
76 | u16 divider; | |
77 | u16 fdr; /* including dfsrr */ | |
78 | }; | |
79 | ||
6e56dd3d | 80 | struct mpc_i2c_data { |
a9352211 WG |
81 | void (*setup)(struct device_node *node, struct mpc_i2c *i2c, |
82 | u32 clock, u32 prescaler); | |
f2bd5efe | 83 | u32 prescaler; |
1da177e4 LT |
84 | }; |
85 | ||
8101a300 | 86 | static inline void writeccr(struct mpc_i2c *i2c, u32 x) |
1da177e4 LT |
87 | { |
88 | writeb(x, i2c->base + MPC_I2C_CR); | |
89 | } | |
90 | ||
7d12e780 | 91 | static irqreturn_t mpc_i2c_isr(int irq, void *dev_id) |
1da177e4 LT |
92 | { |
93 | struct mpc_i2c *i2c = dev_id; | |
94 | if (readb(i2c->base + MPC_I2C_SR) & CSR_MIF) { | |
95 | /* Read again to allow register to stabilise */ | |
96 | i2c->interrupt = readb(i2c->base + MPC_I2C_SR); | |
97 | writeb(0, i2c->base + MPC_I2C_SR); | |
1ab082d7 | 98 | wake_up(&i2c->queue); |
9c836d0c | 99 | return IRQ_HANDLED; |
1da177e4 | 100 | } |
9c836d0c | 101 | return IRQ_NONE; |
1da177e4 LT |
102 | } |
103 | ||
254db9b5 DP |
104 | /* Sometimes 9th clock pulse isn't generated, and slave doesn't release |
105 | * the bus, because it wants to send ACK. | |
106 | * Following sequence of enabling/disabling and sending start/stop generates | |
0c2daaaf | 107 | * the 9 pulses, so it's all OK. |
254db9b5 DP |
108 | */ |
109 | static void mpc_i2c_fixup(struct mpc_i2c *i2c) | |
110 | { | |
0c2daaaf AD |
111 | int k; |
112 | u32 delay_val = 1000000 / i2c->real_clk + 1; | |
113 | ||
114 | if (delay_val < 2) | |
115 | delay_val = 2; | |
116 | ||
117 | for (k = 9; k; k--) { | |
118 | writeccr(i2c, 0); | |
119 | writeccr(i2c, CCR_MSTA | CCR_MTX | CCR_MEN); | |
d49019a0 | 120 | readb(i2c->base + MPC_I2C_DR); |
0c2daaaf AD |
121 | writeccr(i2c, CCR_MEN); |
122 | udelay(delay_val << 1); | |
123 | } | |
254db9b5 DP |
124 | } |
125 | ||
1da177e4 LT |
126 | static int i2c_wait(struct mpc_i2c *i2c, unsigned timeout, int writing) |
127 | { | |
128 | unsigned long orig_jiffies = jiffies; | |
ab0831d0 | 129 | u32 cmd_err; |
1da177e4 LT |
130 | int result = 0; |
131 | ||
bf727e01 | 132 | if (!i2c->irq) { |
1da177e4 LT |
133 | while (!(readb(i2c->base + MPC_I2C_SR) & CSR_MIF)) { |
134 | schedule(); | |
135 | if (time_after(jiffies, orig_jiffies + timeout)) { | |
54377cd0 | 136 | dev_dbg(i2c->dev, "timeout\n"); |
5af0e07f | 137 | writeccr(i2c, 0); |
ab0831d0 | 138 | result = -ETIMEDOUT; |
1da177e4 LT |
139 | break; |
140 | } | |
141 | } | |
ab0831d0 | 142 | cmd_err = readb(i2c->base + MPC_I2C_SR); |
1da177e4 LT |
143 | writeb(0, i2c->base + MPC_I2C_SR); |
144 | } else { | |
145 | /* Interrupt mode */ | |
1ab082d7 | 146 | result = wait_event_timeout(i2c->queue, |
8a52c6b4 | 147 | (i2c->interrupt & CSR_MIF), timeout); |
1da177e4 | 148 | |
1ab082d7 | 149 | if (unlikely(!(i2c->interrupt & CSR_MIF))) { |
54377cd0 | 150 | dev_dbg(i2c->dev, "wait timeout\n"); |
5af0e07f | 151 | writeccr(i2c, 0); |
1da177e4 LT |
152 | result = -ETIMEDOUT; |
153 | } | |
154 | ||
ab0831d0 | 155 | cmd_err = i2c->interrupt; |
1da177e4 LT |
156 | i2c->interrupt = 0; |
157 | } | |
158 | ||
159 | if (result < 0) | |
160 | return result; | |
161 | ||
ab0831d0 | 162 | if (!(cmd_err & CSR_MCF)) { |
54377cd0 | 163 | dev_dbg(i2c->dev, "unfinished\n"); |
1da177e4 LT |
164 | return -EIO; |
165 | } | |
166 | ||
ab0831d0 | 167 | if (cmd_err & CSR_MAL) { |
54377cd0 | 168 | dev_dbg(i2c->dev, "MAL\n"); |
ab0831d0 | 169 | return -EAGAIN; |
1da177e4 LT |
170 | } |
171 | ||
ab0831d0 | 172 | if (writing && (cmd_err & CSR_RXAK)) { |
54377cd0 | 173 | dev_dbg(i2c->dev, "No RXAK\n"); |
1da177e4 LT |
174 | /* generate stop */ |
175 | writeccr(i2c, CCR_MEN); | |
ab0831d0 | 176 | return -ENXIO; |
1da177e4 LT |
177 | } |
178 | return 0; | |
179 | } | |
180 | ||
f00d738f | 181 | #if defined(CONFIG_PPC_MPC52xx) || defined(CONFIG_PPC_MPC512x) |
0b255e92 | 182 | static const struct mpc_i2c_divider mpc_i2c_dividers_52xx[] = { |
f2bd5efe WG |
183 | {20, 0x20}, {22, 0x21}, {24, 0x22}, {26, 0x23}, |
184 | {28, 0x24}, {30, 0x01}, {32, 0x25}, {34, 0x02}, | |
185 | {36, 0x26}, {40, 0x27}, {44, 0x04}, {48, 0x28}, | |
186 | {52, 0x63}, {56, 0x29}, {60, 0x41}, {64, 0x2a}, | |
187 | {68, 0x07}, {72, 0x2b}, {80, 0x2c}, {88, 0x09}, | |
188 | {96, 0x2d}, {104, 0x0a}, {112, 0x2e}, {120, 0x81}, | |
189 | {128, 0x2f}, {136, 0x47}, {144, 0x0c}, {160, 0x30}, | |
190 | {176, 0x49}, {192, 0x31}, {208, 0x4a}, {224, 0x32}, | |
191 | {240, 0x0f}, {256, 0x33}, {272, 0x87}, {288, 0x10}, | |
192 | {320, 0x34}, {352, 0x89}, {384, 0x35}, {416, 0x8a}, | |
193 | {448, 0x36}, {480, 0x13}, {512, 0x37}, {576, 0x14}, | |
194 | {640, 0x38}, {768, 0x39}, {896, 0x3a}, {960, 0x17}, | |
195 | {1024, 0x3b}, {1152, 0x18}, {1280, 0x3c}, {1536, 0x3d}, | |
196 | {1792, 0x3e}, {1920, 0x1b}, {2048, 0x3f}, {2304, 0x1c}, | |
197 | {2560, 0x1d}, {3072, 0x1e}, {3584, 0x7e}, {3840, 0x1f}, | |
198 | {4096, 0x7f}, {4608, 0x5c}, {5120, 0x5d}, {6144, 0x5e}, | |
199 | {7168, 0xbe}, {7680, 0x5f}, {8192, 0xbf}, {9216, 0x9c}, | |
200 | {10240, 0x9d}, {12288, 0x9e}, {15360, 0x9f} | |
201 | }; | |
202 | ||
0b255e92 | 203 | static int mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock, |
0c2daaaf | 204 | int prescaler, u32 *real_clk) |
f2bd5efe | 205 | { |
1904b034 | 206 | const struct mpc_i2c_divider *div = NULL; |
f2bd5efe WG |
207 | unsigned int pvr = mfspr(SPRN_PVR); |
208 | u32 divider; | |
209 | int i; | |
210 | ||
0c2daaaf AD |
211 | if (clock == MPC_I2C_CLOCK_LEGACY) { |
212 | /* see below - default fdr = 0x3f -> div = 2048 */ | |
213 | *real_clk = mpc5xxx_get_bus_frequency(node) / 2048; | |
f2bd5efe | 214 | return -EINVAL; |
0c2daaaf | 215 | } |
f2bd5efe WG |
216 | |
217 | /* Determine divider value */ | |
87c441e5 | 218 | divider = mpc5xxx_get_bus_frequency(node) / clock; |
f2bd5efe WG |
219 | |
220 | /* | |
221 | * We want to choose an FDR/DFSR that generates an I2C bus speed that | |
222 | * is equal to or lower than the requested speed. | |
223 | */ | |
1904b034 | 224 | for (i = 0; i < ARRAY_SIZE(mpc_i2c_dividers_52xx); i++) { |
f2bd5efe WG |
225 | div = &mpc_i2c_dividers_52xx[i]; |
226 | /* Old MPC5200 rev A CPUs do not support the high bits */ | |
227 | if (div->fdr & 0xc0 && pvr == 0x80822011) | |
228 | continue; | |
229 | if (div->divider >= divider) | |
230 | break; | |
231 | } | |
232 | ||
0c2daaaf AD |
233 | *real_clk = mpc5xxx_get_bus_frequency(node) / div->divider; |
234 | return (int)div->fdr; | |
f2bd5efe WG |
235 | } |
236 | ||
0b255e92 | 237 | static void mpc_i2c_setup_52xx(struct device_node *node, |
a9352211 WG |
238 | struct mpc_i2c *i2c, |
239 | u32 clock, u32 prescaler) | |
f2bd5efe | 240 | { |
1904b034 WG |
241 | int ret, fdr; |
242 | ||
f00d738f WG |
243 | if (clock == MPC_I2C_CLOCK_PRESERVE) { |
244 | dev_dbg(i2c->dev, "using fdr %d\n", | |
245 | readb(i2c->base + MPC_I2C_FDR)); | |
246 | return; | |
247 | } | |
248 | ||
0c2daaaf | 249 | ret = mpc_i2c_get_fdr_52xx(node, clock, prescaler, &i2c->real_clk); |
1904b034 | 250 | fdr = (ret >= 0) ? ret : 0x3f; /* backward compatibility */ |
f2bd5efe | 251 | |
f2bd5efe | 252 | writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR); |
1904b034 WG |
253 | |
254 | if (ret >= 0) | |
0c2daaaf AD |
255 | dev_info(i2c->dev, "clock %u Hz (fdr=%d)\n", i2c->real_clk, |
256 | fdr); | |
f2bd5efe | 257 | } |
f00d738f | 258 | #else /* !(CONFIG_PPC_MPC52xx || CONFIG_PPC_MPC512x) */ |
0b255e92 | 259 | static void mpc_i2c_setup_52xx(struct device_node *node, |
a9352211 WG |
260 | struct mpc_i2c *i2c, |
261 | u32 clock, u32 prescaler) | |
f2bd5efe WG |
262 | { |
263 | } | |
f00d738f WG |
264 | #endif /* CONFIG_PPC_MPC52xx || CONFIG_PPC_MPC512x */ |
265 | ||
266 | #ifdef CONFIG_PPC_MPC512x | |
0b255e92 | 267 | static void mpc_i2c_setup_512x(struct device_node *node, |
f00d738f WG |
268 | struct mpc_i2c *i2c, |
269 | u32 clock, u32 prescaler) | |
270 | { | |
271 | struct device_node *node_ctrl; | |
272 | void __iomem *ctrl; | |
273 | const u32 *pval; | |
274 | u32 idx; | |
275 | ||
276 | /* Enable I2C interrupts for mpc5121 */ | |
277 | node_ctrl = of_find_compatible_node(NULL, NULL, | |
278 | "fsl,mpc5121-i2c-ctrl"); | |
279 | if (node_ctrl) { | |
280 | ctrl = of_iomap(node_ctrl, 0); | |
281 | if (ctrl) { | |
282 | /* Interrupt enable bits for i2c-0/1/2: bit 24/26/28 */ | |
283 | pval = of_get_property(node, "reg", NULL); | |
284 | idx = (*pval & 0xff) / 0x20; | |
285 | setbits32(ctrl, 1 << (24 + idx * 2)); | |
286 | iounmap(ctrl); | |
287 | } | |
288 | of_node_put(node_ctrl); | |
289 | } | |
290 | ||
291 | /* The clock setup for the 52xx works also fine for the 512x */ | |
292 | mpc_i2c_setup_52xx(node, i2c, clock, prescaler); | |
293 | } | |
294 | #else /* CONFIG_PPC_MPC512x */ | |
0b255e92 | 295 | static void mpc_i2c_setup_512x(struct device_node *node, |
f00d738f WG |
296 | struct mpc_i2c *i2c, |
297 | u32 clock, u32 prescaler) | |
298 | { | |
299 | } | |
300 | #endif /* CONFIG_PPC_MPC512x */ | |
f2bd5efe WG |
301 | |
302 | #ifdef CONFIG_FSL_SOC | |
0b255e92 | 303 | static const struct mpc_i2c_divider mpc_i2c_dividers_8xxx[] = { |
f2bd5efe WG |
304 | {160, 0x0120}, {192, 0x0121}, {224, 0x0122}, {256, 0x0123}, |
305 | {288, 0x0100}, {320, 0x0101}, {352, 0x0601}, {384, 0x0102}, | |
306 | {416, 0x0602}, {448, 0x0126}, {480, 0x0103}, {512, 0x0127}, | |
307 | {544, 0x0b03}, {576, 0x0104}, {608, 0x1603}, {640, 0x0105}, | |
308 | {672, 0x2003}, {704, 0x0b05}, {736, 0x2b03}, {768, 0x0106}, | |
309 | {800, 0x3603}, {832, 0x0b06}, {896, 0x012a}, {960, 0x0107}, | |
310 | {1024, 0x012b}, {1088, 0x1607}, {1152, 0x0108}, {1216, 0x2b07}, | |
311 | {1280, 0x0109}, {1408, 0x1609}, {1536, 0x010a}, {1664, 0x160a}, | |
312 | {1792, 0x012e}, {1920, 0x010b}, {2048, 0x012f}, {2176, 0x2b0b}, | |
313 | {2304, 0x010c}, {2560, 0x010d}, {2816, 0x2b0d}, {3072, 0x010e}, | |
314 | {3328, 0x2b0e}, {3584, 0x0132}, {3840, 0x010f}, {4096, 0x0133}, | |
315 | {4608, 0x0110}, {5120, 0x0111}, {6144, 0x0112}, {7168, 0x0136}, | |
316 | {7680, 0x0113}, {8192, 0x0137}, {9216, 0x0114}, {10240, 0x0115}, | |
317 | {12288, 0x0116}, {14336, 0x013a}, {15360, 0x0117}, {16384, 0x013b}, | |
318 | {18432, 0x0118}, {20480, 0x0119}, {24576, 0x011a}, {28672, 0x013e}, | |
319 | {30720, 0x011b}, {32768, 0x013f}, {36864, 0x011c}, {40960, 0x011d}, | |
320 | {49152, 0x011e}, {61440, 0x011f} | |
321 | }; | |
322 | ||
0b255e92 | 323 | static u32 mpc_i2c_get_sec_cfg_8xxx(void) |
f2bd5efe WG |
324 | { |
325 | struct device_node *node = NULL; | |
326 | u32 __iomem *reg; | |
327 | u32 val = 0; | |
328 | ||
329 | node = of_find_node_by_name(NULL, "global-utilities"); | |
330 | if (node) { | |
331 | const u32 *prop = of_get_property(node, "reg", NULL); | |
332 | if (prop) { | |
333 | /* | |
334 | * Map and check POR Device Status Register 2 | |
335 | * (PORDEVSR2) at 0xE0014 | |
336 | */ | |
337 | reg = ioremap(get_immrbase() + *prop + 0x14, 0x4); | |
338 | if (!reg) | |
339 | printk(KERN_ERR | |
340 | "Error: couldn't map PORDEVSR2\n"); | |
341 | else | |
342 | val = in_be32(reg) & 0x00000080; /* sec-cfg */ | |
343 | iounmap(reg); | |
344 | } | |
345 | } | |
ebba48b7 | 346 | of_node_put(node); |
f2bd5efe WG |
347 | |
348 | return val; | |
349 | } | |
350 | ||
8ce795cb VL |
351 | static u32 mpc_i2c_get_prescaler_8xxx(void) |
352 | { | |
353 | /* mpc83xx and mpc82xx all have prescaler 1 */ | |
354 | u32 prescaler = 1; | |
355 | ||
356 | /* mpc85xx */ | |
357 | if (pvr_version_is(PVR_VER_E500V1) || pvr_version_is(PVR_VER_E500V2) | |
358 | || pvr_version_is(PVR_VER_E500MC) | |
359 | || pvr_version_is(PVR_VER_E5500) | |
360 | || pvr_version_is(PVR_VER_E6500)) { | |
361 | unsigned int svr = mfspr(SPRN_SVR); | |
362 | ||
363 | if ((SVR_SOC_VER(svr) == SVR_8540) | |
364 | || (SVR_SOC_VER(svr) == SVR_8541) | |
365 | || (SVR_SOC_VER(svr) == SVR_8560) | |
366 | || (SVR_SOC_VER(svr) == SVR_8555) | |
367 | || (SVR_SOC_VER(svr) == SVR_8610)) | |
368 | /* the above 85xx SoCs have prescaler 1 */ | |
369 | prescaler = 1; | |
370 | else | |
371 | /* all the other 85xx have prescaler 2 */ | |
372 | prescaler = 2; | |
373 | } | |
374 | ||
375 | return prescaler; | |
376 | } | |
377 | ||
0b255e92 | 378 | static int mpc_i2c_get_fdr_8xxx(struct device_node *node, u32 clock, |
0c2daaaf | 379 | u32 prescaler, u32 *real_clk) |
f2bd5efe WG |
380 | { |
381 | const struct mpc_i2c_divider *div = NULL; | |
382 | u32 divider; | |
383 | int i; | |
384 | ||
0c2daaaf AD |
385 | if (clock == MPC_I2C_CLOCK_LEGACY) { |
386 | /* see below - default fdr = 0x1031 -> div = 16 * 3072 */ | |
387 | *real_clk = fsl_get_sys_freq() / prescaler / (16 * 3072); | |
f2bd5efe | 388 | return -EINVAL; |
0c2daaaf | 389 | } |
f2bd5efe WG |
390 | |
391 | /* Determine proper divider value */ | |
392 | if (of_device_is_compatible(node, "fsl,mpc8544-i2c")) | |
393 | prescaler = mpc_i2c_get_sec_cfg_8xxx() ? 3 : 2; | |
394 | if (!prescaler) | |
8ce795cb | 395 | prescaler = mpc_i2c_get_prescaler_8xxx(); |
f2bd5efe WG |
396 | |
397 | divider = fsl_get_sys_freq() / clock / prescaler; | |
398 | ||
399 | pr_debug("I2C: src_clock=%d clock=%d divider=%d\n", | |
400 | fsl_get_sys_freq(), clock, divider); | |
401 | ||
402 | /* | |
403 | * We want to choose an FDR/DFSR that generates an I2C bus speed that | |
404 | * is equal to or lower than the requested speed. | |
405 | */ | |
406 | for (i = 0; i < ARRAY_SIZE(mpc_i2c_dividers_8xxx); i++) { | |
407 | div = &mpc_i2c_dividers_8xxx[i]; | |
408 | if (div->divider >= divider) | |
409 | break; | |
410 | } | |
411 | ||
0c2daaaf | 412 | *real_clk = fsl_get_sys_freq() / prescaler / div->divider; |
f2bd5efe WG |
413 | return div ? (int)div->fdr : -EINVAL; |
414 | } | |
415 | ||
0b255e92 | 416 | static void mpc_i2c_setup_8xxx(struct device_node *node, |
a9352211 WG |
417 | struct mpc_i2c *i2c, |
418 | u32 clock, u32 prescaler) | |
f2bd5efe | 419 | { |
1904b034 WG |
420 | int ret, fdr; |
421 | ||
f00d738f WG |
422 | if (clock == MPC_I2C_CLOCK_PRESERVE) { |
423 | dev_dbg(i2c->dev, "using dfsrr %d, fdr %d\n", | |
424 | readb(i2c->base + MPC_I2C_DFSRR), | |
425 | readb(i2c->base + MPC_I2C_FDR)); | |
426 | return; | |
427 | } | |
428 | ||
0c2daaaf | 429 | ret = mpc_i2c_get_fdr_8xxx(node, clock, prescaler, &i2c->real_clk); |
1904b034 | 430 | fdr = (ret >= 0) ? ret : 0x1031; /* backward compatibility */ |
f2bd5efe | 431 | |
f2bd5efe WG |
432 | writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR); |
433 | writeb((fdr >> 8) & 0xff, i2c->base + MPC_I2C_DFSRR); | |
1904b034 WG |
434 | |
435 | if (ret >= 0) | |
436 | dev_info(i2c->dev, "clock %d Hz (dfsrr=%d fdr=%d)\n", | |
0c2daaaf | 437 | i2c->real_clk, fdr >> 8, fdr & 0xff); |
f2bd5efe WG |
438 | } |
439 | ||
440 | #else /* !CONFIG_FSL_SOC */ | |
0b255e92 | 441 | static void mpc_i2c_setup_8xxx(struct device_node *node, |
a9352211 WG |
442 | struct mpc_i2c *i2c, |
443 | u32 clock, u32 prescaler) | |
1da177e4 | 444 | { |
1da177e4 | 445 | } |
f2bd5efe | 446 | #endif /* CONFIG_FSL_SOC */ |
1da177e4 LT |
447 | |
448 | static void mpc_i2c_start(struct mpc_i2c *i2c) | |
449 | { | |
450 | /* Clear arbitration */ | |
451 | writeb(0, i2c->base + MPC_I2C_SR); | |
452 | /* Start with MEN */ | |
453 | writeccr(i2c, CCR_MEN); | |
454 | } | |
455 | ||
456 | static void mpc_i2c_stop(struct mpc_i2c *i2c) | |
457 | { | |
458 | writeccr(i2c, CCR_MEN); | |
459 | } | |
460 | ||
461 | static int mpc_write(struct mpc_i2c *i2c, int target, | |
8101a300 | 462 | const u8 *data, int length, int restart) |
1da177e4 | 463 | { |
4bd28ebd | 464 | int i, result; |
1da177e4 LT |
465 | unsigned timeout = i2c->adap.timeout; |
466 | u32 flags = restart ? CCR_RSTA : 0; | |
467 | ||
1da177e4 LT |
468 | /* Start as master */ |
469 | writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags); | |
470 | /* Write target byte */ | |
471 | writeb((target << 1), i2c->base + MPC_I2C_DR); | |
472 | ||
4bd28ebd JS |
473 | result = i2c_wait(i2c, timeout, 1); |
474 | if (result < 0) | |
475 | return result; | |
1da177e4 LT |
476 | |
477 | for (i = 0; i < length; i++) { | |
478 | /* Write data byte */ | |
479 | writeb(data[i], i2c->base + MPC_I2C_DR); | |
480 | ||
4bd28ebd JS |
481 | result = i2c_wait(i2c, timeout, 1); |
482 | if (result < 0) | |
483 | return result; | |
1da177e4 LT |
484 | } |
485 | ||
486 | return 0; | |
487 | } | |
488 | ||
489 | static int mpc_read(struct mpc_i2c *i2c, int target, | |
3f0e1e4b | 490 | u8 *data, int length, int restart, bool recv_len) |
1da177e4 LT |
491 | { |
492 | unsigned timeout = i2c->adap.timeout; | |
4bd28ebd | 493 | int i, result; |
1da177e4 LT |
494 | u32 flags = restart ? CCR_RSTA : 0; |
495 | ||
1da177e4 LT |
496 | /* Switch to read - restart */ |
497 | writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags); | |
498 | /* Write target address byte - this time with the read flag set */ | |
499 | writeb((target << 1) | 1, i2c->base + MPC_I2C_DR); | |
500 | ||
4bd28ebd JS |
501 | result = i2c_wait(i2c, timeout, 1); |
502 | if (result < 0) | |
503 | return result; | |
1da177e4 LT |
504 | |
505 | if (length) { | |
3f0e1e4b | 506 | if (length == 1 && !recv_len) |
1da177e4 LT |
507 | writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_TXAK); |
508 | else | |
509 | writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA); | |
510 | /* Dummy read */ | |
511 | readb(i2c->base + MPC_I2C_DR); | |
512 | } | |
513 | ||
514 | for (i = 0; i < length; i++) { | |
3f0e1e4b TY |
515 | u8 byte; |
516 | ||
4bd28ebd JS |
517 | result = i2c_wait(i2c, timeout, 0); |
518 | if (result < 0) | |
519 | return result; | |
1da177e4 | 520 | |
3f0e1e4b TY |
521 | /* |
522 | * For block reads, we have to know the total length (1st byte) | |
523 | * before we can determine if we are done. | |
524 | */ | |
525 | if (i || !recv_len) { | |
526 | /* Generate txack on next to last byte */ | |
527 | if (i == length - 2) | |
528 | writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | |
529 | | CCR_TXAK); | |
530 | /* Do not generate stop on last byte */ | |
531 | if (i == length - 1) | |
532 | writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | |
533 | | CCR_MTX); | |
534 | } | |
535 | ||
536 | byte = readb(i2c->base + MPC_I2C_DR); | |
537 | ||
538 | /* | |
539 | * Adjust length if first received byte is length. | |
540 | * The length is 1 length byte plus actually data length | |
541 | */ | |
542 | if (i == 0 && recv_len) { | |
543 | if (byte == 0 || byte > I2C_SMBUS_BLOCK_MAX) | |
544 | return -EPROTO; | |
545 | length += byte; | |
546 | /* | |
547 | * For block reads, generate txack here if data length | |
548 | * is 1 byte (total length is 2 bytes). | |
549 | */ | |
550 | if (length == 2) | |
551 | writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | |
552 | | CCR_TXAK); | |
553 | } | |
554 | data[i] = byte; | |
1da177e4 LT |
555 | } |
556 | ||
557 | return length; | |
558 | } | |
559 | ||
560 | static int mpc_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) | |
561 | { | |
562 | struct i2c_msg *pmsg; | |
563 | int i; | |
564 | int ret = 0; | |
565 | unsigned long orig_jiffies = jiffies; | |
566 | struct mpc_i2c *i2c = i2c_get_adapdata(adap); | |
567 | ||
568 | mpc_i2c_start(i2c); | |
569 | ||
570 | /* Allow bus up to 1s to become not busy */ | |
571 | while (readb(i2c->base + MPC_I2C_SR) & CSR_MBB) { | |
572 | if (signal_pending(current)) { | |
54377cd0 | 573 | dev_dbg(i2c->dev, "Interrupted\n"); |
5af0e07f | 574 | writeccr(i2c, 0); |
1da177e4 LT |
575 | return -EINTR; |
576 | } | |
577 | if (time_after(jiffies, orig_jiffies + HZ)) { | |
0c2daaaf AD |
578 | u8 status = readb(i2c->base + MPC_I2C_SR); |
579 | ||
54377cd0 | 580 | dev_dbg(i2c->dev, "timeout\n"); |
0c2daaaf AD |
581 | if ((status & (CSR_MCF | CSR_MBB | CSR_RXAK)) != 0) { |
582 | writeb(status & ~CSR_MAL, | |
583 | i2c->base + MPC_I2C_SR); | |
254db9b5 | 584 | mpc_i2c_fixup(i2c); |
0c2daaaf | 585 | } |
1da177e4 LT |
586 | return -EIO; |
587 | } | |
588 | schedule(); | |
589 | } | |
590 | ||
591 | for (i = 0; ret >= 0 && i < num; i++) { | |
592 | pmsg = &msgs[i]; | |
54377cd0 WG |
593 | dev_dbg(i2c->dev, |
594 | "Doing %s %d bytes to 0x%02x - %d of %d messages\n", | |
595 | pmsg->flags & I2C_M_RD ? "read" : "write", | |
596 | pmsg->len, pmsg->addr, i + 1, num); | |
3f0e1e4b TY |
597 | if (pmsg->flags & I2C_M_RD) { |
598 | bool recv_len = pmsg->flags & I2C_M_RECV_LEN; | |
599 | ||
600 | ret = mpc_read(i2c, pmsg->addr, pmsg->buf, pmsg->len, i, | |
601 | recv_len); | |
602 | if (recv_len && ret > 0) | |
603 | pmsg->len = ret; | |
604 | } else { | |
1da177e4 LT |
605 | ret = |
606 | mpc_write(i2c, pmsg->addr, pmsg->buf, pmsg->len, i); | |
3f0e1e4b | 607 | } |
1da177e4 | 608 | } |
0c25aefa JT |
609 | mpc_i2c_stop(i2c); /* Initiate STOP */ |
610 | orig_jiffies = jiffies; | |
611 | /* Wait until STOP is seen, allow up to 1 s */ | |
612 | while (readb(i2c->base + MPC_I2C_SR) & CSR_MBB) { | |
613 | if (time_after(jiffies, orig_jiffies + HZ)) { | |
614 | u8 status = readb(i2c->base + MPC_I2C_SR); | |
615 | ||
616 | dev_dbg(i2c->dev, "timeout\n"); | |
617 | if ((status & (CSR_MCF | CSR_MBB | CSR_RXAK)) != 0) { | |
618 | writeb(status & ~CSR_MAL, | |
619 | i2c->base + MPC_I2C_SR); | |
620 | mpc_i2c_fixup(i2c); | |
621 | } | |
622 | return -EIO; | |
623 | } | |
624 | cond_resched(); | |
625 | } | |
1da177e4 LT |
626 | return (ret < 0) ? ret : num; |
627 | } | |
628 | ||
629 | static u32 mpc_functionality(struct i2c_adapter *adap) | |
630 | { | |
3f0e1e4b TY |
631 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
632 | | I2C_FUNC_SMBUS_READ_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL; | |
1da177e4 LT |
633 | } |
634 | ||
8f9082c5 | 635 | static const struct i2c_algorithm mpc_algo = { |
1da177e4 LT |
636 | .master_xfer = mpc_xfer, |
637 | .functionality = mpc_functionality, | |
638 | }; | |
639 | ||
640 | static struct i2c_adapter mpc_ops = { | |
641 | .owner = THIS_MODULE, | |
1da177e4 | 642 | .algo = &mpc_algo, |
8a52c6b4 | 643 | .timeout = HZ, |
1da177e4 LT |
644 | }; |
645 | ||
b1608d69 | 646 | static const struct of_device_id mpc_i2c_of_match[]; |
0b255e92 | 647 | static int fsl_i2c_probe(struct platform_device *op) |
8c86cb12 | 648 | { |
b1608d69 | 649 | const struct of_device_id *match; |
8c86cb12 | 650 | struct mpc_i2c *i2c; |
f2bd5efe | 651 | const u32 *prop; |
f00d738f | 652 | u32 clock = MPC_I2C_CLOCK_LEGACY; |
f2bd5efe WG |
653 | int result = 0; |
654 | int plen; | |
421476ae | 655 | struct resource res; |
b3bfce2b GS |
656 | struct clk *clk; |
657 | int err; | |
8c86cb12 | 658 | |
b1608d69 GL |
659 | match = of_match_device(mpc_i2c_of_match, &op->dev); |
660 | if (!match) | |
1c48a5c9 GL |
661 | return -EINVAL; |
662 | ||
4bd28ebd JS |
663 | i2c = kzalloc(sizeof(*i2c), GFP_KERNEL); |
664 | if (!i2c) | |
8c86cb12 | 665 | return -ENOMEM; |
8c86cb12 | 666 | |
54377cd0 WG |
667 | i2c->dev = &op->dev; /* for debug and error output */ |
668 | ||
0d1cde23 | 669 | init_waitqueue_head(&i2c->queue); |
8c86cb12 | 670 | |
61c7a080 | 671 | i2c->base = of_iomap(op->dev.of_node, 0); |
8c86cb12 | 672 | if (!i2c->base) { |
54377cd0 | 673 | dev_err(i2c->dev, "failed to map controller\n"); |
8c86cb12 KG |
674 | result = -ENOMEM; |
675 | goto fail_map; | |
676 | } | |
677 | ||
61c7a080 | 678 | i2c->irq = irq_of_parse_and_map(op->dev.of_node, 0); |
bf727e01 | 679 | if (i2c->irq) { /* no i2c->irq implies polling */ |
0d1cde23 JS |
680 | result = request_irq(i2c->irq, mpc_i2c_isr, |
681 | IRQF_SHARED, "i2c-mpc", i2c); | |
682 | if (result < 0) { | |
54377cd0 | 683 | dev_err(i2c->dev, "failed to attach interrupt\n"); |
0d1cde23 | 684 | goto fail_request; |
8c86cb12 | 685 | } |
0d1cde23 | 686 | } |
8101a300 | 687 | |
b3bfce2b GS |
688 | /* |
689 | * enable clock for the I2C peripheral (non fatal), | |
690 | * keep a reference upon successful allocation | |
691 | */ | |
692 | clk = devm_clk_get(&op->dev, NULL); | |
693 | if (!IS_ERR(clk)) { | |
694 | err = clk_prepare_enable(clk); | |
695 | if (err) { | |
696 | dev_err(&op->dev, "failed to enable clock\n"); | |
697 | goto fail_request; | |
698 | } else { | |
699 | i2c->clk_per = clk; | |
700 | } | |
701 | } | |
702 | ||
61c7a080 | 703 | if (of_get_property(op->dev.of_node, "fsl,preserve-clocking", NULL)) { |
f00d738f WG |
704 | clock = MPC_I2C_CLOCK_PRESERVE; |
705 | } else { | |
61c7a080 GL |
706 | prop = of_get_property(op->dev.of_node, "clock-frequency", |
707 | &plen); | |
f2bd5efe WG |
708 | if (prop && plen == sizeof(u32)) |
709 | clock = *prop; | |
f00d738f | 710 | } |
f2bd5efe | 711 | |
b1608d69 | 712 | if (match->data) { |
215e691c | 713 | const struct mpc_i2c_data *data = match->data; |
61c7a080 | 714 | data->setup(op->dev.of_node, i2c, clock, data->prescaler); |
f00d738f WG |
715 | } else { |
716 | /* Backwards compatibility */ | |
61c7a080 GL |
717 | if (of_get_property(op->dev.of_node, "dfsrr", NULL)) |
718 | mpc_i2c_setup_8xxx(op->dev.of_node, i2c, clock, 0); | |
f2bd5efe | 719 | } |
0d1cde23 | 720 | |
0c2daaaf AD |
721 | prop = of_get_property(op->dev.of_node, "fsl,timeout", &plen); |
722 | if (prop && plen == sizeof(u32)) { | |
723 | mpc_ops.timeout = *prop * HZ / 1000000; | |
724 | if (mpc_ops.timeout < 5) | |
725 | mpc_ops.timeout = 5; | |
726 | } | |
727 | dev_info(i2c->dev, "timeout %u us\n", mpc_ops.timeout * 1000000 / HZ); | |
728 | ||
c2c64954 | 729 | platform_set_drvdata(op, i2c); |
8c86cb12 KG |
730 | |
731 | i2c->adap = mpc_ops; | |
421476ae GR |
732 | of_address_to_resource(op->dev.of_node, 0, &res); |
733 | scnprintf(i2c->adap.name, sizeof(i2c->adap.name), | |
734 | "MPC adapter at 0x%llx", (unsigned long long)res.start); | |
8c86cb12 | 735 | i2c_set_adapdata(&i2c->adap, i2c); |
0d1cde23 | 736 | i2c->adap.dev.parent = &op->dev; |
9fd04992 | 737 | i2c->adap.dev.of_node = of_node_get(op->dev.of_node); |
0d1cde23 JS |
738 | |
739 | result = i2c_add_adapter(&i2c->adap); | |
740 | if (result < 0) { | |
54377cd0 | 741 | dev_err(i2c->dev, "failed to add adapter\n"); |
8c86cb12 KG |
742 | goto fail_add; |
743 | } | |
744 | ||
745 | return result; | |
746 | ||
0d1cde23 | 747 | fail_add: |
b3bfce2b GS |
748 | if (i2c->clk_per) |
749 | clk_disable_unprepare(i2c->clk_per); | |
0d1cde23 JS |
750 | free_irq(i2c->irq, i2c); |
751 | fail_request: | |
752 | irq_dispose_mapping(i2c->irq); | |
8101a300 | 753 | iounmap(i2c->base); |
0d1cde23 | 754 | fail_map: |
8c86cb12 KG |
755 | kfree(i2c); |
756 | return result; | |
757 | }; | |
758 | ||
0b255e92 | 759 | static int fsl_i2c_remove(struct platform_device *op) |
8c86cb12 | 760 | { |
c2c64954 | 761 | struct mpc_i2c *i2c = platform_get_drvdata(op); |
8c86cb12 KG |
762 | |
763 | i2c_del_adapter(&i2c->adap); | |
8c86cb12 | 764 | |
b3bfce2b GS |
765 | if (i2c->clk_per) |
766 | clk_disable_unprepare(i2c->clk_per); | |
767 | ||
bf727e01 | 768 | if (i2c->irq) |
8c86cb12 KG |
769 | free_irq(i2c->irq, i2c); |
770 | ||
0d1cde23 | 771 | irq_dispose_mapping(i2c->irq); |
8c86cb12 KG |
772 | iounmap(i2c->base); |
773 | kfree(i2c); | |
774 | return 0; | |
775 | }; | |
776 | ||
0a488c49 | 777 | #ifdef CONFIG_PM_SLEEP |
531183e5 ZC |
778 | static int mpc_i2c_suspend(struct device *dev) |
779 | { | |
780 | struct mpc_i2c *i2c = dev_get_drvdata(dev); | |
781 | ||
782 | i2c->fdr = readb(i2c->base + MPC_I2C_FDR); | |
783 | i2c->dfsrr = readb(i2c->base + MPC_I2C_DFSRR); | |
784 | ||
785 | return 0; | |
786 | } | |
787 | ||
788 | static int mpc_i2c_resume(struct device *dev) | |
789 | { | |
790 | struct mpc_i2c *i2c = dev_get_drvdata(dev); | |
791 | ||
792 | writeb(i2c->fdr, i2c->base + MPC_I2C_FDR); | |
793 | writeb(i2c->dfsrr, i2c->base + MPC_I2C_DFSRR); | |
794 | ||
795 | return 0; | |
796 | } | |
797 | ||
0a488c49 JH |
798 | static SIMPLE_DEV_PM_OPS(mpc_i2c_pm_ops, mpc_i2c_suspend, mpc_i2c_resume); |
799 | #define MPC_I2C_PM_OPS (&mpc_i2c_pm_ops) | |
800 | #else | |
801 | #define MPC_I2C_PM_OPS NULL | |
531183e5 ZC |
802 | #endif |
803 | ||
0b255e92 | 804 | static const struct mpc_i2c_data mpc_i2c_data_512x = { |
f00d738f WG |
805 | .setup = mpc_i2c_setup_512x, |
806 | }; | |
807 | ||
0b255e92 | 808 | static const struct mpc_i2c_data mpc_i2c_data_52xx = { |
a9352211 | 809 | .setup = mpc_i2c_setup_52xx, |
6e56dd3d WG |
810 | }; |
811 | ||
0b255e92 | 812 | static const struct mpc_i2c_data mpc_i2c_data_8313 = { |
a9352211 | 813 | .setup = mpc_i2c_setup_8xxx, |
6e56dd3d WG |
814 | }; |
815 | ||
0b255e92 | 816 | static const struct mpc_i2c_data mpc_i2c_data_8543 = { |
a9352211 | 817 | .setup = mpc_i2c_setup_8xxx, |
6e56dd3d WG |
818 | .prescaler = 2, |
819 | }; | |
820 | ||
0b255e92 | 821 | static const struct mpc_i2c_data mpc_i2c_data_8544 = { |
a9352211 | 822 | .setup = mpc_i2c_setup_8xxx, |
6e56dd3d WG |
823 | .prescaler = 3, |
824 | }; | |
825 | ||
0d1cde23 | 826 | static const struct of_device_id mpc_i2c_of_match[] = { |
6e56dd3d WG |
827 | {.compatible = "mpc5200-i2c", .data = &mpc_i2c_data_52xx, }, |
828 | {.compatible = "fsl,mpc5200b-i2c", .data = &mpc_i2c_data_52xx, }, | |
829 | {.compatible = "fsl,mpc5200-i2c", .data = &mpc_i2c_data_52xx, }, | |
f00d738f | 830 | {.compatible = "fsl,mpc5121-i2c", .data = &mpc_i2c_data_512x, }, |
6e56dd3d WG |
831 | {.compatible = "fsl,mpc8313-i2c", .data = &mpc_i2c_data_8313, }, |
832 | {.compatible = "fsl,mpc8543-i2c", .data = &mpc_i2c_data_8543, }, | |
833 | {.compatible = "fsl,mpc8544-i2c", .data = &mpc_i2c_data_8544, }, | |
f2bd5efe | 834 | /* Backward compatibility */ |
f2bd5efe | 835 | {.compatible = "fsl-i2c", }, |
0d1cde23 JS |
836 | {}, |
837 | }; | |
838 | MODULE_DEVICE_TABLE(of, mpc_i2c_of_match); | |
839 | ||
8c86cb12 | 840 | /* Structure for a device driver */ |
1c48a5c9 | 841 | static struct platform_driver mpc_i2c_driver = { |
0d1cde23 | 842 | .probe = fsl_i2c_probe, |
0b255e92 | 843 | .remove = fsl_i2c_remove, |
4018294b | 844 | .driver = { |
4018294b GL |
845 | .name = DRV_NAME, |
846 | .of_match_table = mpc_i2c_of_match, | |
0a488c49 | 847 | .pm = MPC_I2C_PM_OPS, |
3ae5eaec | 848 | }, |
8c86cb12 KG |
849 | }; |
850 | ||
a3664b51 | 851 | module_platform_driver(mpc_i2c_driver); |
8c86cb12 | 852 | |
1da177e4 | 853 | MODULE_AUTHOR("Adrian Cox <adrian@humboldt.co.uk>"); |
8101a300 | 854 | MODULE_DESCRIPTION("I2C-Bus adapter for MPC107 bridge and " |
f00d738f | 855 | "MPC824x/83xx/85xx/86xx/512x/52xx processors"); |
1da177e4 | 856 | MODULE_LICENSE("GPL"); |