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drivers: clean-up prom.h implicit includes
[deliverable/linux.git] / drivers / i2c / busses / i2c-mpc.c
CommitLineData
1da177e4
LT		 1/*
2 * (C) Copyright 2003-2004
3 * Humboldt Solutions Ltd, adrian@humboldt.co.uk.
4
5 * This is a combined i2c adapter and algorithm driver for the
6 * MPC107/Tsi107 PowerPC northbridge and processors that include
7 * the same I2C unit (8240, 8245, 85xx).
8 *
9 * Release 0.8
10 *
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
14 */
15
1da177e4
LT		 16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/sched.h>
19#include <linux/init.h>
5af50730
RH		 20#include <linux/of_address.h>
21#include <linux/of_irq.h>
0d1cde23 22#include <linux/of_platform.h>
5a0e3ad6 23#include <linux/slab.h>
d052d1be 24
b3bfce2b 25#include <linux/clk.h>
8101a300 26#include <linux/io.h>
1da177e4 27#include <linux/fsl_devices.h>
1da177e4
LT		 28#include <linux/i2c.h>
29#include <linux/interrupt.h>
30#include <linux/delay.h>
31
f2bd5efe
WG		 32#include <asm/mpc52xx.h>
33#include <sysdev/fsl_soc.h>
34
0d1cde23
JS		 35#define DRV_NAME "mpc-i2c"
36
f00d738f
WG		 37#define MPC_I2C_CLOCK_LEGACY 0
38#define MPC_I2C_CLOCK_PRESERVE (~0U)
39
8101a300
WG		 40#define MPC_I2C_FDR 0x04
41#define MPC_I2C_CR 0x08
42#define MPC_I2C_SR 0x0c
43#define MPC_I2C_DR 0x10
1da177e4 44#define MPC_I2C_DFSRR 0x14
1da177e4
LT		 45
46#define CCR_MEN 0x80
47#define CCR_MIEN 0x40
48#define CCR_MSTA 0x20
49#define CCR_MTX 0x10
50#define CCR_TXAK 0x08
51#define CCR_RSTA 0x04
52
53#define CSR_MCF 0x80
54#define CSR_MAAS 0x40
55#define CSR_MBB 0x20
56#define CSR_MAL 0x10
57#define CSR_SRW 0x04
58#define CSR_MIF 0x02
59#define CSR_RXAK 0x01
60
61struct mpc_i2c {
54377cd0 62 struct device *dev;
7366d36c 63 void __iomem *base;
1da177e4
LT		 64 u32 interrupt;
65 wait_queue_head_t queue;
66 struct i2c_adapter adap;
67 int irq;
0c2daaaf 68 u32 real_clk;
0a488c49 69#ifdef CONFIG_PM_SLEEP
531183e5
ZC		 70 u8 fdr, dfsrr;
71#endif
b3bfce2b 72 struct clk *clk_per;
f2bd5efe
WG		 73};
74
75struct mpc_i2c_divider {
76 u16 divider;
77 u16 fdr; /* including dfsrr */
78};
79
6e56dd3d 80struct mpc_i2c_data {
a9352211
WG		 81 void (*setup)(struct device_node *node, struct mpc_i2c *i2c,
82 u32 clock, u32 prescaler);
f2bd5efe 83 u32 prescaler;
1da177e4
LT		 84};
85
8101a300 86static inline void writeccr(struct mpc_i2c *i2c, u32 x)
1da177e4
LT		 87{
88 writeb(x, i2c->base + MPC_I2C_CR);
89}
90
7d12e780 91static irqreturn_t mpc_i2c_isr(int irq, void *dev_id)
1da177e4
LT		 92{
93 struct mpc_i2c *i2c = dev_id;
94 if (readb(i2c->base + MPC_I2C_SR) & CSR_MIF) {
95 /* Read again to allow register to stabilise */
96 i2c->interrupt = readb(i2c->base + MPC_I2C_SR);
97 writeb(0, i2c->base + MPC_I2C_SR);
1ab082d7 98 wake_up(&i2c->queue);
1da177e4
LT		 99 }
100 return IRQ_HANDLED;
101}
102
254db9b5
DP		 103/* Sometimes 9th clock pulse isn't generated, and slave doesn't release
104 * the bus, because it wants to send ACK.
105 * Following sequence of enabling/disabling and sending start/stop generates
0c2daaaf 106 * the 9 pulses, so it's all OK.
254db9b5
DP		 107 */
108static void mpc_i2c_fixup(struct mpc_i2c *i2c)
109{
0c2daaaf
AD		 110 int k;
111 u32 delay_val = 1000000 / i2c->real_clk + 1;
112
113 if (delay_val < 2)
114 delay_val = 2;
115
116 for (k = 9; k; k--) {
117 writeccr(i2c, 0);
118 writeccr(i2c, CCR_MSTA | CCR_MTX | CCR_MEN);
119 udelay(delay_val);
120 writeccr(i2c, CCR_MEN);
121 udelay(delay_val << 1);
122 }
254db9b5
DP		 123}
124
1da177e4
LT		 125static int i2c_wait(struct mpc_i2c *i2c, unsigned timeout, int writing)
126{
127 unsigned long orig_jiffies = jiffies;
128 u32 x;
129 int result = 0;
130
bf727e01 131 if (!i2c->irq) {
1da177e4
LT		 132 while (!(readb(i2c->base + MPC_I2C_SR) & CSR_MIF)) {
133 schedule();
134 if (time_after(jiffies, orig_jiffies + timeout)) {
54377cd0 135 dev_dbg(i2c->dev, "timeout\n");
5af0e07f 136 writeccr(i2c, 0);
1da177e4
LT		 137 result = -EIO;
138 break;
139 }
140 }
141 x = readb(i2c->base + MPC_I2C_SR);
142 writeb(0, i2c->base + MPC_I2C_SR);
143 } else {
144 /* Interrupt mode */
1ab082d7 145 result = wait_event_timeout(i2c->queue,
8a52c6b4 146 (i2c->interrupt & CSR_MIF), timeout);
1da177e4 147
1ab082d7 148 if (unlikely(!(i2c->interrupt & CSR_MIF))) {
54377cd0 149 dev_dbg(i2c->dev, "wait timeout\n");
5af0e07f 150 writeccr(i2c, 0);
1da177e4
LT		 151 result = -ETIMEDOUT;
152 }
153
154 x = i2c->interrupt;
155 i2c->interrupt = 0;
156 }
157
158 if (result < 0)
159 return result;
160
161 if (!(x & CSR_MCF)) {
54377cd0 162 dev_dbg(i2c->dev, "unfinished\n");
1da177e4
LT		 163 return -EIO;
164 }
165
166 if (x & CSR_MAL) {
54377cd0 167 dev_dbg(i2c->dev, "MAL\n");
1da177e4
LT		 168 return -EIO;
169 }
170
171 if (writing && (x & CSR_RXAK)) {
54377cd0 172 dev_dbg(i2c->dev, "No RXAK\n");
1da177e4
LT		 173 /* generate stop */
174 writeccr(i2c, CCR_MEN);
175 return -EIO;
176 }
177 return 0;
178}
179
f00d738f 180#if defined(CONFIG_PPC_MPC52xx) || defined(CONFIG_PPC_MPC512x)
0b255e92 181static const struct mpc_i2c_divider mpc_i2c_dividers_52xx[] = {
f2bd5efe
WG		 182 {20, 0x20}, {22, 0x21}, {24, 0x22}, {26, 0x23},
183 {28, 0x24}, {30, 0x01}, {32, 0x25}, {34, 0x02},
184 {36, 0x26}, {40, 0x27}, {44, 0x04}, {48, 0x28},
185 {52, 0x63}, {56, 0x29}, {60, 0x41}, {64, 0x2a},
186 {68, 0x07}, {72, 0x2b}, {80, 0x2c}, {88, 0x09},
187 {96, 0x2d}, {104, 0x0a}, {112, 0x2e}, {120, 0x81},
188 {128, 0x2f}, {136, 0x47}, {144, 0x0c}, {160, 0x30},
189 {176, 0x49}, {192, 0x31}, {208, 0x4a}, {224, 0x32},
190 {240, 0x0f}, {256, 0x33}, {272, 0x87}, {288, 0x10},
191 {320, 0x34}, {352, 0x89}, {384, 0x35}, {416, 0x8a},
192 {448, 0x36}, {480, 0x13}, {512, 0x37}, {576, 0x14},
193 {640, 0x38}, {768, 0x39}, {896, 0x3a}, {960, 0x17},
194 {1024, 0x3b}, {1152, 0x18}, {1280, 0x3c}, {1536, 0x3d},
195 {1792, 0x3e}, {1920, 0x1b}, {2048, 0x3f}, {2304, 0x1c},
196 {2560, 0x1d}, {3072, 0x1e}, {3584, 0x7e}, {3840, 0x1f},
197 {4096, 0x7f}, {4608, 0x5c}, {5120, 0x5d}, {6144, 0x5e},
198 {7168, 0xbe}, {7680, 0x5f}, {8192, 0xbf}, {9216, 0x9c},
199 {10240, 0x9d}, {12288, 0x9e}, {15360, 0x9f}
200};
201
0b255e92 202static int mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock,
0c2daaaf 203 int prescaler, u32 *real_clk)
f2bd5efe 204{
1904b034 205 const struct mpc_i2c_divider *div = NULL;
f2bd5efe
WG		 206 unsigned int pvr = mfspr(SPRN_PVR);
207 u32 divider;
208 int i;
209
0c2daaaf
AD		 210 if (clock == MPC_I2C_CLOCK_LEGACY) {
211 /* see below - default fdr = 0x3f -> div = 2048 */
212 *real_clk = mpc5xxx_get_bus_frequency(node) / 2048;
f2bd5efe 213 return -EINVAL;
0c2daaaf 214 }
f2bd5efe
WG		 215
216 /* Determine divider value */
87c441e5 217 divider = mpc5xxx_get_bus_frequency(node) / clock;
f2bd5efe
WG		 218
219 /*
220 * We want to choose an FDR/DFSR that generates an I2C bus speed that
221 * is equal to or lower than the requested speed.
222 */
1904b034 223 for (i = 0; i < ARRAY_SIZE(mpc_i2c_dividers_52xx); i++) {
f2bd5efe
WG		 224 div = &mpc_i2c_dividers_52xx[i];
225 /* Old MPC5200 rev A CPUs do not support the high bits */
226 if (div->fdr & 0xc0 && pvr == 0x80822011)
227 continue;
228 if (div->divider >= divider)
229 break;
230 }
231
0c2daaaf
AD		 232 *real_clk = mpc5xxx_get_bus_frequency(node) / div->divider;
233 return (int)div->fdr;
f2bd5efe
WG		 234}
235
0b255e92 236static void mpc_i2c_setup_52xx(struct device_node *node,
a9352211
WG		 237 struct mpc_i2c *i2c,
238 u32 clock, u32 prescaler)
f2bd5efe 239{
1904b034
WG		 240 int ret, fdr;
241
f00d738f
WG		 242 if (clock == MPC_I2C_CLOCK_PRESERVE) {
243 dev_dbg(i2c->dev, "using fdr %d\n",
244 readb(i2c->base + MPC_I2C_FDR));
245 return;
246 }
247
0c2daaaf 248 ret = mpc_i2c_get_fdr_52xx(node, clock, prescaler, &i2c->real_clk);
1904b034 249 fdr = (ret >= 0) ? ret : 0x3f; /* backward compatibility */
f2bd5efe 250
f2bd5efe 251 writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR);
1904b034
WG		 252
253 if (ret >= 0)
0c2daaaf
AD		 254 dev_info(i2c->dev, "clock %u Hz (fdr=%d)\n", i2c->real_clk,
255 fdr);
f2bd5efe 256}
f00d738f 257#else /* !(CONFIG_PPC_MPC52xx || CONFIG_PPC_MPC512x) */
0b255e92 258static void mpc_i2c_setup_52xx(struct device_node *node,
a9352211
WG		 259 struct mpc_i2c *i2c,
260 u32 clock, u32 prescaler)
f2bd5efe
WG		 261{
262}
f00d738f
WG		 263#endif /* CONFIG_PPC_MPC52xx || CONFIG_PPC_MPC512x */
264
265#ifdef CONFIG_PPC_MPC512x
0b255e92 266static void mpc_i2c_setup_512x(struct device_node *node,
f00d738f
WG		 267 struct mpc_i2c *i2c,
268 u32 clock, u32 prescaler)
269{
270 struct device_node *node_ctrl;
271 void __iomem *ctrl;
272 const u32 *pval;
273 u32 idx;
274
275 /* Enable I2C interrupts for mpc5121 */
276 node_ctrl = of_find_compatible_node(NULL, NULL,
277 "fsl,mpc5121-i2c-ctrl");
278 if (node_ctrl) {
279 ctrl = of_iomap(node_ctrl, 0);
280 if (ctrl) {
281 /* Interrupt enable bits for i2c-0/1/2: bit 24/26/28 */
282 pval = of_get_property(node, "reg", NULL);
283 idx = (*pval & 0xff) / 0x20;
284 setbits32(ctrl, 1 << (24 + idx * 2));
285 iounmap(ctrl);
286 }
287 of_node_put(node_ctrl);
288 }
289
290 /* The clock setup for the 52xx works also fine for the 512x */
291 mpc_i2c_setup_52xx(node, i2c, clock, prescaler);
292}
293#else /* CONFIG_PPC_MPC512x */
0b255e92 294static void mpc_i2c_setup_512x(struct device_node *node,
f00d738f
WG		 295 struct mpc_i2c *i2c,
296 u32 clock, u32 prescaler)
297{
298}
299#endif /* CONFIG_PPC_MPC512x */
f2bd5efe
WG		 300
301#ifdef CONFIG_FSL_SOC
0b255e92 302static const struct mpc_i2c_divider mpc_i2c_dividers_8xxx[] = {
f2bd5efe
WG		 303 {160, 0x0120}, {192, 0x0121}, {224, 0x0122}, {256, 0x0123},
304 {288, 0x0100}, {320, 0x0101}, {352, 0x0601}, {384, 0x0102},
305 {416, 0x0602}, {448, 0x0126}, {480, 0x0103}, {512, 0x0127},
306 {544, 0x0b03}, {576, 0x0104}, {608, 0x1603}, {640, 0x0105},
307 {672, 0x2003}, {704, 0x0b05}, {736, 0x2b03}, {768, 0x0106},
308 {800, 0x3603}, {832, 0x0b06}, {896, 0x012a}, {960, 0x0107},
309 {1024, 0x012b}, {1088, 0x1607}, {1152, 0x0108}, {1216, 0x2b07},
310 {1280, 0x0109}, {1408, 0x1609}, {1536, 0x010a}, {1664, 0x160a},
311 {1792, 0x012e}, {1920, 0x010b}, {2048, 0x012f}, {2176, 0x2b0b},
312 {2304, 0x010c}, {2560, 0x010d}, {2816, 0x2b0d}, {3072, 0x010e},
313 {3328, 0x2b0e}, {3584, 0x0132}, {3840, 0x010f}, {4096, 0x0133},
314 {4608, 0x0110}, {5120, 0x0111}, {6144, 0x0112}, {7168, 0x0136},
315 {7680, 0x0113}, {8192, 0x0137}, {9216, 0x0114}, {10240, 0x0115},
316 {12288, 0x0116}, {14336, 0x013a}, {15360, 0x0117}, {16384, 0x013b},
317 {18432, 0x0118}, {20480, 0x0119}, {24576, 0x011a}, {28672, 0x013e},
318 {30720, 0x011b}, {32768, 0x013f}, {36864, 0x011c}, {40960, 0x011d},
319 {49152, 0x011e}, {61440, 0x011f}
320};
321
0b255e92 322static u32 mpc_i2c_get_sec_cfg_8xxx(void)
f2bd5efe
WG		 323{
324 struct device_node *node = NULL;
325 u32 __iomem *reg;
326 u32 val = 0;
327
328 node = of_find_node_by_name(NULL, "global-utilities");
329 if (node) {
330 const u32 *prop = of_get_property(node, "reg", NULL);
331 if (prop) {
332 /*
333 * Map and check POR Device Status Register 2
334 * (PORDEVSR2) at 0xE0014
335 */
336 reg = ioremap(get_immrbase() + *prop + 0x14, 0x4);
337 if (!reg)
338 printk(KERN_ERR
339 "Error: couldn't map PORDEVSR2\n");
340 else
341 val = in_be32(reg) & 0x00000080; /* sec-cfg */
342 iounmap(reg);
343 }
344 }
345 if (node)
346 of_node_put(node);
347
348 return val;
349}
350
0b255e92 351static int mpc_i2c_get_fdr_8xxx(struct device_node *node, u32 clock,
0c2daaaf 352 u32 prescaler, u32 *real_clk)
f2bd5efe
WG		 353{
354 const struct mpc_i2c_divider *div = NULL;
355 u32 divider;
356 int i;
357
0c2daaaf
AD		 358 if (clock == MPC_I2C_CLOCK_LEGACY) {
359 /* see below - default fdr = 0x1031 -> div = 16 * 3072 */
360 *real_clk = fsl_get_sys_freq() / prescaler / (16 * 3072);
f2bd5efe 361 return -EINVAL;
0c2daaaf 362 }
f2bd5efe
WG		 363
364 /* Determine proper divider value */
365 if (of_device_is_compatible(node, "fsl,mpc8544-i2c"))
366 prescaler = mpc_i2c_get_sec_cfg_8xxx() ? 3 : 2;
367 if (!prescaler)
368 prescaler = 1;
369
370 divider = fsl_get_sys_freq() / clock / prescaler;
371
372 pr_debug("I2C: src_clock=%d clock=%d divider=%d\n",
373 fsl_get_sys_freq(), clock, divider);
374
375 /*
376 * We want to choose an FDR/DFSR that generates an I2C bus speed that
377 * is equal to or lower than the requested speed.
378 */
379 for (i = 0; i < ARRAY_SIZE(mpc_i2c_dividers_8xxx); i++) {
380 div = &mpc_i2c_dividers_8xxx[i];
381 if (div->divider >= divider)
382 break;
383 }
384
0c2daaaf 385 *real_clk = fsl_get_sys_freq() / prescaler / div->divider;
f2bd5efe
WG		 386 return div ? (int)div->fdr : -EINVAL;
387}
388
0b255e92 389static void mpc_i2c_setup_8xxx(struct device_node *node,
a9352211
WG		 390 struct mpc_i2c *i2c,
391 u32 clock, u32 prescaler)
f2bd5efe 392{
1904b034
WG		 393 int ret, fdr;
394
f00d738f
WG		 395 if (clock == MPC_I2C_CLOCK_PRESERVE) {
396 dev_dbg(i2c->dev, "using dfsrr %d, fdr %d\n",
397 readb(i2c->base + MPC_I2C_DFSRR),
398 readb(i2c->base + MPC_I2C_FDR));
399 return;
400 }
401
0c2daaaf 402 ret = mpc_i2c_get_fdr_8xxx(node, clock, prescaler, &i2c->real_clk);
1904b034 403 fdr = (ret >= 0) ? ret : 0x1031; /* backward compatibility */
f2bd5efe 404
f2bd5efe
WG		 405 writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR);
406 writeb((fdr >> 8) & 0xff, i2c->base + MPC_I2C_DFSRR);
1904b034
WG		 407
408 if (ret >= 0)
409 dev_info(i2c->dev, "clock %d Hz (dfsrr=%d fdr=%d)\n",
0c2daaaf 410 i2c->real_clk, fdr >> 8, fdr & 0xff);
f2bd5efe
WG		 411}
412
413#else /* !CONFIG_FSL_SOC */
0b255e92 414static void mpc_i2c_setup_8xxx(struct device_node *node,
a9352211
WG		 415 struct mpc_i2c *i2c,
416 u32 clock, u32 prescaler)
1da177e4 417{
1da177e4 418}
f2bd5efe 419#endif /* CONFIG_FSL_SOC */
1da177e4
LT		 420
421static void mpc_i2c_start(struct mpc_i2c *i2c)
422{
423 /* Clear arbitration */
424 writeb(0, i2c->base + MPC_I2C_SR);
425 /* Start with MEN */
426 writeccr(i2c, CCR_MEN);
427}
428
429static void mpc_i2c_stop(struct mpc_i2c *i2c)
430{
431 writeccr(i2c, CCR_MEN);
432}
433
434static int mpc_write(struct mpc_i2c *i2c, int target,
8101a300 435 const u8 *data, int length, int restart)
1da177e4 436{
4bd28ebd 437 int i, result;
1da177e4
LT		 438 unsigned timeout = i2c->adap.timeout;
439 u32 flags = restart ? CCR_RSTA : 0;
440
1da177e4
LT		 441 /* Start as master */
442 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags);
443 /* Write target byte */
444 writeb((target << 1), i2c->base + MPC_I2C_DR);
445
4bd28ebd
JS		 446 result = i2c_wait(i2c, timeout, 1);
447 if (result < 0)
448 return result;
1da177e4
LT		 449
450 for (i = 0; i < length; i++) {
451 /* Write data byte */
452 writeb(data[i], i2c->base + MPC_I2C_DR);
453
4bd28ebd
JS		 454 result = i2c_wait(i2c, timeout, 1);
455 if (result < 0)
456 return result;
1da177e4
LT		 457 }
458
459 return 0;
460}
461
462static int mpc_read(struct mpc_i2c *i2c, int target,
3f0e1e4b 463 u8 *data, int length, int restart, bool recv_len)
1da177e4
LT		 464{
465 unsigned timeout = i2c->adap.timeout;
4bd28ebd 466 int i, result;
1da177e4
LT		 467 u32 flags = restart ? CCR_RSTA : 0;
468
1da177e4
LT		 469 /* Switch to read - restart */
470 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags);
471 /* Write target address byte - this time with the read flag set */
472 writeb((target << 1) | 1, i2c->base + MPC_I2C_DR);
473
4bd28ebd
JS		 474 result = i2c_wait(i2c, timeout, 1);
475 if (result < 0)
476 return result;
1da177e4
LT		 477
478 if (length) {
3f0e1e4b 479 if (length == 1 && !recv_len)
1da177e4
LT		 480 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_TXAK);
481 else
482 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA);
483 /* Dummy read */
484 readb(i2c->base + MPC_I2C_DR);
485 }
486
487 for (i = 0; i < length; i++) {
3f0e1e4b
TY		 488 u8 byte;
489
4bd28ebd
JS		 490 result = i2c_wait(i2c, timeout, 0);
491 if (result < 0)
492 return result;
1da177e4 493
3f0e1e4b
TY		 494 /*
495 * For block reads, we have to know the total length (1st byte)
496 * before we can determine if we are done.
497 */
498 if (i || !recv_len) {
499 /* Generate txack on next to last byte */
500 if (i == length - 2)
501 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA
502 | CCR_TXAK);
503 /* Do not generate stop on last byte */
504 if (i == length - 1)
505 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA
506 | CCR_MTX);
507 }
508
509 byte = readb(i2c->base + MPC_I2C_DR);
510
511 /*
512 * Adjust length if first received byte is length.
513 * The length is 1 length byte plus actually data length
514 */
515 if (i == 0 && recv_len) {
516 if (byte == 0 || byte > I2C_SMBUS_BLOCK_MAX)
517 return -EPROTO;
518 length += byte;
519 /*
520 * For block reads, generate txack here if data length
521 * is 1 byte (total length is 2 bytes).
522 */
523 if (length == 2)
524 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA
525 | CCR_TXAK);
526 }
527 data[i] = byte;
1da177e4
LT		 528 }
529
530 return length;
531}
532
533static int mpc_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
534{
535 struct i2c_msg *pmsg;
536 int i;
537 int ret = 0;
538 unsigned long orig_jiffies = jiffies;
539 struct mpc_i2c *i2c = i2c_get_adapdata(adap);
540
541 mpc_i2c_start(i2c);
542
543 /* Allow bus up to 1s to become not busy */
544 while (readb(i2c->base + MPC_I2C_SR) & CSR_MBB) {
545 if (signal_pending(current)) {
54377cd0 546 dev_dbg(i2c->dev, "Interrupted\n");
5af0e07f 547 writeccr(i2c, 0);
1da177e4
LT		 548 return -EINTR;
549 }
550 if (time_after(jiffies, orig_jiffies + HZ)) {
0c2daaaf
AD		 551 u8 status = readb(i2c->base + MPC_I2C_SR);
552
54377cd0 553 dev_dbg(i2c->dev, "timeout\n");
0c2daaaf
AD		 554 if ((status & (CSR_MCF | CSR_MBB | CSR_RXAK)) != 0) {
555 writeb(status & ~CSR_MAL,
556 i2c->base + MPC_I2C_SR);
254db9b5 557 mpc_i2c_fixup(i2c);
0c2daaaf 558 }
1da177e4
LT		 559 return -EIO;
560 }
561 schedule();
562 }
563
564 for (i = 0; ret >= 0 && i < num; i++) {
565 pmsg = &msgs[i];
54377cd0
WG		 566 dev_dbg(i2c->dev,
567 "Doing %s %d bytes to 0x%02x - %d of %d messages\n",
568 pmsg->flags & I2C_M_RD ? "read" : "write",
569 pmsg->len, pmsg->addr, i + 1, num);
3f0e1e4b
TY		 570 if (pmsg->flags & I2C_M_RD) {
571 bool recv_len = pmsg->flags & I2C_M_RECV_LEN;
572
573 ret = mpc_read(i2c, pmsg->addr, pmsg->buf, pmsg->len, i,
574 recv_len);
575 if (recv_len && ret > 0)
576 pmsg->len = ret;
577 } else {
1da177e4
LT		 578 ret =
579 mpc_write(i2c, pmsg->addr, pmsg->buf, pmsg->len, i);
3f0e1e4b 580 }
1da177e4 581 }
0c25aefa
JT		 582 mpc_i2c_stop(i2c); /* Initiate STOP */
583 orig_jiffies = jiffies;
584 /* Wait until STOP is seen, allow up to 1 s */
585 while (readb(i2c->base + MPC_I2C_SR) & CSR_MBB) {
586 if (time_after(jiffies, orig_jiffies + HZ)) {
587 u8 status = readb(i2c->base + MPC_I2C_SR);
588
589 dev_dbg(i2c->dev, "timeout\n");
590 if ((status & (CSR_MCF | CSR_MBB | CSR_RXAK)) != 0) {
591 writeb(status & ~CSR_MAL,
592 i2c->base + MPC_I2C_SR);
593 mpc_i2c_fixup(i2c);
594 }
595 return -EIO;
596 }
597 cond_resched();
598 }
1da177e4
LT		 599 return (ret < 0) ? ret : num;
600}
601
602static u32 mpc_functionality(struct i2c_adapter *adap)
603{
3f0e1e4b
TY		 604 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL
605 | I2C_FUNC_SMBUS_READ_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL;
1da177e4
LT		 606}
607
8f9082c5 608static const struct i2c_algorithm mpc_algo = {
1da177e4
LT		 609 .master_xfer = mpc_xfer,
610 .functionality = mpc_functionality,
611};
612
613static struct i2c_adapter mpc_ops = {
614 .owner = THIS_MODULE,
1da177e4 615 .algo = &mpc_algo,
8a52c6b4 616 .timeout = HZ,
1da177e4
LT		 617};
618
b1608d69 619static const struct of_device_id mpc_i2c_of_match[];
0b255e92 620static int fsl_i2c_probe(struct platform_device *op)
8c86cb12 621{
b1608d69 622 const struct of_device_id *match;
8c86cb12 623 struct mpc_i2c *i2c;
f2bd5efe 624 const u32 *prop;
f00d738f 625 u32 clock = MPC_I2C_CLOCK_LEGACY;
f2bd5efe
WG		 626 int result = 0;
627 int plen;
421476ae 628 struct resource res;
b3bfce2b
GS		 629 struct clk *clk;
630 int err;
8c86cb12 631
b1608d69
GL		 632 match = of_match_device(mpc_i2c_of_match, &op->dev);
633 if (!match)
1c48a5c9
GL		 634 return -EINVAL;
635
4bd28ebd
JS		 636 i2c = kzalloc(sizeof(*i2c), GFP_KERNEL);
637 if (!i2c)
8c86cb12 638 return -ENOMEM;
8c86cb12 639
54377cd0
WG		 640 i2c->dev = &op->dev; /* for debug and error output */
641
0d1cde23 642 init_waitqueue_head(&i2c->queue);
8c86cb12 643
61c7a080 644 i2c->base = of_iomap(op->dev.of_node, 0);
8c86cb12 645 if (!i2c->base) {
54377cd0 646 dev_err(i2c->dev, "failed to map controller\n");
8c86cb12
KG		 647 result = -ENOMEM;
648 goto fail_map;
649 }
650
61c7a080 651 i2c->irq = irq_of_parse_and_map(op->dev.of_node, 0);
bf727e01 652 if (i2c->irq) { /* no i2c->irq implies polling */
0d1cde23
JS		 653 result = request_irq(i2c->irq, mpc_i2c_isr,
654 IRQF_SHARED, "i2c-mpc", i2c);
655 if (result < 0) {
54377cd0 656 dev_err(i2c->dev, "failed to attach interrupt\n");
0d1cde23 657 goto fail_request;
8c86cb12 658 }
0d1cde23 659 }
8101a300 660
b3bfce2b
GS		 661 /*
662 * enable clock for the I2C peripheral (non fatal),
663 * keep a reference upon successful allocation
664 */
665 clk = devm_clk_get(&op->dev, NULL);
666 if (!IS_ERR(clk)) {
667 err = clk_prepare_enable(clk);
668 if (err) {
669 dev_err(&op->dev, "failed to enable clock\n");
670 goto fail_request;
671 } else {
672 i2c->clk_per = clk;
673 }
674 }
675
61c7a080 676 if (of_get_property(op->dev.of_node, "fsl,preserve-clocking", NULL)) {
f00d738f
WG		 677 clock = MPC_I2C_CLOCK_PRESERVE;
678 } else {
61c7a080
GL		 679 prop = of_get_property(op->dev.of_node, "clock-frequency",
680 &plen);
f2bd5efe
WG		 681 if (prop && plen == sizeof(u32))
682 clock = *prop;
f00d738f 683 }
f2bd5efe 684
b1608d69 685 if (match->data) {
215e691c 686 const struct mpc_i2c_data *data = match->data;
61c7a080 687 data->setup(op->dev.of_node, i2c, clock, data->prescaler);
f00d738f
WG		 688 } else {
689 /* Backwards compatibility */
61c7a080
GL		 690 if (of_get_property(op->dev.of_node, "dfsrr", NULL))
691 mpc_i2c_setup_8xxx(op->dev.of_node, i2c, clock, 0);
f2bd5efe 692 }
0d1cde23 693
0c2daaaf
AD		 694 prop = of_get_property(op->dev.of_node, "fsl,timeout", &plen);
695 if (prop && plen == sizeof(u32)) {
696 mpc_ops.timeout = *prop * HZ / 1000000;
697 if (mpc_ops.timeout < 5)
698 mpc_ops.timeout = 5;
699 }
700 dev_info(i2c->dev, "timeout %u us\n", mpc_ops.timeout * 1000000 / HZ);
701
c2c64954 702 platform_set_drvdata(op, i2c);
8c86cb12
KG		 703
704 i2c->adap = mpc_ops;
421476ae
GR		 705 of_address_to_resource(op->dev.of_node, 0, &res);
706 scnprintf(i2c->adap.name, sizeof(i2c->adap.name),
707 "MPC adapter at 0x%llx", (unsigned long long)res.start);
8c86cb12 708 i2c_set_adapdata(&i2c->adap, i2c);
0d1cde23 709 i2c->adap.dev.parent = &op->dev;
9fd04992 710 i2c->adap.dev.of_node = of_node_get(op->dev.of_node);
0d1cde23
JS		 711
712 result = i2c_add_adapter(&i2c->adap);
713 if (result < 0) {
54377cd0 714 dev_err(i2c->dev, "failed to add adapter\n");
8c86cb12
KG		 715 goto fail_add;
716 }
717
718 return result;
719
0d1cde23 720 fail_add:
b3bfce2b
GS		 721 if (i2c->clk_per)
722 clk_disable_unprepare(i2c->clk_per);
0d1cde23
JS		 723 free_irq(i2c->irq, i2c);
724 fail_request:
725 irq_dispose_mapping(i2c->irq);
8101a300 726 iounmap(i2c->base);
0d1cde23 727 fail_map:
8c86cb12
KG		 728 kfree(i2c);
729 return result;
730};
731
0b255e92 732static int fsl_i2c_remove(struct platform_device *op)
8c86cb12 733{
c2c64954 734 struct mpc_i2c *i2c = platform_get_drvdata(op);
8c86cb12
KG		 735
736 i2c_del_adapter(&i2c->adap);
8c86cb12 737
b3bfce2b
GS		 738 if (i2c->clk_per)
739 clk_disable_unprepare(i2c->clk_per);
740
bf727e01 741 if (i2c->irq)
8c86cb12
KG		 742 free_irq(i2c->irq, i2c);
743
0d1cde23 744 irq_dispose_mapping(i2c->irq);
8c86cb12
KG		 745 iounmap(i2c->base);
746 kfree(i2c);
747 return 0;
748};
749
0a488c49 750#ifdef CONFIG_PM_SLEEP
531183e5
ZC		 751static int mpc_i2c_suspend(struct device *dev)
752{
753 struct mpc_i2c *i2c = dev_get_drvdata(dev);
754
755 i2c->fdr = readb(i2c->base + MPC_I2C_FDR);
756 i2c->dfsrr = readb(i2c->base + MPC_I2C_DFSRR);
757
758 return 0;
759}
760
761static int mpc_i2c_resume(struct device *dev)
762{
763 struct mpc_i2c *i2c = dev_get_drvdata(dev);
764
765 writeb(i2c->fdr, i2c->base + MPC_I2C_FDR);
766 writeb(i2c->dfsrr, i2c->base + MPC_I2C_DFSRR);
767
768 return 0;
769}
770
0a488c49
JH		 771static SIMPLE_DEV_PM_OPS(mpc_i2c_pm_ops, mpc_i2c_suspend, mpc_i2c_resume);
772#define MPC_I2C_PM_OPS (&mpc_i2c_pm_ops)
773#else
774#define MPC_I2C_PM_OPS NULL
531183e5
ZC		 775#endif
776
0b255e92 777static const struct mpc_i2c_data mpc_i2c_data_512x = {
f00d738f
WG		 778 .setup = mpc_i2c_setup_512x,
779};
780
0b255e92 781static const struct mpc_i2c_data mpc_i2c_data_52xx = {
a9352211 782 .setup = mpc_i2c_setup_52xx,
6e56dd3d
WG		 783};
784
0b255e92 785static const struct mpc_i2c_data mpc_i2c_data_8313 = {
a9352211 786 .setup = mpc_i2c_setup_8xxx,
6e56dd3d
WG		 787};
788
0b255e92 789static const struct mpc_i2c_data mpc_i2c_data_8543 = {
a9352211 790 .setup = mpc_i2c_setup_8xxx,
6e56dd3d
WG		 791 .prescaler = 2,
792};
793
0b255e92 794static const struct mpc_i2c_data mpc_i2c_data_8544 = {
a9352211 795 .setup = mpc_i2c_setup_8xxx,
6e56dd3d
WG		 796 .prescaler = 3,
797};
798
0d1cde23 799static const struct of_device_id mpc_i2c_of_match[] = {
6e56dd3d
WG		 800 {.compatible = "mpc5200-i2c", .data = &mpc_i2c_data_52xx, },
801 {.compatible = "fsl,mpc5200b-i2c", .data = &mpc_i2c_data_52xx, },
802 {.compatible = "fsl,mpc5200-i2c", .data = &mpc_i2c_data_52xx, },
f00d738f 803 {.compatible = "fsl,mpc5121-i2c", .data = &mpc_i2c_data_512x, },
6e56dd3d
WG		 804 {.compatible = "fsl,mpc8313-i2c", .data = &mpc_i2c_data_8313, },
805 {.compatible = "fsl,mpc8543-i2c", .data = &mpc_i2c_data_8543, },
806 {.compatible = "fsl,mpc8544-i2c", .data = &mpc_i2c_data_8544, },
f2bd5efe 807 /* Backward compatibility */
f2bd5efe 808 {.compatible = "fsl-i2c", },
0d1cde23
JS		 809 {},
810};
811MODULE_DEVICE_TABLE(of, mpc_i2c_of_match);
812
8c86cb12 813/* Structure for a device driver */
1c48a5c9 814static struct platform_driver mpc_i2c_driver = {
0d1cde23 815 .probe = fsl_i2c_probe,
0b255e92 816 .remove = fsl_i2c_remove,
4018294b
GL		 817 .driver = {
818 .owner = THIS_MODULE,
819 .name = DRV_NAME,
820 .of_match_table = mpc_i2c_of_match,
0a488c49 821 .pm = MPC_I2C_PM_OPS,
3ae5eaec 822 },
8c86cb12
KG		 823};
824
a3664b51 825module_platform_driver(mpc_i2c_driver);
8c86cb12 826
1da177e4 827MODULE_AUTHOR("Adrian Cox <adrian@humboldt.co.uk>");
8101a300 828MODULE_DESCRIPTION("I2C-Bus adapter for MPC107 bridge and "
f00d738f 829 "MPC824x/83xx/85xx/86xx/512x/52xx processors");
1da177e4 830MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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