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Merge tag 'pci-v3.15-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaa...
[deliverable/linux.git] / drivers / i2c / busses / i2c-mv64xxx.c
CommitLineData
1da177e4 1/*
a0832798
TP		 2 * Driver for the i2c controller on the Marvell line of host bridges
3 * (e.g, gt642[46]0, mv643[46]0, mv644[46]0, and Orion SoC family).
1da177e4
LT		 4 *
5 * Author: Mark A. Greer <mgreer@mvista.com>
6 *
7 * 2005 (c) MontaVista, Software, Inc. This file is licensed under
8 * the terms of the GNU General Public License version 2. This program
9 * is licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 */
12#include <linux/kernel.h>
5a0e3ad6 13#include <linux/slab.h>
1da177e4
LT		 14#include <linux/module.h>
15#include <linux/spinlock.h>
16#include <linux/i2c.h>
17#include <linux/interrupt.h>
a0832798 18#include <linux/mv643xx_i2c.h>
d052d1be 19#include <linux/platform_device.h>
21782180 20#include <linux/io.h>
b61d1575 21#include <linux/of.h>
004e8ed7 22#include <linux/of_device.h>
b61d1575 23#include <linux/of_irq.h>
b61d1575
AL		 24#include <linux/clk.h>
25#include <linux/err.h>
c1d15b68 26#include <linux/delay.h>
1da177e4 27
683e69b8
MR		 28#define MV64XXX_I2C_ADDR_ADDR(val) ((val & 0x7f) << 1)
29#define MV64XXX_I2C_BAUD_DIV_N(val) (val & 0x7)
30#define MV64XXX_I2C_BAUD_DIV_M(val) ((val & 0xf) << 3)
31
1da177e4
LT		 32#define MV64XXX_I2C_REG_CONTROL_ACK 0x00000004
33#define MV64XXX_I2C_REG_CONTROL_IFLG 0x00000008
34#define MV64XXX_I2C_REG_CONTROL_STOP 0x00000010
35#define MV64XXX_I2C_REG_CONTROL_START 0x00000020
36#define MV64XXX_I2C_REG_CONTROL_TWSIEN 0x00000040
37#define MV64XXX_I2C_REG_CONTROL_INTEN 0x00000080
38
39/* Ctlr status values */
40#define MV64XXX_I2C_STATUS_BUS_ERR 0x00
41#define MV64XXX_I2C_STATUS_MAST_START 0x08
42#define MV64XXX_I2C_STATUS_MAST_REPEAT_START 0x10
43#define MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK 0x18
44#define MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK 0x20
45#define MV64XXX_I2C_STATUS_MAST_WR_ACK 0x28
46#define MV64XXX_I2C_STATUS_MAST_WR_NO_ACK 0x30
47#define MV64XXX_I2C_STATUS_MAST_LOST_ARB 0x38
48#define MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK 0x40
49#define MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK 0x48
50#define MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK 0x50
51#define MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK 0x58
52#define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK 0xd0
53#define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_NO_ACK 0xd8
54#define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK 0xe0
55#define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_NO_ACK 0xe8
56#define MV64XXX_I2C_STATUS_NO_STATUS 0xf8
57
930ab3d4
GC		 58/* Register defines (I2C bridge) */
59#define MV64XXX_I2C_REG_TX_DATA_LO 0xc0
60#define MV64XXX_I2C_REG_TX_DATA_HI 0xc4
61#define MV64XXX_I2C_REG_RX_DATA_LO 0xc8
62#define MV64XXX_I2C_REG_RX_DATA_HI 0xcc
63#define MV64XXX_I2C_REG_BRIDGE_CONTROL 0xd0
64#define MV64XXX_I2C_REG_BRIDGE_STATUS 0xd4
65#define MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE 0xd8
66#define MV64XXX_I2C_REG_BRIDGE_INTR_MASK 0xdC
67#define MV64XXX_I2C_REG_BRIDGE_TIMING 0xe0
68
69/* Bridge Control values */
70#define MV64XXX_I2C_BRIDGE_CONTROL_WR 0x00000001
71#define MV64XXX_I2C_BRIDGE_CONTROL_RD 0x00000002
72#define MV64XXX_I2C_BRIDGE_CONTROL_ADDR_SHIFT 2
73#define MV64XXX_I2C_BRIDGE_CONTROL_ADDR_EXT 0x00001000
74#define MV64XXX_I2C_BRIDGE_CONTROL_TX_SIZE_SHIFT 13
75#define MV64XXX_I2C_BRIDGE_CONTROL_RX_SIZE_SHIFT 16
76#define MV64XXX_I2C_BRIDGE_CONTROL_ENABLE 0x00080000
77
78/* Bridge Status values */
79#define MV64XXX_I2C_BRIDGE_STATUS_ERROR 0x00000001
80#define MV64XXX_I2C_STATUS_OFFLOAD_ERROR 0xf0000001
81#define MV64XXX_I2C_STATUS_OFFLOAD_OK 0xf0000000
82
83
1da177e4
LT		 84/* Driver states */
85enum {
86 MV64XXX_I2C_STATE_INVALID,
87 MV64XXX_I2C_STATE_IDLE,
88 MV64XXX_I2C_STATE_WAITING_FOR_START_COND,
eda6bee6 89 MV64XXX_I2C_STATE_WAITING_FOR_RESTART,
1da177e4
LT		 90 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK,
91 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK,
92 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK,
93 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA,
1da177e4
LT		 94};
95
96/* Driver actions */
97enum {
98 MV64XXX_I2C_ACTION_INVALID,
99 MV64XXX_I2C_ACTION_CONTINUE,
100 MV64XXX_I2C_ACTION_SEND_START,
eda6bee6 101 MV64XXX_I2C_ACTION_SEND_RESTART,
930ab3d4 102 MV64XXX_I2C_ACTION_OFFLOAD_RESTART,
1da177e4
LT		 103 MV64XXX_I2C_ACTION_SEND_ADDR_1,
104 MV64XXX_I2C_ACTION_SEND_ADDR_2,
105 MV64XXX_I2C_ACTION_SEND_DATA,
106 MV64XXX_I2C_ACTION_RCV_DATA,
107 MV64XXX_I2C_ACTION_RCV_DATA_STOP,
108 MV64XXX_I2C_ACTION_SEND_STOP,
930ab3d4 109 MV64XXX_I2C_ACTION_OFFLOAD_SEND_STOP,
1da177e4
LT		 110};
111
004e8ed7
MR		 112struct mv64xxx_i2c_regs {
113 u8 addr;
114 u8 ext_addr;
115 u8 data;
116 u8 control;
117 u8 status;
118 u8 clock;
119 u8 soft_reset;
120};
121
1da177e4 122struct mv64xxx_i2c_data {
4243fa0b
RK		 123 struct i2c_msg *msgs;
124 int num_msgs;
1da177e4
LT		 125 int irq;
126 u32 state;
127 u32 action;
e91c021c 128 u32 aborting;
1da177e4
LT		 129 u32 cntl_bits;
130 void __iomem *reg_base;
004e8ed7 131 struct mv64xxx_i2c_regs reg_offsets;
1da177e4
LT		 132 u32 addr1;
133 u32 addr2;
134 u32 bytes_left;
135 u32 byte_posn;
eda6bee6 136 u32 send_stop;
1da177e4
LT		 137 u32 block;
138 int rc;
139 u32 freq_m;
140 u32 freq_n;
b61d1575
AL		 141#if defined(CONFIG_HAVE_CLK)
142 struct clk *clk;
143#endif
1da177e4
LT		 144 wait_queue_head_t waitq;
145 spinlock_t lock;
146 struct i2c_msg *msg;
147 struct i2c_adapter adapter;
930ab3d4 148 bool offload_enabled;
c1d15b68
GC		 149/* 5us delay in order to avoid repeated start timing violation */
150 bool errata_delay;
1da177e4
LT		 151};
152
004e8ed7
MR		 153static struct mv64xxx_i2c_regs mv64xxx_i2c_regs_mv64xxx = {
154 .addr = 0x00,
155 .ext_addr = 0x10,
156 .data = 0x04,
157 .control = 0x08,
158 .status = 0x0c,
159 .clock = 0x0c,
160 .soft_reset = 0x1c,
161};
162
3d66ac7d
MR		 163static struct mv64xxx_i2c_regs mv64xxx_i2c_regs_sun4i = {
164 .addr = 0x00,
165 .ext_addr = 0x04,
166 .data = 0x08,
167 .control = 0x0c,
168 .status = 0x10,
169 .clock = 0x14,
170 .soft_reset = 0x18,
171};
172
3420afbc
RK		 173static void
174mv64xxx_i2c_prepare_for_io(struct mv64xxx_i2c_data *drv_data,
175 struct i2c_msg *msg)
176{
177 u32 dir = 0;
178
179 drv_data->msg = msg;
180 drv_data->byte_posn = 0;
181 drv_data->bytes_left = msg->len;
182 drv_data->aborting = 0;
183 drv_data->rc = 0;
184 drv_data->cntl_bits = MV64XXX_I2C_REG_CONTROL_ACK |
185 MV64XXX_I2C_REG_CONTROL_INTEN | MV64XXX_I2C_REG_CONTROL_TWSIEN;
186
187 if (msg->flags & I2C_M_RD)
188 dir = 1;
189
190 if (msg->flags & I2C_M_TEN) {
191 drv_data->addr1 = 0xf0 | (((u32)msg->addr & 0x300) >> 7) | dir;
192 drv_data->addr2 = (u32)msg->addr & 0xff;
193 } else {
683e69b8 194 drv_data->addr1 = MV64XXX_I2C_ADDR_ADDR((u32)msg->addr) | dir;
3420afbc
RK		 195 drv_data->addr2 = 0;
196 }
197}
198
930ab3d4
GC		 199static int mv64xxx_i2c_offload_msg(struct mv64xxx_i2c_data *drv_data)
200{
201 unsigned long data_reg_hi = 0;
202 unsigned long data_reg_lo = 0;
203 unsigned long ctrl_reg;
204 struct i2c_msg *msg = drv_data->msgs;
205
79970db2
WS		 206 if (!drv_data->offload_enabled)
207 return -EOPNOTSUPP;
208
930ab3d4
GC		 209 drv_data->msg = msg;
210 drv_data->byte_posn = 0;
211 drv_data->bytes_left = msg->len;
212 drv_data->aborting = 0;
213 drv_data->rc = 0;
214 /* Only regular transactions can be offloaded */
215 if ((msg->flags & ~(I2C_M_TEN | I2C_M_RD)) != 0)
216 return -EINVAL;
217
218 /* Only 1-8 byte transfers can be offloaded */
219 if (msg->len < 1 || msg->len > 8)
220 return -EINVAL;
221
222 /* Build transaction */
223 ctrl_reg = MV64XXX_I2C_BRIDGE_CONTROL_ENABLE |
224 (msg->addr << MV64XXX_I2C_BRIDGE_CONTROL_ADDR_SHIFT);
225
226 if ((msg->flags & I2C_M_TEN) != 0)
227 ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_ADDR_EXT;
228
229 if ((msg->flags & I2C_M_RD) == 0) {
230 u8 local_buf[8] = { 0 };
231
232 memcpy(local_buf, msg->buf, msg->len);
233 data_reg_lo = cpu_to_le32(*((u32 *)local_buf));
234 data_reg_hi = cpu_to_le32(*((u32 *)(local_buf+4)));
235
236 ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_WR |
237 (msg->len - 1) << MV64XXX_I2C_BRIDGE_CONTROL_TX_SIZE_SHIFT;
238
85b3a935 239 writel(data_reg_lo,
930ab3d4 240 drv_data->reg_base + MV64XXX_I2C_REG_TX_DATA_LO);
85b3a935 241 writel(data_reg_hi,
930ab3d4
GC		 242 drv_data->reg_base + MV64XXX_I2C_REG_TX_DATA_HI);
243
244 } else {
245 ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_RD |
246 (msg->len - 1) << MV64XXX_I2C_BRIDGE_CONTROL_RX_SIZE_SHIFT;
247 }
248
249 /* Execute transaction */
250 writel(ctrl_reg, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL);
251
252 return 0;
253}
254
255static void
256mv64xxx_i2c_update_offload_data(struct mv64xxx_i2c_data *drv_data)
257{
258 struct i2c_msg *msg = drv_data->msg;
259
260 if (msg->flags & I2C_M_RD) {
261 u32 data_reg_lo = readl(drv_data->reg_base +
262 MV64XXX_I2C_REG_RX_DATA_LO);
263 u32 data_reg_hi = readl(drv_data->reg_base +
264 MV64XXX_I2C_REG_RX_DATA_HI);
265 u8 local_buf[8] = { 0 };
266
267 *((u32 *)local_buf) = le32_to_cpu(data_reg_lo);
268 *((u32 *)(local_buf+4)) = le32_to_cpu(data_reg_hi);
269 memcpy(msg->buf, local_buf, msg->len);
270 }
271
272}
1da177e4
LT		 273/*
274 *****************************************************************************
275 *
276 * Finite State Machine & Interrupt Routines
277 *
278 *****************************************************************************
279 */
a07ad1cc
DF		 280
281/* Reset hardware and initialize FSM */
282static void
283mv64xxx_i2c_hw_init(struct mv64xxx_i2c_data *drv_data)
284{
930ab3d4
GC		 285 if (drv_data->offload_enabled) {
286 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL);
287 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_TIMING);
288 writel(0, drv_data->reg_base +
289 MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE);
290 writel(0, drv_data->reg_base +
291 MV64XXX_I2C_REG_BRIDGE_INTR_MASK);
292 }
293
004e8ed7 294 writel(0, drv_data->reg_base + drv_data->reg_offsets.soft_reset);
683e69b8 295 writel(MV64XXX_I2C_BAUD_DIV_M(drv_data->freq_m) | MV64XXX_I2C_BAUD_DIV_N(drv_data->freq_n),
004e8ed7
MR		 296 drv_data->reg_base + drv_data->reg_offsets.clock);
297 writel(0, drv_data->reg_base + drv_data->reg_offsets.addr);
298 writel(0, drv_data->reg_base + drv_data->reg_offsets.ext_addr);
a07ad1cc 299 writel(MV64XXX_I2C_REG_CONTROL_TWSIEN | MV64XXX_I2C_REG_CONTROL_STOP,
004e8ed7 300 drv_data->reg_base + drv_data->reg_offsets.control);
a07ad1cc
DF		 301 drv_data->state = MV64XXX_I2C_STATE_IDLE;
302}
303
1da177e4
LT		 304static void
305mv64xxx_i2c_fsm(struct mv64xxx_i2c_data *drv_data, u32 status)
306{
307 /*
308 * If state is idle, then this is likely the remnants of an old
309 * operation that driver has given up on or the user has killed.
310 * If so, issue the stop condition and go to idle.
311 */
312 if (drv_data->state == MV64XXX_I2C_STATE_IDLE) {
313 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
314 return;
315 }
316
1da177e4
LT		 317 /* The status from the ctlr [mostly] tells us what to do next */
318 switch (status) {
319 /* Start condition interrupt */
320 case MV64XXX_I2C_STATUS_MAST_START: /* 0x08 */
321 case MV64XXX_I2C_STATUS_MAST_REPEAT_START: /* 0x10 */
322 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_1;
323 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK;
324 break;
325
326 /* Performing a write */
327 case MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK: /* 0x18 */
328 if (drv_data->msg->flags & I2C_M_TEN) {
329 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2;
330 drv_data->state =
331 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK;
332 break;
333 }
334 /* FALLTHRU */
335 case MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK: /* 0xd0 */
336 case MV64XXX_I2C_STATUS_MAST_WR_ACK: /* 0x28 */
e91c021c
MG		 337 if ((drv_data->bytes_left == 0)
338 || (drv_data->aborting
339 && (drv_data->byte_posn != 0))) {
4243fa0b 340 if (drv_data->send_stop || drv_data->aborting) {
eda6bee6
RG		 341 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
342 drv_data->state = MV64XXX_I2C_STATE_IDLE;
343 } else {
344 drv_data->action =
345 MV64XXX_I2C_ACTION_SEND_RESTART;
346 drv_data->state =
347 MV64XXX_I2C_STATE_WAITING_FOR_RESTART;
348 }
e91c021c 349 } else {
1da177e4
LT		 350 drv_data->action = MV64XXX_I2C_ACTION_SEND_DATA;
351 drv_data->state =
352 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK;
353 drv_data->bytes_left--;
1da177e4
LT		 354 }
355 break;
356
357 /* Performing a read */
358 case MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK: /* 40 */
359 if (drv_data->msg->flags & I2C_M_TEN) {
360 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2;
361 drv_data->state =
362 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK;
363 break;
364 }
365 /* FALLTHRU */
366 case MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK: /* 0xe0 */
367 if (drv_data->bytes_left == 0) {
368 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
369 drv_data->state = MV64XXX_I2C_STATE_IDLE;
370 break;
371 }
372 /* FALLTHRU */
373 case MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK: /* 0x50 */
374 if (status != MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK)
375 drv_data->action = MV64XXX_I2C_ACTION_CONTINUE;
376 else {
377 drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA;
378 drv_data->bytes_left--;
379 }
380 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA;
381
e91c021c 382 if ((drv_data->bytes_left == 1) || drv_data->aborting)
1da177e4
LT		 383 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_ACK;
384 break;
385
386 case MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK: /* 0x58 */
387 drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA_STOP;
388 drv_data->state = MV64XXX_I2C_STATE_IDLE;
389 break;
390
391 case MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK: /* 0x20 */
392 case MV64XXX_I2C_STATUS_MAST_WR_NO_ACK: /* 30 */
393 case MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK: /* 48 */
394 /* Doesn't seem to be a device at other end */
395 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
396 drv_data->state = MV64XXX_I2C_STATE_IDLE;
6faa3535 397 drv_data->rc = -ENXIO;
1da177e4
LT		 398 break;
399
930ab3d4
GC		 400 case MV64XXX_I2C_STATUS_OFFLOAD_OK:
401 if (drv_data->send_stop || drv_data->aborting) {
402 drv_data->action = MV64XXX_I2C_ACTION_OFFLOAD_SEND_STOP;
403 drv_data->state = MV64XXX_I2C_STATE_IDLE;
404 } else {
405 drv_data->action = MV64XXX_I2C_ACTION_OFFLOAD_RESTART;
406 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_RESTART;
407 }
408 break;
409
1da177e4
LT		 410 default:
411 dev_err(&drv_data->adapter.dev,
412 "mv64xxx_i2c_fsm: Ctlr Error -- state: 0x%x, "
413 "status: 0x%x, addr: 0x%x, flags: 0x%x\n",
414 drv_data->state, status, drv_data->msg->addr,
415 drv_data->msg->flags);
416 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
a07ad1cc 417 mv64xxx_i2c_hw_init(drv_data);
1da177e4
LT		 418 drv_data->rc = -EIO;
419 }
420}
421
422static void
423mv64xxx_i2c_do_action(struct mv64xxx_i2c_data *drv_data)
424{
425 switch(drv_data->action) {
930ab3d4
GC		 426 case MV64XXX_I2C_ACTION_OFFLOAD_RESTART:
427 mv64xxx_i2c_update_offload_data(drv_data);
428 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL);
429 writel(0, drv_data->reg_base +
430 MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE);
431 /* FALLTHRU */
eda6bee6 432 case MV64XXX_I2C_ACTION_SEND_RESTART:
4243fa0b
RK		 433 /* We should only get here if we have further messages */
434 BUG_ON(drv_data->num_msgs == 0);
435
4243fa0b
RK		 436 drv_data->msgs++;
437 drv_data->num_msgs--;
79970db2 438 if (mv64xxx_i2c_offload_msg(drv_data) < 0) {
930ab3d4
GC		 439 drv_data->cntl_bits |= MV64XXX_I2C_REG_CONTROL_START;
440 writel(drv_data->cntl_bits,
441 drv_data->reg_base + drv_data->reg_offsets.control);
4243fa0b 442
930ab3d4
GC		 443 /* Setup for the next message */
444 mv64xxx_i2c_prepare_for_io(drv_data, drv_data->msgs);
445 }
c1d15b68
GC		 446 if (drv_data->errata_delay)
447 udelay(5);
448
4243fa0b
RK		 449 /*
450 * We're never at the start of the message here, and by this
451 * time it's already too late to do any protocol mangling.
452 * Thankfully, do not advertise support for that feature.
453 */
454 drv_data->send_stop = drv_data->num_msgs == 1;
eda6bee6
RG		 455 break;
456
1da177e4
LT		 457 case MV64XXX_I2C_ACTION_CONTINUE:
458 writel(drv_data->cntl_bits,
004e8ed7 459 drv_data->reg_base + drv_data->reg_offsets.control);
1da177e4
LT		 460 break;
461
462 case MV64XXX_I2C_ACTION_SEND_START:
79970db2
WS		 463 /* Can we offload this msg ? */
464 if (mv64xxx_i2c_offload_msg(drv_data) < 0) {
465 /* No, switch to standard path */
466 mv64xxx_i2c_prepare_for_io(drv_data, drv_data->msgs);
467 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_START,
468 drv_data->reg_base + drv_data->reg_offsets.control);
469 }
1da177e4
LT		 470 break;
471
472 case MV64XXX_I2C_ACTION_SEND_ADDR_1:
473 writel(drv_data->addr1,
004e8ed7 474 drv_data->reg_base + drv_data->reg_offsets.data);
1da177e4 475 writel(drv_data->cntl_bits,
004e8ed7 476 drv_data->reg_base + drv_data->reg_offsets.control);
1da177e4
LT		 477 break;
478
479 case MV64XXX_I2C_ACTION_SEND_ADDR_2:
480 writel(drv_data->addr2,
004e8ed7 481 drv_data->reg_base + drv_data->reg_offsets.data);
1da177e4 482 writel(drv_data->cntl_bits,
004e8ed7 483 drv_data->reg_base + drv_data->reg_offsets.control);
1da177e4
LT		 484 break;
485
486 case MV64XXX_I2C_ACTION_SEND_DATA:
487 writel(drv_data->msg->buf[drv_data->byte_posn++],
004e8ed7 488 drv_data->reg_base + drv_data->reg_offsets.data);
1da177e4 489 writel(drv_data->cntl_bits,
004e8ed7 490 drv_data->reg_base + drv_data->reg_offsets.control);
1da177e4
LT		 491 break;
492
493 case MV64XXX_I2C_ACTION_RCV_DATA:
494 drv_data->msg->buf[drv_data->byte_posn++] =
004e8ed7 495 readl(drv_data->reg_base + drv_data->reg_offsets.data);
1da177e4 496 writel(drv_data->cntl_bits,
004e8ed7 497 drv_data->reg_base + drv_data->reg_offsets.control);
1da177e4
LT		 498 break;
499
500 case MV64XXX_I2C_ACTION_RCV_DATA_STOP:
501 drv_data->msg->buf[drv_data->byte_posn++] =
004e8ed7 502 readl(drv_data->reg_base + drv_data->reg_offsets.data);
1da177e4
LT		 503 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN;
504 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP,
004e8ed7 505 drv_data->reg_base + drv_data->reg_offsets.control);
1da177e4 506 drv_data->block = 0;
c1d15b68
GC		 507 if (drv_data->errata_delay)
508 udelay(5);
509
d295a86e 510 wake_up(&drv_data->waitq);
1da177e4
LT		 511 break;
512
513 case MV64XXX_I2C_ACTION_INVALID:
514 default:
515 dev_err(&drv_data->adapter.dev,
516 "mv64xxx_i2c_do_action: Invalid action: %d\n",
517 drv_data->action);
518 drv_data->rc = -EIO;
930ab3d4 519
1da177e4
LT		 520 /* FALLTHRU */
521 case MV64XXX_I2C_ACTION_SEND_STOP:
522 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN;
523 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP,
004e8ed7 524 drv_data->reg_base + drv_data->reg_offsets.control);
1da177e4 525 drv_data->block = 0;
d295a86e 526 wake_up(&drv_data->waitq);
1da177e4 527 break;
930ab3d4
GC		 528
529 case MV64XXX_I2C_ACTION_OFFLOAD_SEND_STOP:
530 mv64xxx_i2c_update_offload_data(drv_data);
531 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL);
532 writel(0, drv_data->reg_base +
533 MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE);
534 drv_data->block = 0;
535 wake_up(&drv_data->waitq);
536 break;
1da177e4
LT		 537 }
538}
539
b0999cc5 540static irqreturn_t
7d12e780 541mv64xxx_i2c_intr(int irq, void *dev_id)
1da177e4
LT		 542{
543 struct mv64xxx_i2c_data *drv_data = dev_id;
544 unsigned long flags;
545 u32 status;
b0999cc5 546 irqreturn_t rc = IRQ_NONE;
1da177e4
LT		 547
548 spin_lock_irqsave(&drv_data->lock, flags);
930ab3d4
GC		 549
550 if (drv_data->offload_enabled) {
551 while (readl(drv_data->reg_base +
552 MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE)) {
553 int reg_status = readl(drv_data->reg_base +
554 MV64XXX_I2C_REG_BRIDGE_STATUS);
555 if (reg_status & MV64XXX_I2C_BRIDGE_STATUS_ERROR)
556 status = MV64XXX_I2C_STATUS_OFFLOAD_ERROR;
557 else
558 status = MV64XXX_I2C_STATUS_OFFLOAD_OK;
559 mv64xxx_i2c_fsm(drv_data, status);
560 mv64xxx_i2c_do_action(drv_data);
561 rc = IRQ_HANDLED;
562 }
563 }
004e8ed7 564 while (readl(drv_data->reg_base + drv_data->reg_offsets.control) &
1da177e4 565 MV64XXX_I2C_REG_CONTROL_IFLG) {
004e8ed7 566 status = readl(drv_data->reg_base + drv_data->reg_offsets.status);
1da177e4
LT		 567 mv64xxx_i2c_fsm(drv_data, status);
568 mv64xxx_i2c_do_action(drv_data);
569 rc = IRQ_HANDLED;
570 }
571 spin_unlock_irqrestore(&drv_data->lock, flags);
572
573 return rc;
574}
575
576/*
577 *****************************************************************************
578 *
579 * I2C Msg Execution Routines
580 *
581 *****************************************************************************
582 */
1da177e4
LT		 583static void
584mv64xxx_i2c_wait_for_completion(struct mv64xxx_i2c_data *drv_data)
585{
586 long time_left;
587 unsigned long flags;
588 char abort = 0;
589
d295a86e 590 time_left = wait_event_timeout(drv_data->waitq,
8a52c6b4 591 !drv_data->block, drv_data->adapter.timeout);
1da177e4
LT		 592
593 spin_lock_irqsave(&drv_data->lock, flags);
594 if (!time_left) { /* Timed out */
595 drv_data->rc = -ETIMEDOUT;
596 abort = 1;
597 } else if (time_left < 0) { /* Interrupted/Error */
598 drv_data->rc = time_left; /* errno value */
599 abort = 1;
600 }
601
602 if (abort && drv_data->block) {
e91c021c 603 drv_data->aborting = 1;
1da177e4
LT		 604 spin_unlock_irqrestore(&drv_data->lock, flags);
605
606 time_left = wait_event_timeout(drv_data->waitq,
8a52c6b4 607 !drv_data->block, drv_data->adapter.timeout);
1da177e4 608
e91c021c 609 if ((time_left <= 0) && drv_data->block) {
1da177e4
LT		 610 drv_data->state = MV64XXX_I2C_STATE_IDLE;
611 dev_err(&drv_data->adapter.dev,
e91c021c
MG		 612 "mv64xxx: I2C bus locked, block: %d, "
613 "time_left: %d\n", drv_data->block,
614 (int)time_left);
a07ad1cc 615 mv64xxx_i2c_hw_init(drv_data);
1da177e4
LT		 616 }
617 } else
618 spin_unlock_irqrestore(&drv_data->lock, flags);
619}
620
621static int
eda6bee6 622mv64xxx_i2c_execute_msg(struct mv64xxx_i2c_data *drv_data, struct i2c_msg *msg,
4243fa0b 623 int is_last)
1da177e4
LT		 624{
625 unsigned long flags;
626
627 spin_lock_irqsave(&drv_data->lock, flags);
1da177e4 628
79970db2
WS		 629 drv_data->action = MV64XXX_I2C_ACTION_SEND_START;
630 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_START_COND;
631
eda6bee6 632 drv_data->send_stop = is_last;
1da177e4
LT		 633 drv_data->block = 1;
634 mv64xxx_i2c_do_action(drv_data);
635 spin_unlock_irqrestore(&drv_data->lock, flags);
636
637 mv64xxx_i2c_wait_for_completion(drv_data);
638 return drv_data->rc;
639}
640
641/*
642 *****************************************************************************
643 *
644 * I2C Core Support Routines (Interface to higher level I2C code)
645 *
646 *****************************************************************************
647 */
648static u32
649mv64xxx_i2c_functionality(struct i2c_adapter *adap)
650{
651 return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SMBUS_EMUL;
652}
653
654static int
655mv64xxx_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
656{
657 struct mv64xxx_i2c_data *drv_data = i2c_get_adapdata(adap);
4243fa0b 658 int rc, ret = num;
1da177e4 659
4243fa0b
RK		 660 BUG_ON(drv_data->msgs != NULL);
661 drv_data->msgs = msgs;
662 drv_data->num_msgs = num;
663
664 rc = mv64xxx_i2c_execute_msg(drv_data, &msgs[0], num == 1);
665 if (rc < 0)
666 ret = rc;
667
668 drv_data->num_msgs = 0;
669 drv_data->msgs = NULL;
1da177e4 670
4243fa0b 671 return ret;
1da177e4
LT		 672}
673
8f9082c5 674static const struct i2c_algorithm mv64xxx_i2c_algo = {
1da177e4
LT		 675 .master_xfer = mv64xxx_i2c_xfer,
676 .functionality = mv64xxx_i2c_functionality,
677};
678
679/*
680 *****************************************************************************
681 *
682 * Driver Interface & Early Init Routines
683 *
684 *****************************************************************************
685 */
004e8ed7 686static const struct of_device_id mv64xxx_i2c_of_match_table[] = {
3d66ac7d 687 { .compatible = "allwinner,sun4i-i2c", .data = &mv64xxx_i2c_regs_sun4i},
004e8ed7 688 { .compatible = "marvell,mv64xxx-i2c", .data = &mv64xxx_i2c_regs_mv64xxx},
930ab3d4 689 { .compatible = "marvell,mv78230-i2c", .data = &mv64xxx_i2c_regs_mv64xxx},
6cf70ae9 690 { .compatible = "marvell,mv78230-a0-i2c", .data = &mv64xxx_i2c_regs_mv64xxx},
004e8ed7
MR		 691 {}
692};
693MODULE_DEVICE_TABLE(of, mv64xxx_i2c_of_match_table);
694
b61d1575 695#ifdef CONFIG_OF
c1a99467 696#ifdef CONFIG_HAVE_CLK
0b255e92 697static int
b61d1575
AL		 698mv64xxx_calc_freq(const int tclk, const int n, const int m)
699{
700 return tclk / (10 * (m + 1) * (2 << n));
701}
702
0b255e92 703static bool
b61d1575
AL		 704mv64xxx_find_baud_factors(const u32 req_freq, const u32 tclk, u32 *best_n,
705 u32 *best_m)
706{
707 int freq, delta, best_delta = INT_MAX;
708 int m, n;
709
710 for (n = 0; n <= 7; n++)
711 for (m = 0; m <= 15; m++) {
712 freq = mv64xxx_calc_freq(tclk, n, m);
713 delta = req_freq - freq;
714 if (delta >= 0 && delta < best_delta) {
715 *best_m = m;
716 *best_n = n;
717 best_delta = delta;
718 }
719 if (best_delta == 0)
720 return true;
721 }
722 if (best_delta == INT_MAX)
723 return false;
724 return true;
725}
c1a99467 726#endif /* CONFIG_HAVE_CLK */
b61d1575 727
0b255e92 728static int
b61d1575 729mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data,
004e8ed7 730 struct device *dev)
b61d1575 731{
b61d1575
AL		 732 /* CLK is mandatory when using DT to describe the i2c bus. We
733 * need to know tclk in order to calculate bus clock
734 * factors.
735 */
736#if !defined(CONFIG_HAVE_CLK)
737 /* Have OF but no CLK */
738 return -ENODEV;
739#else
c1a99467
TR		 740 const struct of_device_id *device;
741 struct device_node *np = dev->of_node;
742 u32 bus_freq, tclk;
743 int rc = 0;
744
b61d1575
AL		 745 if (IS_ERR(drv_data->clk)) {
746 rc = -ENODEV;
747 goto out;
748 }
749 tclk = clk_get_rate(drv_data->clk);
4c730a06
GC		 750
751 rc = of_property_read_u32(np, "clock-frequency", &bus_freq);
752 if (rc)
753 bus_freq = 100000; /* 100kHz by default */
754
b61d1575
AL		 755 if (!mv64xxx_find_baud_factors(bus_freq, tclk,
756 &drv_data->freq_n, &drv_data->freq_m)) {
757 rc = -EINVAL;
758 goto out;
759 }
760 drv_data->irq = irq_of_parse_and_map(np, 0);
761
762 /* Its not yet defined how timeouts will be specified in device tree.
763 * So hard code the value to 1 second.
764 */
765 drv_data->adapter.timeout = HZ;
004e8ed7
MR		 766
767 device = of_match_device(mv64xxx_i2c_of_match_table, dev);
768 if (!device)
769 return -ENODEV;
770
771 memcpy(&drv_data->reg_offsets, device->data, sizeof(drv_data->reg_offsets));
772
930ab3d4
GC		 773 /*
774 * For controllers embedded in new SoCs activate the
c1d15b68 775 * Transaction Generator support and the errata fix.
930ab3d4 776 */
c1d15b68 777 if (of_device_is_compatible(np, "marvell,mv78230-i2c")) {
930ab3d4 778 drv_data->offload_enabled = true;
c1d15b68
GC		 779 drv_data->errata_delay = true;
780 }
930ab3d4 781
6cf70ae9
GC		 782 if (of_device_is_compatible(np, "marvell,mv78230-a0-i2c")) {
783 drv_data->offload_enabled = false;
784 drv_data->errata_delay = true;
785 }
b61d1575
AL		 786out:
787 return rc;
788#endif
789}
790#else /* CONFIG_OF */
0b255e92 791static int
b61d1575 792mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data,
004e8ed7 793 struct device *dev)
b61d1575
AL		 794{
795 return -ENODEV;
796}
797#endif /* CONFIG_OF */
798
0b255e92 799static int
3ae5eaec 800mv64xxx_i2c_probe(struct platform_device *pd)
1da177e4 801{
1da177e4 802 struct mv64xxx_i2c_data *drv_data;
6d4028c6 803 struct mv64xxx_i2c_pdata *pdata = dev_get_platdata(&pd->dev);
16874b07 804 struct resource *r;
1da177e4
LT		 805 int rc;
806
b61d1575 807 if ((!pdata && !pd->dev.of_node))
1da177e4
LT		 808 return -ENODEV;
809
2c911103
RK		 810 drv_data = devm_kzalloc(&pd->dev, sizeof(struct mv64xxx_i2c_data),
811 GFP_KERNEL);
1da177e4
LT		 812 if (!drv_data)
813 return -ENOMEM;
814
16874b07
RK		 815 r = platform_get_resource(pd, IORESOURCE_MEM, 0);
816 drv_data->reg_base = devm_ioremap_resource(&pd->dev, r);
2c911103
RK		 817 if (IS_ERR(drv_data->reg_base))
818 return PTR_ERR(drv_data->reg_base);
1da177e4 819
e91c021c 820 strlcpy(drv_data->adapter.name, MV64XXX_I2C_CTLR_NAME " adapter",
2096b956 821 sizeof(drv_data->adapter.name));
1da177e4
LT		 822
823 init_waitqueue_head(&drv_data->waitq);
824 spin_lock_init(&drv_data->lock);
825
b61d1575
AL		 826#if defined(CONFIG_HAVE_CLK)
827 /* Not all platforms have a clk */
4c5c95f5 828 drv_data->clk = devm_clk_get(&pd->dev, NULL);
b61d1575
AL		 829 if (!IS_ERR(drv_data->clk)) {
830 clk_prepare(drv_data->clk);
831 clk_enable(drv_data->clk);
832 }
833#endif
834 if (pdata) {
835 drv_data->freq_m = pdata->freq_m;
836 drv_data->freq_n = pdata->freq_n;
837 drv_data->irq = platform_get_irq(pd, 0);
838 drv_data->adapter.timeout = msecs_to_jiffies(pdata->timeout);
930ab3d4 839 drv_data->offload_enabled = false;
004e8ed7 840 memcpy(&drv_data->reg_offsets, &mv64xxx_i2c_regs_mv64xxx, sizeof(drv_data->reg_offsets));
b61d1575 841 } else if (pd->dev.of_node) {
004e8ed7 842 rc = mv64xxx_of_config(drv_data, &pd->dev);
b61d1575 843 if (rc)
2c911103 844 goto exit_clk;
b61d1575 845 }
48944738
DV		 846 if (drv_data->irq < 0) {
847 rc = -ENXIO;
2c911103 848 goto exit_clk;
48944738 849 }
b61d1575 850
12a917f6 851 drv_data->adapter.dev.parent = &pd->dev;
1da177e4
LT		 852 drv_data->adapter.algo = &mv64xxx_i2c_algo;
853 drv_data->adapter.owner = THIS_MODULE;
3401b2ff 854 drv_data->adapter.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
65b22ad9 855 drv_data->adapter.nr = pd->id;
b61d1575 856 drv_data->adapter.dev.of_node = pd->dev.of_node;
3ae5eaec 857 platform_set_drvdata(pd, drv_data);
1da177e4
LT		 858 i2c_set_adapdata(&drv_data->adapter, drv_data);
859
3269bb63
MB		 860 mv64xxx_i2c_hw_init(drv_data);
861
0c195afb
RK		 862 rc = request_irq(drv_data->irq, mv64xxx_i2c_intr, 0,
863 MV64XXX_I2C_CTLR_NAME, drv_data);
864 if (rc) {
dfded4ae 865 dev_err(&drv_data->adapter.dev,
0c195afb
RK		 866 "mv64xxx: Can't register intr handler irq%d: %d\n",
867 drv_data->irq, rc);
2c911103 868 goto exit_clk;
65b22ad9 869 } else if ((rc = i2c_add_numbered_adapter(&drv_data->adapter)) != 0) {
dfded4ae
MG		 870 dev_err(&drv_data->adapter.dev,
871 "mv64xxx: Can't add i2c adapter, rc: %d\n", -rc);
1da177e4
LT		 872 goto exit_free_irq;
873 }
874
1da177e4
LT		 875 return 0;
876
2c911103
RK		 877exit_free_irq:
878 free_irq(drv_data->irq, drv_data);
879exit_clk:
b61d1575
AL		 880#if defined(CONFIG_HAVE_CLK)
881 /* Not all platforms have a clk */
882 if (!IS_ERR(drv_data->clk)) {
883 clk_disable(drv_data->clk);
884 clk_unprepare(drv_data->clk);
885 }
886#endif
1da177e4
LT		 887 return rc;
888}
889
0b255e92 890static int
3ae5eaec 891mv64xxx_i2c_remove(struct platform_device *dev)
1da177e4 892{
3ae5eaec 893 struct mv64xxx_i2c_data *drv_data = platform_get_drvdata(dev);
1da177e4 894
bf51a8c5 895 i2c_del_adapter(&drv_data->adapter);
1da177e4 896 free_irq(drv_data->irq, drv_data);
b61d1575
AL		 897#if defined(CONFIG_HAVE_CLK)
898 /* Not all platforms have a clk */
899 if (!IS_ERR(drv_data->clk)) {
900 clk_disable(drv_data->clk);
901 clk_unprepare(drv_data->clk);
902 }
903#endif
1da177e4 904
bf51a8c5 905 return 0;
1da177e4
LT		 906}
907
3ae5eaec 908static struct platform_driver mv64xxx_i2c_driver = {
1da177e4 909 .probe = mv64xxx_i2c_probe,
0b255e92 910 .remove = mv64xxx_i2c_remove,
3ae5eaec
RK		 911 .driver = {
912 .owner = THIS_MODULE,
913 .name = MV64XXX_I2C_CTLR_NAME,
4e905323 914 .of_match_table = mv64xxx_i2c_of_match_table,
3ae5eaec 915 },
1da177e4
LT		 916};
917
a3664b51 918module_platform_driver(mv64xxx_i2c_driver);
1da177e4
LT		 919
920MODULE_AUTHOR("Mark A. Greer <mgreer@mvista.com>");
921MODULE_DESCRIPTION("Marvell mv64xxx host bridge i2c ctlr driver");
922MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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