[deliverable/linux.git] / drivers / i2c / busses / i2c-mv64xxx.c

/*
 * Driver for the i2c controller on the Marvell line of host bridges for MIPS
 * and PPC (e.g, gt642[46]0, mv643[46]0, mv644[46]0).
 *
 * Author: Mark A. Greer <mgreer@mvista.com>
 *
 * 2005 (c) MontaVista, Software, Inc.  This file is licensed under
 * the terms of the GNU General Public License version 2.  This program
 * is licensed "as is" without any warranty of any kind, whether express
 * or implied.
 */
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/spinlock.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/mv643xx.h>
#include <linux/platform_device.h>

#include <asm/io.h>

/* Register defines */
#define	MV64XXX_I2C_REG_SLAVE_ADDR			0x00
#define	MV64XXX_I2C_REG_DATA				0x04
#define	MV64XXX_I2C_REG_CONTROL				0x08
#define	MV64XXX_I2C_REG_STATUS				0x0c
#define	MV64XXX_I2C_REG_BAUD				0x0c
#define	MV64XXX_I2C_REG_EXT_SLAVE_ADDR			0x10
#define	MV64XXX_I2C_REG_SOFT_RESET			0x1c

#define	MV64XXX_I2C_REG_CONTROL_ACK			0x00000004
#define	MV64XXX_I2C_REG_CONTROL_IFLG			0x00000008
#define	MV64XXX_I2C_REG_CONTROL_STOP			0x00000010
#define	MV64XXX_I2C_REG_CONTROL_START			0x00000020
#define	MV64XXX_I2C_REG_CONTROL_TWSIEN			0x00000040
#define	MV64XXX_I2C_REG_CONTROL_INTEN			0x00000080

/* Ctlr status values */
#define	MV64XXX_I2C_STATUS_BUS_ERR			0x00
#define	MV64XXX_I2C_STATUS_MAST_START			0x08
#define	MV64XXX_I2C_STATUS_MAST_REPEAT_START		0x10
#define	MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK		0x18
#define	MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK		0x20
#define	MV64XXX_I2C_STATUS_MAST_WR_ACK			0x28
#define	MV64XXX_I2C_STATUS_MAST_WR_NO_ACK		0x30
#define	MV64XXX_I2C_STATUS_MAST_LOST_ARB		0x38
#define	MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK		0x40
#define	MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK		0x48
#define	MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK		0x50
#define	MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK		0x58
#define	MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK		0xd0
#define	MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_NO_ACK	0xd8
#define	MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK		0xe0
#define	MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_NO_ACK	0xe8
#define	MV64XXX_I2C_STATUS_NO_STATUS			0xf8

/* Driver states */
enum {
	MV64XXX_I2C_STATE_INVALID,
	MV64XXX_I2C_STATE_IDLE,
	MV64XXX_I2C_STATE_WAITING_FOR_START_COND,
	MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK,
	MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK,
	MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK,
	MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA,
};

/* Driver actions */
enum {
	MV64XXX_I2C_ACTION_INVALID,
	MV64XXX_I2C_ACTION_CONTINUE,
	MV64XXX_I2C_ACTION_SEND_START,
	MV64XXX_I2C_ACTION_SEND_ADDR_1,
	MV64XXX_I2C_ACTION_SEND_ADDR_2,
	MV64XXX_I2C_ACTION_SEND_DATA,
	MV64XXX_I2C_ACTION_RCV_DATA,
	MV64XXX_I2C_ACTION_RCV_DATA_STOP,
	MV64XXX_I2C_ACTION_SEND_STOP,
};

struct mv64xxx_i2c_data {
	int			irq;
	u32			state;
	u32			action;
	u32			aborting;
	u32			cntl_bits;
	void __iomem		*reg_base;
	u32			reg_base_p;
	u32			addr1;
	u32			addr2;
	u32			bytes_left;
	u32			byte_posn;
	u32			block;
	int			rc;
	u32			freq_m;
	u32			freq_n;
	wait_queue_head_t	waitq;
	spinlock_t		lock;
	struct i2c_msg		*msg;
	struct i2c_adapter	adapter;
};

/*
 *****************************************************************************
 *
 *	Finite State Machine & Interrupt Routines
 *
 *****************************************************************************
 */

/* Reset hardware and initialize FSM */
static void
mv64xxx_i2c_hw_init(struct mv64xxx_i2c_data *drv_data)
{
	writel(0, drv_data->reg_base + MV64XXX_I2C_REG_SOFT_RESET);
	writel((((drv_data->freq_m & 0xf) << 3) | (drv_data->freq_n & 0x7)),
		drv_data->reg_base + MV64XXX_I2C_REG_BAUD);
	writel(0, drv_data->reg_base + MV64XXX_I2C_REG_SLAVE_ADDR);
	writel(0, drv_data->reg_base + MV64XXX_I2C_REG_EXT_SLAVE_ADDR);
	writel(MV64XXX_I2C_REG_CONTROL_TWSIEN | MV64XXX_I2C_REG_CONTROL_STOP,
		drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
	drv_data->state = MV64XXX_I2C_STATE_IDLE;
}

static void
mv64xxx_i2c_fsm(struct mv64xxx_i2c_data *drv_data, u32 status)
{
	/*
	 * If state is idle, then this is likely the remnants of an old
	 * operation that driver has given up on or the user has killed.
	 * If so, issue the stop condition and go to idle.
	 */
	if (drv_data->state == MV64XXX_I2C_STATE_IDLE) {
		drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
		return;
	}

	/* The status from the ctlr [mostly] tells us what to do next */
	switch (status) {
	/* Start condition interrupt */
	case MV64XXX_I2C_STATUS_MAST_START: /* 0x08 */
	case MV64XXX_I2C_STATUS_MAST_REPEAT_START: /* 0x10 */
		drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_1;
		drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK;
		break;

	/* Performing a write */
	case MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK: /* 0x18 */
		if (drv_data->msg->flags & I2C_M_TEN) {
			drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2;
			drv_data->state =
				MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK;
			break;
		}
		/* FALLTHRU */
	case MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK: /* 0xd0 */
	case MV64XXX_I2C_STATUS_MAST_WR_ACK: /* 0x28 */
		if ((drv_data->bytes_left == 0)
				|| (drv_data->aborting
					&& (drv_data->byte_posn != 0))) {
			drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
			drv_data->state = MV64XXX_I2C_STATE_IDLE;
		} else {
			drv_data->action = MV64XXX_I2C_ACTION_SEND_DATA;
			drv_data->state =
				MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK;
			drv_data->bytes_left--;
		}
		break;

	/* Performing a read */
	case MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK: /* 40 */
		if (drv_data->msg->flags & I2C_M_TEN) {
			drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2;
			drv_data->state =
				MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK;
			break;
		}
		/* FALLTHRU */
	case MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK: /* 0xe0 */
		if (drv_data->bytes_left == 0) {
			drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
			drv_data->state = MV64XXX_I2C_STATE_IDLE;
			break;
		}
		/* FALLTHRU */
	case MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK: /* 0x50 */
		if (status != MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK)
			drv_data->action = MV64XXX_I2C_ACTION_CONTINUE;
		else {
			drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA;
			drv_data->bytes_left--;
		}
		drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA;

		if ((drv_data->bytes_left == 1) || drv_data->aborting)
			drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_ACK;
		break;

	case MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK: /* 0x58 */
		drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA_STOP;
		drv_data->state = MV64XXX_I2C_STATE_IDLE;
		break;

	case MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK: /* 0x20 */
	case MV64XXX_I2C_STATUS_MAST_WR_NO_ACK: /* 30 */
	case MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK: /* 48 */
		/* Doesn't seem to be a device at other end */
		drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
		drv_data->state = MV64XXX_I2C_STATE_IDLE;
		drv_data->rc = -ENODEV;
		break;

	default:
		dev_err(&drv_data->adapter.dev,
			"mv64xxx_i2c_fsm: Ctlr Error -- state: 0x%x, "
			"status: 0x%x, addr: 0x%x, flags: 0x%x\n",
			 drv_data->state, status, drv_data->msg->addr,
			 drv_data->msg->flags);
		drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
		mv64xxx_i2c_hw_init(drv_data);
		drv_data->rc = -EIO;
	}
}

static void
mv64xxx_i2c_do_action(struct mv64xxx_i2c_data *drv_data)
{
	switch(drv_data->action) {
	case MV64XXX_I2C_ACTION_CONTINUE:
		writel(drv_data->cntl_bits,
			drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
		break;

	case MV64XXX_I2C_ACTION_SEND_START:
		writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_START,
			drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
		break;

	case MV64XXX_I2C_ACTION_SEND_ADDR_1:
		writel(drv_data->addr1,
			drv_data->reg_base + MV64XXX_I2C_REG_DATA);
		writel(drv_data->cntl_bits,
			drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
		break;

	case MV64XXX_I2C_ACTION_SEND_ADDR_2:
		writel(drv_data->addr2,
			drv_data->reg_base + MV64XXX_I2C_REG_DATA);
		writel(drv_data->cntl_bits,
			drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
		break;

	case MV64XXX_I2C_ACTION_SEND_DATA:
		writel(drv_data->msg->buf[drv_data->byte_posn++],
			drv_data->reg_base + MV64XXX_I2C_REG_DATA);
		writel(drv_data->cntl_bits,
			drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
		break;

	case MV64XXX_I2C_ACTION_RCV_DATA:
		drv_data->msg->buf[drv_data->byte_posn++] =
			readl(drv_data->reg_base + MV64XXX_I2C_REG_DATA);
		writel(drv_data->cntl_bits,
			drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
		break;

	case MV64XXX_I2C_ACTION_RCV_DATA_STOP:
		drv_data->msg->buf[drv_data->byte_posn++] =
			readl(drv_data->reg_base + MV64XXX_I2C_REG_DATA);
		drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN;
		writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP,
			drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
		drv_data->block = 0;
		wake_up_interruptible(&drv_data->waitq);
		break;

	case MV64XXX_I2C_ACTION_INVALID:
	default:
		dev_err(&drv_data->adapter.dev,
			"mv64xxx_i2c_do_action: Invalid action: %d\n",
			drv_data->action);
		drv_data->rc = -EIO;
		/* FALLTHRU */
	case MV64XXX_I2C_ACTION_SEND_STOP:
		drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN;
		writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP,
			drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
		drv_data->block = 0;
		wake_up_interruptible(&drv_data->waitq);
		break;
	}
}

static int
mv64xxx_i2c_intr(int irq, void *dev_id)
{
	struct mv64xxx_i2c_data	*drv_data = dev_id;
	unsigned long	flags;
	u32		status;
	int		rc = IRQ_NONE;

	spin_lock_irqsave(&drv_data->lock, flags);
	while (readl(drv_data->reg_base + MV64XXX_I2C_REG_CONTROL) &
						MV64XXX_I2C_REG_CONTROL_IFLG) {
		status = readl(drv_data->reg_base + MV64XXX_I2C_REG_STATUS);
		mv64xxx_i2c_fsm(drv_data, status);
		mv64xxx_i2c_do_action(drv_data);
		rc = IRQ_HANDLED;
	}
	spin_unlock_irqrestore(&drv_data->lock, flags);

	return rc;
}

/*
 *****************************************************************************
 *
 *	I2C Msg Execution Routines
 *
 *****************************************************************************
 */
static void
mv64xxx_i2c_prepare_for_io(struct mv64xxx_i2c_data *drv_data,
	struct i2c_msg *msg)
{
	u32	dir = 0;

	drv_data->msg = msg;
	drv_data->byte_posn = 0;
	drv_data->bytes_left = msg->len;
	drv_data->aborting = 0;
	drv_data->rc = 0;
	drv_data->cntl_bits = MV64XXX_I2C_REG_CONTROL_ACK |
		MV64XXX_I2C_REG_CONTROL_INTEN | MV64XXX_I2C_REG_CONTROL_TWSIEN;

	if (msg->flags & I2C_M_RD)
		dir = 1;

	if (msg->flags & I2C_M_REV_DIR_ADDR)
		dir ^= 1;

	if (msg->flags & I2C_M_TEN) {
		drv_data->addr1 = 0xf0 | (((u32)msg->addr & 0x300) >> 7) | dir;
		drv_data->addr2 = (u32)msg->addr & 0xff;
	} else {
		drv_data->addr1 = ((u32)msg->addr & 0x7f) << 1 | dir;
		drv_data->addr2 = 0;
	}
}

static void
mv64xxx_i2c_wait_for_completion(struct mv64xxx_i2c_data *drv_data)
{
	long		time_left;
	unsigned long	flags;
	char		abort = 0;

	time_left = wait_event_interruptible_timeout(drv_data->waitq,
		!drv_data->block, msecs_to_jiffies(drv_data->adapter.timeout));

	spin_lock_irqsave(&drv_data->lock, flags);
	if (!time_left) { /* Timed out */
		drv_data->rc = -ETIMEDOUT;
		abort = 1;
	} else if (time_left < 0) { /* Interrupted/Error */
		drv_data->rc = time_left; /* errno value */
		abort = 1;
	}

	if (abort && drv_data->block) {
		drv_data->aborting = 1;
		spin_unlock_irqrestore(&drv_data->lock, flags);

		time_left = wait_event_timeout(drv_data->waitq,
			!drv_data->block,
			msecs_to_jiffies(drv_data->adapter.timeout));

		if ((time_left <= 0) && drv_data->block) {
			drv_data->state = MV64XXX_I2C_STATE_IDLE;
			dev_err(&drv_data->adapter.dev,
				"mv64xxx: I2C bus locked, block: %d, "
				"time_left: %d\n", drv_data->block,
				(int)time_left);
			mv64xxx_i2c_hw_init(drv_data);
		}
	} else
		spin_unlock_irqrestore(&drv_data->lock, flags);
}

static int
mv64xxx_i2c_execute_msg(struct mv64xxx_i2c_data *drv_data, struct i2c_msg *msg)
{
	unsigned long	flags;

	spin_lock_irqsave(&drv_data->lock, flags);
	mv64xxx_i2c_prepare_for_io(drv_data, msg);

	if (unlikely(msg->flags & I2C_M_NOSTART)) { /* Skip start/addr phases */
		if (drv_data->msg->flags & I2C_M_RD) {
			/* No action to do, wait for slave to send a byte */
			drv_data->action = MV64XXX_I2C_ACTION_CONTINUE;
			drv_data->state =
				MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA;
		} else {
			drv_data->action = MV64XXX_I2C_ACTION_SEND_DATA;
			drv_data->state =
				MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK;
			drv_data->bytes_left--;
		}
	} else {
		drv_data->action = MV64XXX_I2C_ACTION_SEND_START;
		drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_START_COND;
	}

	drv_data->block = 1;
	mv64xxx_i2c_do_action(drv_data);
	spin_unlock_irqrestore(&drv_data->lock, flags);

	mv64xxx_i2c_wait_for_completion(drv_data);
	return drv_data->rc;
}

/*
 *****************************************************************************
 *
 *	I2C Core Support Routines (Interface to higher level I2C code)
 *
 *****************************************************************************
 */
static u32
mv64xxx_i2c_functionality(struct i2c_adapter *adap)
{
	return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SMBUS_EMUL;
}

static int
mv64xxx_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
{
	struct mv64xxx_i2c_data *drv_data = i2c_get_adapdata(adap);
	int	i, rc;

	for (i=0; i<num; i++)
		if ((rc = mv64xxx_i2c_execute_msg(drv_data, &msgs[i])) < 0)
			return rc;

	return num;
}

static const struct i2c_algorithm mv64xxx_i2c_algo = {
	.master_xfer = mv64xxx_i2c_xfer,
	.functionality = mv64xxx_i2c_functionality,
};

/*
 *****************************************************************************
 *
 *	Driver Interface & Early Init Routines
 *
 *****************************************************************************
 */
static int __devinit
mv64xxx_i2c_map_regs(struct platform_device *pd,
	struct mv64xxx_i2c_data *drv_data)
{
	struct resource	*r;

	if ((r = platform_get_resource(pd, IORESOURCE_MEM, 0)) &&
		request_mem_region(r->start, MV64XXX_I2C_REG_BLOCK_SIZE,
			drv_data->adapter.name)) {

		drv_data->reg_base = ioremap(r->start,
			MV64XXX_I2C_REG_BLOCK_SIZE);
		drv_data->reg_base_p = r->start;
	} else
		return -ENOMEM;

	return 0;
}

static void __devexit
mv64xxx_i2c_unmap_regs(struct mv64xxx_i2c_data *drv_data)
{
	if (drv_data->reg_base) {
		iounmap(drv_data->reg_base);
		release_mem_region(drv_data->reg_base_p,
			MV64XXX_I2C_REG_BLOCK_SIZE);
	}

	drv_data->reg_base = NULL;
	drv_data->reg_base_p = 0;
}

static int __devinit
mv64xxx_i2c_probe(struct platform_device *pd)
{
	struct mv64xxx_i2c_data		*drv_data;
	struct mv64xxx_i2c_pdata	*pdata = pd->dev.platform_data;
	int	rc;

	if ((pd->id != 0) || !pdata)
		return -ENODEV;

	drv_data = kzalloc(sizeof(struct mv64xxx_i2c_data), GFP_KERNEL);
	if (!drv_data)
		return -ENOMEM;

	if (mv64xxx_i2c_map_regs(pd, drv_data)) {
		rc = -ENODEV;
		goto exit_kfree;
	}

	strlcpy(drv_data->adapter.name, MV64XXX_I2C_CTLR_NAME " adapter",
		sizeof(drv_data->adapter.name));

	init_waitqueue_head(&drv_data->waitq);
	spin_lock_init(&drv_data->lock);

	drv_data->freq_m = pdata->freq_m;
	drv_data->freq_n = pdata->freq_n;
	drv_data->irq = platform_get_irq(pd, 0);
	if (drv_data->irq < 0) {
		rc = -ENXIO;
		goto exit_unmap_regs;
	}
	drv_data->adapter.dev.parent = &pd->dev;
	drv_data->adapter.id = I2C_HW_MV64XXX;
	drv_data->adapter.algo = &mv64xxx_i2c_algo;
	drv_data->adapter.owner = THIS_MODULE;
	drv_data->adapter.class = I2C_CLASS_HWMON;
	drv_data->adapter.timeout = pdata->timeout;
	drv_data->adapter.retries = pdata->retries;
	drv_data->adapter.nr = pd->id;
	platform_set_drvdata(pd, drv_data);
	i2c_set_adapdata(&drv_data->adapter, drv_data);

	mv64xxx_i2c_hw_init(drv_data);

	if (request_irq(drv_data->irq, mv64xxx_i2c_intr, 0,
			MV64XXX_I2C_CTLR_NAME, drv_data)) {
		dev_err(&drv_data->adapter.dev,
			"mv64xxx: Can't register intr handler irq: %d\n",
			drv_data->irq);
		rc = -EINVAL;
		goto exit_unmap_regs;
	} else if ((rc = i2c_add_numbered_adapter(&drv_data->adapter)) != 0) {
		dev_err(&drv_data->adapter.dev,
			"mv64xxx: Can't add i2c adapter, rc: %d\n", -rc);
		goto exit_free_irq;
	}

	return 0;

	exit_free_irq:
		free_irq(drv_data->irq, drv_data);
	exit_unmap_regs:
		mv64xxx_i2c_unmap_regs(drv_data);
	exit_kfree:
		kfree(drv_data);
	return rc;
}

static int __devexit
mv64xxx_i2c_remove(struct platform_device *dev)
{
	struct mv64xxx_i2c_data		*drv_data = platform_get_drvdata(dev);
	int	rc;

	rc = i2c_del_adapter(&drv_data->adapter);
	free_irq(drv_data->irq, drv_data);
	mv64xxx_i2c_unmap_regs(drv_data);
	kfree(drv_data);

	return rc;
}

static struct platform_driver mv64xxx_i2c_driver = {
	.probe	= mv64xxx_i2c_probe,
	.remove	= mv64xxx_i2c_remove,
	.driver	= {
		.owner	= THIS_MODULE,
		.name	= MV64XXX_I2C_CTLR_NAME,
	},
};

static int __init
mv64xxx_i2c_init(void)
{
	return platform_driver_register(&mv64xxx_i2c_driver);
}

static void __exit
mv64xxx_i2c_exit(void)
{
	platform_driver_unregister(&mv64xxx_i2c_driver);
}

module_init(mv64xxx_i2c_init);
module_exit(mv64xxx_i2c_exit);

MODULE_AUTHOR("Mark A. Greer <mgreer@mvista.com>");
MODULE_DESCRIPTION("Marvell mv64xxx host bridge i2c ctlr driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4	1	/*
1da177e4 LT	2	* Driver for the i2c controller on the Marvell line of host bridges for MIPS
	3	* and PPC (e.g, gt642[46]0, mv643[46]0, mv644[46]0).
	4	*
	5	* Author: Mark A. Greer <mgreer@mvista.com>
	6	*
	7	* 2005 (c) MontaVista, Software, Inc. This file is licensed under
	8	* the terms of the GNU General Public License version 2. This program
	9	* is licensed "as is" without any warranty of any kind, whether express
	10	* or implied.
	11	*/
	12	#include <linux/kernel.h>
	13	#include <linux/module.h>
	14	#include <linux/spinlock.h>
	15	#include <linux/i2c.h>
	16	#include <linux/interrupt.h>
	17	#include <linux/mv643xx.h>
d052d1be RK	18	#include <linux/platform_device.h>
d052d1be RK	19
1da177e4 LT	20	#include <asm/io.h>
	21
	22	/* Register defines */
	23	#define MV64XXX_I2C_REG_SLAVE_ADDR 0x00
	24	#define MV64XXX_I2C_REG_DATA 0x04
	25	#define MV64XXX_I2C_REG_CONTROL 0x08
	26	#define MV64XXX_I2C_REG_STATUS 0x0c
	27	#define MV64XXX_I2C_REG_BAUD 0x0c
	28	#define MV64XXX_I2C_REG_EXT_SLAVE_ADDR 0x10
	29	#define MV64XXX_I2C_REG_SOFT_RESET 0x1c
	30
	31	#define MV64XXX_I2C_REG_CONTROL_ACK 0x00000004
	32	#define MV64XXX_I2C_REG_CONTROL_IFLG 0x00000008
	33	#define MV64XXX_I2C_REG_CONTROL_STOP 0x00000010
	34	#define MV64XXX_I2C_REG_CONTROL_START 0x00000020
	35	#define MV64XXX_I2C_REG_CONTROL_TWSIEN 0x00000040
	36	#define MV64XXX_I2C_REG_CONTROL_INTEN 0x00000080
	37
	38	/* Ctlr status values */
	39	#define MV64XXX_I2C_STATUS_BUS_ERR 0x00
	40	#define MV64XXX_I2C_STATUS_MAST_START 0x08
	41	#define MV64XXX_I2C_STATUS_MAST_REPEAT_START 0x10
	42	#define MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK 0x18
	43	#define MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK 0x20
	44	#define MV64XXX_I2C_STATUS_MAST_WR_ACK 0x28
	45	#define MV64XXX_I2C_STATUS_MAST_WR_NO_ACK 0x30
	46	#define MV64XXX_I2C_STATUS_MAST_LOST_ARB 0x38
	47	#define MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK 0x40
	48	#define MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK 0x48
	49	#define MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK 0x50
	50	#define MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK 0x58
	51	#define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK 0xd0
	52	#define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_NO_ACK 0xd8
	53	#define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK 0xe0
	54	#define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_NO_ACK 0xe8
	55	#define MV64XXX_I2C_STATUS_NO_STATUS 0xf8
	56
	57	/* Driver states */
	58	enum {
	59	MV64XXX_I2C_STATE_INVALID,
	60	MV64XXX_I2C_STATE_IDLE,
	61	MV64XXX_I2C_STATE_WAITING_FOR_START_COND,
	62	MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK,
	63	MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK,
	64	MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK,
	65	MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA,
1da177e4 LT	66	};
	67
	68	/* Driver actions */
	69	enum {
	70	MV64XXX_I2C_ACTION_INVALID,
	71	MV64XXX_I2C_ACTION_CONTINUE,
	72	MV64XXX_I2C_ACTION_SEND_START,
	73	MV64XXX_I2C_ACTION_SEND_ADDR_1,
	74	MV64XXX_I2C_ACTION_SEND_ADDR_2,
	75	MV64XXX_I2C_ACTION_SEND_DATA,
	76	MV64XXX_I2C_ACTION_RCV_DATA,
	77	MV64XXX_I2C_ACTION_RCV_DATA_STOP,
	78	MV64XXX_I2C_ACTION_SEND_STOP,
	79	};
	80
	81	struct mv64xxx_i2c_data {
	82	int irq;
	83	u32 state;
	84	u32 action;
e91c021c	85	u32 aborting;
1da177e4 LT	86	u32 cntl_bits;
	87	void __iomem *reg_base;
	88	u32 reg_base_p;
	89	u32 addr1;
	90	u32 addr2;
	91	u32 bytes_left;
	92	u32 byte_posn;
	93	u32 block;
	94	int rc;
	95	u32 freq_m;
	96	u32 freq_n;
	97	wait_queue_head_t waitq;
	98	spinlock_t lock;
	99	struct i2c_msg *msg;
	100	struct i2c_adapter adapter;
	101	};
	102
	103	/*
	104	*****************************************************************************
	105	*
	106	* Finite State Machine & Interrupt Routines
	107	*
	108	*****************************************************************************
	109	*/
a07ad1cc DF	110
	111	/* Reset hardware and initialize FSM */
	112	static void
	113	mv64xxx_i2c_hw_init(struct mv64xxx_i2c_data *drv_data)
	114	{
	115	writel(0, drv_data->reg_base + MV64XXX_I2C_REG_SOFT_RESET);
	116	writel((((drv_data->freq_m & 0xf) << 3) \| (drv_data->freq_n & 0x7)),
	117	drv_data->reg_base + MV64XXX_I2C_REG_BAUD);
	118	writel(0, drv_data->reg_base + MV64XXX_I2C_REG_SLAVE_ADDR);
	119	writel(0, drv_data->reg_base + MV64XXX_I2C_REG_EXT_SLAVE_ADDR);
	120	writel(MV64XXX_I2C_REG_CONTROL_TWSIEN \| MV64XXX_I2C_REG_CONTROL_STOP,
	121	drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
	122	drv_data->state = MV64XXX_I2C_STATE_IDLE;
	123	}
	124
1da177e4 LT	125	static void
	126	mv64xxx_i2c_fsm(struct mv64xxx_i2c_data *drv_data, u32 status)
	127	{
	128	/*
	129	* If state is idle, then this is likely the remnants of an old
	130	* operation that driver has given up on or the user has killed.
	131	* If so, issue the stop condition and go to idle.
	132	*/
	133	if (drv_data->state == MV64XXX_I2C_STATE_IDLE) {
	134	drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
	135	return;
	136	}
	137
1da177e4 LT	138	/* The status from the ctlr [mostly] tells us what to do next */
	139	switch (status) {
	140	/* Start condition interrupt */
	141	case MV64XXX_I2C_STATUS_MAST_START: /* 0x08 */
	142	case MV64XXX_I2C_STATUS_MAST_REPEAT_START: /* 0x10 */
	143	drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_1;
	144	drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK;
	145	break;
	146
	147	/* Performing a write */
	148	case MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK: /* 0x18 */
	149	if (drv_data->msg->flags & I2C_M_TEN) {
	150	drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2;
	151	drv_data->state =
	152	MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK;
	153	break;
	154	}
	155	/* FALLTHRU */
	156	case MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK: /* 0xd0 */
	157	case MV64XXX_I2C_STATUS_MAST_WR_ACK: /* 0x28 */
e91c021c MG	158	if ((drv_data->bytes_left == 0)
	159	\|\| (drv_data->aborting
	160	&& (drv_data->byte_posn != 0))) {
	161	drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
	162	drv_data->state = MV64XXX_I2C_STATE_IDLE;
	163	} else {
1da177e4 LT	164	drv_data->action = MV64XXX_I2C_ACTION_SEND_DATA;
	165	drv_data->state =
	166	MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK;
	167	drv_data->bytes_left--;
1da177e4 LT	168	}
	169	break;
	170
	171	/* Performing a read */
	172	case MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK: /* 40 */
	173	if (drv_data->msg->flags & I2C_M_TEN) {
	174	drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2;
	175	drv_data->state =
	176	MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK;
	177	break;
	178	}
	179	/* FALLTHRU */
	180	case MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK: /* 0xe0 */
	181	if (drv_data->bytes_left == 0) {
	182	drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
	183	drv_data->state = MV64XXX_I2C_STATE_IDLE;
	184	break;
	185	}
	186	/* FALLTHRU */
	187	case MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK: /* 0x50 */
	188	if (status != MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK)
	189	drv_data->action = MV64XXX_I2C_ACTION_CONTINUE;
	190	else {
	191	drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA;
	192	drv_data->bytes_left--;
	193	}
	194	drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA;
	195
e91c021c	196	if ((drv_data->bytes_left == 1) \|\| drv_data->aborting)
1da177e4 LT	197	drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_ACK;
	198	break;
	199
	200	case MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK: /* 0x58 */
	201	drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA_STOP;
	202	drv_data->state = MV64XXX_I2C_STATE_IDLE;
	203	break;
	204
	205	case MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK: /* 0x20 */
	206	case MV64XXX_I2C_STATUS_MAST_WR_NO_ACK: /* 30 */
	207	case MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK: /* 48 */
	208	/* Doesn't seem to be a device at other end */
	209	drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
	210	drv_data->state = MV64XXX_I2C_STATE_IDLE;
	211	drv_data->rc = -ENODEV;
	212	break;
	213
	214	default:
	215	dev_err(&drv_data->adapter.dev,
	216	"mv64xxx_i2c_fsm: Ctlr Error -- state: 0x%x, "
	217	"status: 0x%x, addr: 0x%x, flags: 0x%x\n",
	218	drv_data->state, status, drv_data->msg->addr,
	219	drv_data->msg->flags);
	220	drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
a07ad1cc	221	mv64xxx_i2c_hw_init(drv_data);
1da177e4 LT	222	drv_data->rc = -EIO;
	223	}
	224	}
	225
	226	static void
	227	mv64xxx_i2c_do_action(struct mv64xxx_i2c_data *drv_data)
	228	{
	229	switch(drv_data->action) {
	230	case MV64XXX_I2C_ACTION_CONTINUE:
	231	writel(drv_data->cntl_bits,
	232	drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
	233	break;
	234
	235	case MV64XXX_I2C_ACTION_SEND_START:
	236	writel(drv_data->cntl_bits \| MV64XXX_I2C_REG_CONTROL_START,
	237	drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
	238	break;
	239
	240	case MV64XXX_I2C_ACTION_SEND_ADDR_1:
	241	writel(drv_data->addr1,
	242	drv_data->reg_base + MV64XXX_I2C_REG_DATA);
	243	writel(drv_data->cntl_bits,
	244	drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
	245	break;
	246
	247	case MV64XXX_I2C_ACTION_SEND_ADDR_2:
	248	writel(drv_data->addr2,
	249	drv_data->reg_base + MV64XXX_I2C_REG_DATA);
	250	writel(drv_data->cntl_bits,
	251	drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
	252	break;
	253
	254	case MV64XXX_I2C_ACTION_SEND_DATA:
	255	writel(drv_data->msg->buf[drv_data->byte_posn++],
	256	drv_data->reg_base + MV64XXX_I2C_REG_DATA);
	257	writel(drv_data->cntl_bits,
	258	drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
	259	break;
	260
	261	case MV64XXX_I2C_ACTION_RCV_DATA:
	262	drv_data->msg->buf[drv_data->byte_posn++] =
	263	readl(drv_data->reg_base + MV64XXX_I2C_REG_DATA);
	264	writel(drv_data->cntl_bits,
	265	drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
	266	break;
	267
	268	case MV64XXX_I2C_ACTION_RCV_DATA_STOP:
	269	drv_data->msg->buf[drv_data->byte_posn++] =
	270	readl(drv_data->reg_base + MV64XXX_I2C_REG_DATA);
	271	drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN;
	272	writel(drv_data->cntl_bits \| MV64XXX_I2C_REG_CONTROL_STOP,
	273	drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
	274	drv_data->block = 0;
	275	wake_up_interruptible(&drv_data->waitq);
	276	break;
	277
	278	case MV64XXX_I2C_ACTION_INVALID:
	279	default:
	280	dev_err(&drv_data->adapter.dev,
	281	"mv64xxx_i2c_do_action: Invalid action: %d\n",
	282	drv_data->action);
	283	drv_data->rc = -EIO;
	284	/* FALLTHRU */
	285	case MV64XXX_I2C_ACTION_SEND_STOP:
286	drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN;
287	writel(drv_data->cntl_bits \| MV64XXX_I2C_REG_CONTROL_STOP,
288	drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
289	drv_data->block = 0;
290	wake_up_interruptible(&drv_data->waitq);
291	break;
292	}
293	}
294
295	static int
7d12e780	296	mv64xxx_i2c_intr(int irq, void *dev_id)
1da177e4 LT	297	{
	298	struct mv64xxx_i2c_data *drv_data = dev_id;
	299	unsigned long flags;
	300	u32 status;
	301	int rc = IRQ_NONE;
	302
	303	spin_lock_irqsave(&drv_data->lock, flags);
	304	while (readl(drv_data->reg_base + MV64XXX_I2C_REG_CONTROL) &
	305	MV64XXX_I2C_REG_CONTROL_IFLG) {
	306	status = readl(drv_data->reg_base + MV64XXX_I2C_REG_STATUS);
	307	mv64xxx_i2c_fsm(drv_data, status);
	308	mv64xxx_i2c_do_action(drv_data);
	309	rc = IRQ_HANDLED;
	310	}
	311	spin_unlock_irqrestore(&drv_data->lock, flags);
	312
	313	return rc;
	314	}
	315
	316	/*
	317	*****************************************************************************
	318	*
	319	* I2C Msg Execution Routines
	320	*
	321	*****************************************************************************
	322	*/
	323	static void
	324	mv64xxx_i2c_prepare_for_io(struct mv64xxx_i2c_data *drv_data,
	325	struct i2c_msg *msg)
	326	{
	327	u32 dir = 0;
	328
	329	drv_data->msg = msg;
	330	drv_data->byte_posn = 0;
	331	drv_data->bytes_left = msg->len;
e91c021c	332	drv_data->aborting = 0;
1da177e4 LT	333	drv_data->rc = 0;
	334	drv_data->cntl_bits = MV64XXX_I2C_REG_CONTROL_ACK \|
	335	MV64XXX_I2C_REG_CONTROL_INTEN \| MV64XXX_I2C_REG_CONTROL_TWSIEN;
	336
	337	if (msg->flags & I2C_M_RD)
	338	dir = 1;
	339
	340	if (msg->flags & I2C_M_REV_DIR_ADDR)
	341	dir ^= 1;
	342
	343	if (msg->flags & I2C_M_TEN) {
	344	drv_data->addr1 = 0xf0 \| (((u32)msg->addr & 0x300) >> 7) \| dir;
	345	drv_data->addr2 = (u32)msg->addr & 0xff;
	346	} else {
	347	drv_data->addr1 = ((u32)msg->addr & 0x7f) << 1 \| dir;
	348	drv_data->addr2 = 0;
	349	}
	350	}
	351
	352	static void
	353	mv64xxx_i2c_wait_for_completion(struct mv64xxx_i2c_data *drv_data)
	354	{
	355	long time_left;
	356	unsigned long flags;
	357	char abort = 0;
	358
	359	time_left = wait_event_interruptible_timeout(drv_data->waitq,
	360	!drv_data->block, msecs_to_jiffies(drv_data->adapter.timeout));
	361
	362	spin_lock_irqsave(&drv_data->lock, flags);
	363	if (!time_left) { /* Timed out */
	364	drv_data->rc = -ETIMEDOUT;
	365	abort = 1;
	366	} else if (time_left < 0) { /* Interrupted/Error */
	367	drv_data->rc = time_left; /* errno value */
	368	abort = 1;
	369	}
	370
	371	if (abort && drv_data->block) {
e91c021c	372	drv_data->aborting = 1;
1da177e4 LT	373	spin_unlock_irqrestore(&drv_data->lock, flags);
	374
	375	time_left = wait_event_timeout(drv_data->waitq,
	376	!drv_data->block,
	377	msecs_to_jiffies(drv_data->adapter.timeout));
	378
e91c021c	379	if ((time_left <= 0) && drv_data->block) {
1da177e4 LT	380	drv_data->state = MV64XXX_I2C_STATE_IDLE;
1da177e4 LT	381	dev_err(&drv_data->adapter.dev,
e91c021c MG	382	"mv64xxx: I2C bus locked, block: %d, "
	383	"time_left: %d\n", drv_data->block,
	384	(int)time_left);
a07ad1cc	385	mv64xxx_i2c_hw_init(drv_data);
1da177e4 LT	386	}
	387	} else
	388	spin_unlock_irqrestore(&drv_data->lock, flags);
	389	}
	390
	391	static int
	392	mv64xxx_i2c_execute_msg(struct mv64xxx_i2c_data drv_data, struct i2c_msg msg)
	393	{
	394	unsigned long flags;
	395
	396	spin_lock_irqsave(&drv_data->lock, flags);
	397	mv64xxx_i2c_prepare_for_io(drv_data, msg);
	398
	399	if (unlikely(msg->flags & I2C_M_NOSTART)) { /* Skip start/addr phases */
	400	if (drv_data->msg->flags & I2C_M_RD) {
	401	/* No action to do, wait for slave to send a byte */
	402	drv_data->action = MV64XXX_I2C_ACTION_CONTINUE;
	403	drv_data->state =
	404	MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA;
	405	} else {
	406	drv_data->action = MV64XXX_I2C_ACTION_SEND_DATA;
	407	drv_data->state =
	408	MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK;
	409	drv_data->bytes_left--;
	410	}
	411	} else {
	412	drv_data->action = MV64XXX_I2C_ACTION_SEND_START;
	413	drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_START_COND;
	414	}
	415
	416	drv_data->block = 1;
	417	mv64xxx_i2c_do_action(drv_data);
	418	spin_unlock_irqrestore(&drv_data->lock, flags);
	419
	420	mv64xxx_i2c_wait_for_completion(drv_data);
	421	return drv_data->rc;
	422	}
	423
	424	/*
	425	*****************************************************************************
	426	*
	427	* I2C Core Support Routines (Interface to higher level I2C code)
	428	*
	429	*****************************************************************************
	430	*/
	431	static u32
	432	mv64xxx_i2c_functionality(struct i2c_adapter *adap)
	433	{
	434	return I2C_FUNC_I2C \| I2C_FUNC_10BIT_ADDR \| I2C_FUNC_SMBUS_EMUL;
	435	}
	436
	437	static int
	438	mv64xxx_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
	439	{
	440	struct mv64xxx_i2c_data *drv_data = i2c_get_adapdata(adap);
d1b2f0a9	441	int i, rc;
1da177e4 LT	442
1da177e4 LT	443	for (i=0; i<num; i++)
d1b2f0a9 JD	444	if ((rc = mv64xxx_i2c_execute_msg(drv_data, &msgs[i])) < 0)
d1b2f0a9 JD	445	return rc;
1da177e4	446
d1b2f0a9	447	return num;
1da177e4 LT	448	}
1da177e4 LT	449
8f9082c5	450	static const struct i2c_algorithm mv64xxx_i2c_algo = {
1da177e4 LT	451	.master_xfer = mv64xxx_i2c_xfer,
	452	.functionality = mv64xxx_i2c_functionality,
	453	};
	454
	455	/*
	456	*****************************************************************************
	457	*
	458	* Driver Interface & Early Init Routines
	459	*
	460	*****************************************************************************
	461	*/
1da177e4 LT	462	static int __devinit
	463	mv64xxx_i2c_map_regs(struct platform_device *pd,
	464	struct mv64xxx_i2c_data *drv_data)
	465	{
	466	struct resource *r;
	467
	468	if ((r = platform_get_resource(pd, IORESOURCE_MEM, 0)) &&
	469	request_mem_region(r->start, MV64XXX_I2C_REG_BLOCK_SIZE,
	470	drv_data->adapter.name)) {
	471
	472	drv_data->reg_base = ioremap(r->start,
	473	MV64XXX_I2C_REG_BLOCK_SIZE);
	474	drv_data->reg_base_p = r->start;
	475	} else
	476	return -ENOMEM;
	477
	478	return 0;
	479	}
	480
	481	static void __devexit
	482	mv64xxx_i2c_unmap_regs(struct mv64xxx_i2c_data *drv_data)
	483	{
	484	if (drv_data->reg_base) {
	485	iounmap(drv_data->reg_base);
	486	release_mem_region(drv_data->reg_base_p,
	487	MV64XXX_I2C_REG_BLOCK_SIZE);
	488	}
	489
	490	drv_data->reg_base = NULL;
	491	drv_data->reg_base_p = 0;
	492	}
	493
	494	static int __devinit
3ae5eaec	495	mv64xxx_i2c_probe(struct platform_device *pd)
1da177e4	496	{
1da177e4	497	struct mv64xxx_i2c_data *drv_data;
3ae5eaec	498	struct mv64xxx_i2c_pdata *pdata = pd->dev.platform_data;
1da177e4 LT	499	int rc;
	500
	501	if ((pd->id != 0) \|\| !pdata)
	502	return -ENODEV;
	503
5263ebb5	504	drv_data = kzalloc(sizeof(struct mv64xxx_i2c_data), GFP_KERNEL);
1da177e4 LT	505	if (!drv_data)
	506	return -ENOMEM;
	507
1da177e4 LT	508	if (mv64xxx_i2c_map_regs(pd, drv_data)) {
	509	rc = -ENODEV;
	510	goto exit_kfree;
	511	}
	512
e91c021c	513	strlcpy(drv_data->adapter.name, MV64XXX_I2C_CTLR_NAME " adapter",
2096b956	514	sizeof(drv_data->adapter.name));
1da177e4 LT	515
	516	init_waitqueue_head(&drv_data->waitq);
	517	spin_lock_init(&drv_data->lock);
	518
	519	drv_data->freq_m = pdata->freq_m;
	520	drv_data->freq_n = pdata->freq_n;
	521	drv_data->irq = platform_get_irq(pd, 0);
48944738 DV	522	if (drv_data->irq < 0) {
	523	rc = -ENXIO;
	524	goto exit_unmap_regs;
	525	}
12a917f6	526	drv_data->adapter.dev.parent = &pd->dev;
c7a46533	527	drv_data->adapter.id = I2C_HW_MV64XXX;
1da177e4 LT	528	drv_data->adapter.algo = &mv64xxx_i2c_algo;
	529	drv_data->adapter.owner = THIS_MODULE;
	530	drv_data->adapter.class = I2C_CLASS_HWMON;
	531	drv_data->adapter.timeout = pdata->timeout;
	532	drv_data->adapter.retries = pdata->retries;
65b22ad9	533	drv_data->adapter.nr = pd->id;
3ae5eaec	534	platform_set_drvdata(pd, drv_data);
1da177e4 LT	535	i2c_set_adapdata(&drv_data->adapter, drv_data);
1da177e4 LT	536
3269bb63 MB	537	mv64xxx_i2c_hw_init(drv_data);
3269bb63 MB	538
1da177e4	539	if (request_irq(drv_data->irq, mv64xxx_i2c_intr, 0,
dfded4ae MG	540	MV64XXX_I2C_CTLR_NAME, drv_data)) {
	541	dev_err(&drv_data->adapter.dev,
	542	"mv64xxx: Can't register intr handler irq: %d\n",
	543	drv_data->irq);
1da177e4 LT	544	rc = -EINVAL;
1da177e4 LT	545	goto exit_unmap_regs;
65b22ad9	546	} else if ((rc = i2c_add_numbered_adapter(&drv_data->adapter)) != 0) {
dfded4ae MG	547	dev_err(&drv_data->adapter.dev,
dfded4ae MG	548	"mv64xxx: Can't add i2c adapter, rc: %d\n", -rc);
1da177e4 LT	549	goto exit_free_irq;
	550	}
	551
1da177e4 LT	552	return 0;
	553
	554	exit_free_irq:
	555	free_irq(drv_data->irq, drv_data);
	556	exit_unmap_regs:
	557	mv64xxx_i2c_unmap_regs(drv_data);
	558	exit_kfree:
	559	kfree(drv_data);
	560	return rc;
	561	}
	562
	563	static int __devexit
3ae5eaec	564	mv64xxx_i2c_remove(struct platform_device *dev)
1da177e4	565	{
3ae5eaec	566	struct mv64xxx_i2c_data *drv_data = platform_get_drvdata(dev);
1da177e4 LT	567	int rc;
	568
	569	rc = i2c_del_adapter(&drv_data->adapter);
	570	free_irq(drv_data->irq, drv_data);
	571	mv64xxx_i2c_unmap_regs(drv_data);
	572	kfree(drv_data);
	573
	574	return rc;
	575	}
	576
3ae5eaec	577	static struct platform_driver mv64xxx_i2c_driver = {
1da177e4 LT	578	.probe = mv64xxx_i2c_probe,
1da177e4 LT	579	.remove = mv64xxx_i2c_remove,
3ae5eaec RK	580	.driver = {
	581	.owner = THIS_MODULE,
	582	.name = MV64XXX_I2C_CTLR_NAME,
	583	},
1da177e4 LT	584	};
	585
	586	static int __init
	587	mv64xxx_i2c_init(void)
	588	{
3ae5eaec	589	return platform_driver_register(&mv64xxx_i2c_driver);
1da177e4 LT	590	}
	591
	592	static void __exit
	593	mv64xxx_i2c_exit(void)
	594	{
3ae5eaec	595	platform_driver_unregister(&mv64xxx_i2c_driver);
1da177e4 LT	596	}
	597
	598	module_init(mv64xxx_i2c_init);
	599	module_exit(mv64xxx_i2c_exit);
	600
	601	MODULE_AUTHOR("Mark A. Greer <mgreer@mvista.com>");
	602	MODULE_DESCRIPTION("Marvell mv64xxx host bridge i2c ctlr driver");
	603	MODULE_LICENSE("GPL");