[deliverable/linux.git] / drivers / i2c / busses / i2c-ocores.c

/*
 * i2c-ocores.c: I2C bus driver for OpenCores I2C controller
 * (http://www.opencores.org/projects.cgi/web/i2c/overview).
 *
 * Peter Korsgaard <jacmet@sunsite.dk>
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2.  This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 */

/*
 * Device tree configuration:
 *
 * Required properties:
 * - compatible      : "opencores,i2c-ocores"
 * - reg             : bus address start and address range size of device
 * - interrupts      : interrupt number
 * - regstep         : size of device registers in bytes
 * - clock-frequency : frequency of bus clock in Hz
 * 
 * Example:
 *
 *  i2c0: ocores@a0000000 {
 *              compatible = "opencores,i2c-ocores";
 *              reg = <0xa0000000 0x8>;
 *              interrupts = <10>;
 *
 *              regstep = <1>;
 *              clock-frequency = <20000000>;
 *
 * -- Devices connected on this I2C bus get
 * -- defined here; address- and size-cells
 * -- apply to these child devices
 *
 *              #address-cells = <1>;
 *              #size-cells = <0>;
 *
 *              dummy@60 {
 *                     compatible = "dummy";
 *                     reg = <60>;
 *              };
 *  };
 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/platform_device.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/wait.h>
#include <linux/i2c-ocores.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/of_i2c.h>

struct ocores_i2c {
	void __iomem *base;
	int regstep;
	wait_queue_head_t wait;
	struct i2c_adapter adap;
	struct i2c_msg *msg;
	int pos;
	int nmsgs;
	int state; /* see STATE_ */
	int clock_khz;
};

/* registers */
#define OCI2C_PRELOW		0
#define OCI2C_PREHIGH		1
#define OCI2C_CONTROL		2
#define OCI2C_DATA		3
#define OCI2C_CMD		4 /* write only */
#define OCI2C_STATUS		4 /* read only, same address as OCI2C_CMD */

#define OCI2C_CTRL_IEN		0x40
#define OCI2C_CTRL_EN		0x80

#define OCI2C_CMD_START		0x91
#define OCI2C_CMD_STOP		0x41
#define OCI2C_CMD_READ		0x21
#define OCI2C_CMD_WRITE		0x11
#define OCI2C_CMD_READ_ACK	0x21
#define OCI2C_CMD_READ_NACK	0x29
#define OCI2C_CMD_IACK		0x01

#define OCI2C_STAT_IF		0x01
#define OCI2C_STAT_TIP		0x02
#define OCI2C_STAT_ARBLOST	0x20
#define OCI2C_STAT_BUSY		0x40
#define OCI2C_STAT_NACK		0x80

#define STATE_DONE		0
#define STATE_START		1
#define STATE_WRITE		2
#define STATE_READ		3
#define STATE_ERROR		4

static inline void oc_setreg(struct ocores_i2c *i2c, int reg, u8 value)
{
	iowrite8(value, i2c->base + reg * i2c->regstep);
}

static inline u8 oc_getreg(struct ocores_i2c *i2c, int reg)
{
	return ioread8(i2c->base + reg * i2c->regstep);
}

static void ocores_process(struct ocores_i2c *i2c)
{
	struct i2c_msg *msg = i2c->msg;
	u8 stat = oc_getreg(i2c, OCI2C_STATUS);

	if ((i2c->state == STATE_DONE) || (i2c->state == STATE_ERROR)) {
		/* stop has been sent */
		oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK);
		wake_up(&i2c->wait);
		return;
	}

	/* error? */
	if (stat & OCI2C_STAT_ARBLOST) {
		i2c->state = STATE_ERROR;
		oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
		return;
	}

	if ((i2c->state == STATE_START) || (i2c->state == STATE_WRITE)) {
		i2c->state =
			(msg->flags & I2C_M_RD) ? STATE_READ : STATE_WRITE;

		if (stat & OCI2C_STAT_NACK) {
			i2c->state = STATE_ERROR;
			oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
			return;
		}
	} else
		msg->buf[i2c->pos++] = oc_getreg(i2c, OCI2C_DATA);

	/* end of msg? */
	if (i2c->pos == msg->len) {
		i2c->nmsgs--;
		i2c->msg++;
		i2c->pos = 0;
		msg = i2c->msg;

		if (i2c->nmsgs) {	/* end? */
			/* send start? */
			if (!(msg->flags & I2C_M_NOSTART)) {
				u8 addr = (msg->addr << 1);

				if (msg->flags & I2C_M_RD)
					addr |= 1;

				i2c->state = STATE_START;

				oc_setreg(i2c, OCI2C_DATA, addr);
				oc_setreg(i2c, OCI2C_CMD,  OCI2C_CMD_START);
				return;
			} else
				i2c->state = (msg->flags & I2C_M_RD)
					? STATE_READ : STATE_WRITE;
		} else {
			i2c->state = STATE_DONE;
			oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
			return;
		}
	}

	if (i2c->state == STATE_READ) {
		oc_setreg(i2c, OCI2C_CMD, i2c->pos == (msg->len-1) ?
			  OCI2C_CMD_READ_NACK : OCI2C_CMD_READ_ACK);
	} else {
		oc_setreg(i2c, OCI2C_DATA, msg->buf[i2c->pos++]);
		oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_WRITE);
	}
}

static irqreturn_t ocores_isr(int irq, void *dev_id)
{
	struct ocores_i2c *i2c = dev_id;

	ocores_process(i2c);

	return IRQ_HANDLED;
}

static int ocores_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
{
	struct ocores_i2c *i2c = i2c_get_adapdata(adap);

	i2c->msg = msgs;
	i2c->pos = 0;
	i2c->nmsgs = num;
	i2c->state = STATE_START;

	oc_setreg(i2c, OCI2C_DATA,
			(i2c->msg->addr << 1) |
			((i2c->msg->flags & I2C_M_RD) ? 1:0));

	oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START);

	if (wait_event_timeout(i2c->wait, (i2c->state == STATE_ERROR) ||
			       (i2c->state == STATE_DONE), HZ))
		return (i2c->state == STATE_DONE) ? num : -EIO;
	else
		return -ETIMEDOUT;
}

static void ocores_init(struct ocores_i2c *i2c)
{
	int prescale;
	u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);

	/* make sure the device is disabled */
	oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN));

	prescale = (i2c->clock_khz / (5*100)) - 1;
	oc_setreg(i2c, OCI2C_PRELOW, prescale & 0xff);
	oc_setreg(i2c, OCI2C_PREHIGH, prescale >> 8);

	/* Init the device */
	oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK);
	oc_setreg(i2c, OCI2C_CONTROL, ctrl | OCI2C_CTRL_IEN | OCI2C_CTRL_EN);
}


static u32 ocores_func(struct i2c_adapter *adap)
{
	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
}

static const struct i2c_algorithm ocores_algorithm = {
	.master_xfer	= ocores_xfer,
	.functionality	= ocores_func,
};

static struct i2c_adapter ocores_adapter = {
	.owner		= THIS_MODULE,
	.name		= "i2c-ocores",
	.class		= I2C_CLASS_HWMON | I2C_CLASS_SPD,
	.algo		= &ocores_algorithm,
};

#ifdef CONFIG_OF
static int ocores_i2c_of_probe(struct platform_device* pdev,
				struct ocores_i2c* i2c)
{
	const __be32* val;

	val = of_get_property(pdev->dev.of_node, "regstep", NULL);
	if (!val) {
		dev_err(&pdev->dev, "Missing required parameter 'regstep'");
		return -ENODEV;
	}
	i2c->regstep = be32_to_cpup(val);

	val = of_get_property(pdev->dev.of_node, "clock-frequency", NULL);
	if (!val) {
		dev_err(&pdev->dev,
			"Missing required parameter 'clock-frequency'");
		return -ENODEV;
	}
	i2c->clock_khz = be32_to_cpup(val) / 1000;

	return 0;
}
#else
#define ocores_i2c_of_probe(pdev,i2c) -ENODEV
#endif

static int __devinit ocores_i2c_probe(struct platform_device *pdev)
{
	struct ocores_i2c *i2c;
	struct ocores_i2c_platform_data *pdata;
	struct resource *res, *res2;
	int ret;
	int i;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res)
		return -ENODEV;

	res2 = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	if (!res2)
		return -ENODEV;

	i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
	if (!i2c)
		return -ENOMEM;

	if (!devm_request_mem_region(&pdev->dev, res->start,
				     resource_size(res), pdev->name)) {
		dev_err(&pdev->dev, "Memory region busy\n");
		return -EBUSY;
	}

	i2c->base = devm_ioremap_nocache(&pdev->dev, res->start,
					 resource_size(res));
	if (!i2c->base) {
		dev_err(&pdev->dev, "Unable to map registers\n");
		return -EIO;
	}

	pdata = pdev->dev.platform_data;
	if (pdata) {
		i2c->regstep = pdata->regstep;
		i2c->clock_khz = pdata->clock_khz;
	} else {
		ret = ocores_i2c_of_probe(pdev, i2c);
		if (ret)
			return ret;
	}

	ocores_init(i2c);

	init_waitqueue_head(&i2c->wait);
	ret = devm_request_irq(&pdev->dev, res2->start, ocores_isr, 0,
			       pdev->name, i2c);
	if (ret) {
		dev_err(&pdev->dev, "Cannot claim IRQ\n");
		return ret;
	}

	/* hook up driver to tree */
	platform_set_drvdata(pdev, i2c);
	i2c->adap = ocores_adapter;
	i2c_set_adapdata(&i2c->adap, i2c);
	i2c->adap.dev.parent = &pdev->dev;
	i2c->adap.dev.of_node = pdev->dev.of_node;

	/* add i2c adapter to i2c tree */
	ret = i2c_add_adapter(&i2c->adap);
	if (ret) {
		dev_err(&pdev->dev, "Failed to add adapter\n");
		return ret;
	}

	/* add in known devices to the bus */
	if (pdata) {
		for (i = 0; i < pdata->num_devices; i++)
			i2c_new_device(&i2c->adap, pdata->devices + i);
	} else {
		of_i2c_register_devices(&i2c->adap);
	}

	return 0;
}

static int __devexit ocores_i2c_remove(struct platform_device* pdev)
{
	struct ocores_i2c *i2c = platform_get_drvdata(pdev);

	/* disable i2c logic */
	oc_setreg(i2c, OCI2C_CONTROL, oc_getreg(i2c, OCI2C_CONTROL)
		  & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN));

	/* remove adapter & data */
	i2c_del_adapter(&i2c->adap);
	platform_set_drvdata(pdev, NULL);

	return 0;
}

#ifdef CONFIG_PM
static int ocores_i2c_suspend(struct platform_device *pdev, pm_message_t state)
{
	struct ocores_i2c *i2c = platform_get_drvdata(pdev);
	u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);

	/* make sure the device is disabled */
	oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN));

	return 0;
}

static int ocores_i2c_resume(struct platform_device *pdev)
{
	struct ocores_i2c *i2c = platform_get_drvdata(pdev);

	ocores_init(i2c);

	return 0;
}
#else
#define ocores_i2c_suspend	NULL
#define ocores_i2c_resume	NULL
#endif

static struct of_device_id ocores_i2c_match[] = {
	{ .compatible = "opencores,i2c-ocores", },
	{},
};
MODULE_DEVICE_TABLE(of, ocores_i2c_match);

static struct platform_driver ocores_i2c_driver = {
	.probe   = ocores_i2c_probe,
	.remove  = __devexit_p(ocores_i2c_remove),
	.suspend = ocores_i2c_suspend,
	.resume  = ocores_i2c_resume,
	.driver  = {
		.owner = THIS_MODULE,
		.name = "ocores-i2c",
		.of_match_table = ocores_i2c_match,
	},
};

module_platform_driver(ocores_i2c_driver);

MODULE_AUTHOR("Peter Korsgaard <jacmet@sunsite.dk>");
MODULE_DESCRIPTION("OpenCores I2C bus driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:ocores-i2c");
Commit	Line	Data
18f98b1e PK	1	/*
	2	* i2c-ocores.c: I2C bus driver for OpenCores I2C controller
	3	* (http://www.opencores.org/projects.cgi/web/i2c/overview).
	4	*
	5	* Peter Korsgaard <jacmet@sunsite.dk>
	6	*
	7	* This file is licensed under the terms of the GNU General Public License
	8	* version 2. This program is licensed "as is" without any warranty of any
	9	* kind, whether express or implied.
	10	*/
	11
d9240e61 JB	12	/*
	13	* Device tree configuration:
	14	*
	15	* Required properties:
	16	* - compatible : "opencores,i2c-ocores"
	17	* - reg : bus address start and address range size of device
	18	* - interrupts : interrupt number
	19	* - regstep : size of device registers in bytes
	20	* - clock-frequency : frequency of bus clock in Hz
	21	*
	22	* Example:
	23	*
	24	* i2c0: ocores@a0000000 {
	25	* compatible = "opencores,i2c-ocores";
	26	* reg = <0xa0000000 0x8>;
	27	* interrupts = <10>;
	28	*
	29	* regstep = <1>;
	30	* clock-frequency = <20000000>;
	31	*
	32	* -- Devices connected on this I2C bus get
	33	* -- defined here; address- and size-cells
	34	* -- apply to these child devices
	35	*
	36	* #address-cells = <1>;
	37	* #size-cells = <0>;
	38	*
	39	* dummy@60 {
	40	* compatible = "dummy";
	41	* reg = <60>;
	42	* };
	43	* };
	44	*
	45	*/
	46
18f98b1e PK	47	#include <linux/kernel.h>
18f98b1e PK	48	#include <linux/module.h>
18f98b1e PK	49	#include <linux/init.h>
	50	#include <linux/errno.h>
	51	#include <linux/platform_device.h>
	52	#include <linux/i2c.h>
	53	#include <linux/interrupt.h>
	54	#include <linux/wait.h>
	55	#include <linux/i2c-ocores.h>
5a0e3ad6	56	#include <linux/slab.h>
21782180	57	#include <linux/io.h>
a5063f16	58	#include <linux/of_i2c.h>
18f98b1e PK	59
	60	struct ocores_i2c {
	61	void __iomem *base;
	62	int regstep;
	63	wait_queue_head_t wait;
	64	struct i2c_adapter adap;
	65	struct i2c_msg *msg;
	66	int pos;
	67	int nmsgs;
	68	int state; /* see STATE_ */
2373c180	69	int clock_khz;
18f98b1e PK	70	};
	71
	72	/* registers */
	73	#define OCI2C_PRELOW 0
	74	#define OCI2C_PREHIGH 1
	75	#define OCI2C_CONTROL 2
	76	#define OCI2C_DATA 3
1ded969f PK	77	#define OCI2C_CMD 4 /* write only */
1ded969f PK	78	#define OCI2C_STATUS 4 /* read only, same address as OCI2C_CMD */
18f98b1e PK	79
	80	#define OCI2C_CTRL_IEN 0x40
	81	#define OCI2C_CTRL_EN 0x80
	82
	83	#define OCI2C_CMD_START 0x91
	84	#define OCI2C_CMD_STOP 0x41
	85	#define OCI2C_CMD_READ 0x21
	86	#define OCI2C_CMD_WRITE 0x11
	87	#define OCI2C_CMD_READ_ACK 0x21
	88	#define OCI2C_CMD_READ_NACK 0x29
	89	#define OCI2C_CMD_IACK 0x01
	90
	91	#define OCI2C_STAT_IF 0x01
	92	#define OCI2C_STAT_TIP 0x02
	93	#define OCI2C_STAT_ARBLOST 0x20
	94	#define OCI2C_STAT_BUSY 0x40
	95	#define OCI2C_STAT_NACK 0x80
	96
	97	#define STATE_DONE 0
	98	#define STATE_START 1
	99	#define STATE_WRITE 2
	100	#define STATE_READ 3
	101	#define STATE_ERROR 4
	102
	103	static inline void oc_setreg(struct ocores_i2c *i2c, int reg, u8 value)
	104	{
	105	iowrite8(value, i2c->base + reg * i2c->regstep);
	106	}
	107
	108	static inline u8 oc_getreg(struct ocores_i2c *i2c, int reg)
	109	{
	110	return ioread8(i2c->base + reg * i2c->regstep);
	111	}
	112
	113	static void ocores_process(struct ocores_i2c *i2c)
	114	{
	115	struct i2c_msg *msg = i2c->msg;
	116	u8 stat = oc_getreg(i2c, OCI2C_STATUS);
	117
	118	if ((i2c->state == STATE_DONE) \|\| (i2c->state == STATE_ERROR)) {
	119	/* stop has been sent */
	120	oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK);
	121	wake_up(&i2c->wait);
	122	return;
	123	}
	124
	125	/* error? */
	126	if (stat & OCI2C_STAT_ARBLOST) {
	127	i2c->state = STATE_ERROR;
	128	oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
	129	return;
	130	}
	131
	132	if ((i2c->state == STATE_START) \|\| (i2c->state == STATE_WRITE)) {
	133	i2c->state =
	134	(msg->flags & I2C_M_RD) ? STATE_READ : STATE_WRITE;
	135
	136	if (stat & OCI2C_STAT_NACK) {
	137	i2c->state = STATE_ERROR;
	138	oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
	139	return;
	140	}
	141	} else
	142	msg->buf[i2c->pos++] = oc_getreg(i2c, OCI2C_DATA);
143
144	/* end of msg? */
145	if (i2c->pos == msg->len) {
146	i2c->nmsgs--;
147	i2c->msg++;
148	i2c->pos = 0;
149	msg = i2c->msg;
150
151	if (i2c->nmsgs) { /* end? */
152	/* send start? */
153	if (!(msg->flags & I2C_M_NOSTART)) {
154	u8 addr = (msg->addr << 1);
155
156	if (msg->flags & I2C_M_RD)
157	addr \|= 1;
158
159	i2c->state = STATE_START;
160
161	oc_setreg(i2c, OCI2C_DATA, addr);
162	oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START);
163	return;
164	} else
165	i2c->state = (msg->flags & I2C_M_RD)
166	? STATE_READ : STATE_WRITE;
167	} else {
168	i2c->state = STATE_DONE;
169	oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
170	return;
171	}
172	}
173
174	if (i2c->state == STATE_READ) {
175	oc_setreg(i2c, OCI2C_CMD, i2c->pos == (msg->len-1) ?
176	OCI2C_CMD_READ_NACK : OCI2C_CMD_READ_ACK);
177	} else {
178	oc_setreg(i2c, OCI2C_DATA, msg->buf[i2c->pos++]);
179	oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_WRITE);
180	}
181	}
182
7d12e780	183	static irqreturn_t ocores_isr(int irq, void *dev_id)
18f98b1e PK	184	{
	185	struct ocores_i2c *i2c = dev_id;
	186
	187	ocores_process(i2c);
	188
	189	return IRQ_HANDLED;
	190	}
	191
	192	static int ocores_xfer(struct i2c_adapter adap, struct i2c_msg msgs, int num)
	193	{
	194	struct ocores_i2c *i2c = i2c_get_adapdata(adap);
	195
	196	i2c->msg = msgs;
	197	i2c->pos = 0;
	198	i2c->nmsgs = num;
	199	i2c->state = STATE_START;
	200
	201	oc_setreg(i2c, OCI2C_DATA,
	202	(i2c->msg->addr << 1) \|
	203	((i2c->msg->flags & I2C_M_RD) ? 1:0));
	204
	205	oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START);
	206
	207	if (wait_event_timeout(i2c->wait, (i2c->state == STATE_ERROR) \|\|
	208	(i2c->state == STATE_DONE), HZ))
	209	return (i2c->state == STATE_DONE) ? num : -EIO;
	210	else
	211	return -ETIMEDOUT;
	212	}
	213
2373c180	214	static void ocores_init(struct ocores_i2c *i2c)
18f98b1e PK	215	{
	216	int prescale;
	217	u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
	218
	219	/* make sure the device is disabled */
	220	oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~(OCI2C_CTRL_EN\|OCI2C_CTRL_IEN));
	221
2373c180	222	prescale = (i2c->clock_khz / (5*100)) - 1;
18f98b1e PK	223	oc_setreg(i2c, OCI2C_PRELOW, prescale & 0xff);
	224	oc_setreg(i2c, OCI2C_PREHIGH, prescale >> 8);
	225
	226	/* Init the device */
	227	oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK);
	228	oc_setreg(i2c, OCI2C_CONTROL, ctrl \| OCI2C_CTRL_IEN \| OCI2C_CTRL_EN);
	229	}
	230
	231
	232	static u32 ocores_func(struct i2c_adapter *adap)
	233	{
	234	return I2C_FUNC_I2C \| I2C_FUNC_SMBUS_EMUL;
	235	}
	236
8f9082c5	237	static const struct i2c_algorithm ocores_algorithm = {
18f98b1e PK	238	.master_xfer = ocores_xfer,
	239	.functionality = ocores_func,
	240	};
	241
	242	static struct i2c_adapter ocores_adapter = {
	243	.owner = THIS_MODULE,
	244	.name = "i2c-ocores",
3401b2ff	245	.class = I2C_CLASS_HWMON \| I2C_CLASS_SPD,
18f98b1e	246	.algo = &ocores_algorithm,
18f98b1e PK	247	};
18f98b1e PK	248
049bb69d JB	249	#ifdef CONFIG_OF
	250	static int ocores_i2c_of_probe(struct platform_device* pdev,
	251	struct ocores_i2c* i2c)
	252	{
12c38323	253	const __be32* val;
049bb69d JB	254
	255	val = of_get_property(pdev->dev.of_node, "regstep", NULL);
	256	if (!val) {
	257	dev_err(&pdev->dev, "Missing required parameter 'regstep'");
	258	return -ENODEV;
	259	}
	260	i2c->regstep = be32_to_cpup(val);
	261
	262	val = of_get_property(pdev->dev.of_node, "clock-frequency", NULL);
	263	if (!val) {
	264	dev_err(&pdev->dev,
	265	"Missing required parameter 'clock-frequency'");
	266	return -ENODEV;
	267	}
	268	i2c->clock_khz = be32_to_cpup(val) / 1000;
	269
	270	return 0;
	271	}
	272	#else
	273	#define ocores_i2c_of_probe(pdev,i2c) -ENODEV
	274	#endif
18f98b1e PK	275
	276	static int __devinit ocores_i2c_probe(struct platform_device *pdev)
	277	{
	278	struct ocores_i2c *i2c;
	279	struct ocores_i2c_platform_data *pdata;
	280	struct resource res, res2;
	281	int ret;
dd14be4c	282	int i;
18f98b1e PK	283
	284	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	285	if (!res)
	286	return -ENODEV;
	287
	288	res2 = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	289	if (!res2)
	290	return -ENODEV;
	291
47def5b8	292	i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
18f98b1e PK	293	if (!i2c)
	294	return -ENOMEM;
	295
47def5b8 JB	296	if (!devm_request_mem_region(&pdev->dev, res->start,
47def5b8 JB	297	resource_size(res), pdev->name)) {
18f98b1e	298	dev_err(&pdev->dev, "Memory region busy\n");
47def5b8	299	return -EBUSY;
18f98b1e PK	300	}
18f98b1e PK	301
47def5b8 JB	302	i2c->base = devm_ioremap_nocache(&pdev->dev, res->start,
47def5b8 JB	303	resource_size(res));
18f98b1e PK	304	if (!i2c->base) {
18f98b1e PK	305	dev_err(&pdev->dev, "Unable to map registers\n");
47def5b8	306	return -EIO;
18f98b1e PK	307	}
18f98b1e PK	308
3271d382	309	pdata = pdev->dev.platform_data;
049bb69d JB	310	if (pdata) {
	311	i2c->regstep = pdata->regstep;
	312	i2c->clock_khz = pdata->clock_khz;
	313	} else {
	314	ret = ocores_i2c_of_probe(pdev, i2c);
	315	if (ret)
	316	return ret;
	317	}
	318
2373c180	319	ocores_init(i2c);
18f98b1e PK	320
18f98b1e PK	321	init_waitqueue_head(&i2c->wait);
47def5b8 JB	322	ret = devm_request_irq(&pdev->dev, res2->start, ocores_isr, 0,
47def5b8 JB	323	pdev->name, i2c);
18f98b1e PK	324	if (ret) {
18f98b1e PK	325	dev_err(&pdev->dev, "Cannot claim IRQ\n");
47def5b8	326	return ret;
18f98b1e PK	327	}
	328
	329	/* hook up driver to tree */
	330	platform_set_drvdata(pdev, i2c);
	331	i2c->adap = ocores_adapter;
	332	i2c_set_adapdata(&i2c->adap, i2c);
	333	i2c->adap.dev.parent = &pdev->dev;
049bb69d	334	i2c->adap.dev.of_node = pdev->dev.of_node;
18f98b1e PK	335
	336	/* add i2c adapter to i2c tree */
	337	ret = i2c_add_adapter(&i2c->adap);
	338	if (ret) {
	339	dev_err(&pdev->dev, "Failed to add adapter\n");
47def5b8	340	return ret;
18f98b1e PK	341	}
18f98b1e PK	342
dd14be4c	343	/* add in known devices to the bus */
049bb69d JB	344	if (pdata) {
	345	for (i = 0; i < pdata->num_devices; i++)
	346	i2c_new_device(&i2c->adap, pdata->devices + i);
a5063f16 GR	347	} else {
a5063f16 GR	348	of_i2c_register_devices(&i2c->adap);
049bb69d	349	}
dd14be4c	350
18f98b1e	351	return 0;
18f98b1e PK	352	}
	353
	354	static int __devexit ocores_i2c_remove(struct platform_device* pdev)
	355	{
	356	struct ocores_i2c *i2c = platform_get_drvdata(pdev);
18f98b1e PK	357
	358	/* disable i2c logic */
	359	oc_setreg(i2c, OCI2C_CONTROL, oc_getreg(i2c, OCI2C_CONTROL)
	360	& ~(OCI2C_CTRL_EN\|OCI2C_CTRL_IEN));
	361
	362	/* remove adapter & data */
	363	i2c_del_adapter(&i2c->adap);
	364	platform_set_drvdata(pdev, NULL);
	365
18f98b1e PK	366	return 0;
	367	}
	368
2373c180 ML	369	#ifdef CONFIG_PM
	370	static int ocores_i2c_suspend(struct platform_device *pdev, pm_message_t state)
	371	{
	372	struct ocores_i2c *i2c = platform_get_drvdata(pdev);
	373	u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
	374
	375	/* make sure the device is disabled */
	376	oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~(OCI2C_CTRL_EN\|OCI2C_CTRL_IEN));
	377
	378	return 0;
	379	}
	380
	381	static int ocores_i2c_resume(struct platform_device *pdev)
	382	{
	383	struct ocores_i2c *i2c = platform_get_drvdata(pdev);
	384
	385	ocores_init(i2c);
	386
	387	return 0;
	388	}
	389	#else
	390	#define ocores_i2c_suspend NULL
	391	#define ocores_i2c_resume NULL
	392	#endif
	393
049bb69d	394	static struct of_device_id ocores_i2c_match[] = {
c9e358df GL	395	{ .compatible = "opencores,i2c-ocores", },
c9e358df GL	396	{},
049bb69d JB	397	};
049bb69d JB	398	MODULE_DEVICE_TABLE(of, ocores_i2c_match);
049bb69d	399
18f98b1e	400	static struct platform_driver ocores_i2c_driver = {
2373c180 ML	401	.probe = ocores_i2c_probe,
	402	.remove = __devexit_p(ocores_i2c_remove),
	403	.suspend = ocores_i2c_suspend,
	404	.resume = ocores_i2c_resume,
	405	.driver = {
18f98b1e PK	406	.owner = THIS_MODULE,
18f98b1e PK	407	.name = "ocores-i2c",
c9e358df	408	.of_match_table = ocores_i2c_match,
18f98b1e PK	409	},
	410	};
	411
a3664b51	412	module_platform_driver(ocores_i2c_driver);
18f98b1e PK	413
	414	MODULE_AUTHOR("Peter Korsgaard <jacmet@sunsite.dk>");
	415	MODULE_DESCRIPTION("OpenCores I2C bus driver");
	416	MODULE_LICENSE("GPL");
a3664b51	417	MODULE_ALIAS("platform:ocores-i2c");