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Merge tag 'dax-locking-for-4.7' of git://git.kernel.org/pub/scm/linux/kernel/git...
[deliverable/linux.git] / drivers / i2c / busses / i2c-octeon.c
CommitLineData
85660f43
RB		 1/*
2 * (C) Copyright 2009-2010
3 * Nokia Siemens Networks, michael.lawnick.ext@nsn.com
4 *
dfcd8212 5 * Portions Copyright (C) 2010 - 2016 Cavium, Inc.
85660f43
RB		 6 *
7 * This is a driver for the i2c adapter in Cavium Networks' OCTEON processors.
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
4729cbe0 14#include <linux/atomic.h>
f353a218
DD		 15#include <linux/platform_device.h>
16#include <linux/interrupt.h>
85660f43
RB		 17#include <linux/kernel.h>
18#include <linux/module.h>
f353a218 19#include <linux/delay.h>
85660f43 20#include <linux/sched.h>
5a0e3ad6 21#include <linux/slab.h>
85660f43 22#include <linux/i2c.h>
f353a218
DD		 23#include <linux/io.h>
24#include <linux/of.h>
85660f43
RB		 25
26#include <asm/octeon/octeon.h>
27
28#define DRV_NAME "i2c-octeon"
29
dfcd8212
JG		 30/* Register offsets */
31#define SW_TWSI 0x00
32#define TWSI_INT 0x10
d1fbff89 33#define SW_TWSI_EXT 0x18
85660f43
RB		 34
35/* Controller command patterns */
dfcd8212 36#define SW_TWSI_V BIT_ULL(63) /* Valid bit */
d1fbff89 37#define SW_TWSI_EIA BIT_ULL(61) /* Extended internal address */
dfcd8212 38#define SW_TWSI_R BIT_ULL(56) /* Result or read bit */
d1fbff89
DD		 39#define SW_TWSI_SOVR BIT_ULL(55) /* Size override */
40#define SW_TWSI_SIZE_SHIFT 52
41#define SW_TWSI_ADDR_SHIFT 40
42#define SW_TWSI_IA_SHIFT 32 /* Internal address */
dfcd8212
JG		 43
44/* Controller opcode word (bits 60:57) */
45#define SW_TWSI_OP_SHIFT 57
d1fbff89
DD		 46#define SW_TWSI_OP_7 (0ULL << SW_TWSI_OP_SHIFT)
47#define SW_TWSI_OP_7_IA (1ULL << SW_TWSI_OP_SHIFT)
48#define SW_TWSI_OP_10 (2ULL << SW_TWSI_OP_SHIFT)
49#define SW_TWSI_OP_10_IA (3ULL << SW_TWSI_OP_SHIFT)
dfcd8212
JG		 50#define SW_TWSI_OP_TWSI_CLK (4ULL << SW_TWSI_OP_SHIFT)
51#define SW_TWSI_OP_EOP (6ULL << SW_TWSI_OP_SHIFT) /* Extended opcode */
52
53/* Controller extended opcode word (bits 34:32) */
54#define SW_TWSI_EOP_SHIFT 32
55#define SW_TWSI_EOP_TWSI_DATA (SW_TWSI_OP_EOP | 1ULL << SW_TWSI_EOP_SHIFT)
56#define SW_TWSI_EOP_TWSI_CTL (SW_TWSI_OP_EOP | 2ULL << SW_TWSI_EOP_SHIFT)
57#define SW_TWSI_EOP_TWSI_CLKCTL (SW_TWSI_OP_EOP | 3ULL << SW_TWSI_EOP_SHIFT)
58#define SW_TWSI_EOP_TWSI_STAT (SW_TWSI_OP_EOP | 3ULL << SW_TWSI_EOP_SHIFT)
59#define SW_TWSI_EOP_TWSI_RST (SW_TWSI_OP_EOP | 7ULL << SW_TWSI_EOP_SHIFT)
85660f43
RB		 60
61/* Controller command and status bits */
d1fbff89 62#define TWSI_CTL_CE 0x80 /* High level controller enable */
dfcd8212
JG		 63#define TWSI_CTL_ENAB 0x40 /* Bus enable */
64#define TWSI_CTL_STA 0x20 /* Master-mode start, HW clears when done */
65#define TWSI_CTL_STP 0x10 /* Master-mode stop, HW clears when done */
66#define TWSI_CTL_IFLG 0x08 /* HW event, SW writes 0 to ACK */
67#define TWSI_CTL_AAK 0x04 /* Assert ACK */
85660f43 68
b4c715d0
JG		 69/* Status values */
70#define STAT_ERROR 0x00
dfcd8212 71#define STAT_START 0x08
b4c715d0 72#define STAT_REP_START 0x10
dfcd8212 73#define STAT_TXADDR_ACK 0x18
b4c715d0 74#define STAT_TXADDR_NAK 0x20
dfcd8212 75#define STAT_TXDATA_ACK 0x28
b4c715d0
JG		 76#define STAT_TXDATA_NAK 0x30
77#define STAT_LOST_ARB_38 0x38
dfcd8212 78#define STAT_RXADDR_ACK 0x40
b4c715d0 79#define STAT_RXADDR_NAK 0x48
dfcd8212 80#define STAT_RXDATA_ACK 0x50
b4c715d0
JG		 81#define STAT_RXDATA_NAK 0x58
82#define STAT_SLAVE_60 0x60
83#define STAT_LOST_ARB_68 0x68
84#define STAT_SLAVE_70 0x70
85#define STAT_LOST_ARB_78 0x78
86#define STAT_SLAVE_80 0x80
87#define STAT_SLAVE_88 0x88
88#define STAT_GENDATA_ACK 0x90
89#define STAT_GENDATA_NAK 0x98
90#define STAT_SLAVE_A0 0xA0
91#define STAT_SLAVE_A8 0xA8
92#define STAT_LOST_ARB_B0 0xB0
93#define STAT_SLAVE_LOST 0xB8
94#define STAT_SLAVE_NAK 0xC0
95#define STAT_SLAVE_ACK 0xC8
96#define STAT_AD2W_ACK 0xD0
97#define STAT_AD2W_NAK 0xD8
dfcd8212
JG		 98#define STAT_IDLE 0xF8
99
100/* TWSI_INT values */
d1fbff89
DD		 101#define TWSI_INT_ST_INT BIT_ULL(0)
102#define TWSI_INT_TS_INT BIT_ULL(1)
103#define TWSI_INT_CORE_INT BIT_ULL(2)
104#define TWSI_INT_ST_EN BIT_ULL(4)
105#define TWSI_INT_TS_EN BIT_ULL(5)
dfcd8212
JG		 106#define TWSI_INT_CORE_EN BIT_ULL(6)
107#define TWSI_INT_SDA_OVR BIT_ULL(8)
108#define TWSI_INT_SCL_OVR BIT_ULL(9)
c981e34e
JG		 109#define TWSI_INT_SDA BIT_ULL(10)
110#define TWSI_INT_SCL BIT_ULL(11)
85660f43 111
1bb1ff3e
PS		 112#define I2C_OCTEON_EVENT_WAIT 80 /* microseconds */
113
85660f43
RB		 114struct octeon_i2c {
115 wait_queue_head_t queue;
116 struct i2c_adapter adap;
117 int irq;
4729cbe0 118 int hlc_irq; /* For cn7890 only */
f353a218 119 u32 twsi_freq;
85660f43 120 int sys_freq;
85660f43 121 void __iomem *twsi_base;
85660f43 122 struct device *dev;
d1fbff89 123 bool hlc_enabled;
fe600cf6
DD		 124 bool broken_irq_mode;
125 bool broken_irq_check;
4729cbe0
JG		 126 void (*int_enable)(struct octeon_i2c *);
127 void (*int_disable)(struct octeon_i2c *);
128 void (*hlc_int_enable)(struct octeon_i2c *);
129 void (*hlc_int_disable)(struct octeon_i2c *);
130 atomic_t int_enable_cnt;
131 atomic_t hlc_int_enable_cnt;
85660f43
RB		 132};
133
30c24b25
PS		 134static void octeon_i2c_writeq_flush(u64 val, void __iomem *addr)
135{
136 __raw_writeq(val, addr);
137 __raw_readq(addr); /* wait for write to land */
138}
139
85660f43 140/**
9cb9480e 141 * octeon_i2c_reg_write - write an I2C core register
bd7784c2
JG		 142 * @i2c: The struct octeon_i2c
143 * @eop_reg: Register selector
144 * @data: Value to be written
85660f43
RB		 145 *
146 * The I2C core registers are accessed indirectly via the SW_TWSI CSR.
147 */
9cb9480e 148static void octeon_i2c_reg_write(struct octeon_i2c *i2c, u64 eop_reg, u8 data)
85660f43
RB		 149{
150 u64 tmp;
151
152 __raw_writeq(SW_TWSI_V | eop_reg | data, i2c->twsi_base + SW_TWSI);
153 do {
154 tmp = __raw_readq(i2c->twsi_base + SW_TWSI);
155 } while ((tmp & SW_TWSI_V) != 0);
156}
157
c57db709
JG		 158#define octeon_i2c_ctl_write(i2c, val) \
159 octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CTL, val)
160#define octeon_i2c_data_write(i2c, val) \
161 octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_DATA, val)
162
85660f43 163/**
9cb9480e 164 * octeon_i2c_reg_read - read lower bits of an I2C core register
bd7784c2
JG		 165 * @i2c: The struct octeon_i2c
166 * @eop_reg: Register selector
85660f43
RB		 167 *
168 * Returns the data.
169 *
170 * The I2C core registers are accessed indirectly via the SW_TWSI CSR.
171 */
9cb9480e 172static u8 octeon_i2c_reg_read(struct octeon_i2c *i2c, u64 eop_reg)
85660f43
RB		 173{
174 u64 tmp;
175
176 __raw_writeq(SW_TWSI_V | eop_reg | SW_TWSI_R, i2c->twsi_base + SW_TWSI);
177 do {
178 tmp = __raw_readq(i2c->twsi_base + SW_TWSI);
179 } while ((tmp & SW_TWSI_V) != 0);
180
181 return tmp & 0xFF;
182}
183
c57db709
JG		 184#define octeon_i2c_ctl_read(i2c) \
185 octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_CTL)
186#define octeon_i2c_data_read(i2c) \
187 octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_DATA)
188#define octeon_i2c_stat_read(i2c) \
189 octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_STAT)
190
c981e34e
JG		 191/**
192 * octeon_i2c_read_int - read the TWSI_INT register
193 * @i2c: The struct octeon_i2c
194 *
195 * Returns the value of the register.
196 */
197static u64 octeon_i2c_read_int(struct octeon_i2c *i2c)
198{
199 return __raw_readq(i2c->twsi_base + TWSI_INT);
200}
201
85660f43
RB		 202/**
203 * octeon_i2c_write_int - write the TWSI_INT register
bd7784c2
JG		 204 * @i2c: The struct octeon_i2c
205 * @data: Value to be written
85660f43
RB		 206 */
207static void octeon_i2c_write_int(struct octeon_i2c *i2c, u64 data)
208{
30c24b25 209 octeon_i2c_writeq_flush(data, i2c->twsi_base + TWSI_INT);
85660f43
RB		 210}
211
212/**
bd7784c2
JG		 213 * octeon_i2c_int_enable - enable the CORE interrupt
214 * @i2c: The struct octeon_i2c
85660f43
RB		 215 *
216 * The interrupt will be asserted when there is non-STAT_IDLE state in
217 * the SW_TWSI_EOP_TWSI_STAT register.
218 */
219static void octeon_i2c_int_enable(struct octeon_i2c *i2c)
220{
dfcd8212 221 octeon_i2c_write_int(i2c, TWSI_INT_CORE_EN);
85660f43
RB		 222}
223
bd7784c2 224/* disable the CORE interrupt */
85660f43
RB		 225static void octeon_i2c_int_disable(struct octeon_i2c *i2c)
226{
dfcd8212 227 /* clear TS/ST/IFLG events */
85660f43
RB		 228 octeon_i2c_write_int(i2c, 0);
229}
230
4729cbe0
JG		 231/**
232 * octeon_i2c_int_enable78 - enable the CORE interrupt
233 * @i2c: The struct octeon_i2c
234 *
235 * The interrupt will be asserted when there is non-STAT_IDLE state in the
236 * SW_TWSI_EOP_TWSI_STAT register.
237 */
238static void octeon_i2c_int_enable78(struct octeon_i2c *i2c)
239{
240 atomic_inc_return(&i2c->int_enable_cnt);
241 enable_irq(i2c->irq);
242}
243
244static void __octeon_i2c_irq_disable(atomic_t *cnt, int irq)
245{
246 int count;
247
248 /*
249 * The interrupt can be disabled in two places, but we only
250 * want to make the disable_irq_nosync() call once, so keep
251 * track with the atomic variable.
252 */
253 count = atomic_dec_if_positive(cnt);
254 if (count >= 0)
255 disable_irq_nosync(irq);
256}
257
258/* disable the CORE interrupt */
259static void octeon_i2c_int_disable78(struct octeon_i2c *i2c)
260{
261 __octeon_i2c_irq_disable(&i2c->int_enable_cnt, i2c->irq);
262}
263
264/**
265 * octeon_i2c_hlc_int_enable78 - enable the ST interrupt
266 * @i2c: The struct octeon_i2c
267 *
268 * The interrupt will be asserted when there is non-STAT_IDLE state in
269 * the SW_TWSI_EOP_TWSI_STAT register.
270 */
271static void octeon_i2c_hlc_int_enable78(struct octeon_i2c *i2c)
272{
273 atomic_inc_return(&i2c->hlc_int_enable_cnt);
274 enable_irq(i2c->hlc_irq);
275}
276
277/* disable the ST interrupt */
278static void octeon_i2c_hlc_int_disable78(struct octeon_i2c *i2c)
279{
280 __octeon_i2c_irq_disable(&i2c->hlc_int_enable_cnt, i2c->hlc_irq);
281}
282
d1fbff89
DD		 283/*
284 * Cleanup low-level state & enable high-level controller.
285 */
286static void octeon_i2c_hlc_enable(struct octeon_i2c *i2c)
287{
288 int try = 0;
289 u64 val;
290
291 if (i2c->hlc_enabled)
292 return;
293 i2c->hlc_enabled = true;
294
295 while (1) {
296 val = octeon_i2c_ctl_read(i2c);
297 if (!(val & (TWSI_CTL_STA | TWSI_CTL_STP)))
298 break;
299
300 /* clear IFLG event */
301 if (val & TWSI_CTL_IFLG)
302 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);
303
304 if (try++ > 100) {
305 pr_err("%s: giving up\n", __func__);
306 break;
307 }
308
309 /* spin until any start/stop has finished */
310 udelay(10);
311 }
312 octeon_i2c_ctl_write(i2c, TWSI_CTL_CE | TWSI_CTL_AAK | TWSI_CTL_ENAB);
313}
314
315static void octeon_i2c_hlc_disable(struct octeon_i2c *i2c)
316{
317 if (!i2c->hlc_enabled)
318 return;
319
320 i2c->hlc_enabled = false;
321 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);
322}
323
bd7784c2 324/* interrupt service routine */
85660f43
RB		 325static irqreturn_t octeon_i2c_isr(int irq, void *dev_id)
326{
327 struct octeon_i2c *i2c = dev_id;
328
4729cbe0
JG		 329 i2c->int_disable(i2c);
330 wake_up(&i2c->queue);
331
332 return IRQ_HANDLED;
333}
334
335/* HLC interrupt service routine */
336static irqreturn_t octeon_i2c_hlc_isr78(int irq, void *dev_id)
337{
338 struct octeon_i2c *i2c = dev_id;
339
340 i2c->hlc_int_disable(i2c);
2637e5fd 341 wake_up(&i2c->queue);
85660f43
RB		 342
343 return IRQ_HANDLED;
344}
345
1bb1ff3e 346static bool octeon_i2c_test_iflg(struct octeon_i2c *i2c)
85660f43 347{
b69e5c67 348 return (octeon_i2c_ctl_read(i2c) & TWSI_CTL_IFLG);
85660f43
RB		 349}
350
1bb1ff3e
PS		 351static bool octeon_i2c_test_ready(struct octeon_i2c *i2c, bool *first)
352{
353 if (octeon_i2c_test_iflg(i2c))
354 return true;
355
356 if (*first) {
357 *first = false;
358 return false;
359 }
360
361 /*
362 * IRQ has signaled an event but IFLG hasn't changed.
363 * Sleep and retry once.
364 */
365 usleep_range(I2C_OCTEON_EVENT_WAIT, 2 * I2C_OCTEON_EVENT_WAIT);
366 return octeon_i2c_test_iflg(i2c);
367}
368
85660f43 369/**
bd7784c2
JG		 370 * octeon_i2c_wait - wait for the IFLG to be set
371 * @i2c: The struct octeon_i2c
85660f43
RB		 372 *
373 * Returns 0 on success, otherwise a negative errno.
374 */
375static int octeon_i2c_wait(struct octeon_i2c *i2c)
376{
dfcd8212 377 long time_left;
1bb1ff3e 378 bool first = 1;
85660f43 379
fe600cf6
DD		 380 /*
381 * Some chip revisions don't assert the irq in the interrupt
382 * controller. So we must poll for the IFLG change.
383 */
384 if (i2c->broken_irq_mode) {
385 u64 end = get_jiffies_64() + i2c->adap.timeout;
386
387 while (!octeon_i2c_test_iflg(i2c) &&
388 time_before64(get_jiffies_64(), end))
389 usleep_range(I2C_OCTEON_EVENT_WAIT / 2, I2C_OCTEON_EVENT_WAIT);
390
391 return octeon_i2c_test_iflg(i2c) ? 0 : -ETIMEDOUT;
392 }
393
4729cbe0 394 i2c->int_enable(i2c);
1bb1ff3e 395 time_left = wait_event_timeout(i2c->queue, octeon_i2c_test_ready(i2c, &first),
dfcd8212 396 i2c->adap.timeout);
4729cbe0 397 i2c->int_disable(i2c);
fe600cf6
DD		 398
399 if (i2c->broken_irq_check && !time_left &&
400 octeon_i2c_test_iflg(i2c)) {
401 dev_err(i2c->dev, "broken irq connection detected, switching to polling mode.\n");
402 i2c->broken_irq_mode = true;
403 return 0;
404 }
405
1bb1ff3e 406 if (!time_left)
cc33e542 407 return -ETIMEDOUT;
85660f43
RB		 408
409 return 0;
410}
411
b4c715d0
JG		 412static int octeon_i2c_check_status(struct octeon_i2c *i2c, int final_read)
413{
414 u8 stat = octeon_i2c_stat_read(i2c);
415
416 switch (stat) {
417 /* Everything is fine */
418 case STAT_IDLE:
419 case STAT_AD2W_ACK:
420 case STAT_RXADDR_ACK:
421 case STAT_TXADDR_ACK:
422 case STAT_TXDATA_ACK:
423 return 0;
424
425 /* ACK allowed on pre-terminal bytes only */
426 case STAT_RXDATA_ACK:
427 if (!final_read)
428 return 0;
429 return -EIO;
430
431 /* NAK allowed on terminal byte only */
432 case STAT_RXDATA_NAK:
433 if (final_read)
434 return 0;
435 return -EIO;
436
437 /* Arbitration lost */
438 case STAT_LOST_ARB_38:
439 case STAT_LOST_ARB_68:
440 case STAT_LOST_ARB_78:
441 case STAT_LOST_ARB_B0:
442 return -EAGAIN;
443
444 /* Being addressed as slave, should back off & listen */
445 case STAT_SLAVE_60:
446 case STAT_SLAVE_70:
447 case STAT_GENDATA_ACK:
448 case STAT_GENDATA_NAK:
449 return -EOPNOTSUPP;
450
451 /* Core busy as slave */
452 case STAT_SLAVE_80:
453 case STAT_SLAVE_88:
454 case STAT_SLAVE_A0:
455 case STAT_SLAVE_A8:
456 case STAT_SLAVE_LOST:
457 case STAT_SLAVE_NAK:
458 case STAT_SLAVE_ACK:
459 return -EOPNOTSUPP;
460
461 case STAT_TXDATA_NAK:
462 return -EIO;
463 case STAT_TXADDR_NAK:
464 case STAT_RXADDR_NAK:
465 case STAT_AD2W_NAK:
466 return -ENXIO;
467 default:
468 dev_err(i2c->dev, "unhandled state: %d\n", stat);
469 return -EIO;
470 }
471}
472
1bb1ff3e
PS		 473static bool octeon_i2c_hlc_test_valid(struct octeon_i2c *i2c)
474{
475 return (__raw_readq(i2c->twsi_base + SW_TWSI) & SW_TWSI_V) == 0;
476}
477
478static bool octeon_i2c_hlc_test_ready(struct octeon_i2c *i2c, bool *first)
d1fbff89 479{
1bb1ff3e
PS		 480 /* check if valid bit is cleared */
481 if (octeon_i2c_hlc_test_valid(i2c))
482 return true;
d1fbff89 483
1bb1ff3e
PS		 484 if (*first) {
485 *first = false;
486 return false;
487 }
488
489 /*
490 * IRQ has signaled an event but valid bit isn't cleared.
491 * Sleep and retry once.
492 */
493 usleep_range(I2C_OCTEON_EVENT_WAIT, 2 * I2C_OCTEON_EVENT_WAIT);
494 return octeon_i2c_hlc_test_valid(i2c);
d1fbff89
DD		 495}
496
497static void octeon_i2c_hlc_int_enable(struct octeon_i2c *i2c)
498{
499 octeon_i2c_write_int(i2c, TWSI_INT_ST_EN);
500}
501
502static void octeon_i2c_hlc_int_clear(struct octeon_i2c *i2c)
503{
504 /* clear ST/TS events, listen for neither */
505 octeon_i2c_write_int(i2c, TWSI_INT_ST_INT | TWSI_INT_TS_INT);
506}
507
508/**
509 * octeon_i2c_hlc_wait - wait for an HLC operation to complete
510 * @i2c: The struct octeon_i2c
511 *
512 * Returns 0 on success, otherwise -ETIMEDOUT.
513 */
514static int octeon_i2c_hlc_wait(struct octeon_i2c *i2c)
515{
1bb1ff3e 516 bool first = 1;
d1fbff89
DD		 517 int time_left;
518
fe600cf6
DD		 519 /*
520 * Some cn38xx boards don't assert the irq in the interrupt
521 * controller. So we must poll for the valid bit change.
522 */
523 if (i2c->broken_irq_mode) {
524 u64 end = get_jiffies_64() + i2c->adap.timeout;
525
526 while (!octeon_i2c_hlc_test_valid(i2c) &&
527 time_before64(get_jiffies_64(), end))
528 usleep_range(I2C_OCTEON_EVENT_WAIT / 2, I2C_OCTEON_EVENT_WAIT);
529
530 return octeon_i2c_hlc_test_valid(i2c) ? 0 : -ETIMEDOUT;
531 }
532
4729cbe0 533 i2c->hlc_int_enable(i2c);
d1fbff89 534 time_left = wait_event_timeout(i2c->queue,
1bb1ff3e 535 octeon_i2c_hlc_test_ready(i2c, &first),
d1fbff89 536 i2c->adap.timeout);
4729cbe0 537 i2c->hlc_int_disable(i2c);
fe600cf6 538 if (!time_left)
d1fbff89 539 octeon_i2c_hlc_int_clear(i2c);
fe600cf6
DD		 540
541 if (i2c->broken_irq_check && !time_left &&
542 octeon_i2c_hlc_test_valid(i2c)) {
543 dev_err(i2c->dev, "broken irq connection detected, switching to polling mode.\n");
544 i2c->broken_irq_mode = true;
545 return 0;
d1fbff89 546 }
fe600cf6
DD		 547
548 if (!time_left)
549 return -ETIMEDOUT;
d1fbff89
DD		 550 return 0;
551}
552
553/* high-level-controller pure read of up to 8 bytes */
554static int octeon_i2c_hlc_read(struct octeon_i2c *i2c, struct i2c_msg *msgs)
555{
556 int i, j, ret = 0;
557 u64 cmd;
558
559 octeon_i2c_hlc_enable(i2c);
560 octeon_i2c_hlc_int_clear(i2c);
561
562 cmd = SW_TWSI_V | SW_TWSI_R | SW_TWSI_SOVR;
563 /* SIZE */
564 cmd |= (u64)(msgs[0].len - 1) << SW_TWSI_SIZE_SHIFT;
565 /* A */
566 cmd |= (u64)(msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT;
567
568 if (msgs[0].flags & I2C_M_TEN)
569 cmd |= SW_TWSI_OP_10;
570 else
571 cmd |= SW_TWSI_OP_7;
572
573 octeon_i2c_writeq_flush(cmd, i2c->twsi_base + SW_TWSI);
574 ret = octeon_i2c_hlc_wait(i2c);
575 if (ret)
576 goto err;
577
578 cmd = __raw_readq(i2c->twsi_base + SW_TWSI);
579 if ((cmd & SW_TWSI_R) == 0)
580 return -EAGAIN;
581
582 for (i = 0, j = msgs[0].len - 1; i < msgs[0].len && i < 4; i++, j--)
583 msgs[0].buf[j] = (cmd >> (8 * i)) & 0xff;
584
585 if (msgs[0].len > 4) {
586 cmd = __raw_readq(i2c->twsi_base + SW_TWSI_EXT);
587 for (i = 0; i < msgs[0].len - 4 && i < 4; i++, j--)
588 msgs[0].buf[j] = (cmd >> (8 * i)) & 0xff;
589 }
590
591err:
592 return ret;
593}
594
595/* high-level-controller pure write of up to 8 bytes */
596static int octeon_i2c_hlc_write(struct octeon_i2c *i2c, struct i2c_msg *msgs)
597{
598 int i, j, ret = 0;
599 u64 cmd;
600
601 octeon_i2c_hlc_enable(i2c);
602 octeon_i2c_hlc_int_clear(i2c);
603
604 cmd = SW_TWSI_V | SW_TWSI_SOVR;
605 /* SIZE */
606 cmd |= (u64)(msgs[0].len - 1) << SW_TWSI_SIZE_SHIFT;
607 /* A */
608 cmd |= (u64)(msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT;
609
610 if (msgs[0].flags & I2C_M_TEN)
611 cmd |= SW_TWSI_OP_10;
612 else
613 cmd |= SW_TWSI_OP_7;
614
615 for (i = 0, j = msgs[0].len - 1; i < msgs[0].len && i < 4; i++, j--)
616 cmd |= (u64)msgs[0].buf[j] << (8 * i);
617
618 if (msgs[0].len > 4) {
619 u64 ext = 0;
620
621 for (i = 0; i < msgs[0].len - 4 && i < 4; i++, j--)
622 ext |= (u64)msgs[0].buf[j] << (8 * i);
623 octeon_i2c_writeq_flush(ext, i2c->twsi_base + SW_TWSI_EXT);
624 }
625
626 octeon_i2c_writeq_flush(cmd, i2c->twsi_base + SW_TWSI);
627 ret = octeon_i2c_hlc_wait(i2c);
628 if (ret)
629 goto err;
630
631 cmd = __raw_readq(i2c->twsi_base + SW_TWSI);
632 if ((cmd & SW_TWSI_R) == 0)
633 return -EAGAIN;
634
635 ret = octeon_i2c_check_status(i2c, false);
636
637err:
638 return ret;
639}
640
641/* high-level-controller composite write+read, msg0=addr, msg1=data */
642static int octeon_i2c_hlc_comp_read(struct octeon_i2c *i2c, struct i2c_msg *msgs)
643{
644 int i, j, ret = 0;
645 u64 cmd;
646
647 octeon_i2c_hlc_enable(i2c);
648
649 cmd = SW_TWSI_V | SW_TWSI_R | SW_TWSI_SOVR;
650 /* SIZE */
651 cmd |= (u64)(msgs[1].len - 1) << SW_TWSI_SIZE_SHIFT;
652 /* A */
653 cmd |= (u64)(msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT;
654
655 if (msgs[0].flags & I2C_M_TEN)
656 cmd |= SW_TWSI_OP_10_IA;
657 else
658 cmd |= SW_TWSI_OP_7_IA;
659
660 if (msgs[0].len == 2) {
661 u64 ext = 0;
662
663 cmd |= SW_TWSI_EIA;
664 ext = (u64)msgs[0].buf[0] << SW_TWSI_IA_SHIFT;
665 cmd |= (u64)msgs[0].buf[1] << SW_TWSI_IA_SHIFT;
666 octeon_i2c_writeq_flush(ext, i2c->twsi_base + SW_TWSI_EXT);
667 } else {
668 cmd |= (u64)msgs[0].buf[0] << SW_TWSI_IA_SHIFT;
669 }
670
671 octeon_i2c_hlc_int_clear(i2c);
672 octeon_i2c_writeq_flush(cmd, i2c->twsi_base + SW_TWSI);
673
674 ret = octeon_i2c_hlc_wait(i2c);
675 if (ret)
676 goto err;
677
678 cmd = __raw_readq(i2c->twsi_base + SW_TWSI);
679 if ((cmd & SW_TWSI_R) == 0)
680 return -EAGAIN;
681
682 for (i = 0, j = msgs[1].len - 1; i < msgs[1].len && i < 4; i++, j--)
683 msgs[1].buf[j] = (cmd >> (8 * i)) & 0xff;
684
685 if (msgs[1].len > 4) {
686 cmd = __raw_readq(i2c->twsi_base + SW_TWSI_EXT);
687 for (i = 0; i < msgs[1].len - 4 && i < 4; i++, j--)
688 msgs[1].buf[j] = (cmd >> (8 * i)) & 0xff;
689 }
690
691err:
692 return ret;
693}
694
695/* high-level-controller composite write+write, m[0]len<=2, m[1]len<=8 */
696static int octeon_i2c_hlc_comp_write(struct octeon_i2c *i2c, struct i2c_msg *msgs)
697{
698 bool set_ext = false;
699 int i, j, ret = 0;
700 u64 cmd, ext = 0;
701
702 octeon_i2c_hlc_enable(i2c);
703
704 cmd = SW_TWSI_V | SW_TWSI_SOVR;
705 /* SIZE */
706 cmd |= (u64)(msgs[1].len - 1) << SW_TWSI_SIZE_SHIFT;
707 /* A */
708 cmd |= (u64)(msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT;
709
710 if (msgs[0].flags & I2C_M_TEN)
711 cmd |= SW_TWSI_OP_10_IA;
712 else
713 cmd |= SW_TWSI_OP_7_IA;
714
715 if (msgs[0].len == 2) {
716 cmd |= SW_TWSI_EIA;
717 ext |= (u64)msgs[0].buf[0] << SW_TWSI_IA_SHIFT;
718 set_ext = true;
719 cmd |= (u64)msgs[0].buf[1] << SW_TWSI_IA_SHIFT;
720 } else {
721 cmd |= (u64)msgs[0].buf[0] << SW_TWSI_IA_SHIFT;
722 }
723
724 for (i = 0, j = msgs[1].len - 1; i < msgs[1].len && i < 4; i++, j--)
725 cmd |= (u64)msgs[1].buf[j] << (8 * i);
726
727 if (msgs[1].len > 4) {
728 for (i = 0; i < msgs[1].len - 4 && i < 4; i++, j--)
729 ext |= (u64)msgs[1].buf[j] << (8 * i);
730 set_ext = true;
731 }
732 if (set_ext)
733 octeon_i2c_writeq_flush(ext, i2c->twsi_base + SW_TWSI_EXT);
734
735 octeon_i2c_hlc_int_clear(i2c);
736 octeon_i2c_writeq_flush(cmd, i2c->twsi_base + SW_TWSI);
737
738 ret = octeon_i2c_hlc_wait(i2c);
739 if (ret)
740 goto err;
741
742 cmd = __raw_readq(i2c->twsi_base + SW_TWSI);
743 if ((cmd & SW_TWSI_R) == 0)
744 return -EAGAIN;
745
746 ret = octeon_i2c_check_status(i2c, false);
747
748err:
749 return ret;
750}
751
f541bb38
JG		 752/* calculate and set clock divisors */
753static void octeon_i2c_set_clock(struct octeon_i2c *i2c)
754{
755 int tclk, thp_base, inc, thp_idx, mdiv_idx, ndiv_idx, foscl, diff;
756 int thp = 0x18, mdiv = 2, ndiv = 0, delta_hz = 1000000;
757
758 for (ndiv_idx = 0; ndiv_idx < 8 && delta_hz != 0; ndiv_idx++) {
759 /*
760 * An mdiv value of less than 2 seems to not work well
761 * with ds1337 RTCs, so we constrain it to larger values.
762 */
763 for (mdiv_idx = 15; mdiv_idx >= 2 && delta_hz != 0; mdiv_idx--) {
764 /*
765 * For given ndiv and mdiv values check the
766 * two closest thp values.
767 */
768 tclk = i2c->twsi_freq * (mdiv_idx + 1) * 10;
769 tclk *= (1 << ndiv_idx);
770 thp_base = (i2c->sys_freq / (tclk * 2)) - 1;
771
772 for (inc = 0; inc <= 1; inc++) {
773 thp_idx = thp_base + inc;
774 if (thp_idx < 5 || thp_idx > 0xff)
775 continue;
776
777 foscl = i2c->sys_freq / (2 * (thp_idx + 1));
778 foscl = foscl / (1 << ndiv_idx);
779 foscl = foscl / (mdiv_idx + 1) / 10;
780 diff = abs(foscl - i2c->twsi_freq);
781 if (diff < delta_hz) {
782 delta_hz = diff;
783 thp = thp_idx;
784 mdiv = mdiv_idx;
785 ndiv = ndiv_idx;
786 }
787 }
788 }
789 }
9cb9480e
JG		 790 octeon_i2c_reg_write(i2c, SW_TWSI_OP_TWSI_CLK, thp);
791 octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CLKCTL, (mdiv << 3) | ndiv);
f541bb38
JG		 792}
793
794static int octeon_i2c_init_lowlevel(struct octeon_i2c *i2c)
795{
d1fbff89 796 u8 status = 0;
f541bb38
JG		 797 int tries;
798
f541bb38 799 /* reset controller */
9cb9480e 800 octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_RST, 0);
f541bb38 801
d1fbff89 802 for (tries = 10; tries && status != STAT_IDLE; tries--) {
f541bb38 803 udelay(1);
c57db709 804 status = octeon_i2c_stat_read(i2c);
f541bb38 805 if (status == STAT_IDLE)
d1fbff89 806 break;
f541bb38 807 }
d1fbff89
DD		 808
809 if (status != STAT_IDLE) {
810 dev_err(i2c->dev, "%s: TWSI_RST failed! (0x%x)\n",
811 __func__, status);
812 return -EIO;
813 }
814
815 /* toggle twice to force both teardowns */
816 octeon_i2c_hlc_enable(i2c);
817 octeon_i2c_hlc_disable(i2c);
818 return 0;
f541bb38
JG		 819}
820
c981e34e
JG		 821static int octeon_i2c_recovery(struct octeon_i2c *i2c)
822{
823 int ret;
824
825 ret = i2c_recover_bus(&i2c->adap);
826 if (ret)
827 /* recover failed, try hardware re-init */
828 ret = octeon_i2c_init_lowlevel(i2c);
829 return ret;
830}
831
85660f43 832/**
bd7784c2
JG		 833 * octeon_i2c_start - send START to the bus
834 * @i2c: The struct octeon_i2c
85660f43
RB		 835 *
836 * Returns 0 on success, otherwise a negative errno.
837 */
838static int octeon_i2c_start(struct octeon_i2c *i2c)
839{
c981e34e
JG		 840 int ret;
841 u8 stat;
85660f43 842
d1fbff89
DD		 843 octeon_i2c_hlc_disable(i2c);
844
c57db709 845 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB | TWSI_CTL_STA);
c981e34e
JG		 846 ret = octeon_i2c_wait(i2c);
847 if (ret)
848 goto error;
85660f43 849
c981e34e
JG		 850 stat = octeon_i2c_stat_read(i2c);
851 if (stat == STAT_START || stat == STAT_REP_START)
852 /* START successful, bail out */
853 return 0;
85660f43 854
c981e34e
JG		 855error:
856 /* START failed, try to recover */
857 ret = octeon_i2c_recovery(i2c);
858 return (ret) ? ret : -EAGAIN;
85660f43
RB		 859}
860
dfcd8212
JG		 861/* send STOP to the bus */
862static void octeon_i2c_stop(struct octeon_i2c *i2c)
85660f43 863{
c57db709 864 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB | TWSI_CTL_STP);
85660f43
RB		 865}
866
867/**
bd7784c2
JG		 868 * octeon_i2c_write - send data to the bus via low-level controller
869 * @i2c: The struct octeon_i2c
870 * @target: Target address
871 * @data: Pointer to the data to be sent
872 * @length: Length of the data
85660f43
RB		 873 *
874 * The address is sent over the bus, then the data.
875 *
876 * Returns 0 on success, otherwise a negative errno.
877 */
878static int octeon_i2c_write(struct octeon_i2c *i2c, int target,
879 const u8 *data, int length)
880{
881 int i, result;
85660f43 882
c57db709
JG		 883 octeon_i2c_data_write(i2c, target << 1);
884 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);
85660f43
RB		 885
886 result = octeon_i2c_wait(i2c);
887 if (result)
888 return result;
889
890 for (i = 0; i < length; i++) {
b4c715d0
JG		 891 result = octeon_i2c_check_status(i2c, false);
892 if (result)
893 return result;
85660f43 894
c57db709
JG		 895 octeon_i2c_data_write(i2c, data[i]);
896 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);
85660f43
RB		 897
898 result = octeon_i2c_wait(i2c);
899 if (result)
900 return result;
901 }
902
903 return 0;
904}
905
906/**
bd7784c2
JG		 907 * octeon_i2c_read - receive data from the bus via low-level controller
908 * @i2c: The struct octeon_i2c
909 * @target: Target address
910 * @data: Pointer to the location to store the data
886f6f83
DD		 911 * @rlength: Length of the data
912 * @recv_len: flag for length byte
85660f43
RB		 913 *
914 * The address is sent over the bus, then the data is read.
915 *
916 * Returns 0 on success, otherwise a negative errno.
917 */
918static int octeon_i2c_read(struct octeon_i2c *i2c, int target,
886f6f83 919 u8 *data, u16 *rlength, bool recv_len)
85660f43 920{
886f6f83 921 int i, result, length = *rlength;
b4c715d0 922 bool final_read = false;
85660f43 923
c57db709
JG		 924 octeon_i2c_data_write(i2c, (target << 1) | 1);
925 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);
85660f43
RB		 926
927 result = octeon_i2c_wait(i2c);
928 if (result)
929 return result;
930
b4c715d0
JG		 931 /* address OK ? */
932 result = octeon_i2c_check_status(i2c, false);
933 if (result)
934 return result;
935
85660f43 936 for (i = 0; i < length; i++) {
b4c715d0
JG		 937 /* for the last byte TWSI_CTL_AAK must not be set */
938 if (i + 1 == length)
939 final_read = true;
85660f43 940
b4c715d0
JG		 941 /* clear iflg to allow next event */
942 if (final_read)
c57db709 943 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);
b4c715d0
JG		 944 else
945 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB | TWSI_CTL_AAK);
85660f43
RB		 946
947 result = octeon_i2c_wait(i2c);
948 if (result)
949 return result;
950
c57db709 951 data[i] = octeon_i2c_data_read(i2c);
886f6f83
DD		 952 if (recv_len && i == 0) {
953 if (data[i] > I2C_SMBUS_BLOCK_MAX + 1) {
954 dev_err(i2c->dev,
955 "%s: read len > I2C_SMBUS_BLOCK_MAX %d\n",
956 __func__, data[i]);
957 return -EPROTO;
958 }
959 length += data[i];
960 }
b4c715d0
JG		 961
962 result = octeon_i2c_check_status(i2c, final_read);
963 if (result)
964 return result;
85660f43 965 }
886f6f83 966 *rlength = length;
85660f43
RB		 967 return 0;
968}
969
970/**
bd7784c2
JG		 971 * octeon_i2c_xfer - The driver's master_xfer function
972 * @adap: Pointer to the i2c_adapter structure
973 * @msgs: Pointer to the messages to be processed
974 * @num: Length of the MSGS array
85660f43 975 *
bd7784c2 976 * Returns the number of messages processed, or a negative errno on failure.
85660f43 977 */
dfcd8212 978static int octeon_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
85660f43
RB		 979 int num)
980{
85660f43 981 struct octeon_i2c *i2c = i2c_get_adapdata(adap);
dfcd8212 982 int i, ret = 0;
85660f43 983
d1fbff89
DD		 984 if (num == 1) {
985 if (msgs[0].len > 0 && msgs[0].len <= 8) {
986 if (msgs[0].flags & I2C_M_RD)
987 ret = octeon_i2c_hlc_read(i2c, msgs);
988 else
989 ret = octeon_i2c_hlc_write(i2c, msgs);
990 goto out;
991 }
992 } else if (num == 2) {
993 if ((msgs[0].flags & I2C_M_RD) == 0 &&
994 (msgs[1].flags & I2C_M_RECV_LEN) == 0 &&
995 msgs[0].len > 0 && msgs[0].len <= 2 &&
996 msgs[1].len > 0 && msgs[1].len <= 8 &&
997 msgs[0].addr == msgs[1].addr) {
998 if (msgs[1].flags & I2C_M_RD)
999 ret = octeon_i2c_hlc_comp_read(i2c, msgs);
1000 else
1001 ret = octeon_i2c_hlc_comp_write(i2c, msgs);
1002 goto out;
1003 }
1004 }
1005
85660f43 1006 for (i = 0; ret == 0 && i < num; i++) {
dfcd8212
JG		 1007 struct i2c_msg *pmsg = &msgs[i];
1008
392d01de
JG		 1009 /* zero-length messages are not supported */
1010 if (!pmsg->len) {
1011 ret = -EOPNOTSUPP;
1012 break;
1013 }
1014
c981e34e
JG		 1015 ret = octeon_i2c_start(i2c);
1016 if (ret)
1017 return ret;
1018
85660f43
RB		 1019 if (pmsg->flags & I2C_M_RD)
1020 ret = octeon_i2c_read(i2c, pmsg->addr, pmsg->buf,
886f6f83 1021 &pmsg->len, pmsg->flags & I2C_M_RECV_LEN);
85660f43
RB		 1022 else
1023 ret = octeon_i2c_write(i2c, pmsg->addr, pmsg->buf,
dfcd8212 1024 pmsg->len);
85660f43
RB		 1025 }
1026 octeon_i2c_stop(i2c);
d1fbff89 1027out:
85660f43
RB		 1028 return (ret != 0) ? ret : num;
1029}
1030
c981e34e
JG		 1031static int octeon_i2c_get_scl(struct i2c_adapter *adap)
1032{
1033 struct octeon_i2c *i2c = i2c_get_adapdata(adap);
1034 u64 state;
1035
1036 state = octeon_i2c_read_int(i2c);
1037 return state & TWSI_INT_SCL;
1038}
1039
1040static void octeon_i2c_set_scl(struct i2c_adapter *adap, int val)
1041{
1042 struct octeon_i2c *i2c = i2c_get_adapdata(adap);
1043
1044 octeon_i2c_write_int(i2c, TWSI_INT_SCL_OVR);
1045}
1046
1047static int octeon_i2c_get_sda(struct i2c_adapter *adap)
1048{
1049 struct octeon_i2c *i2c = i2c_get_adapdata(adap);
1050 u64 state;
1051
1052 state = octeon_i2c_read_int(i2c);
1053 return state & TWSI_INT_SDA;
1054}
1055
1056static void octeon_i2c_prepare_recovery(struct i2c_adapter *adap)
1057{
1058 struct octeon_i2c *i2c = i2c_get_adapdata(adap);
1059
1060 /*
1061 * The stop resets the state machine, does not _transmit_ STOP unless
1062 * engine was active.
1063 */
1064 octeon_i2c_stop(i2c);
1065
d1fbff89 1066 octeon_i2c_hlc_disable(i2c);
c981e34e
JG		 1067 octeon_i2c_write_int(i2c, 0);
1068}
1069
1070static void octeon_i2c_unprepare_recovery(struct i2c_adapter *adap)
1071{
1072 struct octeon_i2c *i2c = i2c_get_adapdata(adap);
1073
1074 octeon_i2c_write_int(i2c, 0);
1075}
1076
1077static struct i2c_bus_recovery_info octeon_i2c_recovery_info = {
1078 .recover_bus = i2c_generic_scl_recovery,
1079 .get_scl = octeon_i2c_get_scl,
1080 .set_scl = octeon_i2c_set_scl,
1081 .get_sda = octeon_i2c_get_sda,
1082 .prepare_recovery = octeon_i2c_prepare_recovery,
1083 .unprepare_recovery = octeon_i2c_unprepare_recovery,
1084};
1085
85660f43
RB		 1086static u32 octeon_i2c_functionality(struct i2c_adapter *adap)
1087{
392d01de 1088 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
886f6f83 1089 I2C_FUNC_SMBUS_READ_BLOCK_DATA | I2C_SMBUS_BLOCK_PROC_CALL;
85660f43
RB		 1090}
1091
1092static const struct i2c_algorithm octeon_i2c_algo = {
1093 .master_xfer = octeon_i2c_xfer,
1094 .functionality = octeon_i2c_functionality,
1095};
1096
1097static struct i2c_adapter octeon_i2c_ops = {
1098 .owner = THIS_MODULE,
1099 .name = "OCTEON adapter",
1100 .algo = &octeon_i2c_algo,
85660f43
RB		 1101};
1102
0b255e92 1103static int octeon_i2c_probe(struct platform_device *pdev)
85660f43 1104{
dfcd8212 1105 struct device_node *node = pdev->dev.of_node;
4729cbe0 1106 int irq, result = 0, hlc_irq = 0;
85660f43 1107 struct resource *res_mem;
dfcd8212 1108 struct octeon_i2c *i2c;
4729cbe0
JG		 1109 bool cn78xx_style;
1110
1111 cn78xx_style = of_device_is_compatible(node, "cavium,octeon-7890-twsi");
1112 if (cn78xx_style) {
1113 hlc_irq = platform_get_irq(pdev, 0);
1114 if (hlc_irq < 0)
1115 return hlc_irq;
85660f43 1116
4729cbe0
JG		 1117 irq = platform_get_irq(pdev, 2);
1118 if (irq < 0)
1119 return irq;
1120 } else {
1121 /* All adaptors have an irq. */
1122 irq = platform_get_irq(pdev, 0);
1123 if (irq < 0)
1124 return irq;
1125 }
85660f43 1126
f353a218 1127 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
85660f43 1128 if (!i2c) {
85660f43
RB		 1129 result = -ENOMEM;
1130 goto out;
1131 }
1132 i2c->dev = &pdev->dev;
85660f43
RB		 1133
1134 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
54108e56
JG		 1135 i2c->twsi_base = devm_ioremap_resource(&pdev->dev, res_mem);
1136 if (IS_ERR(i2c->twsi_base)) {
1137 result = PTR_ERR(i2c->twsi_base);
f353a218 1138 goto out;
85660f43
RB		 1139 }
1140
f353a218
DD		 1141 /*
1142 * "clock-rate" is a legacy binding, the official binding is
1143 * "clock-frequency". Try the official one first and then
1144 * fall back if it doesn't exist.
1145 */
dfcd8212
JG		 1146 if (of_property_read_u32(node, "clock-frequency", &i2c->twsi_freq) &&
1147 of_property_read_u32(node, "clock-rate", &i2c->twsi_freq)) {
f353a218
DD		 1148 dev_err(i2c->dev,
1149 "no I2C 'clock-rate' or 'clock-frequency' property\n");
85660f43 1150 result = -ENXIO;
f353a218 1151 goto out;
85660f43
RB		 1152 }
1153
f353a218 1154 i2c->sys_freq = octeon_get_io_clock_rate();
85660f43 1155
85660f43
RB		 1156 init_waitqueue_head(&i2c->queue);
1157
1158 i2c->irq = irq;
1159
4729cbe0
JG		 1160 if (cn78xx_style) {
1161 i2c->hlc_irq = hlc_irq;
1162
1163 i2c->int_enable = octeon_i2c_int_enable78;
1164 i2c->int_disable = octeon_i2c_int_disable78;
1165 i2c->hlc_int_enable = octeon_i2c_hlc_int_enable78;
1166 i2c->hlc_int_disable = octeon_i2c_hlc_int_disable78;
1167
1168 irq_set_status_flags(i2c->irq, IRQ_NOAUTOEN);
1169 irq_set_status_flags(i2c->hlc_irq, IRQ_NOAUTOEN);
1170
1171 result = devm_request_irq(&pdev->dev, i2c->hlc_irq,
1172 octeon_i2c_hlc_isr78, 0,
1173 DRV_NAME, i2c);
1174 if (result < 0) {
1175 dev_err(i2c->dev, "failed to attach interrupt\n");
1176 goto out;
1177 }
1178 } else {
1179 i2c->int_enable = octeon_i2c_int_enable;
1180 i2c->int_disable = octeon_i2c_int_disable;
1181 i2c->hlc_int_enable = octeon_i2c_hlc_int_enable;
1182 i2c->hlc_int_disable = octeon_i2c_int_disable;
1183 }
1184
f353a218
DD		 1185 result = devm_request_irq(&pdev->dev, i2c->irq,
1186 octeon_i2c_isr, 0, DRV_NAME, i2c);
85660f43
RB		 1187 if (result < 0) {
1188 dev_err(i2c->dev, "failed to attach interrupt\n");
f353a218 1189 goto out;
85660f43
RB		 1190 }
1191
fe600cf6
DD		 1192 if (OCTEON_IS_MODEL(OCTEON_CN38XX))
1193 i2c->broken_irq_check = true;
1194
dfcd8212 1195 result = octeon_i2c_init_lowlevel(i2c);
85660f43
RB		 1196 if (result) {
1197 dev_err(i2c->dev, "init low level failed\n");
f353a218 1198 goto out;
85660f43
RB		 1199 }
1200
dfcd8212 1201 octeon_i2c_set_clock(i2c);
85660f43
RB		 1202
1203 i2c->adap = octeon_i2c_ops;
a035d71b
JG		 1204 i2c->adap.timeout = msecs_to_jiffies(2);
1205 i2c->adap.retries = 5;
c981e34e 1206 i2c->adap.bus_recovery_info = &octeon_i2c_recovery_info;
85660f43 1207 i2c->adap.dev.parent = &pdev->dev;
dfcd8212 1208 i2c->adap.dev.of_node = node;
85660f43
RB		 1209 i2c_set_adapdata(&i2c->adap, i2c);
1210 platform_set_drvdata(pdev, i2c);
1211
f353a218 1212 result = i2c_add_adapter(&i2c->adap);
85660f43
RB		 1213 if (result < 0) {
1214 dev_err(i2c->dev, "failed to add adapter\n");
55827f4a 1215 goto out;
85660f43 1216 }
dfcd8212 1217 dev_info(i2c->dev, "probed\n");
f353a218 1218 return 0;
85660f43 1219
85660f43
RB		 1220out:
1221 return result;
1222};
1223
0b255e92 1224static int octeon_i2c_remove(struct platform_device *pdev)
85660f43
RB		 1225{
1226 struct octeon_i2c *i2c = platform_get_drvdata(pdev);
1227
1228 i2c_del_adapter(&i2c->adap);
85660f43
RB		 1229 return 0;
1230};
1231
dfcd8212
JG		 1232static const struct of_device_id octeon_i2c_match[] = {
1233 { .compatible = "cavium,octeon-3860-twsi", },
4729cbe0 1234 { .compatible = "cavium,octeon-7890-twsi", },
f353a218
DD		 1235 {},
1236};
1237MODULE_DEVICE_TABLE(of, octeon_i2c_match);
1238
85660f43
RB		 1239static struct platform_driver octeon_i2c_driver = {
1240 .probe = octeon_i2c_probe,
0b255e92 1241 .remove = octeon_i2c_remove,
85660f43 1242 .driver = {
85660f43 1243 .name = DRV_NAME,
f353a218 1244 .of_match_table = octeon_i2c_match,
85660f43
RB		 1245 },
1246};
1247
a3664b51 1248module_platform_driver(octeon_i2c_driver);
85660f43
RB		 1249
1250MODULE_AUTHOR("Michael Lawnick <michael.lawnick.ext@nsn.com>");
1251MODULE_DESCRIPTION("I2C-Bus adapter for Cavium OCTEON processors");
1252MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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