projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
i2c: octeon: Add flush writeq helper function
[deliverable/linux.git] / drivers / i2c / busses / i2c-octeon.c
CommitLineData
85660f43
RB		 1/*
2 * (C) Copyright 2009-2010
3 * Nokia Siemens Networks, michael.lawnick.ext@nsn.com
4 *
dfcd8212 5 * Portions Copyright (C) 2010 - 2016 Cavium, Inc.
85660f43
RB		 6 *
7 * This is a driver for the i2c adapter in Cavium Networks' OCTEON processors.
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
f353a218
DD		 14#include <linux/platform_device.h>
15#include <linux/interrupt.h>
85660f43
RB		 16#include <linux/kernel.h>
17#include <linux/module.h>
f353a218 18#include <linux/delay.h>
85660f43 19#include <linux/sched.h>
5a0e3ad6 20#include <linux/slab.h>
85660f43 21#include <linux/i2c.h>
f353a218
DD		 22#include <linux/io.h>
23#include <linux/of.h>
85660f43
RB		 24
25#include <asm/octeon/octeon.h>
26
27#define DRV_NAME "i2c-octeon"
28
dfcd8212
JG		 29/* Register offsets */
30#define SW_TWSI 0x00
31#define TWSI_INT 0x10
85660f43
RB		 32
33/* Controller command patterns */
dfcd8212
JG		 34#define SW_TWSI_V BIT_ULL(63) /* Valid bit */
35#define SW_TWSI_R BIT_ULL(56) /* Result or read bit */
36
37/* Controller opcode word (bits 60:57) */
38#define SW_TWSI_OP_SHIFT 57
39#define SW_TWSI_OP_TWSI_CLK (4ULL << SW_TWSI_OP_SHIFT)
40#define SW_TWSI_OP_EOP (6ULL << SW_TWSI_OP_SHIFT) /* Extended opcode */
41
42/* Controller extended opcode word (bits 34:32) */
43#define SW_TWSI_EOP_SHIFT 32
44#define SW_TWSI_EOP_TWSI_DATA (SW_TWSI_OP_EOP | 1ULL << SW_TWSI_EOP_SHIFT)
45#define SW_TWSI_EOP_TWSI_CTL (SW_TWSI_OP_EOP | 2ULL << SW_TWSI_EOP_SHIFT)
46#define SW_TWSI_EOP_TWSI_CLKCTL (SW_TWSI_OP_EOP | 3ULL << SW_TWSI_EOP_SHIFT)
47#define SW_TWSI_EOP_TWSI_STAT (SW_TWSI_OP_EOP | 3ULL << SW_TWSI_EOP_SHIFT)
48#define SW_TWSI_EOP_TWSI_RST (SW_TWSI_OP_EOP | 7ULL << SW_TWSI_EOP_SHIFT)
85660f43
RB		 49
50/* Controller command and status bits */
dfcd8212
JG		 51#define TWSI_CTL_CE 0x80
52#define TWSI_CTL_ENAB 0x40 /* Bus enable */
53#define TWSI_CTL_STA 0x20 /* Master-mode start, HW clears when done */
54#define TWSI_CTL_STP 0x10 /* Master-mode stop, HW clears when done */
55#define TWSI_CTL_IFLG 0x08 /* HW event, SW writes 0 to ACK */
56#define TWSI_CTL_AAK 0x04 /* Assert ACK */
85660f43 57
b4c715d0
JG		 58/* Status values */
59#define STAT_ERROR 0x00
dfcd8212 60#define STAT_START 0x08
b4c715d0 61#define STAT_REP_START 0x10
dfcd8212 62#define STAT_TXADDR_ACK 0x18
b4c715d0 63#define STAT_TXADDR_NAK 0x20
dfcd8212 64#define STAT_TXDATA_ACK 0x28
b4c715d0
JG		 65#define STAT_TXDATA_NAK 0x30
66#define STAT_LOST_ARB_38 0x38
dfcd8212 67#define STAT_RXADDR_ACK 0x40
b4c715d0 68#define STAT_RXADDR_NAK 0x48
dfcd8212 69#define STAT_RXDATA_ACK 0x50
b4c715d0
JG		 70#define STAT_RXDATA_NAK 0x58
71#define STAT_SLAVE_60 0x60
72#define STAT_LOST_ARB_68 0x68
73#define STAT_SLAVE_70 0x70
74#define STAT_LOST_ARB_78 0x78
75#define STAT_SLAVE_80 0x80
76#define STAT_SLAVE_88 0x88
77#define STAT_GENDATA_ACK 0x90
78#define STAT_GENDATA_NAK 0x98
79#define STAT_SLAVE_A0 0xA0
80#define STAT_SLAVE_A8 0xA8
81#define STAT_LOST_ARB_B0 0xB0
82#define STAT_SLAVE_LOST 0xB8
83#define STAT_SLAVE_NAK 0xC0
84#define STAT_SLAVE_ACK 0xC8
85#define STAT_AD2W_ACK 0xD0
86#define STAT_AD2W_NAK 0xD8
dfcd8212
JG		 87#define STAT_IDLE 0xF8
88
89/* TWSI_INT values */
90#define TWSI_INT_CORE_EN BIT_ULL(6)
91#define TWSI_INT_SDA_OVR BIT_ULL(8)
92#define TWSI_INT_SCL_OVR BIT_ULL(9)
c981e34e
JG		 93#define TWSI_INT_SDA BIT_ULL(10)
94#define TWSI_INT_SCL BIT_ULL(11)
85660f43
RB		 95
96struct octeon_i2c {
97 wait_queue_head_t queue;
98 struct i2c_adapter adap;
99 int irq;
f353a218 100 u32 twsi_freq;
85660f43 101 int sys_freq;
85660f43 102 void __iomem *twsi_base;
85660f43
RB		 103 struct device *dev;
104};
105
30c24b25
PS		 106static void octeon_i2c_writeq_flush(u64 val, void __iomem *addr)
107{
108 __raw_writeq(val, addr);
109 __raw_readq(addr); /* wait for write to land */
110}
111
85660f43 112/**
9cb9480e 113 * octeon_i2c_reg_write - write an I2C core register
bd7784c2
JG		 114 * @i2c: The struct octeon_i2c
115 * @eop_reg: Register selector
116 * @data: Value to be written
85660f43
RB		 117 *
118 * The I2C core registers are accessed indirectly via the SW_TWSI CSR.
119 */
9cb9480e 120static void octeon_i2c_reg_write(struct octeon_i2c *i2c, u64 eop_reg, u8 data)
85660f43
RB		 121{
122 u64 tmp;
123
124 __raw_writeq(SW_TWSI_V | eop_reg | data, i2c->twsi_base + SW_TWSI);
125 do {
126 tmp = __raw_readq(i2c->twsi_base + SW_TWSI);
127 } while ((tmp & SW_TWSI_V) != 0);
128}
129
c57db709
JG		 130#define octeon_i2c_ctl_write(i2c, val) \
131 octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CTL, val)
132#define octeon_i2c_data_write(i2c, val) \
133 octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_DATA, val)
134
85660f43 135/**
9cb9480e 136 * octeon_i2c_reg_read - read lower bits of an I2C core register
bd7784c2
JG		 137 * @i2c: The struct octeon_i2c
138 * @eop_reg: Register selector
85660f43
RB		 139 *
140 * Returns the data.
141 *
142 * The I2C core registers are accessed indirectly via the SW_TWSI CSR.
143 */
9cb9480e 144static u8 octeon_i2c_reg_read(struct octeon_i2c *i2c, u64 eop_reg)
85660f43
RB		 145{
146 u64 tmp;
147
148 __raw_writeq(SW_TWSI_V | eop_reg | SW_TWSI_R, i2c->twsi_base + SW_TWSI);
149 do {
150 tmp = __raw_readq(i2c->twsi_base + SW_TWSI);
151 } while ((tmp & SW_TWSI_V) != 0);
152
153 return tmp & 0xFF;
154}
155
c57db709
JG		 156#define octeon_i2c_ctl_read(i2c) \
157 octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_CTL)
158#define octeon_i2c_data_read(i2c) \
159 octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_DATA)
160#define octeon_i2c_stat_read(i2c) \
161 octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_STAT)
162
c981e34e
JG		 163/**
164 * octeon_i2c_read_int - read the TWSI_INT register
165 * @i2c: The struct octeon_i2c
166 *
167 * Returns the value of the register.
168 */
169static u64 octeon_i2c_read_int(struct octeon_i2c *i2c)
170{
171 return __raw_readq(i2c->twsi_base + TWSI_INT);
172}
173
85660f43
RB		 174/**
175 * octeon_i2c_write_int - write the TWSI_INT register
bd7784c2
JG		 176 * @i2c: The struct octeon_i2c
177 * @data: Value to be written
85660f43
RB		 178 */
179static void octeon_i2c_write_int(struct octeon_i2c *i2c, u64 data)
180{
30c24b25 181 octeon_i2c_writeq_flush(data, i2c->twsi_base + TWSI_INT);
85660f43
RB		 182}
183
184/**
bd7784c2
JG		 185 * octeon_i2c_int_enable - enable the CORE interrupt
186 * @i2c: The struct octeon_i2c
85660f43
RB		 187 *
188 * The interrupt will be asserted when there is non-STAT_IDLE state in
189 * the SW_TWSI_EOP_TWSI_STAT register.
190 */
191static void octeon_i2c_int_enable(struct octeon_i2c *i2c)
192{
dfcd8212 193 octeon_i2c_write_int(i2c, TWSI_INT_CORE_EN);
85660f43
RB		 194}
195
bd7784c2 196/* disable the CORE interrupt */
85660f43
RB		 197static void octeon_i2c_int_disable(struct octeon_i2c *i2c)
198{
dfcd8212 199 /* clear TS/ST/IFLG events */
85660f43
RB		 200 octeon_i2c_write_int(i2c, 0);
201}
202
bd7784c2 203/* interrupt service routine */
85660f43
RB		 204static irqreturn_t octeon_i2c_isr(int irq, void *dev_id)
205{
206 struct octeon_i2c *i2c = dev_id;
207
208 octeon_i2c_int_disable(i2c);
2637e5fd 209 wake_up(&i2c->queue);
85660f43
RB		 210
211 return IRQ_HANDLED;
212}
213
85660f43
RB		 214static int octeon_i2c_test_iflg(struct octeon_i2c *i2c)
215{
b69e5c67 216 return (octeon_i2c_ctl_read(i2c) & TWSI_CTL_IFLG);
85660f43
RB		 217}
218
219/**
bd7784c2
JG		 220 * octeon_i2c_wait - wait for the IFLG to be set
221 * @i2c: The struct octeon_i2c
85660f43
RB		 222 *
223 * Returns 0 on success, otherwise a negative errno.
224 */
225static int octeon_i2c_wait(struct octeon_i2c *i2c)
226{
dfcd8212 227 long time_left;
85660f43
RB		 228
229 octeon_i2c_int_enable(i2c);
dfcd8212
JG		 230 time_left = wait_event_timeout(i2c->queue, octeon_i2c_test_iflg(i2c),
231 i2c->adap.timeout);
85660f43 232 octeon_i2c_int_disable(i2c);
dfcd8212 233 if (!time_left) {
85660f43 234 dev_dbg(i2c->dev, "%s: timeout\n", __func__);
cc33e542 235 return -ETIMEDOUT;
85660f43
RB		 236 }
237
238 return 0;
239}
240
b4c715d0
JG		 241static int octeon_i2c_check_status(struct octeon_i2c *i2c, int final_read)
242{
243 u8 stat = octeon_i2c_stat_read(i2c);
244
245 switch (stat) {
246 /* Everything is fine */
247 case STAT_IDLE:
248 case STAT_AD2W_ACK:
249 case STAT_RXADDR_ACK:
250 case STAT_TXADDR_ACK:
251 case STAT_TXDATA_ACK:
252 return 0;
253
254 /* ACK allowed on pre-terminal bytes only */
255 case STAT_RXDATA_ACK:
256 if (!final_read)
257 return 0;
258 return -EIO;
259
260 /* NAK allowed on terminal byte only */
261 case STAT_RXDATA_NAK:
262 if (final_read)
263 return 0;
264 return -EIO;
265
266 /* Arbitration lost */
267 case STAT_LOST_ARB_38:
268 case STAT_LOST_ARB_68:
269 case STAT_LOST_ARB_78:
270 case STAT_LOST_ARB_B0:
271 return -EAGAIN;
272
273 /* Being addressed as slave, should back off & listen */
274 case STAT_SLAVE_60:
275 case STAT_SLAVE_70:
276 case STAT_GENDATA_ACK:
277 case STAT_GENDATA_NAK:
278 return -EOPNOTSUPP;
279
280 /* Core busy as slave */
281 case STAT_SLAVE_80:
282 case STAT_SLAVE_88:
283 case STAT_SLAVE_A0:
284 case STAT_SLAVE_A8:
285 case STAT_SLAVE_LOST:
286 case STAT_SLAVE_NAK:
287 case STAT_SLAVE_ACK:
288 return -EOPNOTSUPP;
289
290 case STAT_TXDATA_NAK:
291 return -EIO;
292 case STAT_TXADDR_NAK:
293 case STAT_RXADDR_NAK:
294 case STAT_AD2W_NAK:
295 return -ENXIO;
296 default:
297 dev_err(i2c->dev, "unhandled state: %d\n", stat);
298 return -EIO;
299 }
300}
301
f541bb38
JG		 302/* calculate and set clock divisors */
303static void octeon_i2c_set_clock(struct octeon_i2c *i2c)
304{
305 int tclk, thp_base, inc, thp_idx, mdiv_idx, ndiv_idx, foscl, diff;
306 int thp = 0x18, mdiv = 2, ndiv = 0, delta_hz = 1000000;
307
308 for (ndiv_idx = 0; ndiv_idx < 8 && delta_hz != 0; ndiv_idx++) {
309 /*
310 * An mdiv value of less than 2 seems to not work well
311 * with ds1337 RTCs, so we constrain it to larger values.
312 */
313 for (mdiv_idx = 15; mdiv_idx >= 2 && delta_hz != 0; mdiv_idx--) {
314 /*
315 * For given ndiv and mdiv values check the
316 * two closest thp values.
317 */
318 tclk = i2c->twsi_freq * (mdiv_idx + 1) * 10;
319 tclk *= (1 << ndiv_idx);
320 thp_base = (i2c->sys_freq / (tclk * 2)) - 1;
321
322 for (inc = 0; inc <= 1; inc++) {
323 thp_idx = thp_base + inc;
324 if (thp_idx < 5 || thp_idx > 0xff)
325 continue;
326
327 foscl = i2c->sys_freq / (2 * (thp_idx + 1));
328 foscl = foscl / (1 << ndiv_idx);
329 foscl = foscl / (mdiv_idx + 1) / 10;
330 diff = abs(foscl - i2c->twsi_freq);
331 if (diff < delta_hz) {
332 delta_hz = diff;
333 thp = thp_idx;
334 mdiv = mdiv_idx;
335 ndiv = ndiv_idx;
336 }
337 }
338 }
339 }
9cb9480e
JG		 340 octeon_i2c_reg_write(i2c, SW_TWSI_OP_TWSI_CLK, thp);
341 octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CLKCTL, (mdiv << 3) | ndiv);
f541bb38
JG		 342}
343
344static int octeon_i2c_init_lowlevel(struct octeon_i2c *i2c)
345{
346 u8 status;
347 int tries;
348
349 /* disable high level controller, enable bus access */
c57db709 350 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);
f541bb38
JG		 351
352 /* reset controller */
9cb9480e 353 octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_RST, 0);
f541bb38
JG		 354
355 for (tries = 10; tries; tries--) {
356 udelay(1);
c57db709 357 status = octeon_i2c_stat_read(i2c);
f541bb38
JG		 358 if (status == STAT_IDLE)
359 return 0;
360 }
361 dev_err(i2c->dev, "%s: TWSI_RST failed! (0x%x)\n", __func__, status);
362 return -EIO;
363}
364
c981e34e
JG		 365static int octeon_i2c_recovery(struct octeon_i2c *i2c)
366{
367 int ret;
368
369 ret = i2c_recover_bus(&i2c->adap);
370 if (ret)
371 /* recover failed, try hardware re-init */
372 ret = octeon_i2c_init_lowlevel(i2c);
373 return ret;
374}
375
85660f43 376/**
bd7784c2
JG		 377 * octeon_i2c_start - send START to the bus
378 * @i2c: The struct octeon_i2c
85660f43
RB		 379 *
380 * Returns 0 on success, otherwise a negative errno.
381 */
382static int octeon_i2c_start(struct octeon_i2c *i2c)
383{
c981e34e
JG		 384 int ret;
385 u8 stat;
85660f43 386
c57db709 387 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB | TWSI_CTL_STA);
c981e34e
JG		 388 ret = octeon_i2c_wait(i2c);
389 if (ret)
390 goto error;
85660f43 391
c981e34e
JG		 392 stat = octeon_i2c_stat_read(i2c);
393 if (stat == STAT_START || stat == STAT_REP_START)
394 /* START successful, bail out */
395 return 0;
85660f43 396
c981e34e
JG		 397error:
398 /* START failed, try to recover */
399 ret = octeon_i2c_recovery(i2c);
400 return (ret) ? ret : -EAGAIN;
85660f43
RB		 401}
402
dfcd8212
JG		 403/* send STOP to the bus */
404static void octeon_i2c_stop(struct octeon_i2c *i2c)
85660f43 405{
c57db709 406 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB | TWSI_CTL_STP);
85660f43
RB		 407}
408
409/**
bd7784c2
JG		 410 * octeon_i2c_write - send data to the bus via low-level controller
411 * @i2c: The struct octeon_i2c
412 * @target: Target address
413 * @data: Pointer to the data to be sent
414 * @length: Length of the data
85660f43
RB		 415 *
416 * The address is sent over the bus, then the data.
417 *
418 * Returns 0 on success, otherwise a negative errno.
419 */
420static int octeon_i2c_write(struct octeon_i2c *i2c, int target,
421 const u8 *data, int length)
422{
423 int i, result;
85660f43 424
c57db709
JG		 425 octeon_i2c_data_write(i2c, target << 1);
426 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);
85660f43
RB		 427
428 result = octeon_i2c_wait(i2c);
429 if (result)
430 return result;
431
432 for (i = 0; i < length; i++) {
b4c715d0
JG		 433 result = octeon_i2c_check_status(i2c, false);
434 if (result)
435 return result;
85660f43 436
c57db709
JG		 437 octeon_i2c_data_write(i2c, data[i]);
438 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);
85660f43
RB		 439
440 result = octeon_i2c_wait(i2c);
441 if (result)
442 return result;
443 }
444
445 return 0;
446}
447
448/**
bd7784c2
JG		 449 * octeon_i2c_read - receive data from the bus via low-level controller
450 * @i2c: The struct octeon_i2c
451 * @target: Target address
452 * @data: Pointer to the location to store the data
886f6f83
DD		 453 * @rlength: Length of the data
454 * @recv_len: flag for length byte
85660f43
RB		 455 *
456 * The address is sent over the bus, then the data is read.
457 *
458 * Returns 0 on success, otherwise a negative errno.
459 */
460static int octeon_i2c_read(struct octeon_i2c *i2c, int target,
886f6f83 461 u8 *data, u16 *rlength, bool recv_len)
85660f43 462{
886f6f83 463 int i, result, length = *rlength;
b4c715d0 464 bool final_read = false;
85660f43
RB		 465
466 if (length < 1)
467 return -EINVAL;
468
c57db709
JG		 469 octeon_i2c_data_write(i2c, (target << 1) | 1);
470 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);
85660f43
RB		 471
472 result = octeon_i2c_wait(i2c);
473 if (result)
474 return result;
475
b4c715d0
JG		 476 /* address OK ? */
477 result = octeon_i2c_check_status(i2c, false);
478 if (result)
479 return result;
480
85660f43 481 for (i = 0; i < length; i++) {
b4c715d0
JG		 482 /* for the last byte TWSI_CTL_AAK must not be set */
483 if (i + 1 == length)
484 final_read = true;
85660f43 485
b4c715d0
JG		 486 /* clear iflg to allow next event */
487 if (final_read)
c57db709 488 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);
b4c715d0
JG		 489 else
490 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB | TWSI_CTL_AAK);
85660f43
RB		 491
492 result = octeon_i2c_wait(i2c);
493 if (result)
494 return result;
495
c57db709 496 data[i] = octeon_i2c_data_read(i2c);
886f6f83
DD		 497 if (recv_len && i == 0) {
498 if (data[i] > I2C_SMBUS_BLOCK_MAX + 1) {
499 dev_err(i2c->dev,
500 "%s: read len > I2C_SMBUS_BLOCK_MAX %d\n",
501 __func__, data[i]);
502 return -EPROTO;
503 }
504 length += data[i];
505 }
b4c715d0
JG		 506
507 result = octeon_i2c_check_status(i2c, final_read);
508 if (result)
509 return result;
85660f43 510 }
886f6f83 511 *rlength = length;
85660f43
RB		 512 return 0;
513}
514
515/**
bd7784c2
JG		 516 * octeon_i2c_xfer - The driver's master_xfer function
517 * @adap: Pointer to the i2c_adapter structure
518 * @msgs: Pointer to the messages to be processed
519 * @num: Length of the MSGS array
85660f43 520 *
bd7784c2 521 * Returns the number of messages processed, or a negative errno on failure.
85660f43 522 */
dfcd8212 523static int octeon_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
85660f43
RB		 524 int num)
525{
85660f43 526 struct octeon_i2c *i2c = i2c_get_adapdata(adap);
dfcd8212 527 int i, ret = 0;
85660f43
RB		 528
529 for (i = 0; ret == 0 && i < num; i++) {
dfcd8212
JG		 530 struct i2c_msg *pmsg = &msgs[i];
531
c981e34e
JG		 532 ret = octeon_i2c_start(i2c);
533 if (ret)
534 return ret;
535
85660f43
RB		 536 if (pmsg->flags & I2C_M_RD)
537 ret = octeon_i2c_read(i2c, pmsg->addr, pmsg->buf,
886f6f83 538 &pmsg->len, pmsg->flags & I2C_M_RECV_LEN);
85660f43
RB		 539 else
540 ret = octeon_i2c_write(i2c, pmsg->addr, pmsg->buf,
dfcd8212 541 pmsg->len);
85660f43
RB		 542 }
543 octeon_i2c_stop(i2c);
544
545 return (ret != 0) ? ret : num;
546}
547
c981e34e
JG		 548static int octeon_i2c_get_scl(struct i2c_adapter *adap)
549{
550 struct octeon_i2c *i2c = i2c_get_adapdata(adap);
551 u64 state;
552
553 state = octeon_i2c_read_int(i2c);
554 return state & TWSI_INT_SCL;
555}
556
557static void octeon_i2c_set_scl(struct i2c_adapter *adap, int val)
558{
559 struct octeon_i2c *i2c = i2c_get_adapdata(adap);
560
561 octeon_i2c_write_int(i2c, TWSI_INT_SCL_OVR);
562}
563
564static int octeon_i2c_get_sda(struct i2c_adapter *adap)
565{
566 struct octeon_i2c *i2c = i2c_get_adapdata(adap);
567 u64 state;
568
569 state = octeon_i2c_read_int(i2c);
570 return state & TWSI_INT_SDA;
571}
572
573static void octeon_i2c_prepare_recovery(struct i2c_adapter *adap)
574{
575 struct octeon_i2c *i2c = i2c_get_adapdata(adap);
576
577 /*
578 * The stop resets the state machine, does not _transmit_ STOP unless
579 * engine was active.
580 */
581 octeon_i2c_stop(i2c);
582
583 octeon_i2c_write_int(i2c, 0);
584}
585
586static void octeon_i2c_unprepare_recovery(struct i2c_adapter *adap)
587{
588 struct octeon_i2c *i2c = i2c_get_adapdata(adap);
589
590 octeon_i2c_write_int(i2c, 0);
591}
592
593static struct i2c_bus_recovery_info octeon_i2c_recovery_info = {
594 .recover_bus = i2c_generic_scl_recovery,
595 .get_scl = octeon_i2c_get_scl,
596 .set_scl = octeon_i2c_set_scl,
597 .get_sda = octeon_i2c_get_sda,
598 .prepare_recovery = octeon_i2c_prepare_recovery,
599 .unprepare_recovery = octeon_i2c_unprepare_recovery,
600};
601
85660f43
RB		 602static u32 octeon_i2c_functionality(struct i2c_adapter *adap)
603{
886f6f83
DD		 604 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
605 I2C_FUNC_SMBUS_READ_BLOCK_DATA | I2C_SMBUS_BLOCK_PROC_CALL;
85660f43
RB		 606}
607
608static const struct i2c_algorithm octeon_i2c_algo = {
609 .master_xfer = octeon_i2c_xfer,
610 .functionality = octeon_i2c_functionality,
611};
612
613static struct i2c_adapter octeon_i2c_ops = {
614 .owner = THIS_MODULE,
615 .name = "OCTEON adapter",
616 .algo = &octeon_i2c_algo,
85660f43
RB		 617};
618
0b255e92 619static int octeon_i2c_probe(struct platform_device *pdev)
85660f43 620{
dfcd8212 621 struct device_node *node = pdev->dev.of_node;
85660f43 622 struct resource *res_mem;
dfcd8212
JG		 623 struct octeon_i2c *i2c;
624 int irq, result = 0;
85660f43
RB		 625
626 /* All adaptors have an irq. */
627 irq = platform_get_irq(pdev, 0);
628 if (irq < 0)
629 return irq;
630
f353a218 631 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
85660f43 632 if (!i2c) {
85660f43
RB		 633 result = -ENOMEM;
634 goto out;
635 }
636 i2c->dev = &pdev->dev;
85660f43
RB		 637
638 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
54108e56
JG		 639 i2c->twsi_base = devm_ioremap_resource(&pdev->dev, res_mem);
640 if (IS_ERR(i2c->twsi_base)) {
641 result = PTR_ERR(i2c->twsi_base);
f353a218 642 goto out;
85660f43
RB		 643 }
644
f353a218
DD		 645 /*
646 * "clock-rate" is a legacy binding, the official binding is
647 * "clock-frequency". Try the official one first and then
648 * fall back if it doesn't exist.
649 */
dfcd8212
JG		 650 if (of_property_read_u32(node, "clock-frequency", &i2c->twsi_freq) &&
651 of_property_read_u32(node, "clock-rate", &i2c->twsi_freq)) {
f353a218
DD		 652 dev_err(i2c->dev,
653 "no I2C 'clock-rate' or 'clock-frequency' property\n");
85660f43 654 result = -ENXIO;
f353a218 655 goto out;
85660f43
RB		 656 }
657
f353a218 658 i2c->sys_freq = octeon_get_io_clock_rate();
85660f43 659
85660f43
RB		 660 init_waitqueue_head(&i2c->queue);
661
662 i2c->irq = irq;
663
f353a218
DD		 664 result = devm_request_irq(&pdev->dev, i2c->irq,
665 octeon_i2c_isr, 0, DRV_NAME, i2c);
85660f43
RB		 666 if (result < 0) {
667 dev_err(i2c->dev, "failed to attach interrupt\n");
f353a218 668 goto out;
85660f43
RB		 669 }
670
dfcd8212 671 result = octeon_i2c_init_lowlevel(i2c);
85660f43
RB		 672 if (result) {
673 dev_err(i2c->dev, "init low level failed\n");
f353a218 674 goto out;
85660f43
RB		 675 }
676
dfcd8212 677 octeon_i2c_set_clock(i2c);
85660f43
RB		 678
679 i2c->adap = octeon_i2c_ops;
a035d71b
JG		 680 i2c->adap.timeout = msecs_to_jiffies(2);
681 i2c->adap.retries = 5;
c981e34e 682 i2c->adap.bus_recovery_info = &octeon_i2c_recovery_info;
85660f43 683 i2c->adap.dev.parent = &pdev->dev;
dfcd8212 684 i2c->adap.dev.of_node = node;
85660f43
RB		 685 i2c_set_adapdata(&i2c->adap, i2c);
686 platform_set_drvdata(pdev, i2c);
687
f353a218 688 result = i2c_add_adapter(&i2c->adap);
85660f43
RB		 689 if (result < 0) {
690 dev_err(i2c->dev, "failed to add adapter\n");
55827f4a 691 goto out;
85660f43 692 }
dfcd8212 693 dev_info(i2c->dev, "probed\n");
f353a218 694 return 0;
85660f43 695
85660f43
RB		 696out:
697 return result;
698};
699
0b255e92 700static int octeon_i2c_remove(struct platform_device *pdev)
85660f43
RB		 701{
702 struct octeon_i2c *i2c = platform_get_drvdata(pdev);
703
704 i2c_del_adapter(&i2c->adap);
85660f43
RB		 705 return 0;
706};
707
dfcd8212
JG		 708static const struct of_device_id octeon_i2c_match[] = {
709 { .compatible = "cavium,octeon-3860-twsi", },
f353a218
DD		 710 {},
711};
712MODULE_DEVICE_TABLE(of, octeon_i2c_match);
713
85660f43
RB		 714static struct platform_driver octeon_i2c_driver = {
715 .probe = octeon_i2c_probe,
0b255e92 716 .remove = octeon_i2c_remove,
85660f43 717 .driver = {
85660f43 718 .name = DRV_NAME,
f353a218 719 .of_match_table = octeon_i2c_match,
85660f43
RB		 720 },
721};
722
a3664b51 723module_platform_driver(octeon_i2c_driver);
85660f43
RB		 724
725MODULE_AUTHOR("Michael Lawnick <michael.lawnick.ext@nsn.com>");
726MODULE_DESCRIPTION("I2C-Bus adapter for Cavium OCTEON processors");
727MODULE_LICENSE("GPL");
Linux kernel - Deliverables
This page took 0.398004 seconds and 5 git commands to generate.