[deliverable/linux.git] / drivers / i2c / busses / i2c-octeon.c

/*
 * (C) Copyright 2009-2010
 * Nokia Siemens Networks, michael.lawnick.ext@nsn.com
 *
 * Portions Copyright (C) 2010 - 2016 Cavium, Inc.
 *
 * This is a driver for the i2c adapter in Cavium Networks' OCTEON processors.
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/i2c.h>
#include <linux/io.h>
#include <linux/of.h>

#include <asm/octeon/octeon.h>

#define DRV_NAME "i2c-octeon"

/* Register offsets */
#define SW_TWSI			0x00
#define TWSI_INT		0x10

/* Controller command patterns */
#define SW_TWSI_V		BIT_ULL(63)	/* Valid bit */
#define SW_TWSI_R		BIT_ULL(56)	/* Result or read bit */

/* Controller opcode word (bits 60:57) */
#define SW_TWSI_OP_SHIFT	57
#define SW_TWSI_OP_TWSI_CLK	(4ULL << SW_TWSI_OP_SHIFT)
#define SW_TWSI_OP_EOP		(6ULL << SW_TWSI_OP_SHIFT) /* Extended opcode */

/* Controller extended opcode word (bits 34:32) */
#define SW_TWSI_EOP_SHIFT	32
#define SW_TWSI_EOP_TWSI_DATA	(SW_TWSI_OP_EOP | 1ULL << SW_TWSI_EOP_SHIFT)
#define SW_TWSI_EOP_TWSI_CTL	(SW_TWSI_OP_EOP | 2ULL << SW_TWSI_EOP_SHIFT)
#define SW_TWSI_EOP_TWSI_CLKCTL	(SW_TWSI_OP_EOP | 3ULL << SW_TWSI_EOP_SHIFT)
#define SW_TWSI_EOP_TWSI_STAT	(SW_TWSI_OP_EOP | 3ULL << SW_TWSI_EOP_SHIFT)
#define SW_TWSI_EOP_TWSI_RST	(SW_TWSI_OP_EOP | 7ULL << SW_TWSI_EOP_SHIFT)

/* Controller command and status bits */
#define TWSI_CTL_CE		0x80
#define TWSI_CTL_ENAB		0x40	/* Bus enable */
#define TWSI_CTL_STA		0x20	/* Master-mode start, HW clears when done */
#define TWSI_CTL_STP		0x10	/* Master-mode stop, HW clears when done */
#define TWSI_CTL_IFLG		0x08	/* HW event, SW writes 0 to ACK */
#define TWSI_CTL_AAK		0x04	/* Assert ACK */

/* Some status values */
#define STAT_START		0x08
#define STAT_RSTART		0x10
#define STAT_TXADDR_ACK		0x18
#define STAT_TXDATA_ACK		0x28
#define STAT_RXADDR_ACK		0x40
#define STAT_RXDATA_ACK		0x50
#define STAT_IDLE		0xF8

/* TWSI_INT values */
#define TWSI_INT_CORE_EN	BIT_ULL(6)
#define TWSI_INT_SDA_OVR	BIT_ULL(8)
#define TWSI_INT_SCL_OVR	BIT_ULL(9)

struct octeon_i2c {
	wait_queue_head_t queue;
	struct i2c_adapter adap;
	int irq;
	u32 twsi_freq;
	int sys_freq;
	void __iomem *twsi_base;
	struct device *dev;
};

/**
 * octeon_i2c_reg_write - write an I2C core register
 * @i2c: The struct octeon_i2c
 * @eop_reg: Register selector
 * @data: Value to be written
 *
 * The I2C core registers are accessed indirectly via the SW_TWSI CSR.
 */
static void octeon_i2c_reg_write(struct octeon_i2c *i2c, u64 eop_reg, u8 data)
{
	u64 tmp;

	__raw_writeq(SW_TWSI_V | eop_reg | data, i2c->twsi_base + SW_TWSI);
	do {
		tmp = __raw_readq(i2c->twsi_base + SW_TWSI);
	} while ((tmp & SW_TWSI_V) != 0);
}

/**
 * octeon_i2c_reg_read - read lower bits of an I2C core register
 * @i2c: The struct octeon_i2c
 * @eop_reg: Register selector
 *
 * Returns the data.
 *
 * The I2C core registers are accessed indirectly via the SW_TWSI CSR.
 */
static u8 octeon_i2c_reg_read(struct octeon_i2c *i2c, u64 eop_reg)
{
	u64 tmp;

	__raw_writeq(SW_TWSI_V | eop_reg | SW_TWSI_R, i2c->twsi_base + SW_TWSI);
	do {
		tmp = __raw_readq(i2c->twsi_base + SW_TWSI);
	} while ((tmp & SW_TWSI_V) != 0);

	return tmp & 0xFF;
}

/**
 * octeon_i2c_write_int - write the TWSI_INT register
 * @i2c: The struct octeon_i2c
 * @data: Value to be written
 */
static void octeon_i2c_write_int(struct octeon_i2c *i2c, u64 data)
{
	__raw_writeq(data, i2c->twsi_base + TWSI_INT);
	__raw_readq(i2c->twsi_base + TWSI_INT);
}

/**
 * octeon_i2c_int_enable - enable the CORE interrupt
 * @i2c: The struct octeon_i2c
 *
 * The interrupt will be asserted when there is non-STAT_IDLE state in
 * the SW_TWSI_EOP_TWSI_STAT register.
 */
static void octeon_i2c_int_enable(struct octeon_i2c *i2c)
{
	octeon_i2c_write_int(i2c, TWSI_INT_CORE_EN);
}

/* disable the CORE interrupt */
static void octeon_i2c_int_disable(struct octeon_i2c *i2c)
{
	/* clear TS/ST/IFLG events */
	octeon_i2c_write_int(i2c, 0);
}

/**
 * octeon_i2c_unblock - unblock the bus
 * @i2c: The struct octeon_i2c
 *
 * If there was a reset while a device was driving 0 to bus, bus is blocked.
 * We toggle it free manually by some clock cycles and send a stop.
 */
static void octeon_i2c_unblock(struct octeon_i2c *i2c)
{
	int i;

	dev_dbg(i2c->dev, "%s\n", __func__);

	for (i = 0; i < 9; i++) {
		octeon_i2c_write_int(i2c, 0);
		udelay(5);
		octeon_i2c_write_int(i2c, TWSI_INT_SCL_OVR);
		udelay(5);
	}
	/* hand-crank a STOP */
	octeon_i2c_write_int(i2c, TWSI_INT_SDA_OVR | TWSI_INT_SCL_OVR);
	udelay(5);
	octeon_i2c_write_int(i2c, TWSI_INT_SDA_OVR);
	udelay(5);
	octeon_i2c_write_int(i2c, 0);
}

/* interrupt service routine */
static irqreturn_t octeon_i2c_isr(int irq, void *dev_id)
{
	struct octeon_i2c *i2c = dev_id;

	octeon_i2c_int_disable(i2c);
	wake_up(&i2c->queue);

	return IRQ_HANDLED;
}


static int octeon_i2c_test_iflg(struct octeon_i2c *i2c)
{
	return (octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_CTL) & TWSI_CTL_IFLG) != 0;
}

/**
 * octeon_i2c_wait - wait for the IFLG to be set
 * @i2c: The struct octeon_i2c
 *
 * Returns 0 on success, otherwise a negative errno.
 */
static int octeon_i2c_wait(struct octeon_i2c *i2c)
{
	long time_left;

	octeon_i2c_int_enable(i2c);
	time_left = wait_event_timeout(i2c->queue, octeon_i2c_test_iflg(i2c),
				       i2c->adap.timeout);
	octeon_i2c_int_disable(i2c);
	if (!time_left) {
		dev_dbg(i2c->dev, "%s: timeout\n", __func__);
		return -ETIMEDOUT;
	}

	return 0;
}

/* calculate and set clock divisors */
static void octeon_i2c_set_clock(struct octeon_i2c *i2c)
{
	int tclk, thp_base, inc, thp_idx, mdiv_idx, ndiv_idx, foscl, diff;
	int thp = 0x18, mdiv = 2, ndiv = 0, delta_hz = 1000000;

	for (ndiv_idx = 0; ndiv_idx < 8 && delta_hz != 0; ndiv_idx++) {
		/*
		 * An mdiv value of less than 2 seems to not work well
		 * with ds1337 RTCs, so we constrain it to larger values.
		 */
		for (mdiv_idx = 15; mdiv_idx >= 2 && delta_hz != 0; mdiv_idx--) {
			/*
			 * For given ndiv and mdiv values check the
			 * two closest thp values.
			 */
			tclk = i2c->twsi_freq * (mdiv_idx + 1) * 10;
			tclk *= (1 << ndiv_idx);
			thp_base = (i2c->sys_freq / (tclk * 2)) - 1;

			for (inc = 0; inc <= 1; inc++) {
				thp_idx = thp_base + inc;
				if (thp_idx < 5 || thp_idx > 0xff)
					continue;

				foscl = i2c->sys_freq / (2 * (thp_idx + 1));
				foscl = foscl / (1 << ndiv_idx);
				foscl = foscl / (mdiv_idx + 1) / 10;
				diff = abs(foscl - i2c->twsi_freq);
				if (diff < delta_hz) {
					delta_hz = diff;
					thp = thp_idx;
					mdiv = mdiv_idx;
					ndiv = ndiv_idx;
				}
			}
		}
	}
	octeon_i2c_reg_write(i2c, SW_TWSI_OP_TWSI_CLK, thp);
	octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CLKCTL, (mdiv << 3) | ndiv);
}

static int octeon_i2c_init_lowlevel(struct octeon_i2c *i2c)
{
	u8 status;
	int tries;

	/* disable high level controller, enable bus access */
	octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);

	/* reset controller */
	octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_RST, 0);

	for (tries = 10; tries; tries--) {
		udelay(1);
		status = octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_STAT);
		if (status == STAT_IDLE)
			return 0;
	}
	dev_err(i2c->dev, "%s: TWSI_RST failed! (0x%x)\n", __func__, status);
	return -EIO;
}

/**
 * octeon_i2c_start - send START to the bus
 * @i2c: The struct octeon_i2c
 *
 * Returns 0 on success, otherwise a negative errno.
 */
static int octeon_i2c_start(struct octeon_i2c *i2c)
{
	int result;
	u8 data;

	octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CTL,
			    TWSI_CTL_ENAB | TWSI_CTL_STA);

	result = octeon_i2c_wait(i2c);
	if (result) {
		if (octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_STAT) == STAT_IDLE) {
			/*
			 * Controller refused to send start flag May
			 * be a client is holding SDA low - let's try
			 * to free it.
			 */
			octeon_i2c_unblock(i2c);
			octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CTL,
					    TWSI_CTL_ENAB | TWSI_CTL_STA);
			result = octeon_i2c_wait(i2c);
		}
		if (result)
			return result;
	}

	data = octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_STAT);
	if ((data != STAT_START) && (data != STAT_RSTART)) {
		dev_err(i2c->dev, "%s: bad status (0x%x)\n", __func__, data);
		return -EIO;
	}

	return 0;
}

/* send STOP to the bus */
static void octeon_i2c_stop(struct octeon_i2c *i2c)
{
	octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CTL,
			    TWSI_CTL_ENAB | TWSI_CTL_STP);
}

/**
 * octeon_i2c_write - send data to the bus via low-level controller
 * @i2c: The struct octeon_i2c
 * @target: Target address
 * @data: Pointer to the data to be sent
 * @length: Length of the data
 *
 * The address is sent over the bus, then the data.
 *
 * Returns 0 on success, otherwise a negative errno.
 */
static int octeon_i2c_write(struct octeon_i2c *i2c, int target,
			    const u8 *data, int length)
{
	int i, result;
	u8 tmp;

	result = octeon_i2c_start(i2c);
	if (result)
		return result;

	octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_DATA, target << 1);
	octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);

	result = octeon_i2c_wait(i2c);
	if (result)
		return result;

	for (i = 0; i < length; i++) {
		tmp = octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_STAT);

		if ((tmp != STAT_TXADDR_ACK) && (tmp != STAT_TXDATA_ACK)) {
			dev_err(i2c->dev,
				"%s: bad status before write (0x%x)\n",
				__func__, tmp);
			return -EIO;
		}

		octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_DATA, data[i]);
		octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);

		result = octeon_i2c_wait(i2c);
		if (result)
			return result;
	}

	return 0;
}

/**
 * octeon_i2c_read - receive data from the bus via low-level controller
 * @i2c: The struct octeon_i2c
 * @target: Target address
 * @data: Pointer to the location to store the data
 * @rlength: Length of the data
 * @recv_len: flag for length byte
 *
 * The address is sent over the bus, then the data is read.
 *
 * Returns 0 on success, otherwise a negative errno.
 */
static int octeon_i2c_read(struct octeon_i2c *i2c, int target,
			   u8 *data, u16 *rlength, bool recv_len)
{
	int i, result, length = *rlength;
	u8 tmp;

	if (length < 1)
		return -EINVAL;

	result = octeon_i2c_start(i2c);
	if (result)
		return result;

	octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_DATA, (target << 1) | 1);
	octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);

	result = octeon_i2c_wait(i2c);
	if (result)
		return result;

	for (i = 0; i < length; i++) {
		tmp = octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_STAT);

		if ((tmp != STAT_RXDATA_ACK) && (tmp != STAT_RXADDR_ACK)) {
			dev_err(i2c->dev,
				"%s: bad status before read (0x%x)\n",
				__func__, tmp);
			return -EIO;
		}

		if (i + 1 < length)
			octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CTL,
					    TWSI_CTL_ENAB | TWSI_CTL_AAK);
		else
			octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CTL,
					    TWSI_CTL_ENAB);

		result = octeon_i2c_wait(i2c);
		if (result)
			return result;

		data[i] = octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_DATA);
		if (recv_len && i == 0) {
			if (data[i] > I2C_SMBUS_BLOCK_MAX + 1) {
				dev_err(i2c->dev,
					"%s: read len > I2C_SMBUS_BLOCK_MAX %d\n",
					__func__, data[i]);
				return -EPROTO;
			}
			length += data[i];
		}
	}
	*rlength = length;
	return 0;
}

/**
 * octeon_i2c_xfer - The driver's master_xfer function
 * @adap: Pointer to the i2c_adapter structure
 * @msgs: Pointer to the messages to be processed
 * @num: Length of the MSGS array
 *
 * Returns the number of messages processed, or a negative errno on failure.
 */
static int octeon_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
			   int num)
{
	struct octeon_i2c *i2c = i2c_get_adapdata(adap);
	int i, ret = 0;

	for (i = 0; ret == 0 && i < num; i++) {
		struct i2c_msg *pmsg = &msgs[i];

		dev_dbg(i2c->dev,
			"Doing %s %d byte(s) to/from 0x%02x - %d of %d messages\n",
			 pmsg->flags & I2C_M_RD ? "read" : "write",
			 pmsg->len, pmsg->addr, i + 1, num);
		if (pmsg->flags & I2C_M_RD)
			ret = octeon_i2c_read(i2c, pmsg->addr, pmsg->buf,
					      &pmsg->len, pmsg->flags & I2C_M_RECV_LEN);
		else
			ret = octeon_i2c_write(i2c, pmsg->addr, pmsg->buf,
					       pmsg->len);
	}
	octeon_i2c_stop(i2c);

	return (ret != 0) ? ret : num;
}

static u32 octeon_i2c_functionality(struct i2c_adapter *adap)
{
	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
	       I2C_FUNC_SMBUS_READ_BLOCK_DATA | I2C_SMBUS_BLOCK_PROC_CALL;
}

static const struct i2c_algorithm octeon_i2c_algo = {
	.master_xfer = octeon_i2c_xfer,
	.functionality = octeon_i2c_functionality,
};

static struct i2c_adapter octeon_i2c_ops = {
	.owner = THIS_MODULE,
	.name = "OCTEON adapter",
	.algo = &octeon_i2c_algo,
};

static int octeon_i2c_probe(struct platform_device *pdev)
{
	struct device_node *node = pdev->dev.of_node;
	struct resource *res_mem;
	struct octeon_i2c *i2c;
	int irq, result = 0;

	/* All adaptors have an irq.  */
	irq = platform_get_irq(pdev, 0);
	if (irq < 0)
		return irq;

	i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
	if (!i2c) {
		result = -ENOMEM;
		goto out;
	}
	i2c->dev = &pdev->dev;

	res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	i2c->twsi_base = devm_ioremap_resource(&pdev->dev, res_mem);
	if (IS_ERR(i2c->twsi_base)) {
		result = PTR_ERR(i2c->twsi_base);
		goto out;
	}

	/*
	 * "clock-rate" is a legacy binding, the official binding is
	 * "clock-frequency".  Try the official one first and then
	 * fall back if it doesn't exist.
	 */
	if (of_property_read_u32(node, "clock-frequency", &i2c->twsi_freq) &&
	    of_property_read_u32(node, "clock-rate", &i2c->twsi_freq)) {
		dev_err(i2c->dev,
			"no I2C 'clock-rate' or 'clock-frequency' property\n");
		result = -ENXIO;
		goto out;
	}

	i2c->sys_freq = octeon_get_io_clock_rate();

	init_waitqueue_head(&i2c->queue);

	i2c->irq = irq;

	result = devm_request_irq(&pdev->dev, i2c->irq,
				  octeon_i2c_isr, 0, DRV_NAME, i2c);
	if (result < 0) {
		dev_err(i2c->dev, "failed to attach interrupt\n");
		goto out;
	}

	result = octeon_i2c_init_lowlevel(i2c);
	if (result) {
		dev_err(i2c->dev, "init low level failed\n");
		goto  out;
	}

	octeon_i2c_set_clock(i2c);

	i2c->adap = octeon_i2c_ops;
	i2c->adap.timeout = msecs_to_jiffies(2);
	i2c->adap.retries = 5;
	i2c->adap.dev.parent = &pdev->dev;
	i2c->adap.dev.of_node = node;
	i2c_set_adapdata(&i2c->adap, i2c);
	platform_set_drvdata(pdev, i2c);

	result = i2c_add_adapter(&i2c->adap);
	if (result < 0) {
		dev_err(i2c->dev, "failed to add adapter\n");
		goto out;
	}
	dev_info(i2c->dev, "probed\n");
	return 0;

out:
	return result;
};

static int octeon_i2c_remove(struct platform_device *pdev)
{
	struct octeon_i2c *i2c = platform_get_drvdata(pdev);

	i2c_del_adapter(&i2c->adap);
	return 0;
};

static const struct of_device_id octeon_i2c_match[] = {
	{ .compatible = "cavium,octeon-3860-twsi", },
	{},
};
MODULE_DEVICE_TABLE(of, octeon_i2c_match);

static struct platform_driver octeon_i2c_driver = {
	.probe		= octeon_i2c_probe,
	.remove		= octeon_i2c_remove,
	.driver		= {
		.name	= DRV_NAME,
		.of_match_table = octeon_i2c_match,
	},
};

module_platform_driver(octeon_i2c_driver);

MODULE_AUTHOR("Michael Lawnick <michael.lawnick.ext@nsn.com>");
MODULE_DESCRIPTION("I2C-Bus adapter for Cavium OCTEON processors");
MODULE_LICENSE("GPL");
Commit	Line	Data
85660f43 RB	1	/*
	2	* (C) Copyright 2009-2010
	3	* Nokia Siemens Networks, michael.lawnick.ext@nsn.com
	4	*
dfcd8212	5	* Portions Copyright (C) 2010 - 2016 Cavium, Inc.
85660f43 RB	6	*
	7	* This is a driver for the i2c adapter in Cavium Networks' OCTEON processors.
	8	*
	9	* This file is licensed under the terms of the GNU General Public
	10	* License version 2. This program is licensed "as is" without any
	11	* warranty of any kind, whether express or implied.
	12	*/
	13
f353a218 DD	14	#include <linux/platform_device.h>
f353a218 DD	15	#include <linux/interrupt.h>
85660f43 RB	16	#include <linux/kernel.h>
85660f43 RB	17	#include <linux/module.h>
f353a218	18	#include <linux/delay.h>
85660f43	19	#include <linux/sched.h>
5a0e3ad6	20	#include <linux/slab.h>
85660f43	21	#include <linux/i2c.h>
f353a218 DD	22	#include <linux/io.h>
f353a218 DD	23	#include <linux/of.h>
85660f43 RB	24
	25	#include <asm/octeon/octeon.h>
	26
	27	#define DRV_NAME "i2c-octeon"
	28
dfcd8212 JG	29	/* Register offsets */
	30	#define SW_TWSI 0x00
	31	#define TWSI_INT 0x10
85660f43 RB	32
85660f43 RB	33	/* Controller command patterns */
dfcd8212 JG	34	#define SW_TWSI_V BIT_ULL(63) /* Valid bit */
	35	#define SW_TWSI_R BIT_ULL(56) /* Result or read bit */
	36
	37	/* Controller opcode word (bits 60:57) */
	38	#define SW_TWSI_OP_SHIFT 57
	39	#define SW_TWSI_OP_TWSI_CLK (4ULL << SW_TWSI_OP_SHIFT)
	40	#define SW_TWSI_OP_EOP (6ULL << SW_TWSI_OP_SHIFT) /* Extended opcode */
	41
	42	/* Controller extended opcode word (bits 34:32) */
	43	#define SW_TWSI_EOP_SHIFT 32
	44	#define SW_TWSI_EOP_TWSI_DATA (SW_TWSI_OP_EOP \| 1ULL << SW_TWSI_EOP_SHIFT)
	45	#define SW_TWSI_EOP_TWSI_CTL (SW_TWSI_OP_EOP \| 2ULL << SW_TWSI_EOP_SHIFT)
	46	#define SW_TWSI_EOP_TWSI_CLKCTL (SW_TWSI_OP_EOP \| 3ULL << SW_TWSI_EOP_SHIFT)
	47	#define SW_TWSI_EOP_TWSI_STAT (SW_TWSI_OP_EOP \| 3ULL << SW_TWSI_EOP_SHIFT)
	48	#define SW_TWSI_EOP_TWSI_RST (SW_TWSI_OP_EOP \| 7ULL << SW_TWSI_EOP_SHIFT)
85660f43 RB	49
85660f43 RB	50	/* Controller command and status bits */
dfcd8212 JG	51	#define TWSI_CTL_CE 0x80
	52	#define TWSI_CTL_ENAB 0x40 /* Bus enable */
	53	#define TWSI_CTL_STA 0x20 /* Master-mode start, HW clears when done */
	54	#define TWSI_CTL_STP 0x10 /* Master-mode stop, HW clears when done */
	55	#define TWSI_CTL_IFLG 0x08 /* HW event, SW writes 0 to ACK */
	56	#define TWSI_CTL_AAK 0x04 /* Assert ACK */
85660f43 RB	57
85660f43 RB	58	/* Some status values */
dfcd8212 JG	59	#define STAT_START 0x08
	60	#define STAT_RSTART 0x10
	61	#define STAT_TXADDR_ACK 0x18
	62	#define STAT_TXDATA_ACK 0x28
	63	#define STAT_RXADDR_ACK 0x40
	64	#define STAT_RXDATA_ACK 0x50
	65	#define STAT_IDLE 0xF8
	66
	67	/* TWSI_INT values */
	68	#define TWSI_INT_CORE_EN BIT_ULL(6)
	69	#define TWSI_INT_SDA_OVR BIT_ULL(8)
	70	#define TWSI_INT_SCL_OVR BIT_ULL(9)
85660f43 RB	71
	72	struct octeon_i2c {
	73	wait_queue_head_t queue;
	74	struct i2c_adapter adap;
	75	int irq;
f353a218	76	u32 twsi_freq;
85660f43	77	int sys_freq;
85660f43	78	void __iomem *twsi_base;
85660f43 RB	79	struct device *dev;
	80	};
	81
	82	/**
9cb9480e	83	* octeon_i2c_reg_write - write an I2C core register
bd7784c2 JG	84	* @i2c: The struct octeon_i2c
	85	* @eop_reg: Register selector
	86	* @data: Value to be written
85660f43 RB	87	*
	88	* The I2C core registers are accessed indirectly via the SW_TWSI CSR.
	89	*/
9cb9480e	90	static void octeon_i2c_reg_write(struct octeon_i2c *i2c, u64 eop_reg, u8 data)
85660f43 RB	91	{
	92	u64 tmp;
	93
	94	__raw_writeq(SW_TWSI_V \| eop_reg \| data, i2c->twsi_base + SW_TWSI);
	95	do {
	96	tmp = __raw_readq(i2c->twsi_base + SW_TWSI);
	97	} while ((tmp & SW_TWSI_V) != 0);
	98	}
	99
	100	/**
9cb9480e	101	* octeon_i2c_reg_read - read lower bits of an I2C core register
bd7784c2 JG	102	* @i2c: The struct octeon_i2c
bd7784c2 JG	103	* @eop_reg: Register selector
85660f43 RB	104	*
	105	* Returns the data.
	106	*
	107	* The I2C core registers are accessed indirectly via the SW_TWSI CSR.
	108	*/
9cb9480e	109	static u8 octeon_i2c_reg_read(struct octeon_i2c *i2c, u64 eop_reg)
85660f43 RB	110	{
	111	u64 tmp;
	112
	113	__raw_writeq(SW_TWSI_V \| eop_reg \| SW_TWSI_R, i2c->twsi_base + SW_TWSI);
	114	do {
	115	tmp = __raw_readq(i2c->twsi_base + SW_TWSI);
	116	} while ((tmp & SW_TWSI_V) != 0);
	117
	118	return tmp & 0xFF;
	119	}
	120
	121	/**
	122	* octeon_i2c_write_int - write the TWSI_INT register
bd7784c2 JG	123	* @i2c: The struct octeon_i2c
bd7784c2 JG	124	* @data: Value to be written
85660f43 RB	125	*/
	126	static void octeon_i2c_write_int(struct octeon_i2c *i2c, u64 data)
	127	{
85660f43	128	__raw_writeq(data, i2c->twsi_base + TWSI_INT);
f353a218	129	__raw_readq(i2c->twsi_base + TWSI_INT);
85660f43 RB	130	}
	131
	132	/**
bd7784c2 JG	133	* octeon_i2c_int_enable - enable the CORE interrupt
bd7784c2 JG	134	* @i2c: The struct octeon_i2c
85660f43 RB	135	*
	136	* The interrupt will be asserted when there is non-STAT_IDLE state in
	137	* the SW_TWSI_EOP_TWSI_STAT register.
	138	*/
	139	static void octeon_i2c_int_enable(struct octeon_i2c *i2c)
	140	{
dfcd8212	141	octeon_i2c_write_int(i2c, TWSI_INT_CORE_EN);
85660f43 RB	142	}
85660f43 RB	143
bd7784c2	144	/* disable the CORE interrupt */
85660f43 RB	145	static void octeon_i2c_int_disable(struct octeon_i2c *i2c)
85660f43 RB	146	{
dfcd8212	147	/* clear TS/ST/IFLG events */
85660f43 RB	148	octeon_i2c_write_int(i2c, 0);
	149	}
	150
	151	/**
bd7784c2 JG	152	* octeon_i2c_unblock - unblock the bus
bd7784c2 JG	153	* @i2c: The struct octeon_i2c
85660f43	154	*
bd7784c2 JG	155	* If there was a reset while a device was driving 0 to bus, bus is blocked.
bd7784c2 JG	156	* We toggle it free manually by some clock cycles and send a stop.
85660f43 RB	157	*/
	158	static void octeon_i2c_unblock(struct octeon_i2c *i2c)
	159	{
	160	int i;
	161
	162	dev_dbg(i2c->dev, "%s\n", __func__);
dfcd8212	163
85660f43	164	for (i = 0; i < 9; i++) {
dfcd8212	165	octeon_i2c_write_int(i2c, 0);
85660f43	166	udelay(5);
dfcd8212	167	octeon_i2c_write_int(i2c, TWSI_INT_SCL_OVR);
85660f43 RB	168	udelay(5);
85660f43 RB	169	}
dfcd8212 JG	170	/* hand-crank a STOP */
dfcd8212 JG	171	octeon_i2c_write_int(i2c, TWSI_INT_SDA_OVR \| TWSI_INT_SCL_OVR);
85660f43	172	udelay(5);
dfcd8212	173	octeon_i2c_write_int(i2c, TWSI_INT_SDA_OVR);
85660f43	174	udelay(5);
dfcd8212	175	octeon_i2c_write_int(i2c, 0);
85660f43 RB	176	}
85660f43 RB	177
bd7784c2	178	/* interrupt service routine */
85660f43 RB	179	static irqreturn_t octeon_i2c_isr(int irq, void *dev_id)
	180	{
	181	struct octeon_i2c *i2c = dev_id;
	182
	183	octeon_i2c_int_disable(i2c);
2637e5fd	184	wake_up(&i2c->queue);
85660f43 RB	185
	186	return IRQ_HANDLED;
	187	}
	188
	189
	190	static int octeon_i2c_test_iflg(struct octeon_i2c *i2c)
	191	{
9cb9480e	192	return (octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_CTL) & TWSI_CTL_IFLG) != 0;
85660f43 RB	193	}
	194
	195	/**
bd7784c2 JG	196	* octeon_i2c_wait - wait for the IFLG to be set
bd7784c2 JG	197	* @i2c: The struct octeon_i2c
85660f43 RB	198	*
	199	* Returns 0 on success, otherwise a negative errno.
	200	*/
	201	static int octeon_i2c_wait(struct octeon_i2c *i2c)
	202	{
dfcd8212	203	long time_left;
85660f43 RB	204
85660f43 RB	205	octeon_i2c_int_enable(i2c);
dfcd8212 JG	206	time_left = wait_event_timeout(i2c->queue, octeon_i2c_test_iflg(i2c),
dfcd8212 JG	207	i2c->adap.timeout);
85660f43	208	octeon_i2c_int_disable(i2c);
dfcd8212	209	if (!time_left) {
85660f43	210	dev_dbg(i2c->dev, "%s: timeout\n", __func__);
cc33e542	211	return -ETIMEDOUT;
85660f43 RB	212	}
	213
	214	return 0;
	215	}
	216
f541bb38 JG	217	/* calculate and set clock divisors */
	218	static void octeon_i2c_set_clock(struct octeon_i2c *i2c)
	219	{
	220	int tclk, thp_base, inc, thp_idx, mdiv_idx, ndiv_idx, foscl, diff;
	221	int thp = 0x18, mdiv = 2, ndiv = 0, delta_hz = 1000000;
	222
	223	for (ndiv_idx = 0; ndiv_idx < 8 && delta_hz != 0; ndiv_idx++) {
	224	/*
	225	* An mdiv value of less than 2 seems to not work well
	226	* with ds1337 RTCs, so we constrain it to larger values.
	227	*/
	228	for (mdiv_idx = 15; mdiv_idx >= 2 && delta_hz != 0; mdiv_idx--) {
	229	/*
	230	* For given ndiv and mdiv values check the
	231	* two closest thp values.
	232	*/
	233	tclk = i2c->twsi_freq * (mdiv_idx + 1) * 10;
	234	tclk *= (1 << ndiv_idx);
	235	thp_base = (i2c->sys_freq / (tclk * 2)) - 1;
	236
	237	for (inc = 0; inc <= 1; inc++) {
	238	thp_idx = thp_base + inc;
	239	if (thp_idx < 5 \|\| thp_idx > 0xff)
	240	continue;
	241
	242	foscl = i2c->sys_freq / (2 * (thp_idx + 1));
	243	foscl = foscl / (1 << ndiv_idx);
	244	foscl = foscl / (mdiv_idx + 1) / 10;
	245	diff = abs(foscl - i2c->twsi_freq);
	246	if (diff < delta_hz) {
	247	delta_hz = diff;
	248	thp = thp_idx;
	249	mdiv = mdiv_idx;
	250	ndiv = ndiv_idx;
	251	}
	252	}
	253	}
	254	}
9cb9480e JG	255	octeon_i2c_reg_write(i2c, SW_TWSI_OP_TWSI_CLK, thp);
9cb9480e JG	256	octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CLKCTL, (mdiv << 3) \| ndiv);
f541bb38 JG	257	}
	258
	259	static int octeon_i2c_init_lowlevel(struct octeon_i2c *i2c)
	260	{
	261	u8 status;
	262	int tries;
	263
	264	/* disable high level controller, enable bus access */
9cb9480e	265	octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);
f541bb38 JG	266
f541bb38 JG	267	/* reset controller */
9cb9480e	268	octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_RST, 0);
f541bb38 JG	269
	270	for (tries = 10; tries; tries--) {
	271	udelay(1);
9cb9480e	272	status = octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_STAT);
f541bb38 JG	273	if (status == STAT_IDLE)
	274	return 0;
	275	}
	276	dev_err(i2c->dev, "%s: TWSI_RST failed! (0x%x)\n", __func__, status);
	277	return -EIO;
	278	}
	279
85660f43	280	/**
bd7784c2 JG	281	* octeon_i2c_start - send START to the bus
bd7784c2 JG	282	* @i2c: The struct octeon_i2c
85660f43 RB	283	*
	284	* Returns 0 on success, otherwise a negative errno.
	285	*/
	286	static int octeon_i2c_start(struct octeon_i2c *i2c)
	287	{
85660f43	288	int result;
dfcd8212	289	u8 data;
85660f43	290
9cb9480e	291	octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CTL,
dfcd8212	292	TWSI_CTL_ENAB \| TWSI_CTL_STA);
85660f43 RB	293
	294	result = octeon_i2c_wait(i2c);
	295	if (result) {
9cb9480e	296	if (octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_STAT) == STAT_IDLE) {
85660f43 RB	297	/*
	298	* Controller refused to send start flag May
	299	* be a client is holding SDA low - let's try
	300	* to free it.
	301	*/
	302	octeon_i2c_unblock(i2c);
9cb9480e	303	octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CTL,
85660f43	304	TWSI_CTL_ENAB \| TWSI_CTL_STA);
85660f43 RB	305	result = octeon_i2c_wait(i2c);
	306	}
	307	if (result)
	308	return result;
	309	}
	310
9cb9480e	311	data = octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_STAT);
85660f43 RB	312	if ((data != STAT_START) && (data != STAT_RSTART)) {
	313	dev_err(i2c->dev, "%s: bad status (0x%x)\n", __func__, data);
	314	return -EIO;
	315	}
	316
	317	return 0;
	318	}
	319
dfcd8212 JG	320	/* send STOP to the bus */
dfcd8212 JG	321	static void octeon_i2c_stop(struct octeon_i2c *i2c)
85660f43	322	{
9cb9480e	323	octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CTL,
85660f43	324	TWSI_CTL_ENAB \| TWSI_CTL_STP);
85660f43 RB	325	}
	326
	327	/**
bd7784c2 JG	328	* octeon_i2c_write - send data to the bus via low-level controller
	329	* @i2c: The struct octeon_i2c
	330	* @target: Target address
	331	* @data: Pointer to the data to be sent
	332	* @length: Length of the data
85660f43 RB	333	*
	334	* The address is sent over the bus, then the data.
	335	*
	336	* Returns 0 on success, otherwise a negative errno.
	337	*/
	338	static int octeon_i2c_write(struct octeon_i2c *i2c, int target,
	339	const u8 *data, int length)
	340	{
	341	int i, result;
	342	u8 tmp;
	343
	344	result = octeon_i2c_start(i2c);
	345	if (result)
	346	return result;
	347
9cb9480e JG	348	octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_DATA, target << 1);
9cb9480e JG	349	octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);
85660f43 RB	350
	351	result = octeon_i2c_wait(i2c);
	352	if (result)
	353	return result;
	354
	355	for (i = 0; i < length; i++) {
9cb9480e	356	tmp = octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_STAT);
dfcd8212	357
85660f43 RB	358	if ((tmp != STAT_TXADDR_ACK) && (tmp != STAT_TXDATA_ACK)) {
	359	dev_err(i2c->dev,
	360	"%s: bad status before write (0x%x)\n",
	361	__func__, tmp);
	362	return -EIO;
	363	}
	364
9cb9480e JG	365	octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_DATA, data[i]);
9cb9480e JG	366	octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);
85660f43 RB	367
	368	result = octeon_i2c_wait(i2c);
	369	if (result)
	370	return result;
	371	}
	372
	373	return 0;
	374	}
	375
	376	/**
bd7784c2 JG	377	* octeon_i2c_read - receive data from the bus via low-level controller
	378	* @i2c: The struct octeon_i2c
	379	* @target: Target address
	380	* @data: Pointer to the location to store the data
886f6f83 DD	381	* @rlength: Length of the data
886f6f83 DD	382	* @recv_len: flag for length byte
85660f43 RB	383	*
	384	* The address is sent over the bus, then the data is read.
	385	*
	386	* Returns 0 on success, otherwise a negative errno.
	387	*/
	388	static int octeon_i2c_read(struct octeon_i2c *i2c, int target,
886f6f83	389	u8 data, u16 rlength, bool recv_len)
85660f43	390	{
886f6f83	391	int i, result, length = *rlength;
85660f43 RB	392	u8 tmp;
	393
	394	if (length < 1)
	395	return -EINVAL;
	396
	397	result = octeon_i2c_start(i2c);
	398	if (result)
	399	return result;
	400
9cb9480e JG	401	octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_DATA, (target << 1) \| 1);
9cb9480e JG	402	octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);
85660f43 RB	403
	404	result = octeon_i2c_wait(i2c);
	405	if (result)
	406	return result;
	407
	408	for (i = 0; i < length; i++) {
9cb9480e	409	tmp = octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_STAT);
dfcd8212	410
85660f43 RB	411	if ((tmp != STAT_RXDATA_ACK) && (tmp != STAT_RXADDR_ACK)) {
	412	dev_err(i2c->dev,
	413	"%s: bad status before read (0x%x)\n",
	414	__func__, tmp);
	415	return -EIO;
	416	}
	417
dfcd8212	418	if (i + 1 < length)
9cb9480e	419	octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CTL,
dfcd8212	420	TWSI_CTL_ENAB \| TWSI_CTL_AAK);
85660f43	421	else
9cb9480e	422	octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CTL,
dfcd8212	423	TWSI_CTL_ENAB);
85660f43 RB	424
	425	result = octeon_i2c_wait(i2c);
	426	if (result)
	427	return result;
	428
9cb9480e	429	data[i] = octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_DATA);
886f6f83 DD	430	if (recv_len && i == 0) {
	431	if (data[i] > I2C_SMBUS_BLOCK_MAX + 1) {
	432	dev_err(i2c->dev,
	433	"%s: read len > I2C_SMBUS_BLOCK_MAX %d\n",
	434	__func__, data[i]);
	435	return -EPROTO;
	436	}
	437	length += data[i];
	438	}
85660f43	439	}
886f6f83	440	*rlength = length;
85660f43 RB	441	return 0;
	442	}
	443
	444	/**
bd7784c2 JG	445	* octeon_i2c_xfer - The driver's master_xfer function
	446	* @adap: Pointer to the i2c_adapter structure
	447	* @msgs: Pointer to the messages to be processed
	448	* @num: Length of the MSGS array
85660f43	449	*
bd7784c2	450	* Returns the number of messages processed, or a negative errno on failure.
85660f43	451	*/
dfcd8212	452	static int octeon_i2c_xfer(struct i2c_adapter adap, struct i2c_msg msgs,
85660f43 RB	453	int num)
85660f43 RB	454	{
85660f43	455	struct octeon_i2c *i2c = i2c_get_adapdata(adap);
dfcd8212	456	int i, ret = 0;
85660f43 RB	457
85660f43 RB	458	for (i = 0; ret == 0 && i < num; i++) {
dfcd8212 JG	459	struct i2c_msg *pmsg = &msgs[i];
dfcd8212 JG	460
85660f43 RB	461	dev_dbg(i2c->dev,
	462	"Doing %s %d byte(s) to/from 0x%02x - %d of %d messages\n",
	463	pmsg->flags & I2C_M_RD ? "read" : "write",
	464	pmsg->len, pmsg->addr, i + 1, num);
	465	if (pmsg->flags & I2C_M_RD)
	466	ret = octeon_i2c_read(i2c, pmsg->addr, pmsg->buf,
886f6f83	467	&pmsg->len, pmsg->flags & I2C_M_RECV_LEN);
85660f43 RB	468	else
85660f43 RB	469	ret = octeon_i2c_write(i2c, pmsg->addr, pmsg->buf,
dfcd8212	470	pmsg->len);
85660f43 RB	471	}
	472	octeon_i2c_stop(i2c);
	473
	474	return (ret != 0) ? ret : num;
	475	}
	476
	477	static u32 octeon_i2c_functionality(struct i2c_adapter *adap)
	478	{
886f6f83 DD	479	return I2C_FUNC_I2C \| I2C_FUNC_SMBUS_EMUL \|
886f6f83 DD	480	I2C_FUNC_SMBUS_READ_BLOCK_DATA \| I2C_SMBUS_BLOCK_PROC_CALL;
85660f43 RB	481	}
	482
	483	static const struct i2c_algorithm octeon_i2c_algo = {
	484	.master_xfer = octeon_i2c_xfer,
	485	.functionality = octeon_i2c_functionality,
	486	};
	487
	488	static struct i2c_adapter octeon_i2c_ops = {
	489	.owner = THIS_MODULE,
	490	.name = "OCTEON adapter",
	491	.algo = &octeon_i2c_algo,
85660f43 RB	492	};
85660f43 RB	493
0b255e92	494	static int octeon_i2c_probe(struct platform_device *pdev)
85660f43	495	{
dfcd8212	496	struct device_node *node = pdev->dev.of_node;
85660f43	497	struct resource *res_mem;
dfcd8212 JG	498	struct octeon_i2c *i2c;
dfcd8212 JG	499	int irq, result = 0;
85660f43 RB	500
	501	/* All adaptors have an irq. */
	502	irq = platform_get_irq(pdev, 0);
	503	if (irq < 0)
	504	return irq;
	505
f353a218	506	i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
85660f43	507	if (!i2c) {
85660f43 RB	508	result = -ENOMEM;
	509	goto out;
	510	}
	511	i2c->dev = &pdev->dev;
85660f43 RB	512
85660f43 RB	513	res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
54108e56 JG	514	i2c->twsi_base = devm_ioremap_resource(&pdev->dev, res_mem);
	515	if (IS_ERR(i2c->twsi_base)) {
	516	result = PTR_ERR(i2c->twsi_base);
f353a218	517	goto out;
85660f43 RB	518	}
85660f43 RB	519
f353a218 DD	520	/*
	521	* "clock-rate" is a legacy binding, the official binding is
	522	* "clock-frequency". Try the official one first and then
	523	* fall back if it doesn't exist.
	524	*/
dfcd8212 JG	525	if (of_property_read_u32(node, "clock-frequency", &i2c->twsi_freq) &&
dfcd8212 JG	526	of_property_read_u32(node, "clock-rate", &i2c->twsi_freq)) {
f353a218 DD	527	dev_err(i2c->dev,
f353a218 DD	528	"no I2C 'clock-rate' or 'clock-frequency' property\n");
85660f43	529	result = -ENXIO;
f353a218	530	goto out;
85660f43 RB	531	}
85660f43 RB	532
f353a218	533	i2c->sys_freq = octeon_get_io_clock_rate();
85660f43	534
85660f43 RB	535	init_waitqueue_head(&i2c->queue);
	536
	537	i2c->irq = irq;
	538
f353a218 DD	539	result = devm_request_irq(&pdev->dev, i2c->irq,
f353a218 DD	540	octeon_i2c_isr, 0, DRV_NAME, i2c);
85660f43 RB	541	if (result < 0) {
85660f43 RB	542	dev_err(i2c->dev, "failed to attach interrupt\n");
f353a218	543	goto out;
85660f43 RB	544	}
85660f43 RB	545
dfcd8212	546	result = octeon_i2c_init_lowlevel(i2c);
85660f43 RB	547	if (result) {
85660f43 RB	548	dev_err(i2c->dev, "init low level failed\n");
f353a218	549	goto out;
85660f43 RB	550	}
85660f43 RB	551
dfcd8212	552	octeon_i2c_set_clock(i2c);
85660f43 RB	553
85660f43 RB	554	i2c->adap = octeon_i2c_ops;
a035d71b JG	555	i2c->adap.timeout = msecs_to_jiffies(2);
a035d71b JG	556	i2c->adap.retries = 5;
85660f43	557	i2c->adap.dev.parent = &pdev->dev;
dfcd8212	558	i2c->adap.dev.of_node = node;
85660f43 RB	559	i2c_set_adapdata(&i2c->adap, i2c);
	560	platform_set_drvdata(pdev, i2c);
	561
f353a218	562	result = i2c_add_adapter(&i2c->adap);
85660f43 RB	563	if (result < 0) {
85660f43 RB	564	dev_err(i2c->dev, "failed to add adapter\n");
55827f4a	565	goto out;
85660f43	566	}
dfcd8212	567	dev_info(i2c->dev, "probed\n");
f353a218	568	return 0;
85660f43	569
85660f43 RB	570	out:
	571	return result;
	572	};
	573
0b255e92	574	static int octeon_i2c_remove(struct platform_device *pdev)
85660f43 RB	575	{
	576	struct octeon_i2c *i2c = platform_get_drvdata(pdev);
	577
	578	i2c_del_adapter(&i2c->adap);
85660f43 RB	579	return 0;
	580	};
	581
dfcd8212 JG	582	static const struct of_device_id octeon_i2c_match[] = {
dfcd8212 JG	583	{ .compatible = "cavium,octeon-3860-twsi", },
f353a218 DD	584	{},
	585	};
	586	MODULE_DEVICE_TABLE(of, octeon_i2c_match);
	587
85660f43 RB	588	static struct platform_driver octeon_i2c_driver = {
85660f43 RB	589	.probe = octeon_i2c_probe,
0b255e92	590	.remove = octeon_i2c_remove,
85660f43	591	.driver = {
85660f43	592	.name = DRV_NAME,
f353a218	593	.of_match_table = octeon_i2c_match,
85660f43 RB	594	},
	595	};
	596
a3664b51	597	module_platform_driver(octeon_i2c_driver);
85660f43 RB	598
	599	MODULE_AUTHOR("Michael Lawnick <michael.lawnick.ext@nsn.com>");
	600	MODULE_DESCRIPTION("I2C-Bus adapter for Cavium OCTEON processors");
	601	MODULE_LICENSE("GPL");