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i2c-omap: Don't compile in OMAP15xx I2C ISR for non-OMAP15xx builds
[deliverable/linux.git] / drivers / i2c / busses / i2c-omap.c
CommitLineData
010d442c
KS		 1/*
2 * TI OMAP I2C master mode driver
3 *
4 * Copyright (C) 2003 MontaVista Software, Inc.
5 * Copyright (C) 2004 Texas Instruments.
6 *
7 * Updated to work with multiple I2C interfaces on 24xx by
8 * Tony Lindgren <tony@atomide.com> and Imre Deak <imre.deak@nokia.com>
9 * Copyright (C) 2005 Nokia Corporation
10 *
96de0e25 11 * Cleaned up by Juha Yrjölä <juha.yrjola@nokia.com>
010d442c
KS		 12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27
28#include <linux/module.h>
29#include <linux/delay.h>
30#include <linux/i2c.h>
31#include <linux/err.h>
32#include <linux/interrupt.h>
33#include <linux/completion.h>
34#include <linux/platform_device.h>
35#include <linux/clk.h>
36
37#include <asm/io.h>
38
39/* timeout waiting for the controller to respond */
40#define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
41
42#define OMAP_I2C_REV_REG 0x00
43#define OMAP_I2C_IE_REG 0x04
44#define OMAP_I2C_STAT_REG 0x08
45#define OMAP_I2C_IV_REG 0x0c
46#define OMAP_I2C_SYSS_REG 0x10
47#define OMAP_I2C_BUF_REG 0x14
48#define OMAP_I2C_CNT_REG 0x18
49#define OMAP_I2C_DATA_REG 0x1c
50#define OMAP_I2C_SYSC_REG 0x20
51#define OMAP_I2C_CON_REG 0x24
52#define OMAP_I2C_OA_REG 0x28
53#define OMAP_I2C_SA_REG 0x2c
54#define OMAP_I2C_PSC_REG 0x30
55#define OMAP_I2C_SCLL_REG 0x34
56#define OMAP_I2C_SCLH_REG 0x38
57#define OMAP_I2C_SYSTEST_REG 0x3c
b6ee52c3 58#define OMAP_I2C_BUFSTAT_REG 0x40
010d442c
KS		 59
60/* I2C Interrupt Enable Register (OMAP_I2C_IE): */
b6ee52c3
NM		 61#define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */
62#define OMAP_I2C_IE_RDR (1 << 13) /* RX Buffer drain int enable */
010d442c
KS		 63#define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */
64#define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */
65#define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */
66#define OMAP_I2C_IE_NACK (1 << 1) /* No ack interrupt enable */
67#define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */
68
69/* I2C Status Register (OMAP_I2C_STAT): */
b6ee52c3
NM		 70#define OMAP_I2C_STAT_XDR (1 << 14) /* TX Buffer draining */
71#define OMAP_I2C_STAT_RDR (1 << 13) /* RX Buffer draining */
010d442c
KS		 72#define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */
73#define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */
74#define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
75#define OMAP_I2C_STAT_AAS (1 << 9) /* Address as slave */
76#define OMAP_I2C_STAT_AD0 (1 << 8) /* Address zero */
77#define OMAP_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
78#define OMAP_I2C_STAT_RRDY (1 << 3) /* Receive data ready */
79#define OMAP_I2C_STAT_ARDY (1 << 2) /* Register access ready */
80#define OMAP_I2C_STAT_NACK (1 << 1) /* No ack interrupt enable */
81#define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost int ena */
82
83/* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
84#define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */
b6ee52c3 85#define OMAP_I2C_BUF_RXFIF_CLR (1 << 14) /* RX FIFO Clear */
010d442c 86#define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */
b6ee52c3 87#define OMAP_I2C_BUF_TXFIF_CLR (1 << 6) /* TX FIFO Clear */
010d442c
KS		 88
89/* I2C Configuration Register (OMAP_I2C_CON): */
90#define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */
91#define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */
b6ee52c3 92#define OMAP_I2C_CON_OPMODE_HS (1 << 12) /* High Speed support */
010d442c
KS		 93#define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */
94#define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */
95#define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */
96#define OMAP_I2C_CON_XA (1 << 8) /* Expand address */
97#define OMAP_I2C_CON_RM (1 << 2) /* Repeat mode (master only) */
98#define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */
99#define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */
100
4574eb68
SMK		 101/* I2C SCL time value when Master */
102#define OMAP_I2C_SCLL_HSSCLL 8
103#define OMAP_I2C_SCLH_HSSCLH 8
104
010d442c
KS		 105/* I2C System Test Register (OMAP_I2C_SYSTEST): */
106#ifdef DEBUG
107#define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */
108#define OMAP_I2C_SYSTEST_FREE (1 << 14) /* Free running mode */
109#define OMAP_I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */
110#define OMAP_I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */
111#define OMAP_I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense in */
112#define OMAP_I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive out */
113#define OMAP_I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense in */
114#define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */
115#endif
116
117/* I2C System Status register (OMAP_I2C_SYSS): */
118#define OMAP_I2C_SYSS_RDONE (1 << 0) /* Reset Done */
119
120/* I2C System Configuration Register (OMAP_I2C_SYSC): */
121#define OMAP_I2C_SYSC_SRST (1 << 1) /* Soft Reset */
122
010d442c
KS		 123struct omap_i2c_dev {
124 struct device *dev;
125 void __iomem *base; /* virtual */
126 int irq;
127 struct clk *iclk; /* Interface clock */
128 struct clk *fclk; /* Functional clock */
129 struct completion cmd_complete;
130 struct resource *ioarea;
4574eb68 131 u32 speed; /* Speed of bus in Khz */
010d442c
KS		 132 u16 cmd_err;
133 u8 *buf;
134 size_t buf_len;
135 struct i2c_adapter adapter;
b6ee52c3
NM		 136 u8 fifo_size; /* use as flag and value
137 * fifo_size==0 implies no fifo
138 * if set, should be trsh+1
139 */
010d442c 140 unsigned rev1:1;
b6ee52c3 141 unsigned b_hw:1; /* bad h/w fixes */
f08ac4e7
TL		 142 unsigned idle:1;
143 u16 iestate; /* Saved interrupt register */
010d442c
KS		 144};
145
146static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev,
147 int reg, u16 val)
148{
149 __raw_writew(val, i2c_dev->base + reg);
150}
151
152static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
153{
154 return __raw_readw(i2c_dev->base + reg);
155}
156
510be9c9 157static int __init omap_i2c_get_clocks(struct omap_i2c_dev *dev)
010d442c 158{
3d522fb4 159 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
010d442c
KS		 160 dev->iclk = clk_get(dev->dev, "i2c_ick");
161 if (IS_ERR(dev->iclk)) {
162 dev->iclk = NULL;
163 return -ENODEV;
164 }
165 }
166
167 dev->fclk = clk_get(dev->dev, "i2c_fck");
168 if (IS_ERR(dev->fclk)) {
169 if (dev->iclk != NULL) {
170 clk_put(dev->iclk);
171 dev->iclk = NULL;
172 }
173 dev->fclk = NULL;
174 return -ENODEV;
175 }
176
177 return 0;
178}
179
180static void omap_i2c_put_clocks(struct omap_i2c_dev *dev)
181{
182 clk_put(dev->fclk);
183 dev->fclk = NULL;
184 if (dev->iclk != NULL) {
185 clk_put(dev->iclk);
186 dev->iclk = NULL;
187 }
188}
189
f08ac4e7 190static void omap_i2c_unidle(struct omap_i2c_dev *dev)
010d442c
KS		 191{
192 if (dev->iclk != NULL)
193 clk_enable(dev->iclk);
194 clk_enable(dev->fclk);
0cbbcffd 195 dev->idle = 0;
f08ac4e7
TL		 196 if (dev->iestate)
197 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
010d442c
KS		 198}
199
f08ac4e7 200static void omap_i2c_idle(struct omap_i2c_dev *dev)
010d442c 201{
f08ac4e7
TL		 202 u16 iv;
203
f08ac4e7
TL		 204 dev->iestate = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
205 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, 0);
0cbbcffd 206 if (dev->rev1) {
f08ac4e7 207 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG); /* Read clears */
0cbbcffd 208 } else {
f08ac4e7 209 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, dev->iestate);
0cbbcffd
PW		 210
211 /* Flush posted write before the dev->idle store occurs */
212 omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
213 }
214 dev->idle = 1;
f08ac4e7 215 clk_disable(dev->fclk);
010d442c
KS		 216 if (dev->iclk != NULL)
217 clk_disable(dev->iclk);
010d442c
KS		 218}
219
220static int omap_i2c_init(struct omap_i2c_dev *dev)
221{
4574eb68
SMK		 222 u16 psc = 0, scll = 0, sclh = 0;
223 u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
010d442c
KS		 224 unsigned long fclk_rate = 12000000;
225 unsigned long timeout;
4574eb68 226 unsigned long internal_clk = 0;
010d442c
KS		 227
228 if (!dev->rev1) {
229 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, OMAP_I2C_SYSC_SRST);
230 /* For some reason we need to set the EN bit before the
231 * reset done bit gets set. */
232 timeout = jiffies + OMAP_I2C_TIMEOUT;
233 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
234 while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) &
235 OMAP_I2C_SYSS_RDONE)) {
236 if (time_after(jiffies, timeout)) {
fce3ff03 237 dev_warn(dev->dev, "timeout waiting "
010d442c
KS		 238 "for controller reset\n");
239 return -ETIMEDOUT;
240 }
241 msleep(1);
242 }
243 }
244 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
245
246 if (cpu_class_is_omap1()) {
247 struct clk *armxor_ck;
248
249 armxor_ck = clk_get(NULL, "armxor_ck");
250 if (IS_ERR(armxor_ck))
251 dev_warn(dev->dev, "Could not get armxor_ck\n");
252 else {
253 fclk_rate = clk_get_rate(armxor_ck);
254 clk_put(armxor_ck);
255 }
256 /* TRM for 5912 says the I2C clock must be prescaled to be
257 * between 7 - 12 MHz. The XOR input clock is typically
258 * 12, 13 or 19.2 MHz. So we should have code that produces:
259 *
260 * XOR MHz Divider Prescaler
261 * 12 1 0
262 * 13 2 1
263 * 19.2 2 1
264 */
d7aef138
JD		 265 if (fclk_rate > 12000000)
266 psc = fclk_rate / 12000000;
010d442c
KS		 267 }
268
3d522fb4 269 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
4574eb68
SMK		 270
271 /* HSI2C controller internal clk rate should be 19.2 Mhz */
272 internal_clk = 19200;
273 fclk_rate = clk_get_rate(dev->fclk) / 1000;
274
275 /* Compute prescaler divisor */
276 psc = fclk_rate / internal_clk;
277 psc = psc - 1;
278
279 /* If configured for High Speed */
280 if (dev->speed > 400) {
281 /* For first phase of HS mode */
282 fsscll = internal_clk / (400 * 2) - 6;
283 fssclh = internal_clk / (400 * 2) - 6;
284
285 /* For second phase of HS mode */
286 hsscll = fclk_rate / (dev->speed * 2) - 6;
287 hssclh = fclk_rate / (dev->speed * 2) - 6;
288 } else {
289 /* To handle F/S modes */
290 fsscll = internal_clk / (dev->speed * 2) - 6;
291 fssclh = internal_clk / (dev->speed * 2) - 6;
292 }
293 scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
294 sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
295 } else {
296 /* Program desired operating rate */
297 fclk_rate /= (psc + 1) * 1000;
298 if (psc > 2)
299 psc = 2;
300 scll = fclk_rate / (dev->speed * 2) - 7 + psc;
301 sclh = fclk_rate / (dev->speed * 2) - 7 + psc;
302 }
303
010d442c
KS		 304 /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
305 omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc);
306
4574eb68
SMK		 307 /* SCL low and high time values */
308 omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, scll);
309 omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, sclh);
010d442c 310
b6ee52c3
NM		 311 if (dev->fifo_size)
312 /* Note: setup required fifo size - 1 */
313 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG,
314 (dev->fifo_size - 1) << 8 | /* RTRSH */
315 OMAP_I2C_BUF_RXFIF_CLR |
316 (dev->fifo_size - 1) | /* XTRSH */
317 OMAP_I2C_BUF_TXFIF_CLR);
318
010d442c
KS		 319 /* Take the I2C module out of reset: */
320 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
321
322 /* Enable interrupts */
323 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG,
324 (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
325 OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
b6ee52c3
NM		 326 OMAP_I2C_IE_AL) | ((dev->fifo_size) ?
327 (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0));
010d442c
KS		 328 return 0;
329}
330
331/*
332 * Waiting on Bus Busy
333 */
334static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev)
335{
336 unsigned long timeout;
337
338 timeout = jiffies + OMAP_I2C_TIMEOUT;
339 while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
340 if (time_after(jiffies, timeout)) {
341 dev_warn(dev->dev, "timeout waiting for bus ready\n");
342 return -ETIMEDOUT;
343 }
344 msleep(1);
345 }
346
347 return 0;
348}
349
350/*
351 * Low level master read/write transaction.
352 */
353static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
354 struct i2c_msg *msg, int stop)
355{
356 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
357 int r;
358 u16 w;
359
360 dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
361 msg->addr, msg->len, msg->flags, stop);
362
363 if (msg->len == 0)
364 return -EINVAL;
365
366 omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);
367
368 /* REVISIT: Could the STB bit of I2C_CON be used with probing? */
369 dev->buf = msg->buf;
370 dev->buf_len = msg->len;
371
372 omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len);
373
b6ee52c3
NM		 374 /* Clear the FIFO Buffers */
375 w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
376 w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR;
377 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w);
378
010d442c
KS		 379 init_completion(&dev->cmd_complete);
380 dev->cmd_err = 0;
381
382 w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
4574eb68
SMK		 383
384 /* High speed configuration */
385 if (dev->speed > 400)
b6ee52c3 386 w |= OMAP_I2C_CON_OPMODE_HS;
4574eb68 387
010d442c
KS		 388 if (msg->flags & I2C_M_TEN)
389 w |= OMAP_I2C_CON_XA;
390 if (!(msg->flags & I2C_M_RD))
391 w |= OMAP_I2C_CON_TRX;
b6ee52c3 392 if (!dev->b_hw && stop)
010d442c
KS		 393 w |= OMAP_I2C_CON_STP;
394 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
395
b6ee52c3
NM		 396 /*
397 * Don't write stt and stp together on some hardware.
398 */
399 if (dev->b_hw && stop) {
400 unsigned long delay = jiffies + OMAP_I2C_TIMEOUT;
401 u16 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
402 while (con & OMAP_I2C_CON_STT) {
403 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
404
405 /* Let the user know if i2c is in a bad state */
406 if (time_after(jiffies, delay)) {
407 dev_err(dev->dev, "controller timed out "
408 "waiting for start condition to finish\n");
409 return -ETIMEDOUT;
410 }
411 cpu_relax();
412 }
413
414 w |= OMAP_I2C_CON_STP;
415 w &= ~OMAP_I2C_CON_STT;
416 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
417 }
418
b7af349b
JN		 419 /*
420 * REVISIT: We should abort the transfer on signals, but the bus goes
421 * into arbitration and we're currently unable to recover from it.
422 */
423 r = wait_for_completion_timeout(&dev->cmd_complete,
424 OMAP_I2C_TIMEOUT);
010d442c
KS		 425 dev->buf_len = 0;
426 if (r < 0)
427 return r;
428 if (r == 0) {
429 dev_err(dev->dev, "controller timed out\n");
430 omap_i2c_init(dev);
431 return -ETIMEDOUT;
432 }
433
434 if (likely(!dev->cmd_err))
435 return 0;
436
437 /* We have an error */
438 if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR |
439 OMAP_I2C_STAT_XUDF)) {
440 omap_i2c_init(dev);
441 return -EIO;
442 }
443
444 if (dev->cmd_err & OMAP_I2C_STAT_NACK) {
445 if (msg->flags & I2C_M_IGNORE_NAK)
446 return 0;
447 if (stop) {
448 w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
449 w |= OMAP_I2C_CON_STP;
450 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
451 }
452 return -EREMOTEIO;
453 }
454 return -EIO;
455}
456
457
458/*
459 * Prepare controller for a transaction and call omap_i2c_xfer_msg
460 * to do the work during IRQ processing.
461 */
462static int
463omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
464{
465 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
466 int i;
467 int r;
468
f08ac4e7 469 omap_i2c_unidle(dev);
010d442c 470
010d442c
KS		 471 if ((r = omap_i2c_wait_for_bb(dev)) < 0)
472 goto out;
473
474 for (i = 0; i < num; i++) {
475 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));
476 if (r != 0)
477 break;
478 }
479
480 if (r == 0)
481 r = num;
482out:
f08ac4e7 483 omap_i2c_idle(dev);
010d442c
KS		 484 return r;
485}
486
487static u32
488omap_i2c_func(struct i2c_adapter *adap)
489{
490 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
491}
492
493static inline void
494omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err)
495{
496 dev->cmd_err |= err;
497 complete(&dev->cmd_complete);
498}
499
500static inline void
501omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat)
502{
503 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
504}
505
43469d8e
PW		 506/* rev1 devices are apparently only on some 15xx */
507#ifdef CONFIG_ARCH_OMAP15XX
508
010d442c 509static irqreturn_t
7d12e780 510omap_i2c_rev1_isr(int this_irq, void *dev_id)
010d442c
KS		 511{
512 struct omap_i2c_dev *dev = dev_id;
513 u16 iv, w;
514
f08ac4e7
TL		 515 if (dev->idle)
516 return IRQ_NONE;
517
010d442c
KS		 518 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
519 switch (iv) {
520 case 0x00: /* None */
521 break;
522 case 0x01: /* Arbitration lost */
523 dev_err(dev->dev, "Arbitration lost\n");
524 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
525 break;
526 case 0x02: /* No acknowledgement */
527 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
528 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
529 break;
530 case 0x03: /* Register access ready */
531 omap_i2c_complete_cmd(dev, 0);
532 break;
533 case 0x04: /* Receive data ready */
534 if (dev->buf_len) {
535 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
536 *dev->buf++ = w;
537 dev->buf_len--;
538 if (dev->buf_len) {
539 *dev->buf++ = w >> 8;
540 dev->buf_len--;
541 }
542 } else
543 dev_err(dev->dev, "RRDY IRQ while no data requested\n");
544 break;
545 case 0x05: /* Transmit data ready */
546 if (dev->buf_len) {
547 w = *dev->buf++;
548 dev->buf_len--;
549 if (dev->buf_len) {
550 w |= *dev->buf++ << 8;
551 dev->buf_len--;
552 }
553 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
554 } else
555 dev_err(dev->dev, "XRDY IRQ while no data to send\n");
556 break;
557 default:
558 return IRQ_NONE;
559 }
560
561 return IRQ_HANDLED;
562}
43469d8e
PW		 563#else
564#define omap_i2c_rev1_isr 0
565#endif
010d442c
KS		 566
567static irqreturn_t
7d12e780 568omap_i2c_isr(int this_irq, void *dev_id)
010d442c
KS		 569{
570 struct omap_i2c_dev *dev = dev_id;
571 u16 bits;
572 u16 stat, w;
b6ee52c3 573 int err, count = 0;
010d442c 574
f08ac4e7
TL		 575 if (dev->idle)
576 return IRQ_NONE;
577
010d442c
KS		 578 bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
579 while ((stat = (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG))) & bits) {
580 dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat);
581 if (count++ == 100) {
582 dev_warn(dev->dev, "Too much work in one IRQ\n");
583 break;
584 }
585
586 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
587
b6ee52c3
NM		 588 err = 0;
589 if (stat & OMAP_I2C_STAT_NACK) {
590 err |= OMAP_I2C_STAT_NACK;
591 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
592 OMAP_I2C_CON_STP);
010d442c 593 }
b6ee52c3
NM		 594 if (stat & OMAP_I2C_STAT_AL) {
595 dev_err(dev->dev, "Arbitration lost\n");
596 err |= OMAP_I2C_STAT_AL;
597 }
598 if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
599 OMAP_I2C_STAT_AL))
600 omap_i2c_complete_cmd(dev, err);
601 if (stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR)) {
602 u8 num_bytes = 1;
603 if (dev->fifo_size) {
604 if (stat & OMAP_I2C_STAT_RRDY)
605 num_bytes = dev->fifo_size;
606 else
607 num_bytes = omap_i2c_read_reg(dev,
608 OMAP_I2C_BUFSTAT_REG);
609 }
610 while (num_bytes) {
611 num_bytes--;
612 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
010d442c 613 if (dev->buf_len) {
b6ee52c3 614 *dev->buf++ = w;
010d442c 615 dev->buf_len--;
b6ee52c3 616 /* Data reg from 2430 is 8 bit wide */
3d522fb4
C		 617 if (!cpu_is_omap2430() &&
618 !cpu_is_omap34xx()) {
b6ee52c3
NM		 619 if (dev->buf_len) {
620 *dev->buf++ = w >> 8;
621 dev->buf_len--;
622 }
623 }
624 } else {
625 if (stat & OMAP_I2C_STAT_RRDY)
626 dev_err(dev->dev,
627 "RRDY IRQ while no data"
628 " requested\n");
629 if (stat & OMAP_I2C_STAT_RDR)
630 dev_err(dev->dev,
631 "RDR IRQ while no data"
632 " requested\n");
633 break;
010d442c 634 }
b6ee52c3
NM		 635 }
636 omap_i2c_ack_stat(dev,
637 stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR));
010d442c
KS		 638 continue;
639 }
b6ee52c3
NM		 640 if (stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR)) {
641 u8 num_bytes = 1;
642 if (dev->fifo_size) {
643 if (stat & OMAP_I2C_STAT_XRDY)
644 num_bytes = dev->fifo_size;
645 else
646 num_bytes = omap_i2c_read_reg(dev,
647 OMAP_I2C_BUFSTAT_REG);
648 }
649 while (num_bytes) {
650 num_bytes--;
651 w = 0;
010d442c 652 if (dev->buf_len) {
b6ee52c3 653 w = *dev->buf++;
010d442c 654 dev->buf_len--;
b6ee52c3 655 /* Data reg from 2430 is 8 bit wide */
3d522fb4
C		 656 if (!cpu_is_omap2430() &&
657 !cpu_is_omap34xx()) {
b6ee52c3
NM		 658 if (dev->buf_len) {
659 w |= *dev->buf++ << 8;
660 dev->buf_len--;
661 }
662 }
663 } else {
664 if (stat & OMAP_I2C_STAT_XRDY)
665 dev_err(dev->dev,
666 "XRDY IRQ while no "
667 "data to send\n");
668 if (stat & OMAP_I2C_STAT_XDR)
669 dev_err(dev->dev,
670 "XDR IRQ while no "
671 "data to send\n");
672 break;
010d442c 673 }
b6ee52c3
NM		 674 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
675 }
676 omap_i2c_ack_stat(dev,
677 stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
010d442c
KS		 678 continue;
679 }
680 if (stat & OMAP_I2C_STAT_ROVR) {
681 dev_err(dev->dev, "Receive overrun\n");
682 dev->cmd_err |= OMAP_I2C_STAT_ROVR;
683 }
684 if (stat & OMAP_I2C_STAT_XUDF) {
b6ee52c3 685 dev_err(dev->dev, "Transmit underflow\n");
010d442c
KS		 686 dev->cmd_err |= OMAP_I2C_STAT_XUDF;
687 }
010d442c
KS		 688 }
689
690 return count ? IRQ_HANDLED : IRQ_NONE;
691}
692
8f9082c5 693static const struct i2c_algorithm omap_i2c_algo = {
010d442c
KS		 694 .master_xfer = omap_i2c_xfer,
695 .functionality = omap_i2c_func,
696};
697
510be9c9 698static int __init
010d442c
KS		 699omap_i2c_probe(struct platform_device *pdev)
700{
701 struct omap_i2c_dev *dev;
702 struct i2c_adapter *adap;
703 struct resource *mem, *irq, *ioarea;
704 int r;
3d522fb4 705 u32 speed = 0;
010d442c
KS		 706
707 /* NOTE: driver uses the static register mapping */
708 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
709 if (!mem) {
710 dev_err(&pdev->dev, "no mem resource?\n");
711 return -ENODEV;
712 }
713 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
714 if (!irq) {
715 dev_err(&pdev->dev, "no irq resource?\n");
716 return -ENODEV;
717 }
718
719 ioarea = request_mem_region(mem->start, (mem->end - mem->start) + 1,
720 pdev->name);
721 if (!ioarea) {
722 dev_err(&pdev->dev, "I2C region already claimed\n");
723 return -EBUSY;
724 }
725
010d442c
KS		 726 dev = kzalloc(sizeof(struct omap_i2c_dev), GFP_KERNEL);
727 if (!dev) {
728 r = -ENOMEM;
729 goto err_release_region;
730 }
731
4574eb68 732 if (pdev->dev.platform_data != NULL)
3d522fb4 733 speed = *(u32 *)pdev->dev.platform_data;
4574eb68 734 else
3d522fb4 735 speed = 100; /* Defualt speed */
4574eb68 736
3d522fb4 737 dev->speed = speed;
010d442c
KS		 738 dev->dev = &pdev->dev;
739 dev->irq = irq->start;
55c381e4
RK		 740 dev->base = ioremap(mem->start, mem->end - mem->start + 1);
741 if (!dev->base) {
742 r = -ENOMEM;
743 goto err_free_mem;
744 }
745
010d442c
KS		 746 platform_set_drvdata(pdev, dev);
747
748 if ((r = omap_i2c_get_clocks(dev)) != 0)
55c381e4 749 goto err_iounmap;
010d442c 750
f08ac4e7 751 omap_i2c_unidle(dev);
010d442c
KS		 752
753 if (cpu_is_omap15xx())
754 dev->rev1 = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) < 0x20;
755
3d522fb4 756 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
b6ee52c3
NM		 757 u16 s;
758
759 /* Set up the fifo size - Get total size */
760 s = (omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3;
761 dev->fifo_size = 0x8 << s;
762
763 /*
764 * Set up notification threshold as half the total available
765 * size. This is to ensure that we can handle the status on int
766 * call back latencies.
767 */
768 dev->fifo_size = (dev->fifo_size / 2);
769 dev->b_hw = 1; /* Enable hardware fixes */
770 }
771
010d442c
KS		 772 /* reset ASAP, clearing any IRQs */
773 omap_i2c_init(dev);
774
775 r = request_irq(dev->irq, dev->rev1 ? omap_i2c_rev1_isr : omap_i2c_isr,
776 0, pdev->name, dev);
777
778 if (r) {
779 dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
780 goto err_unuse_clocks;
781 }
782 r = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff;
783 dev_info(dev->dev, "bus %d rev%d.%d at %d kHz\n",
4574eb68 784 pdev->id, r >> 4, r & 0xf, dev->speed);
010d442c
KS		 785
786 adap = &dev->adapter;
787 i2c_set_adapdata(adap, dev);
788 adap->owner = THIS_MODULE;
789 adap->class = I2C_CLASS_HWMON;
790 strncpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
791 adap->algo = &omap_i2c_algo;
792 adap->dev.parent = &pdev->dev;
793
794 /* i2c device drivers may be active on return from add_adapter() */
7c175499
DB		 795 adap->nr = pdev->id;
796 r = i2c_add_numbered_adapter(adap);
010d442c
KS		 797 if (r) {
798 dev_err(dev->dev, "failure adding adapter\n");
799 goto err_free_irq;
800 }
801
f08ac4e7 802 omap_i2c_idle(dev);
010d442c
KS		 803
804 return 0;
805
806err_free_irq:
807 free_irq(dev->irq, dev);
808err_unuse_clocks:
3e39752d 809 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
f08ac4e7 810 omap_i2c_idle(dev);
010d442c 811 omap_i2c_put_clocks(dev);
55c381e4
RK		 812err_iounmap:
813 iounmap(dev->base);
010d442c
KS		 814err_free_mem:
815 platform_set_drvdata(pdev, NULL);
816 kfree(dev);
817err_release_region:
010d442c
KS		 818 release_mem_region(mem->start, (mem->end - mem->start) + 1);
819
820 return r;
821}
822
823static int
824omap_i2c_remove(struct platform_device *pdev)
825{
826 struct omap_i2c_dev *dev = platform_get_drvdata(pdev);
827 struct resource *mem;
828
829 platform_set_drvdata(pdev, NULL);
830
831 free_irq(dev->irq, dev);
832 i2c_del_adapter(&dev->adapter);
833 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
834 omap_i2c_put_clocks(dev);
55c381e4 835 iounmap(dev->base);
010d442c
KS		 836 kfree(dev);
837 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
838 release_mem_region(mem->start, (mem->end - mem->start) + 1);
839 return 0;
840}
841
842static struct platform_driver omap_i2c_driver = {
843 .probe = omap_i2c_probe,
844 .remove = omap_i2c_remove,
845 .driver = {
846 .name = "i2c_omap",
847 .owner = THIS_MODULE,
848 },
849};
850
851/* I2C may be needed to bring up other drivers */
852static int __init
853omap_i2c_init_driver(void)
854{
855 return platform_driver_register(&omap_i2c_driver);
856}
857subsys_initcall(omap_i2c_init_driver);
858
859static void __exit omap_i2c_exit_driver(void)
860{
861 platform_driver_unregister(&omap_i2c_driver);
862}
863module_exit(omap_i2c_exit_driver);
864
865MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
866MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
867MODULE_LICENSE("GPL");
add8eda7 868MODULE_ALIAS("platform:i2c_omap");
Linux kernel - Deliverables
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