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i2c-omap: Add high-speed support to omap-i2c
[deliverable/linux.git] / drivers / i2c / busses / i2c-omap.c
CommitLineData
010d442c
KS		 1/*
2 * TI OMAP I2C master mode driver
3 *
4 * Copyright (C) 2003 MontaVista Software, Inc.
5 * Copyright (C) 2004 Texas Instruments.
6 *
7 * Updated to work with multiple I2C interfaces on 24xx by
8 * Tony Lindgren <tony@atomide.com> and Imre Deak <imre.deak@nokia.com>
9 * Copyright (C) 2005 Nokia Corporation
10 *
96de0e25 11 * Cleaned up by Juha Yrjölä <juha.yrjola@nokia.com>
010d442c
KS		 12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27
28#include <linux/module.h>
29#include <linux/delay.h>
30#include <linux/i2c.h>
31#include <linux/err.h>
32#include <linux/interrupt.h>
33#include <linux/completion.h>
34#include <linux/platform_device.h>
35#include <linux/clk.h>
36
37#include <asm/io.h>
38
39/* timeout waiting for the controller to respond */
40#define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
41
42#define OMAP_I2C_REV_REG 0x00
43#define OMAP_I2C_IE_REG 0x04
44#define OMAP_I2C_STAT_REG 0x08
45#define OMAP_I2C_IV_REG 0x0c
46#define OMAP_I2C_SYSS_REG 0x10
47#define OMAP_I2C_BUF_REG 0x14
48#define OMAP_I2C_CNT_REG 0x18
49#define OMAP_I2C_DATA_REG 0x1c
50#define OMAP_I2C_SYSC_REG 0x20
51#define OMAP_I2C_CON_REG 0x24
52#define OMAP_I2C_OA_REG 0x28
53#define OMAP_I2C_SA_REG 0x2c
54#define OMAP_I2C_PSC_REG 0x30
55#define OMAP_I2C_SCLL_REG 0x34
56#define OMAP_I2C_SCLH_REG 0x38
57#define OMAP_I2C_SYSTEST_REG 0x3c
58
59/* I2C Interrupt Enable Register (OMAP_I2C_IE): */
60#define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */
61#define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */
62#define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */
63#define OMAP_I2C_IE_NACK (1 << 1) /* No ack interrupt enable */
64#define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */
65
66/* I2C Status Register (OMAP_I2C_STAT): */
67#define OMAP_I2C_STAT_SBD (1 << 15) /* Single byte data */
68#define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */
69#define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */
70#define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
71#define OMAP_I2C_STAT_AAS (1 << 9) /* Address as slave */
72#define OMAP_I2C_STAT_AD0 (1 << 8) /* Address zero */
73#define OMAP_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
74#define OMAP_I2C_STAT_RRDY (1 << 3) /* Receive data ready */
75#define OMAP_I2C_STAT_ARDY (1 << 2) /* Register access ready */
76#define OMAP_I2C_STAT_NACK (1 << 1) /* No ack interrupt enable */
77#define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost int ena */
78
79/* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
80#define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */
81#define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */
82
83/* I2C Configuration Register (OMAP_I2C_CON): */
84#define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */
85#define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */
4574eb68 86#define OMAP_I2C_CON_OPMODE (1 << 12) /* High Speed support */
010d442c
KS		 87#define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */
88#define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */
89#define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */
90#define OMAP_I2C_CON_XA (1 << 8) /* Expand address */
91#define OMAP_I2C_CON_RM (1 << 2) /* Repeat mode (master only) */
92#define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */
93#define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */
94
4574eb68
SMK		 95/* I2C SCL time value when Master */
96#define OMAP_I2C_SCLL_HSSCLL 8
97#define OMAP_I2C_SCLH_HSSCLH 8
98
010d442c
KS		 99/* I2C System Test Register (OMAP_I2C_SYSTEST): */
100#ifdef DEBUG
101#define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */
102#define OMAP_I2C_SYSTEST_FREE (1 << 14) /* Free running mode */
103#define OMAP_I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */
104#define OMAP_I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */
105#define OMAP_I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense in */
106#define OMAP_I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive out */
107#define OMAP_I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense in */
108#define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */
109#endif
110
111/* I2C System Status register (OMAP_I2C_SYSS): */
112#define OMAP_I2C_SYSS_RDONE (1 << 0) /* Reset Done */
113
114/* I2C System Configuration Register (OMAP_I2C_SYSC): */
115#define OMAP_I2C_SYSC_SRST (1 << 1) /* Soft Reset */
116
010d442c
KS		 117struct omap_i2c_dev {
118 struct device *dev;
119 void __iomem *base; /* virtual */
120 int irq;
121 struct clk *iclk; /* Interface clock */
122 struct clk *fclk; /* Functional clock */
123 struct completion cmd_complete;
124 struct resource *ioarea;
4574eb68 125 u32 speed; /* Speed of bus in Khz */
010d442c
KS		 126 u16 cmd_err;
127 u8 *buf;
128 size_t buf_len;
129 struct i2c_adapter adapter;
130 unsigned rev1:1;
f08ac4e7
TL		 131 unsigned idle:1;
132 u16 iestate; /* Saved interrupt register */
010d442c
KS		 133};
134
135static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev,
136 int reg, u16 val)
137{
138 __raw_writew(val, i2c_dev->base + reg);
139}
140
141static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
142{
143 return __raw_readw(i2c_dev->base + reg);
144}
145
146static int omap_i2c_get_clocks(struct omap_i2c_dev *dev)
147{
148 if (cpu_is_omap16xx() || cpu_is_omap24xx()) {
149 dev->iclk = clk_get(dev->dev, "i2c_ick");
150 if (IS_ERR(dev->iclk)) {
151 dev->iclk = NULL;
152 return -ENODEV;
153 }
154 }
155
156 dev->fclk = clk_get(dev->dev, "i2c_fck");
157 if (IS_ERR(dev->fclk)) {
158 if (dev->iclk != NULL) {
159 clk_put(dev->iclk);
160 dev->iclk = NULL;
161 }
162 dev->fclk = NULL;
163 return -ENODEV;
164 }
165
166 return 0;
167}
168
169static void omap_i2c_put_clocks(struct omap_i2c_dev *dev)
170{
171 clk_put(dev->fclk);
172 dev->fclk = NULL;
173 if (dev->iclk != NULL) {
174 clk_put(dev->iclk);
175 dev->iclk = NULL;
176 }
177}
178
f08ac4e7 179static void omap_i2c_unidle(struct omap_i2c_dev *dev)
010d442c
KS		 180{
181 if (dev->iclk != NULL)
182 clk_enable(dev->iclk);
183 clk_enable(dev->fclk);
0cbbcffd 184 dev->idle = 0;
f08ac4e7
TL		 185 if (dev->iestate)
186 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
010d442c
KS		 187}
188
f08ac4e7 189static void omap_i2c_idle(struct omap_i2c_dev *dev)
010d442c 190{
f08ac4e7
TL		 191 u16 iv;
192
f08ac4e7
TL		 193 dev->iestate = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
194 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, 0);
0cbbcffd 195 if (dev->rev1) {
f08ac4e7 196 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG); /* Read clears */
0cbbcffd 197 } else {
f08ac4e7 198 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, dev->iestate);
0cbbcffd
PW		 199
200 /* Flush posted write before the dev->idle store occurs */
201 omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
202 }
203 dev->idle = 1;
f08ac4e7 204 clk_disable(dev->fclk);
010d442c
KS		 205 if (dev->iclk != NULL)
206 clk_disable(dev->iclk);
010d442c
KS		 207}
208
209static int omap_i2c_init(struct omap_i2c_dev *dev)
210{
4574eb68
SMK		 211 u16 psc = 0, scll = 0, sclh = 0;
212 u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
010d442c
KS		 213 unsigned long fclk_rate = 12000000;
214 unsigned long timeout;
4574eb68 215 unsigned long internal_clk = 0;
010d442c
KS		 216
217 if (!dev->rev1) {
218 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, OMAP_I2C_SYSC_SRST);
219 /* For some reason we need to set the EN bit before the
220 * reset done bit gets set. */
221 timeout = jiffies + OMAP_I2C_TIMEOUT;
222 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
223 while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) &
224 OMAP_I2C_SYSS_RDONE)) {
225 if (time_after(jiffies, timeout)) {
fce3ff03 226 dev_warn(dev->dev, "timeout waiting "
010d442c
KS		 227 "for controller reset\n");
228 return -ETIMEDOUT;
229 }
230 msleep(1);
231 }
232 }
233 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
234
235 if (cpu_class_is_omap1()) {
236 struct clk *armxor_ck;
237
238 armxor_ck = clk_get(NULL, "armxor_ck");
239 if (IS_ERR(armxor_ck))
240 dev_warn(dev->dev, "Could not get armxor_ck\n");
241 else {
242 fclk_rate = clk_get_rate(armxor_ck);
243 clk_put(armxor_ck);
244 }
245 /* TRM for 5912 says the I2C clock must be prescaled to be
246 * between 7 - 12 MHz. The XOR input clock is typically
247 * 12, 13 or 19.2 MHz. So we should have code that produces:
248 *
249 * XOR MHz Divider Prescaler
250 * 12 1 0
251 * 13 2 1
252 * 19.2 2 1
253 */
d7aef138
JD		 254 if (fclk_rate > 12000000)
255 psc = fclk_rate / 12000000;
010d442c
KS		 256 }
257
4574eb68
SMK		 258 if (cpu_is_omap2430()) {
259
260 /* HSI2C controller internal clk rate should be 19.2 Mhz */
261 internal_clk = 19200;
262 fclk_rate = clk_get_rate(dev->fclk) / 1000;
263
264 /* Compute prescaler divisor */
265 psc = fclk_rate / internal_clk;
266 psc = psc - 1;
267
268 /* If configured for High Speed */
269 if (dev->speed > 400) {
270 /* For first phase of HS mode */
271 fsscll = internal_clk / (400 * 2) - 6;
272 fssclh = internal_clk / (400 * 2) - 6;
273
274 /* For second phase of HS mode */
275 hsscll = fclk_rate / (dev->speed * 2) - 6;
276 hssclh = fclk_rate / (dev->speed * 2) - 6;
277 } else {
278 /* To handle F/S modes */
279 fsscll = internal_clk / (dev->speed * 2) - 6;
280 fssclh = internal_clk / (dev->speed * 2) - 6;
281 }
282 scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
283 sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
284 } else {
285 /* Program desired operating rate */
286 fclk_rate /= (psc + 1) * 1000;
287 if (psc > 2)
288 psc = 2;
289 scll = fclk_rate / (dev->speed * 2) - 7 + psc;
290 sclh = fclk_rate / (dev->speed * 2) - 7 + psc;
291 }
292
010d442c
KS		 293 /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
294 omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc);
295
4574eb68
SMK		 296 /* SCL low and high time values */
297 omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, scll);
298 omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, sclh);
010d442c
KS		 299
300 /* Take the I2C module out of reset: */
301 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
302
303 /* Enable interrupts */
304 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG,
305 (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
306 OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
307 OMAP_I2C_IE_AL));
308 return 0;
309}
310
311/*
312 * Waiting on Bus Busy
313 */
314static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev)
315{
316 unsigned long timeout;
317
318 timeout = jiffies + OMAP_I2C_TIMEOUT;
319 while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
320 if (time_after(jiffies, timeout)) {
321 dev_warn(dev->dev, "timeout waiting for bus ready\n");
322 return -ETIMEDOUT;
323 }
324 msleep(1);
325 }
326
327 return 0;
328}
329
330/*
331 * Low level master read/write transaction.
332 */
333static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
334 struct i2c_msg *msg, int stop)
335{
336 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
337 int r;
338 u16 w;
339
340 dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
341 msg->addr, msg->len, msg->flags, stop);
342
343 if (msg->len == 0)
344 return -EINVAL;
345
346 omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);
347
348 /* REVISIT: Could the STB bit of I2C_CON be used with probing? */
349 dev->buf = msg->buf;
350 dev->buf_len = msg->len;
351
352 omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len);
353
354 init_completion(&dev->cmd_complete);
355 dev->cmd_err = 0;
356
357 w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
4574eb68
SMK		 358
359 /* High speed configuration */
360 if (dev->speed > 400)
361 w |= OMAP_I2C_CON_OPMODE;
362
010d442c
KS		 363 if (msg->flags & I2C_M_TEN)
364 w |= OMAP_I2C_CON_XA;
365 if (!(msg->flags & I2C_M_RD))
366 w |= OMAP_I2C_CON_TRX;
367 if (stop)
368 w |= OMAP_I2C_CON_STP;
369 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
370
b7af349b
JN		 371 /*
372 * REVISIT: We should abort the transfer on signals, but the bus goes
373 * into arbitration and we're currently unable to recover from it.
374 */
375 r = wait_for_completion_timeout(&dev->cmd_complete,
376 OMAP_I2C_TIMEOUT);
010d442c
KS		 377 dev->buf_len = 0;
378 if (r < 0)
379 return r;
380 if (r == 0) {
381 dev_err(dev->dev, "controller timed out\n");
382 omap_i2c_init(dev);
383 return -ETIMEDOUT;
384 }
385
386 if (likely(!dev->cmd_err))
387 return 0;
388
389 /* We have an error */
390 if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR |
391 OMAP_I2C_STAT_XUDF)) {
392 omap_i2c_init(dev);
393 return -EIO;
394 }
395
396 if (dev->cmd_err & OMAP_I2C_STAT_NACK) {
397 if (msg->flags & I2C_M_IGNORE_NAK)
398 return 0;
399 if (stop) {
400 w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
401 w |= OMAP_I2C_CON_STP;
402 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
403 }
404 return -EREMOTEIO;
405 }
406 return -EIO;
407}
408
409
410/*
411 * Prepare controller for a transaction and call omap_i2c_xfer_msg
412 * to do the work during IRQ processing.
413 */
414static int
415omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
416{
417 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
418 int i;
419 int r;
420
f08ac4e7 421 omap_i2c_unidle(dev);
010d442c 422
010d442c
KS		 423 if ((r = omap_i2c_wait_for_bb(dev)) < 0)
424 goto out;
425
426 for (i = 0; i < num; i++) {
427 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));
428 if (r != 0)
429 break;
430 }
431
432 if (r == 0)
433 r = num;
434out:
f08ac4e7 435 omap_i2c_idle(dev);
010d442c
KS		 436 return r;
437}
438
439static u32
440omap_i2c_func(struct i2c_adapter *adap)
441{
442 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
443}
444
445static inline void
446omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err)
447{
448 dev->cmd_err |= err;
449 complete(&dev->cmd_complete);
450}
451
452static inline void
453omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat)
454{
455 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
456}
457
458static irqreturn_t
7d12e780 459omap_i2c_rev1_isr(int this_irq, void *dev_id)
010d442c
KS		 460{
461 struct omap_i2c_dev *dev = dev_id;
462 u16 iv, w;
463
f08ac4e7
TL		 464 if (dev->idle)
465 return IRQ_NONE;
466
010d442c
KS		 467 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
468 switch (iv) {
469 case 0x00: /* None */
470 break;
471 case 0x01: /* Arbitration lost */
472 dev_err(dev->dev, "Arbitration lost\n");
473 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
474 break;
475 case 0x02: /* No acknowledgement */
476 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
477 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
478 break;
479 case 0x03: /* Register access ready */
480 omap_i2c_complete_cmd(dev, 0);
481 break;
482 case 0x04: /* Receive data ready */
483 if (dev->buf_len) {
484 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
485 *dev->buf++ = w;
486 dev->buf_len--;
487 if (dev->buf_len) {
488 *dev->buf++ = w >> 8;
489 dev->buf_len--;
490 }
491 } else
492 dev_err(dev->dev, "RRDY IRQ while no data requested\n");
493 break;
494 case 0x05: /* Transmit data ready */
495 if (dev->buf_len) {
496 w = *dev->buf++;
497 dev->buf_len--;
498 if (dev->buf_len) {
499 w |= *dev->buf++ << 8;
500 dev->buf_len--;
501 }
502 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
503 } else
504 dev_err(dev->dev, "XRDY IRQ while no data to send\n");
505 break;
506 default:
507 return IRQ_NONE;
508 }
509
510 return IRQ_HANDLED;
511}
512
513static irqreturn_t
7d12e780 514omap_i2c_isr(int this_irq, void *dev_id)
010d442c
KS		 515{
516 struct omap_i2c_dev *dev = dev_id;
517 u16 bits;
518 u16 stat, w;
519 int count = 0;
520
f08ac4e7
TL		 521 if (dev->idle)
522 return IRQ_NONE;
523
010d442c
KS		 524 bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
525 while ((stat = (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG))) & bits) {
526 dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat);
527 if (count++ == 100) {
528 dev_warn(dev->dev, "Too much work in one IRQ\n");
529 break;
530 }
531
532 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
533
534 if (stat & OMAP_I2C_STAT_ARDY) {
535 omap_i2c_complete_cmd(dev, 0);
536 continue;
537 }
538 if (stat & OMAP_I2C_STAT_RRDY) {
539 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
540 if (dev->buf_len) {
541 *dev->buf++ = w;
542 dev->buf_len--;
543 if (dev->buf_len) {
544 *dev->buf++ = w >> 8;
545 dev->buf_len--;
546 }
547 } else
fce3ff03 548 dev_err(dev->dev, "RRDY IRQ while no data "
010d442c
KS		 549 "requested\n");
550 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RRDY);
551 continue;
552 }
553 if (stat & OMAP_I2C_STAT_XRDY) {
554 w = 0;
555 if (dev->buf_len) {
556 w = *dev->buf++;
557 dev->buf_len--;
558 if (dev->buf_len) {
559 w |= *dev->buf++ << 8;
560 dev->buf_len--;
561 }
562 } else
fce3ff03 563 dev_err(dev->dev, "XRDY IRQ while no "
010d442c
KS		 564 "data to send\n");
565 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
566 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XRDY);
567 continue;
568 }
569 if (stat & OMAP_I2C_STAT_ROVR) {
570 dev_err(dev->dev, "Receive overrun\n");
571 dev->cmd_err |= OMAP_I2C_STAT_ROVR;
572 }
573 if (stat & OMAP_I2C_STAT_XUDF) {
574 dev_err(dev->dev, "Transmit overflow\n");
575 dev->cmd_err |= OMAP_I2C_STAT_XUDF;
576 }
577 if (stat & OMAP_I2C_STAT_NACK) {
578 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
579 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
580 OMAP_I2C_CON_STP);
581 }
582 if (stat & OMAP_I2C_STAT_AL) {
583 dev_err(dev->dev, "Arbitration lost\n");
584 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
585 }
586 }
587
588 return count ? IRQ_HANDLED : IRQ_NONE;
589}
590
8f9082c5 591static const struct i2c_algorithm omap_i2c_algo = {
010d442c
KS		 592 .master_xfer = omap_i2c_xfer,
593 .functionality = omap_i2c_func,
594};
595
596static int
597omap_i2c_probe(struct platform_device *pdev)
598{
599 struct omap_i2c_dev *dev;
600 struct i2c_adapter *adap;
601 struct resource *mem, *irq, *ioarea;
602 int r;
4574eb68 603 u32 *speed = NULL;
010d442c
KS		 604
605 /* NOTE: driver uses the static register mapping */
606 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
607 if (!mem) {
608 dev_err(&pdev->dev, "no mem resource?\n");
609 return -ENODEV;
610 }
611 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
612 if (!irq) {
613 dev_err(&pdev->dev, "no irq resource?\n");
614 return -ENODEV;
615 }
616
617 ioarea = request_mem_region(mem->start, (mem->end - mem->start) + 1,
618 pdev->name);
619 if (!ioarea) {
620 dev_err(&pdev->dev, "I2C region already claimed\n");
621 return -EBUSY;
622 }
623
010d442c
KS		 624 dev = kzalloc(sizeof(struct omap_i2c_dev), GFP_KERNEL);
625 if (!dev) {
626 r = -ENOMEM;
627 goto err_release_region;
628 }
629
4574eb68
SMK		 630 if (pdev->dev.platform_data != NULL)
631 speed = (u32 *) pdev->dev.platform_data;
632 else
633 *speed = 100; /* Defualt speed */
634
635 dev->speed = *speed;
010d442c
KS		 636 dev->dev = &pdev->dev;
637 dev->irq = irq->start;
55c381e4
RK		 638 dev->base = ioremap(mem->start, mem->end - mem->start + 1);
639 if (!dev->base) {
640 r = -ENOMEM;
641 goto err_free_mem;
642 }
643
010d442c
KS		 644 platform_set_drvdata(pdev, dev);
645
646 if ((r = omap_i2c_get_clocks(dev)) != 0)
55c381e4 647 goto err_iounmap;
010d442c 648
f08ac4e7 649 omap_i2c_unidle(dev);
010d442c
KS		 650
651 if (cpu_is_omap15xx())
652 dev->rev1 = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) < 0x20;
653
654 /* reset ASAP, clearing any IRQs */
655 omap_i2c_init(dev);
656
657 r = request_irq(dev->irq, dev->rev1 ? omap_i2c_rev1_isr : omap_i2c_isr,
658 0, pdev->name, dev);
659
660 if (r) {
661 dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
662 goto err_unuse_clocks;
663 }
664 r = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff;
665 dev_info(dev->dev, "bus %d rev%d.%d at %d kHz\n",
4574eb68 666 pdev->id, r >> 4, r & 0xf, dev->speed);
010d442c
KS		 667
668 adap = &dev->adapter;
669 i2c_set_adapdata(adap, dev);
670 adap->owner = THIS_MODULE;
671 adap->class = I2C_CLASS_HWMON;
672 strncpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
673 adap->algo = &omap_i2c_algo;
674 adap->dev.parent = &pdev->dev;
675
676 /* i2c device drivers may be active on return from add_adapter() */
7c175499
DB		 677 adap->nr = pdev->id;
678 r = i2c_add_numbered_adapter(adap);
010d442c
KS		 679 if (r) {
680 dev_err(dev->dev, "failure adding adapter\n");
681 goto err_free_irq;
682 }
683
f08ac4e7 684 omap_i2c_idle(dev);
010d442c
KS		 685
686 return 0;
687
688err_free_irq:
689 free_irq(dev->irq, dev);
690err_unuse_clocks:
3e39752d 691 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
f08ac4e7 692 omap_i2c_idle(dev);
010d442c 693 omap_i2c_put_clocks(dev);
55c381e4
RK		 694err_iounmap:
695 iounmap(dev->base);
010d442c
KS		 696err_free_mem:
697 platform_set_drvdata(pdev, NULL);
698 kfree(dev);
699err_release_region:
010d442c
KS		 700 release_mem_region(mem->start, (mem->end - mem->start) + 1);
701
702 return r;
703}
704
705static int
706omap_i2c_remove(struct platform_device *pdev)
707{
708 struct omap_i2c_dev *dev = platform_get_drvdata(pdev);
709 struct resource *mem;
710
711 platform_set_drvdata(pdev, NULL);
712
713 free_irq(dev->irq, dev);
714 i2c_del_adapter(&dev->adapter);
715 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
716 omap_i2c_put_clocks(dev);
55c381e4 717 iounmap(dev->base);
010d442c
KS		 718 kfree(dev);
719 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
720 release_mem_region(mem->start, (mem->end - mem->start) + 1);
721 return 0;
722}
723
724static struct platform_driver omap_i2c_driver = {
725 .probe = omap_i2c_probe,
726 .remove = omap_i2c_remove,
727 .driver = {
728 .name = "i2c_omap",
729 .owner = THIS_MODULE,
730 },
731};
732
733/* I2C may be needed to bring up other drivers */
734static int __init
735omap_i2c_init_driver(void)
736{
737 return platform_driver_register(&omap_i2c_driver);
738}
739subsys_initcall(omap_i2c_init_driver);
740
741static void __exit omap_i2c_exit_driver(void)
742{
743 platform_driver_unregister(&omap_i2c_driver);
744}
745module_exit(omap_i2c_exit_driver);
746
747MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
748MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
749MODULE_LICENSE("GPL");
add8eda7 750MODULE_ALIAS("platform:i2c_omap");
Linux kernel - Deliverables
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