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010d442c KS |
1 | /* |
2 | * TI OMAP I2C master mode driver | |
3 | * | |
4 | * Copyright (C) 2003 MontaVista Software, Inc. | |
010d442c | 5 | * Copyright (C) 2005 Nokia Corporation |
c1a473bd | 6 | * Copyright (C) 2004 - 2007 Texas Instruments. |
010d442c | 7 | * |
c1a473bd TL |
8 | * Originally written by MontaVista Software, Inc. |
9 | * Additional contributions by: | |
10 | * Tony Lindgren <tony@atomide.com> | |
11 | * Imre Deak <imre.deak@nokia.com> | |
12 | * Juha Yrjölä <juha.yrjola@solidboot.com> | |
13 | * Syed Khasim <x0khasim@ti.com> | |
14 | * Nishant Menon <nm@ti.com> | |
010d442c KS |
15 | * |
16 | * This program is free software; you can redistribute it and/or modify | |
17 | * it under the terms of the GNU General Public License as published by | |
18 | * the Free Software Foundation; either version 2 of the License, or | |
19 | * (at your option) any later version. | |
20 | * | |
21 | * This program is distributed in the hope that it will be useful, | |
22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
24 | * GNU General Public License for more details. | |
25 | * | |
26 | * You should have received a copy of the GNU General Public License | |
27 | * along with this program; if not, write to the Free Software | |
28 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
29 | */ | |
30 | ||
31 | #include <linux/module.h> | |
32 | #include <linux/delay.h> | |
33 | #include <linux/i2c.h> | |
34 | #include <linux/err.h> | |
35 | #include <linux/interrupt.h> | |
36 | #include <linux/completion.h> | |
37 | #include <linux/platform_device.h> | |
38 | #include <linux/clk.h> | |
c1a473bd | 39 | #include <linux/io.h> |
5a0e3ad6 | 40 | #include <linux/slab.h> |
20c9d2c4 | 41 | #include <linux/i2c-omap.h> |
010d442c | 42 | |
9c76b878 PW |
43 | /* I2C controller revisions */ |
44 | #define OMAP_I2C_REV_2 0x20 | |
45 | ||
46 | /* I2C controller revisions present on specific hardware */ | |
47 | #define OMAP_I2C_REV_ON_2430 0x36 | |
48 | #define OMAP_I2C_REV_ON_3430 0x3C | |
f38e66e0 | 49 | #define OMAP_I2C_REV_ON_4430 0x40 |
9c76b878 | 50 | |
010d442c KS |
51 | /* timeout waiting for the controller to respond */ |
52 | #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000)) | |
53 | ||
5043e9e7 | 54 | /* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */ |
f38e66e0 SS |
55 | enum { |
56 | OMAP_I2C_REV_REG = 0, | |
57 | OMAP_I2C_IE_REG, | |
58 | OMAP_I2C_STAT_REG, | |
59 | OMAP_I2C_IV_REG, | |
60 | OMAP_I2C_WE_REG, | |
61 | OMAP_I2C_SYSS_REG, | |
62 | OMAP_I2C_BUF_REG, | |
63 | OMAP_I2C_CNT_REG, | |
64 | OMAP_I2C_DATA_REG, | |
65 | OMAP_I2C_SYSC_REG, | |
66 | OMAP_I2C_CON_REG, | |
67 | OMAP_I2C_OA_REG, | |
68 | OMAP_I2C_SA_REG, | |
69 | OMAP_I2C_PSC_REG, | |
70 | OMAP_I2C_SCLL_REG, | |
71 | OMAP_I2C_SCLH_REG, | |
72 | OMAP_I2C_SYSTEST_REG, | |
73 | OMAP_I2C_BUFSTAT_REG, | |
74 | OMAP_I2C_REVNB_LO, | |
75 | OMAP_I2C_REVNB_HI, | |
76 | OMAP_I2C_IRQSTATUS_RAW, | |
77 | OMAP_I2C_IRQENABLE_SET, | |
78 | OMAP_I2C_IRQENABLE_CLR, | |
79 | }; | |
010d442c KS |
80 | |
81 | /* I2C Interrupt Enable Register (OMAP_I2C_IE): */ | |
b6ee52c3 NM |
82 | #define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */ |
83 | #define OMAP_I2C_IE_RDR (1 << 13) /* RX Buffer drain int enable */ | |
010d442c KS |
84 | #define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */ |
85 | #define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */ | |
86 | #define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */ | |
87 | #define OMAP_I2C_IE_NACK (1 << 1) /* No ack interrupt enable */ | |
88 | #define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */ | |
89 | ||
90 | /* I2C Status Register (OMAP_I2C_STAT): */ | |
b6ee52c3 NM |
91 | #define OMAP_I2C_STAT_XDR (1 << 14) /* TX Buffer draining */ |
92 | #define OMAP_I2C_STAT_RDR (1 << 13) /* RX Buffer draining */ | |
010d442c KS |
93 | #define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */ |
94 | #define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */ | |
95 | #define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ | |
96 | #define OMAP_I2C_STAT_AAS (1 << 9) /* Address as slave */ | |
97 | #define OMAP_I2C_STAT_AD0 (1 << 8) /* Address zero */ | |
98 | #define OMAP_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ | |
99 | #define OMAP_I2C_STAT_RRDY (1 << 3) /* Receive data ready */ | |
100 | #define OMAP_I2C_STAT_ARDY (1 << 2) /* Register access ready */ | |
101 | #define OMAP_I2C_STAT_NACK (1 << 1) /* No ack interrupt enable */ | |
102 | #define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost int ena */ | |
103 | ||
5043e9e7 KJ |
104 | /* I2C WE wakeup enable register */ |
105 | #define OMAP_I2C_WE_XDR_WE (1 << 14) /* TX drain wakup */ | |
106 | #define OMAP_I2C_WE_RDR_WE (1 << 13) /* RX drain wakeup */ | |
107 | #define OMAP_I2C_WE_AAS_WE (1 << 9) /* Address as slave wakeup*/ | |
108 | #define OMAP_I2C_WE_BF_WE (1 << 8) /* Bus free wakeup */ | |
109 | #define OMAP_I2C_WE_STC_WE (1 << 6) /* Start condition wakeup */ | |
110 | #define OMAP_I2C_WE_GC_WE (1 << 5) /* General call wakeup */ | |
111 | #define OMAP_I2C_WE_DRDY_WE (1 << 3) /* TX/RX data ready wakeup */ | |
112 | #define OMAP_I2C_WE_ARDY_WE (1 << 2) /* Reg access ready wakeup */ | |
113 | #define OMAP_I2C_WE_NACK_WE (1 << 1) /* No acknowledgment wakeup */ | |
114 | #define OMAP_I2C_WE_AL_WE (1 << 0) /* Arbitration lost wakeup */ | |
115 | ||
116 | #define OMAP_I2C_WE_ALL (OMAP_I2C_WE_XDR_WE | OMAP_I2C_WE_RDR_WE | \ | |
117 | OMAP_I2C_WE_AAS_WE | OMAP_I2C_WE_BF_WE | \ | |
118 | OMAP_I2C_WE_STC_WE | OMAP_I2C_WE_GC_WE | \ | |
119 | OMAP_I2C_WE_DRDY_WE | OMAP_I2C_WE_ARDY_WE | \ | |
120 | OMAP_I2C_WE_NACK_WE | OMAP_I2C_WE_AL_WE) | |
121 | ||
010d442c KS |
122 | /* I2C Buffer Configuration Register (OMAP_I2C_BUF): */ |
123 | #define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */ | |
b6ee52c3 | 124 | #define OMAP_I2C_BUF_RXFIF_CLR (1 << 14) /* RX FIFO Clear */ |
010d442c | 125 | #define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */ |
b6ee52c3 | 126 | #define OMAP_I2C_BUF_TXFIF_CLR (1 << 6) /* TX FIFO Clear */ |
010d442c KS |
127 | |
128 | /* I2C Configuration Register (OMAP_I2C_CON): */ | |
129 | #define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */ | |
130 | #define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */ | |
b6ee52c3 | 131 | #define OMAP_I2C_CON_OPMODE_HS (1 << 12) /* High Speed support */ |
010d442c KS |
132 | #define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */ |
133 | #define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */ | |
134 | #define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */ | |
135 | #define OMAP_I2C_CON_XA (1 << 8) /* Expand address */ | |
136 | #define OMAP_I2C_CON_RM (1 << 2) /* Repeat mode (master only) */ | |
137 | #define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */ | |
138 | #define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */ | |
139 | ||
4574eb68 SMK |
140 | /* I2C SCL time value when Master */ |
141 | #define OMAP_I2C_SCLL_HSSCLL 8 | |
142 | #define OMAP_I2C_SCLH_HSSCLH 8 | |
143 | ||
010d442c KS |
144 | /* I2C System Test Register (OMAP_I2C_SYSTEST): */ |
145 | #ifdef DEBUG | |
146 | #define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */ | |
147 | #define OMAP_I2C_SYSTEST_FREE (1 << 14) /* Free running mode */ | |
148 | #define OMAP_I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */ | |
149 | #define OMAP_I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */ | |
150 | #define OMAP_I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense in */ | |
151 | #define OMAP_I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive out */ | |
152 | #define OMAP_I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense in */ | |
153 | #define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */ | |
154 | #endif | |
155 | ||
fdd07fe6 PW |
156 | /* OCP_SYSSTATUS bit definitions */ |
157 | #define SYSS_RESETDONE_MASK (1 << 0) | |
158 | ||
159 | /* OCP_SYSCONFIG bit definitions */ | |
160 | #define SYSC_CLOCKACTIVITY_MASK (0x3 << 8) | |
161 | #define SYSC_SIDLEMODE_MASK (0x3 << 3) | |
162 | #define SYSC_ENAWAKEUP_MASK (1 << 2) | |
163 | #define SYSC_SOFTRESET_MASK (1 << 1) | |
164 | #define SYSC_AUTOIDLE_MASK (1 << 0) | |
165 | ||
166 | #define SYSC_IDLEMODE_SMART 0x2 | |
167 | #define SYSC_CLOCKACTIVITY_FCLK 0x2 | |
010d442c | 168 | |
f3083d92 | 169 | /* Errata definitions */ |
170 | #define I2C_OMAP_ERRATA_I207 (1 << 0) | |
8a9d97d3 | 171 | #define I2C_OMAP3_1P153 (1 << 1) |
010d442c | 172 | |
010d442c KS |
173 | struct omap_i2c_dev { |
174 | struct device *dev; | |
175 | void __iomem *base; /* virtual */ | |
176 | int irq; | |
d84d3ea3 | 177 | int reg_shift; /* bit shift for I2C register addresses */ |
010d442c KS |
178 | struct clk *iclk; /* Interface clock */ |
179 | struct clk *fclk; /* Functional clock */ | |
180 | struct completion cmd_complete; | |
181 | struct resource *ioarea; | |
20c9d2c4 KJ |
182 | u32 latency; /* maximum mpu wkup latency */ |
183 | void (*set_mpu_wkup_lat)(struct device *dev, | |
184 | long latency); | |
4574eb68 | 185 | u32 speed; /* Speed of bus in Khz */ |
010d442c KS |
186 | u16 cmd_err; |
187 | u8 *buf; | |
f38e66e0 | 188 | u8 *regs; |
010d442c KS |
189 | size_t buf_len; |
190 | struct i2c_adapter adapter; | |
b6ee52c3 NM |
191 | u8 fifo_size; /* use as flag and value |
192 | * fifo_size==0 implies no fifo | |
193 | * if set, should be trsh+1 | |
194 | */ | |
9c76b878 | 195 | u8 rev; |
b6ee52c3 | 196 | unsigned b_hw:1; /* bad h/w fixes */ |
f08ac4e7 TL |
197 | unsigned idle:1; |
198 | u16 iestate; /* Saved interrupt register */ | |
ef871432 RN |
199 | u16 pscstate; |
200 | u16 scllstate; | |
201 | u16 sclhstate; | |
202 | u16 bufstate; | |
203 | u16 syscstate; | |
204 | u16 westate; | |
f3083d92 | 205 | u16 errata; |
010d442c KS |
206 | }; |
207 | ||
f38e66e0 SS |
208 | const static u8 reg_map[] = { |
209 | [OMAP_I2C_REV_REG] = 0x00, | |
210 | [OMAP_I2C_IE_REG] = 0x01, | |
211 | [OMAP_I2C_STAT_REG] = 0x02, | |
212 | [OMAP_I2C_IV_REG] = 0x03, | |
213 | [OMAP_I2C_WE_REG] = 0x03, | |
214 | [OMAP_I2C_SYSS_REG] = 0x04, | |
215 | [OMAP_I2C_BUF_REG] = 0x05, | |
216 | [OMAP_I2C_CNT_REG] = 0x06, | |
217 | [OMAP_I2C_DATA_REG] = 0x07, | |
218 | [OMAP_I2C_SYSC_REG] = 0x08, | |
219 | [OMAP_I2C_CON_REG] = 0x09, | |
220 | [OMAP_I2C_OA_REG] = 0x0a, | |
221 | [OMAP_I2C_SA_REG] = 0x0b, | |
222 | [OMAP_I2C_PSC_REG] = 0x0c, | |
223 | [OMAP_I2C_SCLL_REG] = 0x0d, | |
224 | [OMAP_I2C_SCLH_REG] = 0x0e, | |
225 | [OMAP_I2C_SYSTEST_REG] = 0x0f, | |
226 | [OMAP_I2C_BUFSTAT_REG] = 0x10, | |
227 | }; | |
228 | ||
229 | const static u8 omap4_reg_map[] = { | |
230 | [OMAP_I2C_REV_REG] = 0x04, | |
231 | [OMAP_I2C_IE_REG] = 0x2c, | |
232 | [OMAP_I2C_STAT_REG] = 0x28, | |
233 | [OMAP_I2C_IV_REG] = 0x34, | |
234 | [OMAP_I2C_WE_REG] = 0x34, | |
235 | [OMAP_I2C_SYSS_REG] = 0x90, | |
236 | [OMAP_I2C_BUF_REG] = 0x94, | |
237 | [OMAP_I2C_CNT_REG] = 0x98, | |
238 | [OMAP_I2C_DATA_REG] = 0x9c, | |
239 | [OMAP_I2C_SYSC_REG] = 0x20, | |
240 | [OMAP_I2C_CON_REG] = 0xa4, | |
241 | [OMAP_I2C_OA_REG] = 0xa8, | |
242 | [OMAP_I2C_SA_REG] = 0xac, | |
243 | [OMAP_I2C_PSC_REG] = 0xb0, | |
244 | [OMAP_I2C_SCLL_REG] = 0xb4, | |
245 | [OMAP_I2C_SCLH_REG] = 0xb8, | |
246 | [OMAP_I2C_SYSTEST_REG] = 0xbC, | |
247 | [OMAP_I2C_BUFSTAT_REG] = 0xc0, | |
248 | [OMAP_I2C_REVNB_LO] = 0x00, | |
249 | [OMAP_I2C_REVNB_HI] = 0x04, | |
250 | [OMAP_I2C_IRQSTATUS_RAW] = 0x24, | |
251 | [OMAP_I2C_IRQENABLE_SET] = 0x2c, | |
252 | [OMAP_I2C_IRQENABLE_CLR] = 0x30, | |
253 | }; | |
254 | ||
010d442c KS |
255 | static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev, |
256 | int reg, u16 val) | |
257 | { | |
f38e66e0 SS |
258 | __raw_writew(val, i2c_dev->base + |
259 | (i2c_dev->regs[reg] << i2c_dev->reg_shift)); | |
010d442c KS |
260 | } |
261 | ||
262 | static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg) | |
263 | { | |
f38e66e0 SS |
264 | return __raw_readw(i2c_dev->base + |
265 | (i2c_dev->regs[reg] << i2c_dev->reg_shift)); | |
010d442c KS |
266 | } |
267 | ||
510be9c9 | 268 | static int __init omap_i2c_get_clocks(struct omap_i2c_dev *dev) |
010d442c | 269 | { |
5fe23380 RK |
270 | int ret; |
271 | ||
272 | dev->iclk = clk_get(dev->dev, "ick"); | |
273 | if (IS_ERR(dev->iclk)) { | |
274 | ret = PTR_ERR(dev->iclk); | |
275 | dev->iclk = NULL; | |
276 | return ret; | |
010d442c KS |
277 | } |
278 | ||
1d14de08 | 279 | dev->fclk = clk_get(dev->dev, "fck"); |
010d442c | 280 | if (IS_ERR(dev->fclk)) { |
5fe23380 | 281 | ret = PTR_ERR(dev->fclk); |
010d442c KS |
282 | if (dev->iclk != NULL) { |
283 | clk_put(dev->iclk); | |
284 | dev->iclk = NULL; | |
285 | } | |
286 | dev->fclk = NULL; | |
5fe23380 | 287 | return ret; |
010d442c KS |
288 | } |
289 | ||
290 | return 0; | |
291 | } | |
292 | ||
293 | static void omap_i2c_put_clocks(struct omap_i2c_dev *dev) | |
294 | { | |
295 | clk_put(dev->fclk); | |
296 | dev->fclk = NULL; | |
5fe23380 RK |
297 | clk_put(dev->iclk); |
298 | dev->iclk = NULL; | |
010d442c KS |
299 | } |
300 | ||
f08ac4e7 | 301 | static void omap_i2c_unidle(struct omap_i2c_dev *dev) |
010d442c | 302 | { |
3831f154 PW |
303 | WARN_ON(!dev->idle); |
304 | ||
5fe23380 | 305 | clk_enable(dev->iclk); |
010d442c | 306 | clk_enable(dev->fclk); |
ef871432 RN |
307 | if (cpu_is_omap34xx()) { |
308 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0); | |
309 | omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, dev->pscstate); | |
310 | omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, dev->scllstate); | |
311 | omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, dev->sclhstate); | |
312 | omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, dev->bufstate); | |
313 | omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, dev->syscstate); | |
314 | omap_i2c_write_reg(dev, OMAP_I2C_WE_REG, dev->westate); | |
315 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN); | |
316 | } | |
0cbbcffd | 317 | dev->idle = 0; |
07ac31f6 CM |
318 | |
319 | /* | |
320 | * Don't write to this register if the IE state is 0 as it can | |
321 | * cause deadlock. | |
322 | */ | |
323 | if (dev->iestate) | |
324 | omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate); | |
010d442c KS |
325 | } |
326 | ||
f08ac4e7 | 327 | static void omap_i2c_idle(struct omap_i2c_dev *dev) |
010d442c | 328 | { |
f08ac4e7 TL |
329 | u16 iv; |
330 | ||
3831f154 PW |
331 | WARN_ON(dev->idle); |
332 | ||
f08ac4e7 | 333 | dev->iestate = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG); |
f38e66e0 SS |
334 | if (dev->rev >= OMAP_I2C_REV_ON_4430) |
335 | omap_i2c_write_reg(dev, OMAP_I2C_IRQENABLE_CLR, 1); | |
336 | else | |
337 | omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, 0); | |
338 | ||
9c76b878 | 339 | if (dev->rev < OMAP_I2C_REV_2) { |
c1a473bd | 340 | iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG); /* Read clears */ |
0cbbcffd | 341 | } else { |
f08ac4e7 | 342 | omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, dev->iestate); |
0cbbcffd PW |
343 | |
344 | /* Flush posted write before the dev->idle store occurs */ | |
345 | omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG); | |
346 | } | |
347 | dev->idle = 1; | |
f08ac4e7 | 348 | clk_disable(dev->fclk); |
5fe23380 | 349 | clk_disable(dev->iclk); |
010d442c KS |
350 | } |
351 | ||
352 | static int omap_i2c_init(struct omap_i2c_dev *dev) | |
353 | { | |
ef871432 | 354 | u16 psc = 0, scll = 0, sclh = 0, buf = 0; |
4574eb68 | 355 | u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0; |
010d442c KS |
356 | unsigned long fclk_rate = 12000000; |
357 | unsigned long timeout; | |
4574eb68 | 358 | unsigned long internal_clk = 0; |
010d442c | 359 | |
9c76b878 | 360 | if (dev->rev >= OMAP_I2C_REV_2) { |
57eb81b1 MG |
361 | /* Disable I2C controller before soft reset */ |
362 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, | |
363 | omap_i2c_read_reg(dev, OMAP_I2C_CON_REG) & | |
364 | ~(OMAP_I2C_CON_EN)); | |
365 | ||
fdd07fe6 | 366 | omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK); |
010d442c KS |
367 | /* For some reason we need to set the EN bit before the |
368 | * reset done bit gets set. */ | |
369 | timeout = jiffies + OMAP_I2C_TIMEOUT; | |
370 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN); | |
371 | while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) & | |
fdd07fe6 | 372 | SYSS_RESETDONE_MASK)) { |
010d442c | 373 | if (time_after(jiffies, timeout)) { |
fce3ff03 | 374 | dev_warn(dev->dev, "timeout waiting " |
010d442c KS |
375 | "for controller reset\n"); |
376 | return -ETIMEDOUT; | |
377 | } | |
378 | msleep(1); | |
379 | } | |
fdd07fe6 PW |
380 | |
381 | /* SYSC register is cleared by the reset; rewrite it */ | |
382 | if (dev->rev == OMAP_I2C_REV_ON_2430) { | |
383 | ||
384 | omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, | |
385 | SYSC_AUTOIDLE_MASK); | |
386 | ||
387 | } else if (dev->rev >= OMAP_I2C_REV_ON_3430) { | |
ef871432 RN |
388 | dev->syscstate = SYSC_AUTOIDLE_MASK; |
389 | dev->syscstate |= SYSC_ENAWAKEUP_MASK; | |
390 | dev->syscstate |= (SYSC_IDLEMODE_SMART << | |
fdd07fe6 | 391 | __ffs(SYSC_SIDLEMODE_MASK)); |
ef871432 | 392 | dev->syscstate |= (SYSC_CLOCKACTIVITY_FCLK << |
fdd07fe6 PW |
393 | __ffs(SYSC_CLOCKACTIVITY_MASK)); |
394 | ||
ef871432 RN |
395 | omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, |
396 | dev->syscstate); | |
5043e9e7 KJ |
397 | /* |
398 | * Enabling all wakup sources to stop I2C freezing on | |
399 | * WFI instruction. | |
400 | * REVISIT: Some wkup sources might not be needed. | |
401 | */ | |
ef871432 | 402 | dev->westate = OMAP_I2C_WE_ALL; |
f38e66e0 SS |
403 | if (dev->rev < OMAP_I2C_REV_ON_4430) |
404 | omap_i2c_write_reg(dev, OMAP_I2C_WE_REG, | |
405 | dev->westate); | |
fdd07fe6 | 406 | } |
010d442c KS |
407 | } |
408 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0); | |
409 | ||
410 | if (cpu_class_is_omap1()) { | |
0e9ae109 RK |
411 | /* |
412 | * The I2C functional clock is the armxor_ck, so there's | |
413 | * no need to get "armxor_ck" separately. Now, if OMAP2420 | |
414 | * always returns 12MHz for the functional clock, we can | |
415 | * do this bit unconditionally. | |
416 | */ | |
417 | fclk_rate = clk_get_rate(dev->fclk); | |
418 | ||
010d442c KS |
419 | /* TRM for 5912 says the I2C clock must be prescaled to be |
420 | * between 7 - 12 MHz. The XOR input clock is typically | |
421 | * 12, 13 or 19.2 MHz. So we should have code that produces: | |
422 | * | |
423 | * XOR MHz Divider Prescaler | |
424 | * 12 1 0 | |
425 | * 13 2 1 | |
426 | * 19.2 2 1 | |
427 | */ | |
d7aef138 JD |
428 | if (fclk_rate > 12000000) |
429 | psc = fclk_rate / 12000000; | |
010d442c KS |
430 | } |
431 | ||
f38e66e0 | 432 | if (!(cpu_class_is_omap1() || cpu_is_omap2420())) { |
4574eb68 | 433 | |
84bf2c86 AK |
434 | /* |
435 | * HSI2C controller internal clk rate should be 19.2 Mhz for | |
436 | * HS and for all modes on 2430. On 34xx we can use lower rate | |
437 | * to get longer filter period for better noise suppression. | |
438 | * The filter is iclk (fclk for HS) period. | |
439 | */ | |
ff0f2426 | 440 | if (dev->speed > 400 || cpu_is_omap2430()) |
84bf2c86 AK |
441 | internal_clk = 19200; |
442 | else if (dev->speed > 100) | |
443 | internal_clk = 9600; | |
444 | else | |
445 | internal_clk = 4000; | |
4574eb68 SMK |
446 | fclk_rate = clk_get_rate(dev->fclk) / 1000; |
447 | ||
448 | /* Compute prescaler divisor */ | |
449 | psc = fclk_rate / internal_clk; | |
450 | psc = psc - 1; | |
451 | ||
452 | /* If configured for High Speed */ | |
453 | if (dev->speed > 400) { | |
baf46b4e AK |
454 | unsigned long scl; |
455 | ||
4574eb68 | 456 | /* For first phase of HS mode */ |
baf46b4e AK |
457 | scl = internal_clk / 400; |
458 | fsscll = scl - (scl / 3) - 7; | |
459 | fssclh = (scl / 3) - 5; | |
4574eb68 SMK |
460 | |
461 | /* For second phase of HS mode */ | |
baf46b4e AK |
462 | scl = fclk_rate / dev->speed; |
463 | hsscll = scl - (scl / 3) - 7; | |
464 | hssclh = (scl / 3) - 5; | |
465 | } else if (dev->speed > 100) { | |
466 | unsigned long scl; | |
467 | ||
468 | /* Fast mode */ | |
469 | scl = internal_clk / dev->speed; | |
470 | fsscll = scl - (scl / 3) - 7; | |
471 | fssclh = (scl / 3) - 5; | |
4574eb68 | 472 | } else { |
baf46b4e AK |
473 | /* Standard mode */ |
474 | fsscll = internal_clk / (dev->speed * 2) - 7; | |
475 | fssclh = internal_clk / (dev->speed * 2) - 5; | |
4574eb68 SMK |
476 | } |
477 | scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll; | |
478 | sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh; | |
479 | } else { | |
480 | /* Program desired operating rate */ | |
481 | fclk_rate /= (psc + 1) * 1000; | |
482 | if (psc > 2) | |
483 | psc = 2; | |
484 | scll = fclk_rate / (dev->speed * 2) - 7 + psc; | |
485 | sclh = fclk_rate / (dev->speed * 2) - 7 + psc; | |
486 | } | |
487 | ||
010d442c KS |
488 | /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */ |
489 | omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc); | |
490 | ||
4574eb68 SMK |
491 | /* SCL low and high time values */ |
492 | omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, scll); | |
493 | omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, sclh); | |
010d442c | 494 | |
ef871432 RN |
495 | if (dev->fifo_size) { |
496 | /* Note: setup required fifo size - 1. RTRSH and XTRSH */ | |
497 | buf = (dev->fifo_size - 1) << 8 | OMAP_I2C_BUF_RXFIF_CLR | | |
498 | (dev->fifo_size - 1) | OMAP_I2C_BUF_TXFIF_CLR; | |
499 | omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, buf); | |
500 | } | |
b6ee52c3 | 501 | |
010d442c KS |
502 | /* Take the I2C module out of reset: */ |
503 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN); | |
504 | ||
f3083d92 | 505 | dev->errata = 0; |
506 | ||
507 | if (cpu_is_omap2430() || cpu_is_omap34xx()) | |
508 | dev->errata |= I2C_OMAP_ERRATA_I207; | |
509 | ||
010d442c | 510 | /* Enable interrupts */ |
ef871432 | 511 | dev->iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY | |
c1a473bd TL |
512 | OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK | |
513 | OMAP_I2C_IE_AL) | ((dev->fifo_size) ? | |
ef871432 RN |
514 | (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0); |
515 | omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate); | |
516 | if (cpu_is_omap34xx()) { | |
517 | dev->pscstate = psc; | |
518 | dev->scllstate = scll; | |
519 | dev->sclhstate = sclh; | |
520 | dev->bufstate = buf; | |
521 | } | |
010d442c KS |
522 | return 0; |
523 | } | |
524 | ||
525 | /* | |
526 | * Waiting on Bus Busy | |
527 | */ | |
528 | static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev) | |
529 | { | |
530 | unsigned long timeout; | |
531 | ||
532 | timeout = jiffies + OMAP_I2C_TIMEOUT; | |
533 | while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) { | |
534 | if (time_after(jiffies, timeout)) { | |
535 | dev_warn(dev->dev, "timeout waiting for bus ready\n"); | |
536 | return -ETIMEDOUT; | |
537 | } | |
538 | msleep(1); | |
539 | } | |
540 | ||
541 | return 0; | |
542 | } | |
543 | ||
544 | /* | |
545 | * Low level master read/write transaction. | |
546 | */ | |
547 | static int omap_i2c_xfer_msg(struct i2c_adapter *adap, | |
548 | struct i2c_msg *msg, int stop) | |
549 | { | |
550 | struct omap_i2c_dev *dev = i2c_get_adapdata(adap); | |
551 | int r; | |
552 | u16 w; | |
553 | ||
554 | dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n", | |
555 | msg->addr, msg->len, msg->flags, stop); | |
556 | ||
557 | if (msg->len == 0) | |
558 | return -EINVAL; | |
559 | ||
560 | omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr); | |
561 | ||
562 | /* REVISIT: Could the STB bit of I2C_CON be used with probing? */ | |
563 | dev->buf = msg->buf; | |
564 | dev->buf_len = msg->len; | |
565 | ||
566 | omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len); | |
567 | ||
b6ee52c3 NM |
568 | /* Clear the FIFO Buffers */ |
569 | w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG); | |
570 | w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR; | |
571 | omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w); | |
572 | ||
010d442c KS |
573 | init_completion(&dev->cmd_complete); |
574 | dev->cmd_err = 0; | |
575 | ||
576 | w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT; | |
4574eb68 SMK |
577 | |
578 | /* High speed configuration */ | |
579 | if (dev->speed > 400) | |
b6ee52c3 | 580 | w |= OMAP_I2C_CON_OPMODE_HS; |
4574eb68 | 581 | |
010d442c KS |
582 | if (msg->flags & I2C_M_TEN) |
583 | w |= OMAP_I2C_CON_XA; | |
584 | if (!(msg->flags & I2C_M_RD)) | |
585 | w |= OMAP_I2C_CON_TRX; | |
c1a473bd | 586 | |
b6ee52c3 | 587 | if (!dev->b_hw && stop) |
010d442c | 588 | w |= OMAP_I2C_CON_STP; |
c1a473bd | 589 | |
010d442c KS |
590 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w); |
591 | ||
b6ee52c3 NM |
592 | /* |
593 | * Don't write stt and stp together on some hardware. | |
594 | */ | |
595 | if (dev->b_hw && stop) { | |
596 | unsigned long delay = jiffies + OMAP_I2C_TIMEOUT; | |
597 | u16 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG); | |
598 | while (con & OMAP_I2C_CON_STT) { | |
599 | con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG); | |
600 | ||
601 | /* Let the user know if i2c is in a bad state */ | |
602 | if (time_after(jiffies, delay)) { | |
603 | dev_err(dev->dev, "controller timed out " | |
604 | "waiting for start condition to finish\n"); | |
605 | return -ETIMEDOUT; | |
606 | } | |
607 | cpu_relax(); | |
608 | } | |
609 | ||
610 | w |= OMAP_I2C_CON_STP; | |
611 | w &= ~OMAP_I2C_CON_STT; | |
612 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w); | |
613 | } | |
614 | ||
b7af349b JN |
615 | /* |
616 | * REVISIT: We should abort the transfer on signals, but the bus goes | |
617 | * into arbitration and we're currently unable to recover from it. | |
618 | */ | |
20c9d2c4 KJ |
619 | if (dev->set_mpu_wkup_lat != NULL) |
620 | dev->set_mpu_wkup_lat(dev->dev, dev->latency); | |
b7af349b JN |
621 | r = wait_for_completion_timeout(&dev->cmd_complete, |
622 | OMAP_I2C_TIMEOUT); | |
20c9d2c4 KJ |
623 | if (dev->set_mpu_wkup_lat != NULL) |
624 | dev->set_mpu_wkup_lat(dev->dev, -1); | |
010d442c KS |
625 | dev->buf_len = 0; |
626 | if (r < 0) | |
627 | return r; | |
628 | if (r == 0) { | |
629 | dev_err(dev->dev, "controller timed out\n"); | |
630 | omap_i2c_init(dev); | |
631 | return -ETIMEDOUT; | |
632 | } | |
633 | ||
634 | if (likely(!dev->cmd_err)) | |
635 | return 0; | |
636 | ||
637 | /* We have an error */ | |
638 | if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR | | |
639 | OMAP_I2C_STAT_XUDF)) { | |
640 | omap_i2c_init(dev); | |
641 | return -EIO; | |
642 | } | |
643 | ||
644 | if (dev->cmd_err & OMAP_I2C_STAT_NACK) { | |
645 | if (msg->flags & I2C_M_IGNORE_NAK) | |
646 | return 0; | |
647 | if (stop) { | |
648 | w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG); | |
649 | w |= OMAP_I2C_CON_STP; | |
650 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w); | |
651 | } | |
652 | return -EREMOTEIO; | |
653 | } | |
654 | return -EIO; | |
655 | } | |
656 | ||
657 | ||
658 | /* | |
659 | * Prepare controller for a transaction and call omap_i2c_xfer_msg | |
660 | * to do the work during IRQ processing. | |
661 | */ | |
662 | static int | |
663 | omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) | |
664 | { | |
665 | struct omap_i2c_dev *dev = i2c_get_adapdata(adap); | |
666 | int i; | |
667 | int r; | |
668 | ||
f08ac4e7 | 669 | omap_i2c_unidle(dev); |
010d442c | 670 | |
c1a473bd TL |
671 | r = omap_i2c_wait_for_bb(dev); |
672 | if (r < 0) | |
010d442c KS |
673 | goto out; |
674 | ||
675 | for (i = 0; i < num; i++) { | |
676 | r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1))); | |
677 | if (r != 0) | |
678 | break; | |
679 | } | |
680 | ||
681 | if (r == 0) | |
682 | r = num; | |
5c64eb26 MN |
683 | |
684 | omap_i2c_wait_for_bb(dev); | |
010d442c | 685 | out: |
f08ac4e7 | 686 | omap_i2c_idle(dev); |
010d442c KS |
687 | return r; |
688 | } | |
689 | ||
690 | static u32 | |
691 | omap_i2c_func(struct i2c_adapter *adap) | |
692 | { | |
693 | return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); | |
694 | } | |
695 | ||
696 | static inline void | |
697 | omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err) | |
698 | { | |
699 | dev->cmd_err |= err; | |
700 | complete(&dev->cmd_complete); | |
701 | } | |
702 | ||
703 | static inline void | |
704 | omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat) | |
705 | { | |
706 | omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat); | |
707 | } | |
708 | ||
f3083d92 | 709 | static inline void i2c_omap_errata_i207(struct omap_i2c_dev *dev, u16 stat) |
710 | { | |
711 | /* | |
712 | * I2C Errata(Errata Nos. OMAP2: 1.67, OMAP3: 1.8) | |
713 | * Not applicable for OMAP4. | |
714 | * Under certain rare conditions, RDR could be set again | |
715 | * when the bus is busy, then ignore the interrupt and | |
716 | * clear the interrupt. | |
717 | */ | |
718 | if (stat & OMAP_I2C_STAT_RDR) { | |
719 | /* Step 1: If RDR is set, clear it */ | |
720 | omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR); | |
721 | ||
722 | /* Step 2: */ | |
723 | if (!(omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) | |
724 | & OMAP_I2C_STAT_BB)) { | |
725 | ||
726 | /* Step 3: */ | |
727 | if (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) | |
728 | & OMAP_I2C_STAT_RDR) { | |
729 | omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR); | |
730 | dev_dbg(dev->dev, "RDR when bus is busy.\n"); | |
731 | } | |
732 | ||
733 | } | |
734 | } | |
735 | } | |
736 | ||
43469d8e PW |
737 | /* rev1 devices are apparently only on some 15xx */ |
738 | #ifdef CONFIG_ARCH_OMAP15XX | |
739 | ||
010d442c | 740 | static irqreturn_t |
7d12e780 | 741 | omap_i2c_rev1_isr(int this_irq, void *dev_id) |
010d442c KS |
742 | { |
743 | struct omap_i2c_dev *dev = dev_id; | |
744 | u16 iv, w; | |
745 | ||
f08ac4e7 TL |
746 | if (dev->idle) |
747 | return IRQ_NONE; | |
748 | ||
010d442c KS |
749 | iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG); |
750 | switch (iv) { | |
751 | case 0x00: /* None */ | |
752 | break; | |
753 | case 0x01: /* Arbitration lost */ | |
754 | dev_err(dev->dev, "Arbitration lost\n"); | |
755 | omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL); | |
756 | break; | |
757 | case 0x02: /* No acknowledgement */ | |
758 | omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK); | |
759 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP); | |
760 | break; | |
761 | case 0x03: /* Register access ready */ | |
762 | omap_i2c_complete_cmd(dev, 0); | |
763 | break; | |
764 | case 0x04: /* Receive data ready */ | |
765 | if (dev->buf_len) { | |
766 | w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG); | |
767 | *dev->buf++ = w; | |
768 | dev->buf_len--; | |
769 | if (dev->buf_len) { | |
770 | *dev->buf++ = w >> 8; | |
771 | dev->buf_len--; | |
772 | } | |
773 | } else | |
774 | dev_err(dev->dev, "RRDY IRQ while no data requested\n"); | |
775 | break; | |
776 | case 0x05: /* Transmit data ready */ | |
777 | if (dev->buf_len) { | |
778 | w = *dev->buf++; | |
779 | dev->buf_len--; | |
780 | if (dev->buf_len) { | |
781 | w |= *dev->buf++ << 8; | |
782 | dev->buf_len--; | |
783 | } | |
784 | omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w); | |
785 | } else | |
786 | dev_err(dev->dev, "XRDY IRQ while no data to send\n"); | |
787 | break; | |
788 | default: | |
789 | return IRQ_NONE; | |
790 | } | |
791 | ||
792 | return IRQ_HANDLED; | |
793 | } | |
43469d8e | 794 | #else |
c1a473bd | 795 | #define omap_i2c_rev1_isr NULL |
43469d8e | 796 | #endif |
010d442c | 797 | |
2dd151ab AS |
798 | /* |
799 | * OMAP3430 Errata 1.153: When an XRDY/XDR is hit, wait for XUDF before writing | |
800 | * data to DATA_REG. Otherwise some data bytes can be lost while transferring | |
801 | * them from the memory to the I2C interface. | |
802 | */ | |
803 | static int errata_omap3_1p153(struct omap_i2c_dev *dev, u16 *stat, int *err) | |
804 | { | |
e9f59b9c AS |
805 | unsigned long timeout = 10000; |
806 | ||
807 | while (--timeout && !(*stat & OMAP_I2C_STAT_XUDF)) { | |
2dd151ab AS |
808 | if (*stat & (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) { |
809 | omap_i2c_ack_stat(dev, *stat & (OMAP_I2C_STAT_XRDY | | |
810 | OMAP_I2C_STAT_XDR)); | |
811 | *err |= OMAP_I2C_STAT_XUDF; | |
812 | return -ETIMEDOUT; | |
813 | } | |
e9f59b9c | 814 | |
2dd151ab AS |
815 | cpu_relax(); |
816 | *stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG); | |
817 | } | |
818 | ||
e9f59b9c AS |
819 | if (!timeout) { |
820 | dev_err(dev->dev, "timeout waiting on XUDF bit\n"); | |
821 | return 0; | |
822 | } | |
823 | ||
2dd151ab AS |
824 | return 0; |
825 | } | |
826 | ||
010d442c | 827 | static irqreturn_t |
7d12e780 | 828 | omap_i2c_isr(int this_irq, void *dev_id) |
010d442c KS |
829 | { |
830 | struct omap_i2c_dev *dev = dev_id; | |
831 | u16 bits; | |
832 | u16 stat, w; | |
b6ee52c3 | 833 | int err, count = 0; |
010d442c | 834 | |
f08ac4e7 TL |
835 | if (dev->idle) |
836 | return IRQ_NONE; | |
837 | ||
010d442c KS |
838 | bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG); |
839 | while ((stat = (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG))) & bits) { | |
840 | dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat); | |
841 | if (count++ == 100) { | |
842 | dev_warn(dev->dev, "Too much work in one IRQ\n"); | |
843 | break; | |
844 | } | |
845 | ||
cd086d3a SM |
846 | err = 0; |
847 | complete: | |
dcc4ec26 NM |
848 | /* |
849 | * Ack the stat in one go, but [R/X]DR and [R/X]RDY should be | |
850 | * acked after the data operation is complete. | |
851 | * Ref: TRM SWPU114Q Figure 18-31 | |
852 | */ | |
853 | omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat & | |
854 | ~(OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR | | |
855 | OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR)); | |
010d442c | 856 | |
b6ee52c3 NM |
857 | if (stat & OMAP_I2C_STAT_NACK) { |
858 | err |= OMAP_I2C_STAT_NACK; | |
859 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, | |
860 | OMAP_I2C_CON_STP); | |
010d442c | 861 | } |
b6ee52c3 NM |
862 | if (stat & OMAP_I2C_STAT_AL) { |
863 | dev_err(dev->dev, "Arbitration lost\n"); | |
864 | err |= OMAP_I2C_STAT_AL; | |
865 | } | |
866 | if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK | | |
04c688dd | 867 | OMAP_I2C_STAT_AL)) { |
dd11976a MS |
868 | omap_i2c_ack_stat(dev, stat & |
869 | (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR | | |
870 | OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR)); | |
b6ee52c3 | 871 | omap_i2c_complete_cmd(dev, err); |
04c688dd SM |
872 | return IRQ_HANDLED; |
873 | } | |
b6ee52c3 NM |
874 | if (stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR)) { |
875 | u8 num_bytes = 1; | |
f3083d92 | 876 | |
877 | if (dev->errata & I2C_OMAP_ERRATA_I207) | |
878 | i2c_omap_errata_i207(dev, stat); | |
879 | ||
b6ee52c3 NM |
880 | if (dev->fifo_size) { |
881 | if (stat & OMAP_I2C_STAT_RRDY) | |
882 | num_bytes = dev->fifo_size; | |
bfb6b658 SM |
883 | else /* read RXSTAT on RDR interrupt */ |
884 | num_bytes = (omap_i2c_read_reg(dev, | |
885 | OMAP_I2C_BUFSTAT_REG) | |
886 | >> 8) & 0x3F; | |
b6ee52c3 NM |
887 | } |
888 | while (num_bytes) { | |
889 | num_bytes--; | |
890 | w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG); | |
010d442c | 891 | if (dev->buf_len) { |
b6ee52c3 | 892 | *dev->buf++ = w; |
010d442c | 893 | dev->buf_len--; |
f38e66e0 SS |
894 | /* |
895 | * Data reg in 2430, omap3 and | |
896 | * omap4 is 8 bit wide | |
897 | */ | |
898 | if (cpu_class_is_omap1() || | |
899 | cpu_is_omap2420()) { | |
b6ee52c3 NM |
900 | if (dev->buf_len) { |
901 | *dev->buf++ = w >> 8; | |
902 | dev->buf_len--; | |
903 | } | |
904 | } | |
905 | } else { | |
906 | if (stat & OMAP_I2C_STAT_RRDY) | |
907 | dev_err(dev->dev, | |
908 | "RRDY IRQ while no data" | |
909 | " requested\n"); | |
910 | if (stat & OMAP_I2C_STAT_RDR) | |
911 | dev_err(dev->dev, | |
912 | "RDR IRQ while no data" | |
913 | " requested\n"); | |
914 | break; | |
010d442c | 915 | } |
b6ee52c3 NM |
916 | } |
917 | omap_i2c_ack_stat(dev, | |
918 | stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR)); | |
010d442c KS |
919 | continue; |
920 | } | |
b6ee52c3 NM |
921 | if (stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR)) { |
922 | u8 num_bytes = 1; | |
923 | if (dev->fifo_size) { | |
924 | if (stat & OMAP_I2C_STAT_XRDY) | |
925 | num_bytes = dev->fifo_size; | |
bfb6b658 | 926 | else /* read TXSTAT on XDR interrupt */ |
b6ee52c3 | 927 | num_bytes = omap_i2c_read_reg(dev, |
bfb6b658 SM |
928 | OMAP_I2C_BUFSTAT_REG) |
929 | & 0x3F; | |
b6ee52c3 NM |
930 | } |
931 | while (num_bytes) { | |
932 | num_bytes--; | |
933 | w = 0; | |
010d442c | 934 | if (dev->buf_len) { |
b6ee52c3 | 935 | w = *dev->buf++; |
010d442c | 936 | dev->buf_len--; |
f38e66e0 SS |
937 | /* |
938 | * Data reg in 2430, omap3 and | |
939 | * omap4 is 8 bit wide | |
940 | */ | |
941 | if (cpu_class_is_omap1() || | |
942 | cpu_is_omap2420()) { | |
b6ee52c3 NM |
943 | if (dev->buf_len) { |
944 | w |= *dev->buf++ << 8; | |
945 | dev->buf_len--; | |
946 | } | |
947 | } | |
948 | } else { | |
949 | if (stat & OMAP_I2C_STAT_XRDY) | |
950 | dev_err(dev->dev, | |
951 | "XRDY IRQ while no " | |
952 | "data to send\n"); | |
953 | if (stat & OMAP_I2C_STAT_XDR) | |
954 | dev_err(dev->dev, | |
955 | "XDR IRQ while no " | |
956 | "data to send\n"); | |
957 | break; | |
010d442c | 958 | } |
cd086d3a | 959 | |
8a9d97d3 | 960 | if ((dev->errata & I2C_OMAP3_1P153) && |
2dd151ab AS |
961 | errata_omap3_1p153(dev, &stat, &err)) |
962 | goto complete; | |
cd086d3a | 963 | |
b6ee52c3 NM |
964 | omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w); |
965 | } | |
966 | omap_i2c_ack_stat(dev, | |
967 | stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR)); | |
010d442c KS |
968 | continue; |
969 | } | |
970 | if (stat & OMAP_I2C_STAT_ROVR) { | |
971 | dev_err(dev->dev, "Receive overrun\n"); | |
972 | dev->cmd_err |= OMAP_I2C_STAT_ROVR; | |
973 | } | |
974 | if (stat & OMAP_I2C_STAT_XUDF) { | |
b6ee52c3 | 975 | dev_err(dev->dev, "Transmit underflow\n"); |
010d442c KS |
976 | dev->cmd_err |= OMAP_I2C_STAT_XUDF; |
977 | } | |
010d442c KS |
978 | } |
979 | ||
980 | return count ? IRQ_HANDLED : IRQ_NONE; | |
981 | } | |
982 | ||
8f9082c5 | 983 | static const struct i2c_algorithm omap_i2c_algo = { |
010d442c KS |
984 | .master_xfer = omap_i2c_xfer, |
985 | .functionality = omap_i2c_func, | |
986 | }; | |
987 | ||
1139aea9 | 988 | static int __devinit |
010d442c KS |
989 | omap_i2c_probe(struct platform_device *pdev) |
990 | { | |
991 | struct omap_i2c_dev *dev; | |
992 | struct i2c_adapter *adap; | |
993 | struct resource *mem, *irq, *ioarea; | |
20c9d2c4 | 994 | struct omap_i2c_bus_platform_data *pdata = pdev->dev.platform_data; |
e355204e | 995 | irq_handler_t isr; |
010d442c | 996 | int r; |
3d522fb4 | 997 | u32 speed = 0; |
010d442c KS |
998 | |
999 | /* NOTE: driver uses the static register mapping */ | |
1000 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1001 | if (!mem) { | |
1002 | dev_err(&pdev->dev, "no mem resource?\n"); | |
1003 | return -ENODEV; | |
1004 | } | |
1005 | irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
1006 | if (!irq) { | |
1007 | dev_err(&pdev->dev, "no irq resource?\n"); | |
1008 | return -ENODEV; | |
1009 | } | |
1010 | ||
59330825 | 1011 | ioarea = request_mem_region(mem->start, resource_size(mem), |
010d442c KS |
1012 | pdev->name); |
1013 | if (!ioarea) { | |
1014 | dev_err(&pdev->dev, "I2C region already claimed\n"); | |
1015 | return -EBUSY; | |
1016 | } | |
1017 | ||
010d442c KS |
1018 | dev = kzalloc(sizeof(struct omap_i2c_dev), GFP_KERNEL); |
1019 | if (!dev) { | |
1020 | r = -ENOMEM; | |
1021 | goto err_release_region; | |
1022 | } | |
1023 | ||
20c9d2c4 KJ |
1024 | if (pdata != NULL) { |
1025 | speed = pdata->clkrate; | |
1026 | dev->set_mpu_wkup_lat = pdata->set_mpu_wkup_lat; | |
1027 | } else { | |
1028 | speed = 100; /* Default speed */ | |
1029 | dev->set_mpu_wkup_lat = NULL; | |
1030 | } | |
4574eb68 | 1031 | |
3d522fb4 | 1032 | dev->speed = speed; |
3831f154 | 1033 | dev->idle = 1; |
010d442c KS |
1034 | dev->dev = &pdev->dev; |
1035 | dev->irq = irq->start; | |
c6ffddea | 1036 | dev->base = ioremap(mem->start, resource_size(mem)); |
55c381e4 RK |
1037 | if (!dev->base) { |
1038 | r = -ENOMEM; | |
1039 | goto err_free_mem; | |
1040 | } | |
1041 | ||
010d442c KS |
1042 | platform_set_drvdata(pdev, dev); |
1043 | ||
7c6bd201 MW |
1044 | if (cpu_is_omap7xx()) |
1045 | dev->reg_shift = 1; | |
f38e66e0 SS |
1046 | else if (cpu_is_omap44xx()) |
1047 | dev->reg_shift = 0; | |
7c6bd201 MW |
1048 | else |
1049 | dev->reg_shift = 2; | |
1050 | ||
010d442c | 1051 | if ((r = omap_i2c_get_clocks(dev)) != 0) |
55c381e4 | 1052 | goto err_iounmap; |
010d442c | 1053 | |
f38e66e0 SS |
1054 | if (cpu_is_omap44xx()) |
1055 | dev->regs = (u8 *) omap4_reg_map; | |
1056 | else | |
1057 | dev->regs = (u8 *) reg_map; | |
1058 | ||
f08ac4e7 | 1059 | omap_i2c_unidle(dev); |
010d442c | 1060 | |
9c76b878 | 1061 | dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff; |
010d442c | 1062 | |
8a9d97d3 | 1063 | if (dev->rev <= OMAP_I2C_REV_ON_3430) |
1064 | dev->errata |= I2C_OMAP3_1P153; | |
1065 | ||
f38e66e0 | 1066 | if (!(cpu_class_is_omap1() || cpu_is_omap2420())) { |
b6ee52c3 NM |
1067 | u16 s; |
1068 | ||
1069 | /* Set up the fifo size - Get total size */ | |
1070 | s = (omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3; | |
1071 | dev->fifo_size = 0x8 << s; | |
1072 | ||
1073 | /* | |
1074 | * Set up notification threshold as half the total available | |
1075 | * size. This is to ensure that we can handle the status on int | |
1076 | * call back latencies. | |
1077 | */ | |
f38e66e0 SS |
1078 | if (dev->rev >= OMAP_I2C_REV_ON_4430) { |
1079 | dev->fifo_size = 0; | |
1080 | dev->b_hw = 0; /* Disable hardware fixes */ | |
1081 | } else { | |
1082 | dev->fifo_size = (dev->fifo_size / 2); | |
1083 | dev->b_hw = 1; /* Enable hardware fixes */ | |
1084 | } | |
20c9d2c4 KJ |
1085 | /* calculate wakeup latency constraint for MPU */ |
1086 | if (dev->set_mpu_wkup_lat != NULL) | |
1087 | dev->latency = (1000000 * dev->fifo_size) / | |
1088 | (1000 * speed / 8); | |
b6ee52c3 NM |
1089 | } |
1090 | ||
010d442c KS |
1091 | /* reset ASAP, clearing any IRQs */ |
1092 | omap_i2c_init(dev); | |
1093 | ||
9c76b878 PW |
1094 | isr = (dev->rev < OMAP_I2C_REV_2) ? omap_i2c_rev1_isr : omap_i2c_isr; |
1095 | r = request_irq(dev->irq, isr, 0, pdev->name, dev); | |
010d442c KS |
1096 | |
1097 | if (r) { | |
1098 | dev_err(dev->dev, "failure requesting irq %i\n", dev->irq); | |
1099 | goto err_unuse_clocks; | |
1100 | } | |
9c76b878 | 1101 | |
010d442c | 1102 | dev_info(dev->dev, "bus %d rev%d.%d at %d kHz\n", |
9c76b878 | 1103 | pdev->id, dev->rev >> 4, dev->rev & 0xf, dev->speed); |
010d442c | 1104 | |
3831f154 PW |
1105 | omap_i2c_idle(dev); |
1106 | ||
010d442c KS |
1107 | adap = &dev->adapter; |
1108 | i2c_set_adapdata(adap, dev); | |
1109 | adap->owner = THIS_MODULE; | |
1110 | adap->class = I2C_CLASS_HWMON; | |
783fd6fa | 1111 | strlcpy(adap->name, "OMAP I2C adapter", sizeof(adap->name)); |
010d442c KS |
1112 | adap->algo = &omap_i2c_algo; |
1113 | adap->dev.parent = &pdev->dev; | |
1114 | ||
1115 | /* i2c device drivers may be active on return from add_adapter() */ | |
7c175499 DB |
1116 | adap->nr = pdev->id; |
1117 | r = i2c_add_numbered_adapter(adap); | |
010d442c KS |
1118 | if (r) { |
1119 | dev_err(dev->dev, "failure adding adapter\n"); | |
1120 | goto err_free_irq; | |
1121 | } | |
1122 | ||
010d442c KS |
1123 | return 0; |
1124 | ||
1125 | err_free_irq: | |
1126 | free_irq(dev->irq, dev); | |
1127 | err_unuse_clocks: | |
3e39752d | 1128 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0); |
f08ac4e7 | 1129 | omap_i2c_idle(dev); |
010d442c | 1130 | omap_i2c_put_clocks(dev); |
55c381e4 RK |
1131 | err_iounmap: |
1132 | iounmap(dev->base); | |
010d442c KS |
1133 | err_free_mem: |
1134 | platform_set_drvdata(pdev, NULL); | |
1135 | kfree(dev); | |
1136 | err_release_region: | |
59330825 | 1137 | release_mem_region(mem->start, resource_size(mem)); |
010d442c KS |
1138 | |
1139 | return r; | |
1140 | } | |
1141 | ||
1142 | static int | |
1143 | omap_i2c_remove(struct platform_device *pdev) | |
1144 | { | |
1145 | struct omap_i2c_dev *dev = platform_get_drvdata(pdev); | |
1146 | struct resource *mem; | |
1147 | ||
1148 | platform_set_drvdata(pdev, NULL); | |
1149 | ||
1150 | free_irq(dev->irq, dev); | |
1151 | i2c_del_adapter(&dev->adapter); | |
1152 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0); | |
1153 | omap_i2c_put_clocks(dev); | |
55c381e4 | 1154 | iounmap(dev->base); |
010d442c KS |
1155 | kfree(dev); |
1156 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
59330825 | 1157 | release_mem_region(mem->start, resource_size(mem)); |
010d442c KS |
1158 | return 0; |
1159 | } | |
1160 | ||
1161 | static struct platform_driver omap_i2c_driver = { | |
1162 | .probe = omap_i2c_probe, | |
1163 | .remove = omap_i2c_remove, | |
1164 | .driver = { | |
1165 | .name = "i2c_omap", | |
1166 | .owner = THIS_MODULE, | |
1167 | }, | |
1168 | }; | |
1169 | ||
1170 | /* I2C may be needed to bring up other drivers */ | |
1171 | static int __init | |
1172 | omap_i2c_init_driver(void) | |
1173 | { | |
1174 | return platform_driver_register(&omap_i2c_driver); | |
1175 | } | |
1176 | subsys_initcall(omap_i2c_init_driver); | |
1177 | ||
1178 | static void __exit omap_i2c_exit_driver(void) | |
1179 | { | |
1180 | platform_driver_unregister(&omap_i2c_driver); | |
1181 | } | |
1182 | module_exit(omap_i2c_exit_driver); | |
1183 | ||
1184 | MODULE_AUTHOR("MontaVista Software, Inc. (and others)"); | |
1185 | MODULE_DESCRIPTION("TI OMAP I2C bus adapter"); | |
1186 | MODULE_LICENSE("GPL"); | |
add8eda7 | 1187 | MODULE_ALIAS("platform:i2c_omap"); |