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010d442c KS |
1 | /* |
2 | * TI OMAP I2C master mode driver | |
3 | * | |
4 | * Copyright (C) 2003 MontaVista Software, Inc. | |
010d442c | 5 | * Copyright (C) 2005 Nokia Corporation |
c1a473bd | 6 | * Copyright (C) 2004 - 2007 Texas Instruments. |
010d442c | 7 | * |
c1a473bd TL |
8 | * Originally written by MontaVista Software, Inc. |
9 | * Additional contributions by: | |
10 | * Tony Lindgren <tony@atomide.com> | |
11 | * Imre Deak <imre.deak@nokia.com> | |
12 | * Juha Yrjölä <juha.yrjola@solidboot.com> | |
13 | * Syed Khasim <x0khasim@ti.com> | |
14 | * Nishant Menon <nm@ti.com> | |
010d442c KS |
15 | * |
16 | * This program is free software; you can redistribute it and/or modify | |
17 | * it under the terms of the GNU General Public License as published by | |
18 | * the Free Software Foundation; either version 2 of the License, or | |
19 | * (at your option) any later version. | |
20 | * | |
21 | * This program is distributed in the hope that it will be useful, | |
22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
24 | * GNU General Public License for more details. | |
25 | * | |
26 | * You should have received a copy of the GNU General Public License | |
27 | * along with this program; if not, write to the Free Software | |
28 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
29 | */ | |
30 | ||
31 | #include <linux/module.h> | |
32 | #include <linux/delay.h> | |
33 | #include <linux/i2c.h> | |
34 | #include <linux/err.h> | |
35 | #include <linux/interrupt.h> | |
36 | #include <linux/completion.h> | |
37 | #include <linux/platform_device.h> | |
38 | #include <linux/clk.h> | |
c1a473bd | 39 | #include <linux/io.h> |
5a0e3ad6 | 40 | #include <linux/slab.h> |
20c9d2c4 | 41 | #include <linux/i2c-omap.h> |
27b1fec2 | 42 | #include <linux/pm_runtime.h> |
010d442c | 43 | |
9c76b878 PW |
44 | /* I2C controller revisions */ |
45 | #define OMAP_I2C_REV_2 0x20 | |
46 | ||
47 | /* I2C controller revisions present on specific hardware */ | |
48 | #define OMAP_I2C_REV_ON_2430 0x36 | |
49 | #define OMAP_I2C_REV_ON_3430 0x3C | |
f38e66e0 | 50 | #define OMAP_I2C_REV_ON_4430 0x40 |
9c76b878 | 51 | |
010d442c KS |
52 | /* timeout waiting for the controller to respond */ |
53 | #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000)) | |
54 | ||
5043e9e7 | 55 | /* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */ |
f38e66e0 SS |
56 | enum { |
57 | OMAP_I2C_REV_REG = 0, | |
58 | OMAP_I2C_IE_REG, | |
59 | OMAP_I2C_STAT_REG, | |
60 | OMAP_I2C_IV_REG, | |
61 | OMAP_I2C_WE_REG, | |
62 | OMAP_I2C_SYSS_REG, | |
63 | OMAP_I2C_BUF_REG, | |
64 | OMAP_I2C_CNT_REG, | |
65 | OMAP_I2C_DATA_REG, | |
66 | OMAP_I2C_SYSC_REG, | |
67 | OMAP_I2C_CON_REG, | |
68 | OMAP_I2C_OA_REG, | |
69 | OMAP_I2C_SA_REG, | |
70 | OMAP_I2C_PSC_REG, | |
71 | OMAP_I2C_SCLL_REG, | |
72 | OMAP_I2C_SCLH_REG, | |
73 | OMAP_I2C_SYSTEST_REG, | |
74 | OMAP_I2C_BUFSTAT_REG, | |
b8853088 AG |
75 | /* only on OMAP4430 */ |
76 | OMAP_I2C_IP_V2_REVNB_LO, | |
77 | OMAP_I2C_IP_V2_REVNB_HI, | |
78 | OMAP_I2C_IP_V2_IRQSTATUS_RAW, | |
79 | OMAP_I2C_IP_V2_IRQENABLE_SET, | |
80 | OMAP_I2C_IP_V2_IRQENABLE_CLR, | |
f38e66e0 | 81 | }; |
010d442c KS |
82 | |
83 | /* I2C Interrupt Enable Register (OMAP_I2C_IE): */ | |
b6ee52c3 NM |
84 | #define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */ |
85 | #define OMAP_I2C_IE_RDR (1 << 13) /* RX Buffer drain int enable */ | |
010d442c KS |
86 | #define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */ |
87 | #define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */ | |
88 | #define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */ | |
89 | #define OMAP_I2C_IE_NACK (1 << 1) /* No ack interrupt enable */ | |
90 | #define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */ | |
91 | ||
92 | /* I2C Status Register (OMAP_I2C_STAT): */ | |
b6ee52c3 NM |
93 | #define OMAP_I2C_STAT_XDR (1 << 14) /* TX Buffer draining */ |
94 | #define OMAP_I2C_STAT_RDR (1 << 13) /* RX Buffer draining */ | |
010d442c KS |
95 | #define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */ |
96 | #define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */ | |
97 | #define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ | |
98 | #define OMAP_I2C_STAT_AAS (1 << 9) /* Address as slave */ | |
99 | #define OMAP_I2C_STAT_AD0 (1 << 8) /* Address zero */ | |
100 | #define OMAP_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ | |
101 | #define OMAP_I2C_STAT_RRDY (1 << 3) /* Receive data ready */ | |
102 | #define OMAP_I2C_STAT_ARDY (1 << 2) /* Register access ready */ | |
103 | #define OMAP_I2C_STAT_NACK (1 << 1) /* No ack interrupt enable */ | |
104 | #define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost int ena */ | |
105 | ||
5043e9e7 KJ |
106 | /* I2C WE wakeup enable register */ |
107 | #define OMAP_I2C_WE_XDR_WE (1 << 14) /* TX drain wakup */ | |
108 | #define OMAP_I2C_WE_RDR_WE (1 << 13) /* RX drain wakeup */ | |
109 | #define OMAP_I2C_WE_AAS_WE (1 << 9) /* Address as slave wakeup*/ | |
110 | #define OMAP_I2C_WE_BF_WE (1 << 8) /* Bus free wakeup */ | |
111 | #define OMAP_I2C_WE_STC_WE (1 << 6) /* Start condition wakeup */ | |
112 | #define OMAP_I2C_WE_GC_WE (1 << 5) /* General call wakeup */ | |
113 | #define OMAP_I2C_WE_DRDY_WE (1 << 3) /* TX/RX data ready wakeup */ | |
114 | #define OMAP_I2C_WE_ARDY_WE (1 << 2) /* Reg access ready wakeup */ | |
115 | #define OMAP_I2C_WE_NACK_WE (1 << 1) /* No acknowledgment wakeup */ | |
116 | #define OMAP_I2C_WE_AL_WE (1 << 0) /* Arbitration lost wakeup */ | |
117 | ||
118 | #define OMAP_I2C_WE_ALL (OMAP_I2C_WE_XDR_WE | OMAP_I2C_WE_RDR_WE | \ | |
119 | OMAP_I2C_WE_AAS_WE | OMAP_I2C_WE_BF_WE | \ | |
120 | OMAP_I2C_WE_STC_WE | OMAP_I2C_WE_GC_WE | \ | |
121 | OMAP_I2C_WE_DRDY_WE | OMAP_I2C_WE_ARDY_WE | \ | |
122 | OMAP_I2C_WE_NACK_WE | OMAP_I2C_WE_AL_WE) | |
123 | ||
010d442c KS |
124 | /* I2C Buffer Configuration Register (OMAP_I2C_BUF): */ |
125 | #define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */ | |
b6ee52c3 | 126 | #define OMAP_I2C_BUF_RXFIF_CLR (1 << 14) /* RX FIFO Clear */ |
010d442c | 127 | #define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */ |
b6ee52c3 | 128 | #define OMAP_I2C_BUF_TXFIF_CLR (1 << 6) /* TX FIFO Clear */ |
010d442c KS |
129 | |
130 | /* I2C Configuration Register (OMAP_I2C_CON): */ | |
131 | #define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */ | |
132 | #define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */ | |
b6ee52c3 | 133 | #define OMAP_I2C_CON_OPMODE_HS (1 << 12) /* High Speed support */ |
010d442c KS |
134 | #define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */ |
135 | #define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */ | |
136 | #define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */ | |
137 | #define OMAP_I2C_CON_XA (1 << 8) /* Expand address */ | |
138 | #define OMAP_I2C_CON_RM (1 << 2) /* Repeat mode (master only) */ | |
139 | #define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */ | |
140 | #define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */ | |
141 | ||
4574eb68 SMK |
142 | /* I2C SCL time value when Master */ |
143 | #define OMAP_I2C_SCLL_HSSCLL 8 | |
144 | #define OMAP_I2C_SCLH_HSSCLH 8 | |
145 | ||
010d442c KS |
146 | /* I2C System Test Register (OMAP_I2C_SYSTEST): */ |
147 | #ifdef DEBUG | |
148 | #define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */ | |
149 | #define OMAP_I2C_SYSTEST_FREE (1 << 14) /* Free running mode */ | |
150 | #define OMAP_I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */ | |
151 | #define OMAP_I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */ | |
152 | #define OMAP_I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense in */ | |
153 | #define OMAP_I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive out */ | |
154 | #define OMAP_I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense in */ | |
155 | #define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */ | |
156 | #endif | |
157 | ||
fdd07fe6 PW |
158 | /* OCP_SYSSTATUS bit definitions */ |
159 | #define SYSS_RESETDONE_MASK (1 << 0) | |
160 | ||
161 | /* OCP_SYSCONFIG bit definitions */ | |
162 | #define SYSC_CLOCKACTIVITY_MASK (0x3 << 8) | |
163 | #define SYSC_SIDLEMODE_MASK (0x3 << 3) | |
164 | #define SYSC_ENAWAKEUP_MASK (1 << 2) | |
165 | #define SYSC_SOFTRESET_MASK (1 << 1) | |
166 | #define SYSC_AUTOIDLE_MASK (1 << 0) | |
167 | ||
168 | #define SYSC_IDLEMODE_SMART 0x2 | |
169 | #define SYSC_CLOCKACTIVITY_FCLK 0x2 | |
010d442c | 170 | |
f3083d92 | 171 | /* Errata definitions */ |
172 | #define I2C_OMAP_ERRATA_I207 (1 << 0) | |
8a9d97d3 | 173 | #define I2C_OMAP3_1P153 (1 << 1) |
010d442c | 174 | |
010d442c KS |
175 | struct omap_i2c_dev { |
176 | struct device *dev; | |
177 | void __iomem *base; /* virtual */ | |
178 | int irq; | |
d84d3ea3 | 179 | int reg_shift; /* bit shift for I2C register addresses */ |
010d442c KS |
180 | struct completion cmd_complete; |
181 | struct resource *ioarea; | |
20c9d2c4 KJ |
182 | u32 latency; /* maximum mpu wkup latency */ |
183 | void (*set_mpu_wkup_lat)(struct device *dev, | |
184 | long latency); | |
4574eb68 | 185 | u32 speed; /* Speed of bus in Khz */ |
010d442c KS |
186 | u16 cmd_err; |
187 | u8 *buf; | |
f38e66e0 | 188 | u8 *regs; |
010d442c KS |
189 | size_t buf_len; |
190 | struct i2c_adapter adapter; | |
b6ee52c3 NM |
191 | u8 fifo_size; /* use as flag and value |
192 | * fifo_size==0 implies no fifo | |
193 | * if set, should be trsh+1 | |
194 | */ | |
9c76b878 | 195 | u8 rev; |
b6ee52c3 | 196 | unsigned b_hw:1; /* bad h/w fixes */ |
f08ac4e7 TL |
197 | unsigned idle:1; |
198 | u16 iestate; /* Saved interrupt register */ | |
ef871432 RN |
199 | u16 pscstate; |
200 | u16 scllstate; | |
201 | u16 sclhstate; | |
202 | u16 bufstate; | |
203 | u16 syscstate; | |
204 | u16 westate; | |
f3083d92 | 205 | u16 errata; |
010d442c KS |
206 | }; |
207 | ||
a1295577 | 208 | static const u8 reg_map_ip_v1[] = { |
f38e66e0 SS |
209 | [OMAP_I2C_REV_REG] = 0x00, |
210 | [OMAP_I2C_IE_REG] = 0x01, | |
211 | [OMAP_I2C_STAT_REG] = 0x02, | |
212 | [OMAP_I2C_IV_REG] = 0x03, | |
213 | [OMAP_I2C_WE_REG] = 0x03, | |
214 | [OMAP_I2C_SYSS_REG] = 0x04, | |
215 | [OMAP_I2C_BUF_REG] = 0x05, | |
216 | [OMAP_I2C_CNT_REG] = 0x06, | |
217 | [OMAP_I2C_DATA_REG] = 0x07, | |
218 | [OMAP_I2C_SYSC_REG] = 0x08, | |
219 | [OMAP_I2C_CON_REG] = 0x09, | |
220 | [OMAP_I2C_OA_REG] = 0x0a, | |
221 | [OMAP_I2C_SA_REG] = 0x0b, | |
222 | [OMAP_I2C_PSC_REG] = 0x0c, | |
223 | [OMAP_I2C_SCLL_REG] = 0x0d, | |
224 | [OMAP_I2C_SCLH_REG] = 0x0e, | |
225 | [OMAP_I2C_SYSTEST_REG] = 0x0f, | |
226 | [OMAP_I2C_BUFSTAT_REG] = 0x10, | |
227 | }; | |
228 | ||
a1295577 | 229 | static const u8 reg_map_ip_v2[] = { |
f38e66e0 SS |
230 | [OMAP_I2C_REV_REG] = 0x04, |
231 | [OMAP_I2C_IE_REG] = 0x2c, | |
232 | [OMAP_I2C_STAT_REG] = 0x28, | |
233 | [OMAP_I2C_IV_REG] = 0x34, | |
234 | [OMAP_I2C_WE_REG] = 0x34, | |
235 | [OMAP_I2C_SYSS_REG] = 0x90, | |
236 | [OMAP_I2C_BUF_REG] = 0x94, | |
237 | [OMAP_I2C_CNT_REG] = 0x98, | |
238 | [OMAP_I2C_DATA_REG] = 0x9c, | |
239 | [OMAP_I2C_SYSC_REG] = 0x20, | |
240 | [OMAP_I2C_CON_REG] = 0xa4, | |
241 | [OMAP_I2C_OA_REG] = 0xa8, | |
242 | [OMAP_I2C_SA_REG] = 0xac, | |
243 | [OMAP_I2C_PSC_REG] = 0xb0, | |
244 | [OMAP_I2C_SCLL_REG] = 0xb4, | |
245 | [OMAP_I2C_SCLH_REG] = 0xb8, | |
246 | [OMAP_I2C_SYSTEST_REG] = 0xbC, | |
247 | [OMAP_I2C_BUFSTAT_REG] = 0xc0, | |
b8853088 AG |
248 | [OMAP_I2C_IP_V2_REVNB_LO] = 0x00, |
249 | [OMAP_I2C_IP_V2_REVNB_HI] = 0x04, | |
250 | [OMAP_I2C_IP_V2_IRQSTATUS_RAW] = 0x24, | |
251 | [OMAP_I2C_IP_V2_IRQENABLE_SET] = 0x2c, | |
252 | [OMAP_I2C_IP_V2_IRQENABLE_CLR] = 0x30, | |
f38e66e0 SS |
253 | }; |
254 | ||
010d442c KS |
255 | static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev, |
256 | int reg, u16 val) | |
257 | { | |
f38e66e0 SS |
258 | __raw_writew(val, i2c_dev->base + |
259 | (i2c_dev->regs[reg] << i2c_dev->reg_shift)); | |
010d442c KS |
260 | } |
261 | ||
262 | static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg) | |
263 | { | |
f38e66e0 SS |
264 | return __raw_readw(i2c_dev->base + |
265 | (i2c_dev->regs[reg] << i2c_dev->reg_shift)); | |
010d442c KS |
266 | } |
267 | ||
27b1fec2 | 268 | static void omap_i2c_unidle(struct omap_i2c_dev *dev) |
010d442c | 269 | { |
27b1fec2 RN |
270 | struct platform_device *pdev; |
271 | struct omap_i2c_bus_platform_data *pdata; | |
5fe23380 | 272 | |
27b1fec2 | 273 | WARN_ON(!dev->idle); |
010d442c | 274 | |
27b1fec2 RN |
275 | pdev = to_platform_device(dev->dev); |
276 | pdata = pdev->dev.platform_data; | |
010d442c | 277 | |
27b1fec2 | 278 | pm_runtime_get_sync(&pdev->dev); |
010d442c | 279 | |
ef871432 RN |
280 | if (cpu_is_omap34xx()) { |
281 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0); | |
282 | omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, dev->pscstate); | |
283 | omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, dev->scllstate); | |
284 | omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, dev->sclhstate); | |
285 | omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, dev->bufstate); | |
286 | omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, dev->syscstate); | |
287 | omap_i2c_write_reg(dev, OMAP_I2C_WE_REG, dev->westate); | |
288 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN); | |
289 | } | |
0cbbcffd | 290 | dev->idle = 0; |
07ac31f6 CM |
291 | |
292 | /* | |
293 | * Don't write to this register if the IE state is 0 as it can | |
294 | * cause deadlock. | |
295 | */ | |
296 | if (dev->iestate) | |
297 | omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate); | |
010d442c KS |
298 | } |
299 | ||
f08ac4e7 | 300 | static void omap_i2c_idle(struct omap_i2c_dev *dev) |
010d442c | 301 | { |
27b1fec2 RN |
302 | struct platform_device *pdev; |
303 | struct omap_i2c_bus_platform_data *pdata; | |
f08ac4e7 TL |
304 | u16 iv; |
305 | ||
3831f154 PW |
306 | WARN_ON(dev->idle); |
307 | ||
27b1fec2 RN |
308 | pdev = to_platform_device(dev->dev); |
309 | pdata = pdev->dev.platform_data; | |
310 | ||
f08ac4e7 | 311 | dev->iestate = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG); |
6314f09e | 312 | if (pdata->rev == OMAP_I2C_IP_VERSION_2) |
b8853088 | 313 | omap_i2c_write_reg(dev, OMAP_I2C_IP_V2_IRQENABLE_CLR, 1); |
f38e66e0 SS |
314 | else |
315 | omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, 0); | |
316 | ||
9c76b878 | 317 | if (dev->rev < OMAP_I2C_REV_2) { |
c1a473bd | 318 | iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG); /* Read clears */ |
0cbbcffd | 319 | } else { |
f08ac4e7 | 320 | omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, dev->iestate); |
0cbbcffd PW |
321 | |
322 | /* Flush posted write before the dev->idle store occurs */ | |
323 | omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG); | |
324 | } | |
325 | dev->idle = 1; | |
27b1fec2 RN |
326 | |
327 | pm_runtime_put_sync(&pdev->dev); | |
010d442c KS |
328 | } |
329 | ||
330 | static int omap_i2c_init(struct omap_i2c_dev *dev) | |
331 | { | |
ef871432 | 332 | u16 psc = 0, scll = 0, sclh = 0, buf = 0; |
4574eb68 | 333 | u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0; |
010d442c KS |
334 | unsigned long fclk_rate = 12000000; |
335 | unsigned long timeout; | |
4574eb68 | 336 | unsigned long internal_clk = 0; |
27b1fec2 | 337 | struct clk *fclk; |
010d442c | 338 | |
9c76b878 | 339 | if (dev->rev >= OMAP_I2C_REV_2) { |
57eb81b1 MG |
340 | /* Disable I2C controller before soft reset */ |
341 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, | |
342 | omap_i2c_read_reg(dev, OMAP_I2C_CON_REG) & | |
343 | ~(OMAP_I2C_CON_EN)); | |
344 | ||
fdd07fe6 | 345 | omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK); |
010d442c KS |
346 | /* For some reason we need to set the EN bit before the |
347 | * reset done bit gets set. */ | |
348 | timeout = jiffies + OMAP_I2C_TIMEOUT; | |
349 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN); | |
350 | while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) & | |
fdd07fe6 | 351 | SYSS_RESETDONE_MASK)) { |
010d442c | 352 | if (time_after(jiffies, timeout)) { |
fce3ff03 | 353 | dev_warn(dev->dev, "timeout waiting " |
010d442c KS |
354 | "for controller reset\n"); |
355 | return -ETIMEDOUT; | |
356 | } | |
357 | msleep(1); | |
358 | } | |
fdd07fe6 PW |
359 | |
360 | /* SYSC register is cleared by the reset; rewrite it */ | |
361 | if (dev->rev == OMAP_I2C_REV_ON_2430) { | |
362 | ||
363 | omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, | |
364 | SYSC_AUTOIDLE_MASK); | |
365 | ||
366 | } else if (dev->rev >= OMAP_I2C_REV_ON_3430) { | |
ef871432 RN |
367 | dev->syscstate = SYSC_AUTOIDLE_MASK; |
368 | dev->syscstate |= SYSC_ENAWAKEUP_MASK; | |
369 | dev->syscstate |= (SYSC_IDLEMODE_SMART << | |
fdd07fe6 | 370 | __ffs(SYSC_SIDLEMODE_MASK)); |
ef871432 | 371 | dev->syscstate |= (SYSC_CLOCKACTIVITY_FCLK << |
fdd07fe6 PW |
372 | __ffs(SYSC_CLOCKACTIVITY_MASK)); |
373 | ||
ef871432 RN |
374 | omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, |
375 | dev->syscstate); | |
5043e9e7 KJ |
376 | /* |
377 | * Enabling all wakup sources to stop I2C freezing on | |
378 | * WFI instruction. | |
379 | * REVISIT: Some wkup sources might not be needed. | |
380 | */ | |
ef871432 | 381 | dev->westate = OMAP_I2C_WE_ALL; |
120bdaa4 | 382 | omap_i2c_write_reg(dev, OMAP_I2C_WE_REG, dev->westate); |
fdd07fe6 | 383 | } |
010d442c KS |
384 | } |
385 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0); | |
386 | ||
387 | if (cpu_class_is_omap1()) { | |
0e9ae109 RK |
388 | /* |
389 | * The I2C functional clock is the armxor_ck, so there's | |
390 | * no need to get "armxor_ck" separately. Now, if OMAP2420 | |
391 | * always returns 12MHz for the functional clock, we can | |
392 | * do this bit unconditionally. | |
393 | */ | |
27b1fec2 RN |
394 | fclk = clk_get(dev->dev, "fck"); |
395 | fclk_rate = clk_get_rate(fclk); | |
396 | clk_put(fclk); | |
0e9ae109 | 397 | |
010d442c KS |
398 | /* TRM for 5912 says the I2C clock must be prescaled to be |
399 | * between 7 - 12 MHz. The XOR input clock is typically | |
400 | * 12, 13 or 19.2 MHz. So we should have code that produces: | |
401 | * | |
402 | * XOR MHz Divider Prescaler | |
403 | * 12 1 0 | |
404 | * 13 2 1 | |
405 | * 19.2 2 1 | |
406 | */ | |
d7aef138 JD |
407 | if (fclk_rate > 12000000) |
408 | psc = fclk_rate / 12000000; | |
010d442c KS |
409 | } |
410 | ||
f38e66e0 | 411 | if (!(cpu_class_is_omap1() || cpu_is_omap2420())) { |
4574eb68 | 412 | |
84bf2c86 AK |
413 | /* |
414 | * HSI2C controller internal clk rate should be 19.2 Mhz for | |
415 | * HS and for all modes on 2430. On 34xx we can use lower rate | |
416 | * to get longer filter period for better noise suppression. | |
417 | * The filter is iclk (fclk for HS) period. | |
418 | */ | |
ff0f2426 | 419 | if (dev->speed > 400 || cpu_is_omap2430()) |
84bf2c86 AK |
420 | internal_clk = 19200; |
421 | else if (dev->speed > 100) | |
422 | internal_clk = 9600; | |
423 | else | |
424 | internal_clk = 4000; | |
27b1fec2 RN |
425 | fclk = clk_get(dev->dev, "fck"); |
426 | fclk_rate = clk_get_rate(fclk) / 1000; | |
427 | clk_put(fclk); | |
4574eb68 SMK |
428 | |
429 | /* Compute prescaler divisor */ | |
430 | psc = fclk_rate / internal_clk; | |
431 | psc = psc - 1; | |
432 | ||
433 | /* If configured for High Speed */ | |
434 | if (dev->speed > 400) { | |
baf46b4e AK |
435 | unsigned long scl; |
436 | ||
4574eb68 | 437 | /* For first phase of HS mode */ |
baf46b4e AK |
438 | scl = internal_clk / 400; |
439 | fsscll = scl - (scl / 3) - 7; | |
440 | fssclh = (scl / 3) - 5; | |
4574eb68 SMK |
441 | |
442 | /* For second phase of HS mode */ | |
baf46b4e AK |
443 | scl = fclk_rate / dev->speed; |
444 | hsscll = scl - (scl / 3) - 7; | |
445 | hssclh = (scl / 3) - 5; | |
446 | } else if (dev->speed > 100) { | |
447 | unsigned long scl; | |
448 | ||
449 | /* Fast mode */ | |
450 | scl = internal_clk / dev->speed; | |
451 | fsscll = scl - (scl / 3) - 7; | |
452 | fssclh = (scl / 3) - 5; | |
4574eb68 | 453 | } else { |
baf46b4e AK |
454 | /* Standard mode */ |
455 | fsscll = internal_clk / (dev->speed * 2) - 7; | |
456 | fssclh = internal_clk / (dev->speed * 2) - 5; | |
4574eb68 SMK |
457 | } |
458 | scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll; | |
459 | sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh; | |
460 | } else { | |
461 | /* Program desired operating rate */ | |
462 | fclk_rate /= (psc + 1) * 1000; | |
463 | if (psc > 2) | |
464 | psc = 2; | |
465 | scll = fclk_rate / (dev->speed * 2) - 7 + psc; | |
466 | sclh = fclk_rate / (dev->speed * 2) - 7 + psc; | |
467 | } | |
468 | ||
010d442c KS |
469 | /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */ |
470 | omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc); | |
471 | ||
4574eb68 SMK |
472 | /* SCL low and high time values */ |
473 | omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, scll); | |
474 | omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, sclh); | |
010d442c | 475 | |
ef871432 RN |
476 | if (dev->fifo_size) { |
477 | /* Note: setup required fifo size - 1. RTRSH and XTRSH */ | |
478 | buf = (dev->fifo_size - 1) << 8 | OMAP_I2C_BUF_RXFIF_CLR | | |
479 | (dev->fifo_size - 1) | OMAP_I2C_BUF_TXFIF_CLR; | |
480 | omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, buf); | |
481 | } | |
b6ee52c3 | 482 | |
010d442c KS |
483 | /* Take the I2C module out of reset: */ |
484 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN); | |
485 | ||
f3083d92 | 486 | dev->errata = 0; |
487 | ||
488 | if (cpu_is_omap2430() || cpu_is_omap34xx()) | |
489 | dev->errata |= I2C_OMAP_ERRATA_I207; | |
490 | ||
010d442c | 491 | /* Enable interrupts */ |
ef871432 | 492 | dev->iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY | |
c1a473bd TL |
493 | OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK | |
494 | OMAP_I2C_IE_AL) | ((dev->fifo_size) ? | |
ef871432 RN |
495 | (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0); |
496 | omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate); | |
497 | if (cpu_is_omap34xx()) { | |
498 | dev->pscstate = psc; | |
499 | dev->scllstate = scll; | |
500 | dev->sclhstate = sclh; | |
501 | dev->bufstate = buf; | |
502 | } | |
010d442c KS |
503 | return 0; |
504 | } | |
505 | ||
506 | /* | |
507 | * Waiting on Bus Busy | |
508 | */ | |
509 | static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev) | |
510 | { | |
511 | unsigned long timeout; | |
512 | ||
513 | timeout = jiffies + OMAP_I2C_TIMEOUT; | |
514 | while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) { | |
515 | if (time_after(jiffies, timeout)) { | |
516 | dev_warn(dev->dev, "timeout waiting for bus ready\n"); | |
517 | return -ETIMEDOUT; | |
518 | } | |
519 | msleep(1); | |
520 | } | |
521 | ||
522 | return 0; | |
523 | } | |
524 | ||
525 | /* | |
526 | * Low level master read/write transaction. | |
527 | */ | |
528 | static int omap_i2c_xfer_msg(struct i2c_adapter *adap, | |
529 | struct i2c_msg *msg, int stop) | |
530 | { | |
531 | struct omap_i2c_dev *dev = i2c_get_adapdata(adap); | |
532 | int r; | |
533 | u16 w; | |
534 | ||
535 | dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n", | |
536 | msg->addr, msg->len, msg->flags, stop); | |
537 | ||
538 | if (msg->len == 0) | |
539 | return -EINVAL; | |
540 | ||
541 | omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr); | |
542 | ||
543 | /* REVISIT: Could the STB bit of I2C_CON be used with probing? */ | |
544 | dev->buf = msg->buf; | |
545 | dev->buf_len = msg->len; | |
546 | ||
547 | omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len); | |
548 | ||
b6ee52c3 NM |
549 | /* Clear the FIFO Buffers */ |
550 | w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG); | |
551 | w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR; | |
552 | omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w); | |
553 | ||
010d442c KS |
554 | init_completion(&dev->cmd_complete); |
555 | dev->cmd_err = 0; | |
556 | ||
557 | w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT; | |
4574eb68 SMK |
558 | |
559 | /* High speed configuration */ | |
560 | if (dev->speed > 400) | |
b6ee52c3 | 561 | w |= OMAP_I2C_CON_OPMODE_HS; |
4574eb68 | 562 | |
010d442c KS |
563 | if (msg->flags & I2C_M_TEN) |
564 | w |= OMAP_I2C_CON_XA; | |
565 | if (!(msg->flags & I2C_M_RD)) | |
566 | w |= OMAP_I2C_CON_TRX; | |
c1a473bd | 567 | |
b6ee52c3 | 568 | if (!dev->b_hw && stop) |
010d442c | 569 | w |= OMAP_I2C_CON_STP; |
c1a473bd | 570 | |
010d442c KS |
571 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w); |
572 | ||
b6ee52c3 NM |
573 | /* |
574 | * Don't write stt and stp together on some hardware. | |
575 | */ | |
576 | if (dev->b_hw && stop) { | |
577 | unsigned long delay = jiffies + OMAP_I2C_TIMEOUT; | |
578 | u16 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG); | |
579 | while (con & OMAP_I2C_CON_STT) { | |
580 | con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG); | |
581 | ||
582 | /* Let the user know if i2c is in a bad state */ | |
583 | if (time_after(jiffies, delay)) { | |
584 | dev_err(dev->dev, "controller timed out " | |
585 | "waiting for start condition to finish\n"); | |
586 | return -ETIMEDOUT; | |
587 | } | |
588 | cpu_relax(); | |
589 | } | |
590 | ||
591 | w |= OMAP_I2C_CON_STP; | |
592 | w &= ~OMAP_I2C_CON_STT; | |
593 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w); | |
594 | } | |
595 | ||
b7af349b JN |
596 | /* |
597 | * REVISIT: We should abort the transfer on signals, but the bus goes | |
598 | * into arbitration and we're currently unable to recover from it. | |
599 | */ | |
600 | r = wait_for_completion_timeout(&dev->cmd_complete, | |
601 | OMAP_I2C_TIMEOUT); | |
010d442c KS |
602 | dev->buf_len = 0; |
603 | if (r < 0) | |
604 | return r; | |
605 | if (r == 0) { | |
606 | dev_err(dev->dev, "controller timed out\n"); | |
607 | omap_i2c_init(dev); | |
608 | return -ETIMEDOUT; | |
609 | } | |
610 | ||
611 | if (likely(!dev->cmd_err)) | |
612 | return 0; | |
613 | ||
614 | /* We have an error */ | |
615 | if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR | | |
616 | OMAP_I2C_STAT_XUDF)) { | |
617 | omap_i2c_init(dev); | |
618 | return -EIO; | |
619 | } | |
620 | ||
621 | if (dev->cmd_err & OMAP_I2C_STAT_NACK) { | |
622 | if (msg->flags & I2C_M_IGNORE_NAK) | |
623 | return 0; | |
624 | if (stop) { | |
625 | w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG); | |
626 | w |= OMAP_I2C_CON_STP; | |
627 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w); | |
628 | } | |
629 | return -EREMOTEIO; | |
630 | } | |
631 | return -EIO; | |
632 | } | |
633 | ||
634 | ||
635 | /* | |
636 | * Prepare controller for a transaction and call omap_i2c_xfer_msg | |
637 | * to do the work during IRQ processing. | |
638 | */ | |
639 | static int | |
640 | omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) | |
641 | { | |
642 | struct omap_i2c_dev *dev = i2c_get_adapdata(adap); | |
643 | int i; | |
644 | int r; | |
645 | ||
f08ac4e7 | 646 | omap_i2c_unidle(dev); |
010d442c | 647 | |
c1a473bd TL |
648 | r = omap_i2c_wait_for_bb(dev); |
649 | if (r < 0) | |
010d442c KS |
650 | goto out; |
651 | ||
6a91b558 SO |
652 | if (dev->set_mpu_wkup_lat != NULL) |
653 | dev->set_mpu_wkup_lat(dev->dev, dev->latency); | |
654 | ||
010d442c KS |
655 | for (i = 0; i < num; i++) { |
656 | r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1))); | |
657 | if (r != 0) | |
658 | break; | |
659 | } | |
660 | ||
6a91b558 SO |
661 | if (dev->set_mpu_wkup_lat != NULL) |
662 | dev->set_mpu_wkup_lat(dev->dev, -1); | |
663 | ||
010d442c KS |
664 | if (r == 0) |
665 | r = num; | |
5c64eb26 MN |
666 | |
667 | omap_i2c_wait_for_bb(dev); | |
010d442c | 668 | out: |
f08ac4e7 | 669 | omap_i2c_idle(dev); |
010d442c KS |
670 | return r; |
671 | } | |
672 | ||
673 | static u32 | |
674 | omap_i2c_func(struct i2c_adapter *adap) | |
675 | { | |
676 | return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); | |
677 | } | |
678 | ||
679 | static inline void | |
680 | omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err) | |
681 | { | |
682 | dev->cmd_err |= err; | |
683 | complete(&dev->cmd_complete); | |
684 | } | |
685 | ||
686 | static inline void | |
687 | omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat) | |
688 | { | |
689 | omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat); | |
690 | } | |
691 | ||
f3083d92 | 692 | static inline void i2c_omap_errata_i207(struct omap_i2c_dev *dev, u16 stat) |
693 | { | |
694 | /* | |
695 | * I2C Errata(Errata Nos. OMAP2: 1.67, OMAP3: 1.8) | |
696 | * Not applicable for OMAP4. | |
697 | * Under certain rare conditions, RDR could be set again | |
698 | * when the bus is busy, then ignore the interrupt and | |
699 | * clear the interrupt. | |
700 | */ | |
701 | if (stat & OMAP_I2C_STAT_RDR) { | |
702 | /* Step 1: If RDR is set, clear it */ | |
703 | omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR); | |
704 | ||
705 | /* Step 2: */ | |
706 | if (!(omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) | |
707 | & OMAP_I2C_STAT_BB)) { | |
708 | ||
709 | /* Step 3: */ | |
710 | if (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) | |
711 | & OMAP_I2C_STAT_RDR) { | |
712 | omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR); | |
713 | dev_dbg(dev->dev, "RDR when bus is busy.\n"); | |
714 | } | |
715 | ||
716 | } | |
717 | } | |
718 | } | |
719 | ||
43469d8e PW |
720 | /* rev1 devices are apparently only on some 15xx */ |
721 | #ifdef CONFIG_ARCH_OMAP15XX | |
722 | ||
010d442c | 723 | static irqreturn_t |
7d12e780 | 724 | omap_i2c_rev1_isr(int this_irq, void *dev_id) |
010d442c KS |
725 | { |
726 | struct omap_i2c_dev *dev = dev_id; | |
727 | u16 iv, w; | |
728 | ||
f08ac4e7 TL |
729 | if (dev->idle) |
730 | return IRQ_NONE; | |
731 | ||
010d442c KS |
732 | iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG); |
733 | switch (iv) { | |
734 | case 0x00: /* None */ | |
735 | break; | |
736 | case 0x01: /* Arbitration lost */ | |
737 | dev_err(dev->dev, "Arbitration lost\n"); | |
738 | omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL); | |
739 | break; | |
740 | case 0x02: /* No acknowledgement */ | |
741 | omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK); | |
742 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP); | |
743 | break; | |
744 | case 0x03: /* Register access ready */ | |
745 | omap_i2c_complete_cmd(dev, 0); | |
746 | break; | |
747 | case 0x04: /* Receive data ready */ | |
748 | if (dev->buf_len) { | |
749 | w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG); | |
750 | *dev->buf++ = w; | |
751 | dev->buf_len--; | |
752 | if (dev->buf_len) { | |
753 | *dev->buf++ = w >> 8; | |
754 | dev->buf_len--; | |
755 | } | |
756 | } else | |
757 | dev_err(dev->dev, "RRDY IRQ while no data requested\n"); | |
758 | break; | |
759 | case 0x05: /* Transmit data ready */ | |
760 | if (dev->buf_len) { | |
761 | w = *dev->buf++; | |
762 | dev->buf_len--; | |
763 | if (dev->buf_len) { | |
764 | w |= *dev->buf++ << 8; | |
765 | dev->buf_len--; | |
766 | } | |
767 | omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w); | |
768 | } else | |
769 | dev_err(dev->dev, "XRDY IRQ while no data to send\n"); | |
770 | break; | |
771 | default: | |
772 | return IRQ_NONE; | |
773 | } | |
774 | ||
775 | return IRQ_HANDLED; | |
776 | } | |
43469d8e | 777 | #else |
c1a473bd | 778 | #define omap_i2c_rev1_isr NULL |
43469d8e | 779 | #endif |
010d442c | 780 | |
2dd151ab AS |
781 | /* |
782 | * OMAP3430 Errata 1.153: When an XRDY/XDR is hit, wait for XUDF before writing | |
783 | * data to DATA_REG. Otherwise some data bytes can be lost while transferring | |
784 | * them from the memory to the I2C interface. | |
785 | */ | |
786 | static int errata_omap3_1p153(struct omap_i2c_dev *dev, u16 *stat, int *err) | |
787 | { | |
e9f59b9c AS |
788 | unsigned long timeout = 10000; |
789 | ||
790 | while (--timeout && !(*stat & OMAP_I2C_STAT_XUDF)) { | |
2dd151ab AS |
791 | if (*stat & (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) { |
792 | omap_i2c_ack_stat(dev, *stat & (OMAP_I2C_STAT_XRDY | | |
793 | OMAP_I2C_STAT_XDR)); | |
794 | *err |= OMAP_I2C_STAT_XUDF; | |
795 | return -ETIMEDOUT; | |
796 | } | |
e9f59b9c | 797 | |
2dd151ab AS |
798 | cpu_relax(); |
799 | *stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG); | |
800 | } | |
801 | ||
e9f59b9c AS |
802 | if (!timeout) { |
803 | dev_err(dev->dev, "timeout waiting on XUDF bit\n"); | |
804 | return 0; | |
805 | } | |
806 | ||
2dd151ab AS |
807 | return 0; |
808 | } | |
809 | ||
010d442c | 810 | static irqreturn_t |
7d12e780 | 811 | omap_i2c_isr(int this_irq, void *dev_id) |
010d442c KS |
812 | { |
813 | struct omap_i2c_dev *dev = dev_id; | |
814 | u16 bits; | |
815 | u16 stat, w; | |
b6ee52c3 | 816 | int err, count = 0; |
010d442c | 817 | |
f08ac4e7 TL |
818 | if (dev->idle) |
819 | return IRQ_NONE; | |
820 | ||
010d442c KS |
821 | bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG); |
822 | while ((stat = (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG))) & bits) { | |
823 | dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat); | |
824 | if (count++ == 100) { | |
825 | dev_warn(dev->dev, "Too much work in one IRQ\n"); | |
826 | break; | |
827 | } | |
828 | ||
cd086d3a SM |
829 | err = 0; |
830 | complete: | |
dcc4ec26 NM |
831 | /* |
832 | * Ack the stat in one go, but [R/X]DR and [R/X]RDY should be | |
833 | * acked after the data operation is complete. | |
834 | * Ref: TRM SWPU114Q Figure 18-31 | |
835 | */ | |
836 | omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat & | |
837 | ~(OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR | | |
838 | OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR)); | |
010d442c | 839 | |
b6ee52c3 NM |
840 | if (stat & OMAP_I2C_STAT_NACK) { |
841 | err |= OMAP_I2C_STAT_NACK; | |
842 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, | |
843 | OMAP_I2C_CON_STP); | |
010d442c | 844 | } |
b6ee52c3 NM |
845 | if (stat & OMAP_I2C_STAT_AL) { |
846 | dev_err(dev->dev, "Arbitration lost\n"); | |
847 | err |= OMAP_I2C_STAT_AL; | |
848 | } | |
a5a595cc | 849 | /* |
cb527ede | 850 | * ProDB0017052: Clear ARDY bit twice |
a5a595cc | 851 | */ |
b6ee52c3 | 852 | if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK | |
04c688dd | 853 | OMAP_I2C_STAT_AL)) { |
dd11976a MS |
854 | omap_i2c_ack_stat(dev, stat & |
855 | (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR | | |
cb527ede R |
856 | OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR | |
857 | OMAP_I2C_STAT_ARDY)); | |
b6ee52c3 | 858 | omap_i2c_complete_cmd(dev, err); |
04c688dd SM |
859 | return IRQ_HANDLED; |
860 | } | |
b6ee52c3 NM |
861 | if (stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR)) { |
862 | u8 num_bytes = 1; | |
f3083d92 | 863 | |
864 | if (dev->errata & I2C_OMAP_ERRATA_I207) | |
865 | i2c_omap_errata_i207(dev, stat); | |
866 | ||
b6ee52c3 NM |
867 | if (dev->fifo_size) { |
868 | if (stat & OMAP_I2C_STAT_RRDY) | |
869 | num_bytes = dev->fifo_size; | |
bfb6b658 SM |
870 | else /* read RXSTAT on RDR interrupt */ |
871 | num_bytes = (omap_i2c_read_reg(dev, | |
872 | OMAP_I2C_BUFSTAT_REG) | |
873 | >> 8) & 0x3F; | |
b6ee52c3 NM |
874 | } |
875 | while (num_bytes) { | |
876 | num_bytes--; | |
877 | w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG); | |
010d442c | 878 | if (dev->buf_len) { |
b6ee52c3 | 879 | *dev->buf++ = w; |
010d442c | 880 | dev->buf_len--; |
f38e66e0 SS |
881 | /* |
882 | * Data reg in 2430, omap3 and | |
883 | * omap4 is 8 bit wide | |
884 | */ | |
885 | if (cpu_class_is_omap1() || | |
886 | cpu_is_omap2420()) { | |
b6ee52c3 NM |
887 | if (dev->buf_len) { |
888 | *dev->buf++ = w >> 8; | |
889 | dev->buf_len--; | |
890 | } | |
891 | } | |
892 | } else { | |
893 | if (stat & OMAP_I2C_STAT_RRDY) | |
894 | dev_err(dev->dev, | |
895 | "RRDY IRQ while no data" | |
896 | " requested\n"); | |
897 | if (stat & OMAP_I2C_STAT_RDR) | |
898 | dev_err(dev->dev, | |
899 | "RDR IRQ while no data" | |
900 | " requested\n"); | |
901 | break; | |
010d442c | 902 | } |
b6ee52c3 NM |
903 | } |
904 | omap_i2c_ack_stat(dev, | |
905 | stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR)); | |
010d442c KS |
906 | continue; |
907 | } | |
b6ee52c3 NM |
908 | if (stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR)) { |
909 | u8 num_bytes = 1; | |
910 | if (dev->fifo_size) { | |
911 | if (stat & OMAP_I2C_STAT_XRDY) | |
912 | num_bytes = dev->fifo_size; | |
bfb6b658 | 913 | else /* read TXSTAT on XDR interrupt */ |
b6ee52c3 | 914 | num_bytes = omap_i2c_read_reg(dev, |
bfb6b658 SM |
915 | OMAP_I2C_BUFSTAT_REG) |
916 | & 0x3F; | |
b6ee52c3 NM |
917 | } |
918 | while (num_bytes) { | |
919 | num_bytes--; | |
920 | w = 0; | |
010d442c | 921 | if (dev->buf_len) { |
b6ee52c3 | 922 | w = *dev->buf++; |
010d442c | 923 | dev->buf_len--; |
f38e66e0 SS |
924 | /* |
925 | * Data reg in 2430, omap3 and | |
926 | * omap4 is 8 bit wide | |
927 | */ | |
928 | if (cpu_class_is_omap1() || | |
929 | cpu_is_omap2420()) { | |
b6ee52c3 NM |
930 | if (dev->buf_len) { |
931 | w |= *dev->buf++ << 8; | |
932 | dev->buf_len--; | |
933 | } | |
934 | } | |
935 | } else { | |
936 | if (stat & OMAP_I2C_STAT_XRDY) | |
937 | dev_err(dev->dev, | |
938 | "XRDY IRQ while no " | |
939 | "data to send\n"); | |
940 | if (stat & OMAP_I2C_STAT_XDR) | |
941 | dev_err(dev->dev, | |
942 | "XDR IRQ while no " | |
943 | "data to send\n"); | |
944 | break; | |
010d442c | 945 | } |
cd086d3a | 946 | |
8a9d97d3 | 947 | if ((dev->errata & I2C_OMAP3_1P153) && |
2dd151ab AS |
948 | errata_omap3_1p153(dev, &stat, &err)) |
949 | goto complete; | |
cd086d3a | 950 | |
b6ee52c3 NM |
951 | omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w); |
952 | } | |
953 | omap_i2c_ack_stat(dev, | |
954 | stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR)); | |
010d442c KS |
955 | continue; |
956 | } | |
957 | if (stat & OMAP_I2C_STAT_ROVR) { | |
958 | dev_err(dev->dev, "Receive overrun\n"); | |
959 | dev->cmd_err |= OMAP_I2C_STAT_ROVR; | |
960 | } | |
961 | if (stat & OMAP_I2C_STAT_XUDF) { | |
b6ee52c3 | 962 | dev_err(dev->dev, "Transmit underflow\n"); |
010d442c KS |
963 | dev->cmd_err |= OMAP_I2C_STAT_XUDF; |
964 | } | |
010d442c KS |
965 | } |
966 | ||
967 | return count ? IRQ_HANDLED : IRQ_NONE; | |
968 | } | |
969 | ||
8f9082c5 | 970 | static const struct i2c_algorithm omap_i2c_algo = { |
010d442c KS |
971 | .master_xfer = omap_i2c_xfer, |
972 | .functionality = omap_i2c_func, | |
973 | }; | |
974 | ||
1139aea9 | 975 | static int __devinit |
010d442c KS |
976 | omap_i2c_probe(struct platform_device *pdev) |
977 | { | |
978 | struct omap_i2c_dev *dev; | |
979 | struct i2c_adapter *adap; | |
980 | struct resource *mem, *irq, *ioarea; | |
20c9d2c4 | 981 | struct omap_i2c_bus_platform_data *pdata = pdev->dev.platform_data; |
e355204e | 982 | irq_handler_t isr; |
010d442c | 983 | int r; |
3d522fb4 | 984 | u32 speed = 0; |
010d442c KS |
985 | |
986 | /* NOTE: driver uses the static register mapping */ | |
987 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
988 | if (!mem) { | |
989 | dev_err(&pdev->dev, "no mem resource?\n"); | |
990 | return -ENODEV; | |
991 | } | |
992 | irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
993 | if (!irq) { | |
994 | dev_err(&pdev->dev, "no irq resource?\n"); | |
995 | return -ENODEV; | |
996 | } | |
997 | ||
59330825 | 998 | ioarea = request_mem_region(mem->start, resource_size(mem), |
010d442c KS |
999 | pdev->name); |
1000 | if (!ioarea) { | |
1001 | dev_err(&pdev->dev, "I2C region already claimed\n"); | |
1002 | return -EBUSY; | |
1003 | } | |
1004 | ||
010d442c KS |
1005 | dev = kzalloc(sizeof(struct omap_i2c_dev), GFP_KERNEL); |
1006 | if (!dev) { | |
1007 | r = -ENOMEM; | |
1008 | goto err_release_region; | |
1009 | } | |
1010 | ||
20c9d2c4 KJ |
1011 | if (pdata != NULL) { |
1012 | speed = pdata->clkrate; | |
1013 | dev->set_mpu_wkup_lat = pdata->set_mpu_wkup_lat; | |
1014 | } else { | |
1015 | speed = 100; /* Default speed */ | |
1016 | dev->set_mpu_wkup_lat = NULL; | |
1017 | } | |
4574eb68 | 1018 | |
3d522fb4 | 1019 | dev->speed = speed; |
3831f154 | 1020 | dev->idle = 1; |
010d442c KS |
1021 | dev->dev = &pdev->dev; |
1022 | dev->irq = irq->start; | |
c6ffddea | 1023 | dev->base = ioremap(mem->start, resource_size(mem)); |
55c381e4 RK |
1024 | if (!dev->base) { |
1025 | r = -ENOMEM; | |
1026 | goto err_free_mem; | |
1027 | } | |
1028 | ||
010d442c KS |
1029 | platform_set_drvdata(pdev, dev); |
1030 | ||
7c6bd201 MW |
1031 | if (cpu_is_omap7xx()) |
1032 | dev->reg_shift = 1; | |
f38e66e0 SS |
1033 | else if (cpu_is_omap44xx()) |
1034 | dev->reg_shift = 0; | |
7c6bd201 MW |
1035 | else |
1036 | dev->reg_shift = 2; | |
1037 | ||
a1295577 AG |
1038 | if (pdata->rev == OMAP_I2C_IP_VERSION_2) |
1039 | dev->regs = (u8 *)reg_map_ip_v2; | |
f38e66e0 | 1040 | else |
a1295577 | 1041 | dev->regs = (u8 *)reg_map_ip_v1; |
f38e66e0 | 1042 | |
27b1fec2 | 1043 | pm_runtime_enable(&pdev->dev); |
f08ac4e7 | 1044 | omap_i2c_unidle(dev); |
010d442c | 1045 | |
9c76b878 | 1046 | dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff; |
010d442c | 1047 | |
8a9d97d3 | 1048 | if (dev->rev <= OMAP_I2C_REV_ON_3430) |
1049 | dev->errata |= I2C_OMAP3_1P153; | |
1050 | ||
f38e66e0 | 1051 | if (!(cpu_class_is_omap1() || cpu_is_omap2420())) { |
b6ee52c3 NM |
1052 | u16 s; |
1053 | ||
1054 | /* Set up the fifo size - Get total size */ | |
1055 | s = (omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3; | |
1056 | dev->fifo_size = 0x8 << s; | |
1057 | ||
1058 | /* | |
1059 | * Set up notification threshold as half the total available | |
1060 | * size. This is to ensure that we can handle the status on int | |
1061 | * call back latencies. | |
1062 | */ | |
f38e66e0 SS |
1063 | if (dev->rev >= OMAP_I2C_REV_ON_4430) { |
1064 | dev->fifo_size = 0; | |
1065 | dev->b_hw = 0; /* Disable hardware fixes */ | |
1066 | } else { | |
1067 | dev->fifo_size = (dev->fifo_size / 2); | |
1068 | dev->b_hw = 1; /* Enable hardware fixes */ | |
1069 | } | |
20c9d2c4 KJ |
1070 | /* calculate wakeup latency constraint for MPU */ |
1071 | if (dev->set_mpu_wkup_lat != NULL) | |
1072 | dev->latency = (1000000 * dev->fifo_size) / | |
1073 | (1000 * speed / 8); | |
b6ee52c3 NM |
1074 | } |
1075 | ||
010d442c KS |
1076 | /* reset ASAP, clearing any IRQs */ |
1077 | omap_i2c_init(dev); | |
1078 | ||
9c76b878 PW |
1079 | isr = (dev->rev < OMAP_I2C_REV_2) ? omap_i2c_rev1_isr : omap_i2c_isr; |
1080 | r = request_irq(dev->irq, isr, 0, pdev->name, dev); | |
010d442c KS |
1081 | |
1082 | if (r) { | |
1083 | dev_err(dev->dev, "failure requesting irq %i\n", dev->irq); | |
1084 | goto err_unuse_clocks; | |
1085 | } | |
9c76b878 | 1086 | |
010d442c | 1087 | dev_info(dev->dev, "bus %d rev%d.%d at %d kHz\n", |
9c76b878 | 1088 | pdev->id, dev->rev >> 4, dev->rev & 0xf, dev->speed); |
010d442c | 1089 | |
3831f154 PW |
1090 | omap_i2c_idle(dev); |
1091 | ||
010d442c KS |
1092 | adap = &dev->adapter; |
1093 | i2c_set_adapdata(adap, dev); | |
1094 | adap->owner = THIS_MODULE; | |
1095 | adap->class = I2C_CLASS_HWMON; | |
783fd6fa | 1096 | strlcpy(adap->name, "OMAP I2C adapter", sizeof(adap->name)); |
010d442c KS |
1097 | adap->algo = &omap_i2c_algo; |
1098 | adap->dev.parent = &pdev->dev; | |
1099 | ||
1100 | /* i2c device drivers may be active on return from add_adapter() */ | |
7c175499 DB |
1101 | adap->nr = pdev->id; |
1102 | r = i2c_add_numbered_adapter(adap); | |
010d442c KS |
1103 | if (r) { |
1104 | dev_err(dev->dev, "failure adding adapter\n"); | |
1105 | goto err_free_irq; | |
1106 | } | |
1107 | ||
010d442c KS |
1108 | return 0; |
1109 | ||
1110 | err_free_irq: | |
1111 | free_irq(dev->irq, dev); | |
1112 | err_unuse_clocks: | |
3e39752d | 1113 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0); |
f08ac4e7 | 1114 | omap_i2c_idle(dev); |
55c381e4 | 1115 | iounmap(dev->base); |
010d442c KS |
1116 | err_free_mem: |
1117 | platform_set_drvdata(pdev, NULL); | |
1118 | kfree(dev); | |
1119 | err_release_region: | |
59330825 | 1120 | release_mem_region(mem->start, resource_size(mem)); |
010d442c KS |
1121 | |
1122 | return r; | |
1123 | } | |
1124 | ||
1125 | static int | |
1126 | omap_i2c_remove(struct platform_device *pdev) | |
1127 | { | |
1128 | struct omap_i2c_dev *dev = platform_get_drvdata(pdev); | |
1129 | struct resource *mem; | |
1130 | ||
1131 | platform_set_drvdata(pdev, NULL); | |
1132 | ||
1133 | free_irq(dev->irq, dev); | |
1134 | i2c_del_adapter(&dev->adapter); | |
1135 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0); | |
55c381e4 | 1136 | iounmap(dev->base); |
010d442c KS |
1137 | kfree(dev); |
1138 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
59330825 | 1139 | release_mem_region(mem->start, resource_size(mem)); |
010d442c KS |
1140 | return 0; |
1141 | } | |
1142 | ||
1143 | static struct platform_driver omap_i2c_driver = { | |
1144 | .probe = omap_i2c_probe, | |
1145 | .remove = omap_i2c_remove, | |
1146 | .driver = { | |
f7bb0d9a | 1147 | .name = "omap_i2c", |
010d442c KS |
1148 | .owner = THIS_MODULE, |
1149 | }, | |
1150 | }; | |
1151 | ||
1152 | /* I2C may be needed to bring up other drivers */ | |
1153 | static int __init | |
1154 | omap_i2c_init_driver(void) | |
1155 | { | |
1156 | return platform_driver_register(&omap_i2c_driver); | |
1157 | } | |
1158 | subsys_initcall(omap_i2c_init_driver); | |
1159 | ||
1160 | static void __exit omap_i2c_exit_driver(void) | |
1161 | { | |
1162 | platform_driver_unregister(&omap_i2c_driver); | |
1163 | } | |
1164 | module_exit(omap_i2c_exit_driver); | |
1165 | ||
1166 | MODULE_AUTHOR("MontaVista Software, Inc. (and others)"); | |
1167 | MODULE_DESCRIPTION("TI OMAP I2C bus adapter"); | |
1168 | MODULE_LICENSE("GPL"); | |
f7bb0d9a | 1169 | MODULE_ALIAS("platform:omap_i2c"); |