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010d442c KS |
1 | /* |
2 | * TI OMAP I2C master mode driver | |
3 | * | |
4 | * Copyright (C) 2003 MontaVista Software, Inc. | |
010d442c | 5 | * Copyright (C) 2005 Nokia Corporation |
c1a473bd | 6 | * Copyright (C) 2004 - 2007 Texas Instruments. |
010d442c | 7 | * |
c1a473bd TL |
8 | * Originally written by MontaVista Software, Inc. |
9 | * Additional contributions by: | |
10 | * Tony Lindgren <tony@atomide.com> | |
11 | * Imre Deak <imre.deak@nokia.com> | |
12 | * Juha Yrjölä <juha.yrjola@solidboot.com> | |
13 | * Syed Khasim <x0khasim@ti.com> | |
14 | * Nishant Menon <nm@ti.com> | |
010d442c KS |
15 | * |
16 | * This program is free software; you can redistribute it and/or modify | |
17 | * it under the terms of the GNU General Public License as published by | |
18 | * the Free Software Foundation; either version 2 of the License, or | |
19 | * (at your option) any later version. | |
20 | * | |
21 | * This program is distributed in the hope that it will be useful, | |
22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
24 | * GNU General Public License for more details. | |
25 | * | |
26 | * You should have received a copy of the GNU General Public License | |
27 | * along with this program; if not, write to the Free Software | |
28 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
29 | */ | |
30 | ||
31 | #include <linux/module.h> | |
32 | #include <linux/delay.h> | |
33 | #include <linux/i2c.h> | |
34 | #include <linux/err.h> | |
35 | #include <linux/interrupt.h> | |
36 | #include <linux/completion.h> | |
37 | #include <linux/platform_device.h> | |
38 | #include <linux/clk.h> | |
c1a473bd | 39 | #include <linux/io.h> |
6145197b BC |
40 | #include <linux/of.h> |
41 | #include <linux/of_i2c.h> | |
42 | #include <linux/of_device.h> | |
5a0e3ad6 | 43 | #include <linux/slab.h> |
20c9d2c4 | 44 | #include <linux/i2c-omap.h> |
27b1fec2 | 45 | #include <linux/pm_runtime.h> |
2d4b4520 | 46 | #include <linux/pinctrl/consumer.h> |
010d442c | 47 | |
9c76b878 | 48 | /* I2C controller revisions */ |
4e80f727 | 49 | #define OMAP_I2C_OMAP1_REV_2 0x20 |
9c76b878 PW |
50 | |
51 | /* I2C controller revisions present on specific hardware */ | |
47dcd016 S |
52 | #define OMAP_I2C_REV_ON_2430 0x00000036 |
53 | #define OMAP_I2C_REV_ON_3430_3530 0x0000003C | |
54 | #define OMAP_I2C_REV_ON_3630 0x00000040 | |
55 | #define OMAP_I2C_REV_ON_4430_PLUS 0x50400002 | |
9c76b878 | 56 | |
010d442c KS |
57 | /* timeout waiting for the controller to respond */ |
58 | #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000)) | |
59 | ||
6d8451d5 FB |
60 | /* timeout for pm runtime autosuspend */ |
61 | #define OMAP_I2C_PM_TIMEOUT 1000 /* ms */ | |
62 | ||
5043e9e7 | 63 | /* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */ |
f38e66e0 SS |
64 | enum { |
65 | OMAP_I2C_REV_REG = 0, | |
66 | OMAP_I2C_IE_REG, | |
67 | OMAP_I2C_STAT_REG, | |
68 | OMAP_I2C_IV_REG, | |
69 | OMAP_I2C_WE_REG, | |
70 | OMAP_I2C_SYSS_REG, | |
71 | OMAP_I2C_BUF_REG, | |
72 | OMAP_I2C_CNT_REG, | |
73 | OMAP_I2C_DATA_REG, | |
74 | OMAP_I2C_SYSC_REG, | |
75 | OMAP_I2C_CON_REG, | |
76 | OMAP_I2C_OA_REG, | |
77 | OMAP_I2C_SA_REG, | |
78 | OMAP_I2C_PSC_REG, | |
79 | OMAP_I2C_SCLL_REG, | |
80 | OMAP_I2C_SCLH_REG, | |
81 | OMAP_I2C_SYSTEST_REG, | |
82 | OMAP_I2C_BUFSTAT_REG, | |
b8853088 AG |
83 | /* only on OMAP4430 */ |
84 | OMAP_I2C_IP_V2_REVNB_LO, | |
85 | OMAP_I2C_IP_V2_REVNB_HI, | |
86 | OMAP_I2C_IP_V2_IRQSTATUS_RAW, | |
87 | OMAP_I2C_IP_V2_IRQENABLE_SET, | |
88 | OMAP_I2C_IP_V2_IRQENABLE_CLR, | |
f38e66e0 | 89 | }; |
010d442c KS |
90 | |
91 | /* I2C Interrupt Enable Register (OMAP_I2C_IE): */ | |
b6ee52c3 NM |
92 | #define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */ |
93 | #define OMAP_I2C_IE_RDR (1 << 13) /* RX Buffer drain int enable */ | |
010d442c KS |
94 | #define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */ |
95 | #define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */ | |
96 | #define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */ | |
97 | #define OMAP_I2C_IE_NACK (1 << 1) /* No ack interrupt enable */ | |
98 | #define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */ | |
99 | ||
100 | /* I2C Status Register (OMAP_I2C_STAT): */ | |
b6ee52c3 NM |
101 | #define OMAP_I2C_STAT_XDR (1 << 14) /* TX Buffer draining */ |
102 | #define OMAP_I2C_STAT_RDR (1 << 13) /* RX Buffer draining */ | |
010d442c KS |
103 | #define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */ |
104 | #define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */ | |
105 | #define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ | |
106 | #define OMAP_I2C_STAT_AAS (1 << 9) /* Address as slave */ | |
107 | #define OMAP_I2C_STAT_AD0 (1 << 8) /* Address zero */ | |
108 | #define OMAP_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ | |
109 | #define OMAP_I2C_STAT_RRDY (1 << 3) /* Receive data ready */ | |
110 | #define OMAP_I2C_STAT_ARDY (1 << 2) /* Register access ready */ | |
111 | #define OMAP_I2C_STAT_NACK (1 << 1) /* No ack interrupt enable */ | |
112 | #define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost int ena */ | |
113 | ||
5043e9e7 KJ |
114 | /* I2C WE wakeup enable register */ |
115 | #define OMAP_I2C_WE_XDR_WE (1 << 14) /* TX drain wakup */ | |
116 | #define OMAP_I2C_WE_RDR_WE (1 << 13) /* RX drain wakeup */ | |
117 | #define OMAP_I2C_WE_AAS_WE (1 << 9) /* Address as slave wakeup*/ | |
118 | #define OMAP_I2C_WE_BF_WE (1 << 8) /* Bus free wakeup */ | |
119 | #define OMAP_I2C_WE_STC_WE (1 << 6) /* Start condition wakeup */ | |
120 | #define OMAP_I2C_WE_GC_WE (1 << 5) /* General call wakeup */ | |
121 | #define OMAP_I2C_WE_DRDY_WE (1 << 3) /* TX/RX data ready wakeup */ | |
122 | #define OMAP_I2C_WE_ARDY_WE (1 << 2) /* Reg access ready wakeup */ | |
123 | #define OMAP_I2C_WE_NACK_WE (1 << 1) /* No acknowledgment wakeup */ | |
124 | #define OMAP_I2C_WE_AL_WE (1 << 0) /* Arbitration lost wakeup */ | |
125 | ||
126 | #define OMAP_I2C_WE_ALL (OMAP_I2C_WE_XDR_WE | OMAP_I2C_WE_RDR_WE | \ | |
127 | OMAP_I2C_WE_AAS_WE | OMAP_I2C_WE_BF_WE | \ | |
128 | OMAP_I2C_WE_STC_WE | OMAP_I2C_WE_GC_WE | \ | |
129 | OMAP_I2C_WE_DRDY_WE | OMAP_I2C_WE_ARDY_WE | \ | |
130 | OMAP_I2C_WE_NACK_WE | OMAP_I2C_WE_AL_WE) | |
131 | ||
010d442c KS |
132 | /* I2C Buffer Configuration Register (OMAP_I2C_BUF): */ |
133 | #define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */ | |
b6ee52c3 | 134 | #define OMAP_I2C_BUF_RXFIF_CLR (1 << 14) /* RX FIFO Clear */ |
010d442c | 135 | #define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */ |
b6ee52c3 | 136 | #define OMAP_I2C_BUF_TXFIF_CLR (1 << 6) /* TX FIFO Clear */ |
010d442c KS |
137 | |
138 | /* I2C Configuration Register (OMAP_I2C_CON): */ | |
139 | #define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */ | |
140 | #define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */ | |
b6ee52c3 | 141 | #define OMAP_I2C_CON_OPMODE_HS (1 << 12) /* High Speed support */ |
010d442c KS |
142 | #define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */ |
143 | #define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */ | |
144 | #define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */ | |
145 | #define OMAP_I2C_CON_XA (1 << 8) /* Expand address */ | |
146 | #define OMAP_I2C_CON_RM (1 << 2) /* Repeat mode (master only) */ | |
147 | #define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */ | |
148 | #define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */ | |
149 | ||
4574eb68 SMK |
150 | /* I2C SCL time value when Master */ |
151 | #define OMAP_I2C_SCLL_HSSCLL 8 | |
152 | #define OMAP_I2C_SCLH_HSSCLH 8 | |
153 | ||
010d442c KS |
154 | /* I2C System Test Register (OMAP_I2C_SYSTEST): */ |
155 | #ifdef DEBUG | |
156 | #define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */ | |
157 | #define OMAP_I2C_SYSTEST_FREE (1 << 14) /* Free running mode */ | |
158 | #define OMAP_I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */ | |
159 | #define OMAP_I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */ | |
160 | #define OMAP_I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense in */ | |
161 | #define OMAP_I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive out */ | |
162 | #define OMAP_I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense in */ | |
163 | #define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */ | |
164 | #endif | |
165 | ||
fdd07fe6 PW |
166 | /* OCP_SYSSTATUS bit definitions */ |
167 | #define SYSS_RESETDONE_MASK (1 << 0) | |
168 | ||
169 | /* OCP_SYSCONFIG bit definitions */ | |
170 | #define SYSC_CLOCKACTIVITY_MASK (0x3 << 8) | |
171 | #define SYSC_SIDLEMODE_MASK (0x3 << 3) | |
172 | #define SYSC_ENAWAKEUP_MASK (1 << 2) | |
173 | #define SYSC_SOFTRESET_MASK (1 << 1) | |
174 | #define SYSC_AUTOIDLE_MASK (1 << 0) | |
175 | ||
176 | #define SYSC_IDLEMODE_SMART 0x2 | |
177 | #define SYSC_CLOCKACTIVITY_FCLK 0x2 | |
010d442c | 178 | |
f3083d92 | 179 | /* Errata definitions */ |
180 | #define I2C_OMAP_ERRATA_I207 (1 << 0) | |
c8db38f0 | 181 | #define I2C_OMAP_ERRATA_I462 (1 << 1) |
010d442c | 182 | |
010d442c | 183 | struct omap_i2c_dev { |
3b2f8f82 | 184 | spinlock_t lock; /* IRQ synchronization */ |
010d442c KS |
185 | struct device *dev; |
186 | void __iomem *base; /* virtual */ | |
187 | int irq; | |
d84d3ea3 | 188 | int reg_shift; /* bit shift for I2C register addresses */ |
010d442c KS |
189 | struct completion cmd_complete; |
190 | struct resource *ioarea; | |
49839dc9 PW |
191 | u32 latency; /* maximum mpu wkup latency */ |
192 | void (*set_mpu_wkup_lat)(struct device *dev, | |
193 | long latency); | |
6145197b | 194 | u32 speed; /* Speed of bus in kHz */ |
6145197b | 195 | u32 flags; |
010d442c KS |
196 | u16 cmd_err; |
197 | u8 *buf; | |
f38e66e0 | 198 | u8 *regs; |
010d442c KS |
199 | size_t buf_len; |
200 | struct i2c_adapter adapter; | |
dd74548d | 201 | u8 threshold; |
b6ee52c3 NM |
202 | u8 fifo_size; /* use as flag and value |
203 | * fifo_size==0 implies no fifo | |
204 | * if set, should be trsh+1 | |
205 | */ | |
47dcd016 | 206 | u32 rev; |
b6ee52c3 | 207 | unsigned b_hw:1; /* bad h/w fixes */ |
079d8af2 | 208 | unsigned receiver:1; /* true when we're in receiver mode */ |
f08ac4e7 | 209 | u16 iestate; /* Saved interrupt register */ |
ef871432 RN |
210 | u16 pscstate; |
211 | u16 scllstate; | |
212 | u16 sclhstate; | |
ef871432 RN |
213 | u16 syscstate; |
214 | u16 westate; | |
f3083d92 | 215 | u16 errata; |
2d4b4520 SG |
216 | |
217 | struct pinctrl *pins; | |
010d442c KS |
218 | }; |
219 | ||
a1295577 | 220 | static const u8 reg_map_ip_v1[] = { |
f38e66e0 SS |
221 | [OMAP_I2C_REV_REG] = 0x00, |
222 | [OMAP_I2C_IE_REG] = 0x01, | |
223 | [OMAP_I2C_STAT_REG] = 0x02, | |
224 | [OMAP_I2C_IV_REG] = 0x03, | |
225 | [OMAP_I2C_WE_REG] = 0x03, | |
226 | [OMAP_I2C_SYSS_REG] = 0x04, | |
227 | [OMAP_I2C_BUF_REG] = 0x05, | |
228 | [OMAP_I2C_CNT_REG] = 0x06, | |
229 | [OMAP_I2C_DATA_REG] = 0x07, | |
230 | [OMAP_I2C_SYSC_REG] = 0x08, | |
231 | [OMAP_I2C_CON_REG] = 0x09, | |
232 | [OMAP_I2C_OA_REG] = 0x0a, | |
233 | [OMAP_I2C_SA_REG] = 0x0b, | |
234 | [OMAP_I2C_PSC_REG] = 0x0c, | |
235 | [OMAP_I2C_SCLL_REG] = 0x0d, | |
236 | [OMAP_I2C_SCLH_REG] = 0x0e, | |
237 | [OMAP_I2C_SYSTEST_REG] = 0x0f, | |
238 | [OMAP_I2C_BUFSTAT_REG] = 0x10, | |
239 | }; | |
240 | ||
a1295577 | 241 | static const u8 reg_map_ip_v2[] = { |
f38e66e0 SS |
242 | [OMAP_I2C_REV_REG] = 0x04, |
243 | [OMAP_I2C_IE_REG] = 0x2c, | |
244 | [OMAP_I2C_STAT_REG] = 0x28, | |
245 | [OMAP_I2C_IV_REG] = 0x34, | |
246 | [OMAP_I2C_WE_REG] = 0x34, | |
247 | [OMAP_I2C_SYSS_REG] = 0x90, | |
248 | [OMAP_I2C_BUF_REG] = 0x94, | |
249 | [OMAP_I2C_CNT_REG] = 0x98, | |
250 | [OMAP_I2C_DATA_REG] = 0x9c, | |
2727b175 | 251 | [OMAP_I2C_SYSC_REG] = 0x10, |
f38e66e0 SS |
252 | [OMAP_I2C_CON_REG] = 0xa4, |
253 | [OMAP_I2C_OA_REG] = 0xa8, | |
254 | [OMAP_I2C_SA_REG] = 0xac, | |
255 | [OMAP_I2C_PSC_REG] = 0xb0, | |
256 | [OMAP_I2C_SCLL_REG] = 0xb4, | |
257 | [OMAP_I2C_SCLH_REG] = 0xb8, | |
258 | [OMAP_I2C_SYSTEST_REG] = 0xbC, | |
259 | [OMAP_I2C_BUFSTAT_REG] = 0xc0, | |
b8853088 AG |
260 | [OMAP_I2C_IP_V2_REVNB_LO] = 0x00, |
261 | [OMAP_I2C_IP_V2_REVNB_HI] = 0x04, | |
262 | [OMAP_I2C_IP_V2_IRQSTATUS_RAW] = 0x24, | |
263 | [OMAP_I2C_IP_V2_IRQENABLE_SET] = 0x2c, | |
264 | [OMAP_I2C_IP_V2_IRQENABLE_CLR] = 0x30, | |
f38e66e0 SS |
265 | }; |
266 | ||
010d442c KS |
267 | static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev, |
268 | int reg, u16 val) | |
269 | { | |
f38e66e0 SS |
270 | __raw_writew(val, i2c_dev->base + |
271 | (i2c_dev->regs[reg] << i2c_dev->reg_shift)); | |
010d442c KS |
272 | } |
273 | ||
274 | static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg) | |
275 | { | |
f38e66e0 SS |
276 | return __raw_readw(i2c_dev->base + |
277 | (i2c_dev->regs[reg] << i2c_dev->reg_shift)); | |
010d442c KS |
278 | } |
279 | ||
95dd3032 S |
280 | static void __omap_i2c_init(struct omap_i2c_dev *dev) |
281 | { | |
282 | ||
283 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0); | |
284 | ||
285 | /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */ | |
286 | omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, dev->pscstate); | |
287 | ||
288 | /* SCL low and high time values */ | |
289 | omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, dev->scllstate); | |
290 | omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, dev->sclhstate); | |
291 | if (dev->rev >= OMAP_I2C_REV_ON_3430_3530) | |
292 | omap_i2c_write_reg(dev, OMAP_I2C_WE_REG, dev->westate); | |
293 | ||
294 | /* Take the I2C module out of reset: */ | |
295 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN); | |
296 | ||
297 | /* | |
298 | * Don't write to this register if the IE state is 0 as it can | |
299 | * cause deadlock. | |
300 | */ | |
301 | if (dev->iestate) | |
302 | omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate); | |
303 | } | |
304 | ||
d6c842ad | 305 | static int omap_i2c_reset(struct omap_i2c_dev *dev) |
010d442c | 306 | { |
010d442c | 307 | unsigned long timeout; |
ca85e248 S |
308 | u16 sysc; |
309 | ||
4e80f727 | 310 | if (dev->rev >= OMAP_I2C_OMAP1_REV_2) { |
ca85e248 S |
311 | sysc = omap_i2c_read_reg(dev, OMAP_I2C_SYSC_REG); |
312 | ||
57eb81b1 MG |
313 | /* Disable I2C controller before soft reset */ |
314 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, | |
315 | omap_i2c_read_reg(dev, OMAP_I2C_CON_REG) & | |
316 | ~(OMAP_I2C_CON_EN)); | |
317 | ||
fdd07fe6 | 318 | omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK); |
010d442c KS |
319 | /* For some reason we need to set the EN bit before the |
320 | * reset done bit gets set. */ | |
321 | timeout = jiffies + OMAP_I2C_TIMEOUT; | |
322 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN); | |
323 | while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) & | |
fdd07fe6 | 324 | SYSS_RESETDONE_MASK)) { |
010d442c | 325 | if (time_after(jiffies, timeout)) { |
fce3ff03 | 326 | dev_warn(dev->dev, "timeout waiting " |
010d442c KS |
327 | "for controller reset\n"); |
328 | return -ETIMEDOUT; | |
329 | } | |
330 | msleep(1); | |
331 | } | |
fdd07fe6 PW |
332 | |
333 | /* SYSC register is cleared by the reset; rewrite it */ | |
ca85e248 | 334 | omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, sysc); |
fdd07fe6 | 335 | |
010d442c | 336 | } |
d6c842ad S |
337 | return 0; |
338 | } | |
339 | ||
340 | static int omap_i2c_init(struct omap_i2c_dev *dev) | |
341 | { | |
342 | u16 psc = 0, scll = 0, sclh = 0; | |
343 | u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0; | |
344 | unsigned long fclk_rate = 12000000; | |
345 | unsigned long internal_clk = 0; | |
346 | struct clk *fclk; | |
347 | ||
348 | if (dev->rev >= OMAP_I2C_REV_ON_3430_3530) { | |
349 | /* | |
350 | * Enabling all wakup sources to stop I2C freezing on | |
351 | * WFI instruction. | |
352 | * REVISIT: Some wkup sources might not be needed. | |
353 | */ | |
354 | dev->westate = OMAP_I2C_WE_ALL; | |
355 | } | |
010d442c | 356 | |
6145197b | 357 | if (dev->flags & OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK) { |
0e9ae109 RK |
358 | /* |
359 | * The I2C functional clock is the armxor_ck, so there's | |
360 | * no need to get "armxor_ck" separately. Now, if OMAP2420 | |
361 | * always returns 12MHz for the functional clock, we can | |
362 | * do this bit unconditionally. | |
363 | */ | |
27b1fec2 RN |
364 | fclk = clk_get(dev->dev, "fck"); |
365 | fclk_rate = clk_get_rate(fclk); | |
366 | clk_put(fclk); | |
0e9ae109 | 367 | |
010d442c KS |
368 | /* TRM for 5912 says the I2C clock must be prescaled to be |
369 | * between 7 - 12 MHz. The XOR input clock is typically | |
370 | * 12, 13 or 19.2 MHz. So we should have code that produces: | |
371 | * | |
372 | * XOR MHz Divider Prescaler | |
373 | * 12 1 0 | |
374 | * 13 2 1 | |
375 | * 19.2 2 1 | |
376 | */ | |
d7aef138 JD |
377 | if (fclk_rate > 12000000) |
378 | psc = fclk_rate / 12000000; | |
010d442c KS |
379 | } |
380 | ||
6145197b | 381 | if (!(dev->flags & OMAP_I2C_FLAG_SIMPLE_CLOCK)) { |
4574eb68 | 382 | |
84bf2c86 AK |
383 | /* |
384 | * HSI2C controller internal clk rate should be 19.2 Mhz for | |
385 | * HS and for all modes on 2430. On 34xx we can use lower rate | |
386 | * to get longer filter period for better noise suppression. | |
387 | * The filter is iclk (fclk for HS) period. | |
388 | */ | |
3be0053e | 389 | if (dev->speed > 400 || |
6145197b | 390 | dev->flags & OMAP_I2C_FLAG_FORCE_19200_INT_CLK) |
84bf2c86 AK |
391 | internal_clk = 19200; |
392 | else if (dev->speed > 100) | |
393 | internal_clk = 9600; | |
394 | else | |
395 | internal_clk = 4000; | |
27b1fec2 RN |
396 | fclk = clk_get(dev->dev, "fck"); |
397 | fclk_rate = clk_get_rate(fclk) / 1000; | |
398 | clk_put(fclk); | |
4574eb68 SMK |
399 | |
400 | /* Compute prescaler divisor */ | |
401 | psc = fclk_rate / internal_clk; | |
402 | psc = psc - 1; | |
403 | ||
404 | /* If configured for High Speed */ | |
405 | if (dev->speed > 400) { | |
baf46b4e AK |
406 | unsigned long scl; |
407 | ||
4574eb68 | 408 | /* For first phase of HS mode */ |
baf46b4e AK |
409 | scl = internal_clk / 400; |
410 | fsscll = scl - (scl / 3) - 7; | |
411 | fssclh = (scl / 3) - 5; | |
4574eb68 SMK |
412 | |
413 | /* For second phase of HS mode */ | |
baf46b4e AK |
414 | scl = fclk_rate / dev->speed; |
415 | hsscll = scl - (scl / 3) - 7; | |
416 | hssclh = (scl / 3) - 5; | |
417 | } else if (dev->speed > 100) { | |
418 | unsigned long scl; | |
419 | ||
420 | /* Fast mode */ | |
421 | scl = internal_clk / dev->speed; | |
422 | fsscll = scl - (scl / 3) - 7; | |
423 | fssclh = (scl / 3) - 5; | |
4574eb68 | 424 | } else { |
baf46b4e AK |
425 | /* Standard mode */ |
426 | fsscll = internal_clk / (dev->speed * 2) - 7; | |
427 | fssclh = internal_clk / (dev->speed * 2) - 5; | |
4574eb68 SMK |
428 | } |
429 | scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll; | |
430 | sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh; | |
431 | } else { | |
432 | /* Program desired operating rate */ | |
433 | fclk_rate /= (psc + 1) * 1000; | |
434 | if (psc > 2) | |
435 | psc = 2; | |
436 | scll = fclk_rate / (dev->speed * 2) - 7 + psc; | |
437 | sclh = fclk_rate / (dev->speed * 2) - 7 + psc; | |
438 | } | |
439 | ||
ef871432 | 440 | dev->iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY | |
c1a473bd TL |
441 | OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK | |
442 | OMAP_I2C_IE_AL) | ((dev->fifo_size) ? | |
ef871432 | 443 | (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0); |
95dd3032 S |
444 | |
445 | dev->pscstate = psc; | |
446 | dev->scllstate = scll; | |
447 | dev->sclhstate = sclh; | |
448 | ||
449 | __omap_i2c_init(dev); | |
450 | ||
010d442c KS |
451 | return 0; |
452 | } | |
453 | ||
454 | /* | |
455 | * Waiting on Bus Busy | |
456 | */ | |
457 | static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev) | |
458 | { | |
459 | unsigned long timeout; | |
460 | ||
461 | timeout = jiffies + OMAP_I2C_TIMEOUT; | |
462 | while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) { | |
463 | if (time_after(jiffies, timeout)) { | |
464 | dev_warn(dev->dev, "timeout waiting for bus ready\n"); | |
465 | return -ETIMEDOUT; | |
466 | } | |
467 | msleep(1); | |
468 | } | |
469 | ||
470 | return 0; | |
471 | } | |
472 | ||
dd74548d FB |
473 | static void omap_i2c_resize_fifo(struct omap_i2c_dev *dev, u8 size, bool is_rx) |
474 | { | |
475 | u16 buf; | |
476 | ||
477 | if (dev->flags & OMAP_I2C_FLAG_NO_FIFO) | |
478 | return; | |
479 | ||
480 | /* | |
481 | * Set up notification threshold based on message size. We're doing | |
482 | * this to try and avoid draining feature as much as possible. Whenever | |
483 | * we have big messages to transfer (bigger than our total fifo size) | |
484 | * then we might use draining feature to transfer the remaining bytes. | |
485 | */ | |
486 | ||
487 | dev->threshold = clamp(size, (u8) 1, dev->fifo_size); | |
488 | ||
489 | buf = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG); | |
490 | ||
491 | if (is_rx) { | |
492 | /* Clear RX Threshold */ | |
493 | buf &= ~(0x3f << 8); | |
494 | buf |= ((dev->threshold - 1) << 8) | OMAP_I2C_BUF_RXFIF_CLR; | |
495 | } else { | |
496 | /* Clear TX Threshold */ | |
497 | buf &= ~0x3f; | |
498 | buf |= (dev->threshold - 1) | OMAP_I2C_BUF_TXFIF_CLR; | |
499 | } | |
500 | ||
501 | omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, buf); | |
502 | ||
47dcd016 | 503 | if (dev->rev < OMAP_I2C_REV_ON_3630) |
dd74548d FB |
504 | dev->b_hw = 1; /* Enable hardware fixes */ |
505 | ||
506 | /* calculate wakeup latency constraint for MPU */ | |
49839dc9 PW |
507 | if (dev->set_mpu_wkup_lat != NULL) |
508 | dev->latency = (1000000 * dev->threshold) / | |
509 | (1000 * dev->speed / 8); | |
dd74548d FB |
510 | } |
511 | ||
010d442c KS |
512 | /* |
513 | * Low level master read/write transaction. | |
514 | */ | |
515 | static int omap_i2c_xfer_msg(struct i2c_adapter *adap, | |
516 | struct i2c_msg *msg, int stop) | |
517 | { | |
518 | struct omap_i2c_dev *dev = i2c_get_adapdata(adap); | |
33d54985 | 519 | unsigned long timeout; |
010d442c KS |
520 | u16 w; |
521 | ||
522 | dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n", | |
523 | msg->addr, msg->len, msg->flags, stop); | |
524 | ||
525 | if (msg->len == 0) | |
526 | return -EINVAL; | |
527 | ||
dd74548d FB |
528 | dev->receiver = !!(msg->flags & I2C_M_RD); |
529 | omap_i2c_resize_fifo(dev, msg->len, dev->receiver); | |
530 | ||
010d442c KS |
531 | omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr); |
532 | ||
533 | /* REVISIT: Could the STB bit of I2C_CON be used with probing? */ | |
534 | dev->buf = msg->buf; | |
535 | dev->buf_len = msg->len; | |
536 | ||
d60ece5f FB |
537 | /* make sure writes to dev->buf_len are ordered */ |
538 | barrier(); | |
539 | ||
010d442c KS |
540 | omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len); |
541 | ||
b6ee52c3 NM |
542 | /* Clear the FIFO Buffers */ |
543 | w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG); | |
544 | w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR; | |
545 | omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w); | |
546 | ||
0e33bbb2 | 547 | INIT_COMPLETION(dev->cmd_complete); |
010d442c KS |
548 | dev->cmd_err = 0; |
549 | ||
550 | w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT; | |
4574eb68 SMK |
551 | |
552 | /* High speed configuration */ | |
553 | if (dev->speed > 400) | |
b6ee52c3 | 554 | w |= OMAP_I2C_CON_OPMODE_HS; |
4574eb68 | 555 | |
fb604a3d LP |
556 | if (msg->flags & I2C_M_STOP) |
557 | stop = 1; | |
010d442c KS |
558 | if (msg->flags & I2C_M_TEN) |
559 | w |= OMAP_I2C_CON_XA; | |
560 | if (!(msg->flags & I2C_M_RD)) | |
561 | w |= OMAP_I2C_CON_TRX; | |
c1a473bd | 562 | |
b6ee52c3 | 563 | if (!dev->b_hw && stop) |
010d442c | 564 | w |= OMAP_I2C_CON_STP; |
c1a473bd | 565 | |
010d442c KS |
566 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w); |
567 | ||
b6ee52c3 NM |
568 | /* |
569 | * Don't write stt and stp together on some hardware. | |
570 | */ | |
571 | if (dev->b_hw && stop) { | |
572 | unsigned long delay = jiffies + OMAP_I2C_TIMEOUT; | |
573 | u16 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG); | |
574 | while (con & OMAP_I2C_CON_STT) { | |
575 | con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG); | |
576 | ||
577 | /* Let the user know if i2c is in a bad state */ | |
578 | if (time_after(jiffies, delay)) { | |
579 | dev_err(dev->dev, "controller timed out " | |
580 | "waiting for start condition to finish\n"); | |
581 | return -ETIMEDOUT; | |
582 | } | |
583 | cpu_relax(); | |
584 | } | |
585 | ||
586 | w |= OMAP_I2C_CON_STP; | |
587 | w &= ~OMAP_I2C_CON_STT; | |
588 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w); | |
589 | } | |
590 | ||
b7af349b JN |
591 | /* |
592 | * REVISIT: We should abort the transfer on signals, but the bus goes | |
593 | * into arbitration and we're currently unable to recover from it. | |
594 | */ | |
33d54985 S |
595 | timeout = wait_for_completion_timeout(&dev->cmd_complete, |
596 | OMAP_I2C_TIMEOUT); | |
33d54985 | 597 | if (timeout == 0) { |
010d442c | 598 | dev_err(dev->dev, "controller timed out\n"); |
d6c842ad S |
599 | omap_i2c_reset(dev); |
600 | __omap_i2c_init(dev); | |
010d442c KS |
601 | return -ETIMEDOUT; |
602 | } | |
603 | ||
604 | if (likely(!dev->cmd_err)) | |
605 | return 0; | |
606 | ||
607 | /* We have an error */ | |
608 | if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR | | |
609 | OMAP_I2C_STAT_XUDF)) { | |
d6c842ad S |
610 | omap_i2c_reset(dev); |
611 | __omap_i2c_init(dev); | |
010d442c KS |
612 | return -EIO; |
613 | } | |
614 | ||
615 | if (dev->cmd_err & OMAP_I2C_STAT_NACK) { | |
616 | if (msg->flags & I2C_M_IGNORE_NAK) | |
617 | return 0; | |
618 | if (stop) { | |
619 | w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG); | |
620 | w |= OMAP_I2C_CON_STP; | |
621 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w); | |
622 | } | |
623 | return -EREMOTEIO; | |
624 | } | |
625 | return -EIO; | |
626 | } | |
627 | ||
628 | ||
629 | /* | |
630 | * Prepare controller for a transaction and call omap_i2c_xfer_msg | |
631 | * to do the work during IRQ processing. | |
632 | */ | |
633 | static int | |
634 | omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) | |
635 | { | |
636 | struct omap_i2c_dev *dev = i2c_get_adapdata(adap); | |
637 | int i; | |
638 | int r; | |
639 | ||
3b0fb97c S |
640 | r = pm_runtime_get_sync(dev->dev); |
641 | if (IS_ERR_VALUE(r)) | |
33ec5e81 | 642 | goto out; |
010d442c | 643 | |
c1a473bd TL |
644 | r = omap_i2c_wait_for_bb(dev); |
645 | if (r < 0) | |
010d442c KS |
646 | goto out; |
647 | ||
49839dc9 PW |
648 | if (dev->set_mpu_wkup_lat != NULL) |
649 | dev->set_mpu_wkup_lat(dev->dev, dev->latency); | |
6a91b558 | 650 | |
010d442c KS |
651 | for (i = 0; i < num; i++) { |
652 | r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1))); | |
653 | if (r != 0) | |
654 | break; | |
655 | } | |
656 | ||
657 | if (r == 0) | |
658 | r = num; | |
5c64eb26 MN |
659 | |
660 | omap_i2c_wait_for_bb(dev); | |
1ab36045 S |
661 | |
662 | if (dev->set_mpu_wkup_lat != NULL) | |
663 | dev->set_mpu_wkup_lat(dev->dev, -1); | |
664 | ||
010d442c | 665 | out: |
6d8451d5 FB |
666 | pm_runtime_mark_last_busy(dev->dev); |
667 | pm_runtime_put_autosuspend(dev->dev); | |
010d442c KS |
668 | return r; |
669 | } | |
670 | ||
671 | static u32 | |
672 | omap_i2c_func(struct i2c_adapter *adap) | |
673 | { | |
fb604a3d LP |
674 | return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) | |
675 | I2C_FUNC_PROTOCOL_MANGLING; | |
010d442c KS |
676 | } |
677 | ||
678 | static inline void | |
679 | omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err) | |
680 | { | |
681 | dev->cmd_err |= err; | |
682 | complete(&dev->cmd_complete); | |
683 | } | |
684 | ||
685 | static inline void | |
686 | omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat) | |
687 | { | |
688 | omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat); | |
689 | } | |
690 | ||
f3083d92 | 691 | static inline void i2c_omap_errata_i207(struct omap_i2c_dev *dev, u16 stat) |
692 | { | |
693 | /* | |
694 | * I2C Errata(Errata Nos. OMAP2: 1.67, OMAP3: 1.8) | |
695 | * Not applicable for OMAP4. | |
696 | * Under certain rare conditions, RDR could be set again | |
697 | * when the bus is busy, then ignore the interrupt and | |
698 | * clear the interrupt. | |
699 | */ | |
700 | if (stat & OMAP_I2C_STAT_RDR) { | |
701 | /* Step 1: If RDR is set, clear it */ | |
702 | omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR); | |
703 | ||
704 | /* Step 2: */ | |
705 | if (!(omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) | |
706 | & OMAP_I2C_STAT_BB)) { | |
707 | ||
708 | /* Step 3: */ | |
709 | if (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) | |
710 | & OMAP_I2C_STAT_RDR) { | |
711 | omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR); | |
712 | dev_dbg(dev->dev, "RDR when bus is busy.\n"); | |
713 | } | |
714 | ||
715 | } | |
716 | } | |
717 | } | |
718 | ||
43469d8e PW |
719 | /* rev1 devices are apparently only on some 15xx */ |
720 | #ifdef CONFIG_ARCH_OMAP15XX | |
721 | ||
010d442c | 722 | static irqreturn_t |
4e80f727 | 723 | omap_i2c_omap1_isr(int this_irq, void *dev_id) |
010d442c KS |
724 | { |
725 | struct omap_i2c_dev *dev = dev_id; | |
726 | u16 iv, w; | |
727 | ||
fab67afb | 728 | if (pm_runtime_suspended(dev->dev)) |
f08ac4e7 TL |
729 | return IRQ_NONE; |
730 | ||
010d442c KS |
731 | iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG); |
732 | switch (iv) { | |
733 | case 0x00: /* None */ | |
734 | break; | |
735 | case 0x01: /* Arbitration lost */ | |
736 | dev_err(dev->dev, "Arbitration lost\n"); | |
737 | omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL); | |
738 | break; | |
739 | case 0x02: /* No acknowledgement */ | |
740 | omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK); | |
741 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP); | |
742 | break; | |
743 | case 0x03: /* Register access ready */ | |
744 | omap_i2c_complete_cmd(dev, 0); | |
745 | break; | |
746 | case 0x04: /* Receive data ready */ | |
747 | if (dev->buf_len) { | |
748 | w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG); | |
749 | *dev->buf++ = w; | |
750 | dev->buf_len--; | |
751 | if (dev->buf_len) { | |
752 | *dev->buf++ = w >> 8; | |
753 | dev->buf_len--; | |
754 | } | |
755 | } else | |
756 | dev_err(dev->dev, "RRDY IRQ while no data requested\n"); | |
757 | break; | |
758 | case 0x05: /* Transmit data ready */ | |
759 | if (dev->buf_len) { | |
760 | w = *dev->buf++; | |
761 | dev->buf_len--; | |
762 | if (dev->buf_len) { | |
763 | w |= *dev->buf++ << 8; | |
764 | dev->buf_len--; | |
765 | } | |
766 | omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w); | |
767 | } else | |
768 | dev_err(dev->dev, "XRDY IRQ while no data to send\n"); | |
769 | break; | |
770 | default: | |
771 | return IRQ_NONE; | |
772 | } | |
773 | ||
774 | return IRQ_HANDLED; | |
775 | } | |
43469d8e | 776 | #else |
4e80f727 | 777 | #define omap_i2c_omap1_isr NULL |
43469d8e | 778 | #endif |
010d442c | 779 | |
2dd151ab | 780 | /* |
c8db38f0 | 781 | * OMAP3430 Errata i462: When an XRDY/XDR is hit, wait for XUDF before writing |
2dd151ab AS |
782 | * data to DATA_REG. Otherwise some data bytes can be lost while transferring |
783 | * them from the memory to the I2C interface. | |
784 | */ | |
4151e741 | 785 | static int errata_omap3_i462(struct omap_i2c_dev *dev) |
2dd151ab | 786 | { |
e9f59b9c | 787 | unsigned long timeout = 10000; |
4151e741 | 788 | u16 stat; |
e9f59b9c | 789 | |
4151e741 FB |
790 | do { |
791 | stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG); | |
792 | if (stat & OMAP_I2C_STAT_XUDF) | |
793 | break; | |
794 | ||
795 | if (stat & (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) { | |
540a4790 | 796 | omap_i2c_ack_stat(dev, (OMAP_I2C_STAT_XRDY | |
2dd151ab | 797 | OMAP_I2C_STAT_XDR)); |
b07be0f3 FB |
798 | if (stat & OMAP_I2C_STAT_NACK) { |
799 | dev->cmd_err |= OMAP_I2C_STAT_NACK; | |
800 | omap_i2c_ack_stat(dev, OMAP_I2C_STAT_NACK); | |
801 | } | |
802 | ||
803 | if (stat & OMAP_I2C_STAT_AL) { | |
804 | dev_err(dev->dev, "Arbitration lost\n"); | |
805 | dev->cmd_err |= OMAP_I2C_STAT_AL; | |
2c5de558 | 806 | omap_i2c_ack_stat(dev, OMAP_I2C_STAT_AL); |
b07be0f3 FB |
807 | } |
808 | ||
4151e741 | 809 | return -EIO; |
2dd151ab | 810 | } |
e9f59b9c | 811 | |
2dd151ab | 812 | cpu_relax(); |
4151e741 | 813 | } while (--timeout); |
2dd151ab | 814 | |
e9f59b9c AS |
815 | if (!timeout) { |
816 | dev_err(dev->dev, "timeout waiting on XUDF bit\n"); | |
817 | return 0; | |
818 | } | |
819 | ||
2dd151ab AS |
820 | return 0; |
821 | } | |
822 | ||
3312d25e FB |
823 | static void omap_i2c_receive_data(struct omap_i2c_dev *dev, u8 num_bytes, |
824 | bool is_rdr) | |
825 | { | |
826 | u16 w; | |
827 | ||
828 | while (num_bytes--) { | |
3312d25e FB |
829 | w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG); |
830 | *dev->buf++ = w; | |
831 | dev->buf_len--; | |
832 | ||
833 | /* | |
834 | * Data reg in 2430, omap3 and | |
835 | * omap4 is 8 bit wide | |
836 | */ | |
837 | if (dev->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) { | |
dd74548d FB |
838 | *dev->buf++ = w >> 8; |
839 | dev->buf_len--; | |
3312d25e FB |
840 | } |
841 | } | |
842 | } | |
843 | ||
844 | static int omap_i2c_transmit_data(struct omap_i2c_dev *dev, u8 num_bytes, | |
845 | bool is_xdr) | |
846 | { | |
847 | u16 w; | |
848 | ||
849 | while (num_bytes--) { | |
3312d25e FB |
850 | w = *dev->buf++; |
851 | dev->buf_len--; | |
852 | ||
853 | /* | |
854 | * Data reg in 2430, omap3 and | |
855 | * omap4 is 8 bit wide | |
856 | */ | |
857 | if (dev->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) { | |
dd74548d FB |
858 | w |= *dev->buf++ << 8; |
859 | dev->buf_len--; | |
3312d25e FB |
860 | } |
861 | ||
862 | if (dev->errata & I2C_OMAP_ERRATA_I462) { | |
863 | int ret; | |
864 | ||
865 | ret = errata_omap3_i462(dev); | |
866 | if (ret < 0) | |
867 | return ret; | |
868 | } | |
869 | ||
870 | omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w); | |
871 | } | |
872 | ||
873 | return 0; | |
874 | } | |
875 | ||
010d442c | 876 | static irqreturn_t |
3b2f8f82 | 877 | omap_i2c_isr(int irq, void *dev_id) |
010d442c KS |
878 | { |
879 | struct omap_i2c_dev *dev = dev_id; | |
3b2f8f82 FB |
880 | irqreturn_t ret = IRQ_HANDLED; |
881 | u16 mask; | |
882 | u16 stat; | |
883 | ||
884 | spin_lock(&dev->lock); | |
885 | mask = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG); | |
886 | stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG); | |
887 | ||
888 | if (stat & mask) | |
889 | ret = IRQ_WAKE_THREAD; | |
890 | ||
891 | spin_unlock(&dev->lock); | |
892 | ||
893 | return ret; | |
894 | } | |
895 | ||
010d442c | 896 | static irqreturn_t |
3b2f8f82 | 897 | omap_i2c_isr_thread(int this_irq, void *dev_id) |
010d442c KS |
898 | { |
899 | struct omap_i2c_dev *dev = dev_id; | |
3b2f8f82 | 900 | unsigned long flags; |
010d442c | 901 | u16 bits; |
3312d25e | 902 | u16 stat; |
66b92988 | 903 | int err = 0, count = 0; |
010d442c | 904 | |
3b2f8f82 | 905 | spin_lock_irqsave(&dev->lock, flags); |
66b92988 FB |
906 | do { |
907 | bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG); | |
908 | stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG); | |
909 | stat &= bits; | |
910 | ||
079d8af2 FB |
911 | /* If we're in receiver mode, ignore XDR/XRDY */ |
912 | if (dev->receiver) | |
913 | stat &= ~(OMAP_I2C_STAT_XDR | OMAP_I2C_STAT_XRDY); | |
914 | else | |
915 | stat &= ~(OMAP_I2C_STAT_RDR | OMAP_I2C_STAT_RRDY); | |
010d442c | 916 | |
66b92988 FB |
917 | if (!stat) { |
918 | /* my work here is done */ | |
0bdfe0cb | 919 | goto out; |
66b92988 | 920 | } |
f08ac4e7 | 921 | |
010d442c KS |
922 | dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat); |
923 | if (count++ == 100) { | |
924 | dev_warn(dev->dev, "Too much work in one IRQ\n"); | |
925 | break; | |
926 | } | |
927 | ||
1d7afc95 | 928 | if (stat & OMAP_I2C_STAT_NACK) { |
b6ee52c3 | 929 | err |= OMAP_I2C_STAT_NACK; |
1d7afc95 | 930 | omap_i2c_ack_stat(dev, OMAP_I2C_STAT_NACK); |
0bdfe0cb | 931 | break; |
1d7afc95 | 932 | } |
78e1cf42 | 933 | |
b6ee52c3 NM |
934 | if (stat & OMAP_I2C_STAT_AL) { |
935 | dev_err(dev->dev, "Arbitration lost\n"); | |
936 | err |= OMAP_I2C_STAT_AL; | |
1d7afc95 | 937 | omap_i2c_ack_stat(dev, OMAP_I2C_STAT_AL); |
0bdfe0cb | 938 | break; |
b6ee52c3 | 939 | } |
c55edb99 | 940 | |
a5a595cc | 941 | /* |
cb527ede | 942 | * ProDB0017052: Clear ARDY bit twice |
a5a595cc | 943 | */ |
b6ee52c3 | 944 | if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK | |
04c688dd | 945 | OMAP_I2C_STAT_AL)) { |
540a4790 FB |
946 | omap_i2c_ack_stat(dev, (OMAP_I2C_STAT_RRDY | |
947 | OMAP_I2C_STAT_RDR | | |
948 | OMAP_I2C_STAT_XRDY | | |
949 | OMAP_I2C_STAT_XDR | | |
950 | OMAP_I2C_STAT_ARDY)); | |
0bdfe0cb | 951 | break; |
04c688dd | 952 | } |
c55edb99 | 953 | |
6d9939f6 | 954 | if (stat & OMAP_I2C_STAT_RDR) { |
b6ee52c3 | 955 | u8 num_bytes = 1; |
f3083d92 | 956 | |
6d9939f6 FB |
957 | if (dev->fifo_size) |
958 | num_bytes = dev->buf_len; | |
959 | ||
3312d25e | 960 | omap_i2c_receive_data(dev, num_bytes, true); |
6d9939f6 | 961 | |
f3083d92 | 962 | if (dev->errata & I2C_OMAP_ERRATA_I207) |
963 | i2c_omap_errata_i207(dev, stat); | |
964 | ||
6d9939f6 | 965 | omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR); |
9eb13cf3 | 966 | continue; |
6d9939f6 FB |
967 | } |
968 | ||
969 | if (stat & OMAP_I2C_STAT_RRDY) { | |
970 | u8 num_bytes = 1; | |
971 | ||
dd74548d FB |
972 | if (dev->threshold) |
973 | num_bytes = dev->threshold; | |
6d9939f6 | 974 | |
3312d25e | 975 | omap_i2c_receive_data(dev, num_bytes, false); |
6d9939f6 | 976 | omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RRDY); |
010d442c KS |
977 | continue; |
978 | } | |
c55edb99 | 979 | |
6d9939f6 | 980 | if (stat & OMAP_I2C_STAT_XDR) { |
b6ee52c3 | 981 | u8 num_bytes = 1; |
3312d25e | 982 | int ret; |
6d9939f6 FB |
983 | |
984 | if (dev->fifo_size) | |
985 | num_bytes = dev->buf_len; | |
986 | ||
3312d25e | 987 | ret = omap_i2c_transmit_data(dev, num_bytes, true); |
3312d25e | 988 | if (ret < 0) |
0bdfe0cb | 989 | break; |
6d9939f6 FB |
990 | |
991 | omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XDR); | |
9eb13cf3 | 992 | continue; |
6d9939f6 FB |
993 | } |
994 | ||
995 | if (stat & OMAP_I2C_STAT_XRDY) { | |
996 | u8 num_bytes = 1; | |
3312d25e | 997 | int ret; |
6d9939f6 | 998 | |
dd74548d FB |
999 | if (dev->threshold) |
1000 | num_bytes = dev->threshold; | |
6d9939f6 | 1001 | |
3312d25e | 1002 | ret = omap_i2c_transmit_data(dev, num_bytes, false); |
3312d25e | 1003 | if (ret < 0) |
0bdfe0cb | 1004 | break; |
6d9939f6 FB |
1005 | |
1006 | omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XRDY); | |
010d442c KS |
1007 | continue; |
1008 | } | |
c55edb99 | 1009 | |
010d442c KS |
1010 | if (stat & OMAP_I2C_STAT_ROVR) { |
1011 | dev_err(dev->dev, "Receive overrun\n"); | |
1d7afc95 FB |
1012 | err |= OMAP_I2C_STAT_ROVR; |
1013 | omap_i2c_ack_stat(dev, OMAP_I2C_STAT_ROVR); | |
0bdfe0cb | 1014 | break; |
010d442c | 1015 | } |
c55edb99 | 1016 | |
010d442c | 1017 | if (stat & OMAP_I2C_STAT_XUDF) { |
b6ee52c3 | 1018 | dev_err(dev->dev, "Transmit underflow\n"); |
1d7afc95 FB |
1019 | err |= OMAP_I2C_STAT_XUDF; |
1020 | omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XUDF); | |
0bdfe0cb | 1021 | break; |
010d442c | 1022 | } |
66b92988 | 1023 | } while (stat); |
010d442c | 1024 | |
4a7ec4ed | 1025 | omap_i2c_complete_cmd(dev, err); |
0bdfe0cb FB |
1026 | |
1027 | out: | |
3b2f8f82 | 1028 | spin_unlock_irqrestore(&dev->lock, flags); |
010d442c | 1029 | |
6a85ced2 | 1030 | return IRQ_HANDLED; |
010d442c KS |
1031 | } |
1032 | ||
8f9082c5 | 1033 | static const struct i2c_algorithm omap_i2c_algo = { |
010d442c KS |
1034 | .master_xfer = omap_i2c_xfer, |
1035 | .functionality = omap_i2c_func, | |
1036 | }; | |
1037 | ||
6145197b BC |
1038 | #ifdef CONFIG_OF |
1039 | static struct omap_i2c_bus_platform_data omap3_pdata = { | |
1040 | .rev = OMAP_I2C_IP_VERSION_1, | |
972deb4f | 1041 | .flags = OMAP_I2C_FLAG_BUS_SHIFT_2, |
6145197b BC |
1042 | }; |
1043 | ||
1044 | static struct omap_i2c_bus_platform_data omap4_pdata = { | |
1045 | .rev = OMAP_I2C_IP_VERSION_2, | |
1046 | }; | |
1047 | ||
1048 | static const struct of_device_id omap_i2c_of_match[] = { | |
1049 | { | |
1050 | .compatible = "ti,omap4-i2c", | |
1051 | .data = &omap4_pdata, | |
1052 | }, | |
1053 | { | |
1054 | .compatible = "ti,omap3-i2c", | |
1055 | .data = &omap3_pdata, | |
1056 | }, | |
1057 | { }, | |
1058 | }; | |
1059 | MODULE_DEVICE_TABLE(of, omap_i2c_of_match); | |
1060 | #endif | |
1061 | ||
47dcd016 S |
1062 | #define OMAP_I2C_SCHEME(rev) ((rev & 0xc000) >> 14) |
1063 | ||
1064 | #define OMAP_I2C_REV_SCHEME_0_MAJOR(rev) (rev >> 4) | |
1065 | #define OMAP_I2C_REV_SCHEME_0_MINOR(rev) (rev & 0xf) | |
1066 | ||
1067 | #define OMAP_I2C_REV_SCHEME_1_MAJOR(rev) ((rev & 0x0700) >> 7) | |
1068 | #define OMAP_I2C_REV_SCHEME_1_MINOR(rev) (rev & 0x1f) | |
1069 | #define OMAP_I2C_SCHEME_0 0 | |
1070 | #define OMAP_I2C_SCHEME_1 1 | |
1071 | ||
0b255e92 | 1072 | static int |
010d442c KS |
1073 | omap_i2c_probe(struct platform_device *pdev) |
1074 | { | |
1075 | struct omap_i2c_dev *dev; | |
1076 | struct i2c_adapter *adap; | |
ac79e4b2 | 1077 | struct resource *mem; |
c4dba011 UKK |
1078 | const struct omap_i2c_bus_platform_data *pdata = |
1079 | pdev->dev.platform_data; | |
6145197b BC |
1080 | struct device_node *node = pdev->dev.of_node; |
1081 | const struct of_device_id *match; | |
ac79e4b2 | 1082 | int irq; |
010d442c | 1083 | int r; |
47dcd016 | 1084 | u32 rev; |
cd10c74a | 1085 | u16 minor, major, scheme; |
010d442c | 1086 | |
ac79e4b2 FB |
1087 | irq = platform_get_irq(pdev, 0); |
1088 | if (irq < 0) { | |
010d442c | 1089 | dev_err(&pdev->dev, "no irq resource?\n"); |
ac79e4b2 | 1090 | return irq; |
010d442c KS |
1091 | } |
1092 | ||
d9ebd04d FB |
1093 | dev = devm_kzalloc(&pdev->dev, sizeof(struct omap_i2c_dev), GFP_KERNEL); |
1094 | if (!dev) { | |
1095 | dev_err(&pdev->dev, "Menory allocation failed\n"); | |
1096 | return -ENOMEM; | |
010d442c KS |
1097 | } |
1098 | ||
3cc2d009 | 1099 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
84dbf809 TR |
1100 | dev->base = devm_ioremap_resource(&pdev->dev, mem); |
1101 | if (IS_ERR(dev->base)) | |
1102 | return PTR_ERR(dev->base); | |
010d442c | 1103 | |
6c5aa407 | 1104 | match = of_match_device(of_match_ptr(omap_i2c_of_match), &pdev->dev); |
6145197b BC |
1105 | if (match) { |
1106 | u32 freq = 100000; /* default to 100000 Hz */ | |
1107 | ||
1108 | pdata = match->data; | |
6145197b BC |
1109 | dev->flags = pdata->flags; |
1110 | ||
1111 | of_property_read_u32(node, "clock-frequency", &freq); | |
1112 | /* convert DT freq value in Hz into kHz for speed */ | |
1113 | dev->speed = freq / 1000; | |
1114 | } else if (pdata != NULL) { | |
1115 | dev->speed = pdata->clkrate; | |
1116 | dev->flags = pdata->flags; | |
49839dc9 | 1117 | dev->set_mpu_wkup_lat = pdata->set_mpu_wkup_lat; |
20c9d2c4 | 1118 | } |
4574eb68 | 1119 | |
2d4b4520 SG |
1120 | dev->pins = devm_pinctrl_get_select_default(&pdev->dev); |
1121 | if (IS_ERR(dev->pins)) { | |
1122 | if (PTR_ERR(dev->pins) == -EPROBE_DEFER) | |
1123 | return -EPROBE_DEFER; | |
1124 | ||
1125 | dev_warn(&pdev->dev, "did not get pins for i2c error: %li\n", | |
1126 | PTR_ERR(dev->pins)); | |
1127 | dev->pins = NULL; | |
1128 | } | |
1129 | ||
010d442c | 1130 | dev->dev = &pdev->dev; |
ac79e4b2 | 1131 | dev->irq = irq; |
55c381e4 | 1132 | |
3b2f8f82 | 1133 | spin_lock_init(&dev->lock); |
55c381e4 | 1134 | |
010d442c | 1135 | platform_set_drvdata(pdev, dev); |
0e33bbb2 | 1136 | init_completion(&dev->cmd_complete); |
010d442c | 1137 | |
6145197b | 1138 | dev->reg_shift = (dev->flags >> OMAP_I2C_FLAG_BUS_SHIFT__SHIFT) & 3; |
7c6bd201 | 1139 | |
7f4b08ee | 1140 | pm_runtime_enable(dev->dev); |
6d8451d5 FB |
1141 | pm_runtime_set_autosuspend_delay(dev->dev, OMAP_I2C_PM_TIMEOUT); |
1142 | pm_runtime_use_autosuspend(dev->dev); | |
1143 | ||
3b0fb97c S |
1144 | r = pm_runtime_get_sync(dev->dev); |
1145 | if (IS_ERR_VALUE(r)) | |
1146 | goto err_free_mem; | |
010d442c | 1147 | |
47dcd016 S |
1148 | /* |
1149 | * Read the Rev hi bit-[15:14] ie scheme this is 1 indicates ver2. | |
1150 | * On omap1/3/2 Offset 4 is IE Reg the bit [15:14] is 0 at reset. | |
1151 | * Also since the omap_i2c_read_reg uses reg_map_ip_* a | |
1152 | * raw_readw is done. | |
1153 | */ | |
1154 | rev = __raw_readw(dev->base + 0x04); | |
1155 | ||
cd10c74a S |
1156 | scheme = OMAP_I2C_SCHEME(rev); |
1157 | switch (scheme) { | |
47dcd016 S |
1158 | case OMAP_I2C_SCHEME_0: |
1159 | dev->regs = (u8 *)reg_map_ip_v1; | |
1160 | dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG); | |
1161 | minor = OMAP_I2C_REV_SCHEME_0_MAJOR(dev->rev); | |
1162 | major = OMAP_I2C_REV_SCHEME_0_MAJOR(dev->rev); | |
1163 | break; | |
1164 | case OMAP_I2C_SCHEME_1: | |
1165 | /* FALLTHROUGH */ | |
1166 | default: | |
1167 | dev->regs = (u8 *)reg_map_ip_v2; | |
1168 | rev = (rev << 16) | | |
1169 | omap_i2c_read_reg(dev, OMAP_I2C_IP_V2_REVNB_LO); | |
1170 | minor = OMAP_I2C_REV_SCHEME_1_MINOR(rev); | |
1171 | major = OMAP_I2C_REV_SCHEME_1_MAJOR(rev); | |
1172 | dev->rev = rev; | |
1173 | } | |
010d442c | 1174 | |
9aa8ec67 TK |
1175 | dev->errata = 0; |
1176 | ||
a748021c S |
1177 | if (dev->rev >= OMAP_I2C_REV_ON_2430 && |
1178 | dev->rev < OMAP_I2C_REV_ON_4430_PLUS) | |
9aa8ec67 TK |
1179 | dev->errata |= I2C_OMAP_ERRATA_I207; |
1180 | ||
f518b482 | 1181 | if (dev->rev <= OMAP_I2C_REV_ON_3430_3530) |
c8db38f0 | 1182 | dev->errata |= I2C_OMAP_ERRATA_I462; |
8a9d97d3 | 1183 | |
6145197b | 1184 | if (!(dev->flags & OMAP_I2C_FLAG_NO_FIFO)) { |
b6ee52c3 NM |
1185 | u16 s; |
1186 | ||
1187 | /* Set up the fifo size - Get total size */ | |
1188 | s = (omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3; | |
1189 | dev->fifo_size = 0x8 << s; | |
1190 | ||
1191 | /* | |
1192 | * Set up notification threshold as half the total available | |
1193 | * size. This is to ensure that we can handle the status on int | |
1194 | * call back latencies. | |
1195 | */ | |
1d5a34fe S |
1196 | |
1197 | dev->fifo_size = (dev->fifo_size / 2); | |
1198 | ||
47dcd016 | 1199 | if (dev->rev < OMAP_I2C_REV_ON_3630) |
f38e66e0 | 1200 | dev->b_hw = 1; /* Enable hardware fixes */ |
1d5a34fe | 1201 | |
20c9d2c4 | 1202 | /* calculate wakeup latency constraint for MPU */ |
49839dc9 PW |
1203 | if (dev->set_mpu_wkup_lat != NULL) |
1204 | dev->latency = (1000000 * dev->fifo_size) / | |
1205 | (1000 * dev->speed / 8); | |
b6ee52c3 NM |
1206 | } |
1207 | ||
010d442c KS |
1208 | /* reset ASAP, clearing any IRQs */ |
1209 | omap_i2c_init(dev); | |
1210 | ||
3b2f8f82 FB |
1211 | if (dev->rev < OMAP_I2C_OMAP1_REV_2) |
1212 | r = devm_request_irq(&pdev->dev, dev->irq, omap_i2c_omap1_isr, | |
1213 | IRQF_NO_SUSPEND, pdev->name, dev); | |
1214 | else | |
1215 | r = devm_request_threaded_irq(&pdev->dev, dev->irq, | |
1216 | omap_i2c_isr, omap_i2c_isr_thread, | |
1217 | IRQF_NO_SUSPEND | IRQF_ONESHOT, | |
1218 | pdev->name, dev); | |
010d442c KS |
1219 | |
1220 | if (r) { | |
1221 | dev_err(dev->dev, "failure requesting irq %i\n", dev->irq); | |
1222 | goto err_unuse_clocks; | |
1223 | } | |
9c76b878 | 1224 | |
010d442c KS |
1225 | adap = &dev->adapter; |
1226 | i2c_set_adapdata(adap, dev); | |
1227 | adap->owner = THIS_MODULE; | |
1228 | adap->class = I2C_CLASS_HWMON; | |
783fd6fa | 1229 | strlcpy(adap->name, "OMAP I2C adapter", sizeof(adap->name)); |
010d442c KS |
1230 | adap->algo = &omap_i2c_algo; |
1231 | adap->dev.parent = &pdev->dev; | |
6145197b | 1232 | adap->dev.of_node = pdev->dev.of_node; |
010d442c KS |
1233 | |
1234 | /* i2c device drivers may be active on return from add_adapter() */ | |
7c175499 DB |
1235 | adap->nr = pdev->id; |
1236 | r = i2c_add_numbered_adapter(adap); | |
010d442c KS |
1237 | if (r) { |
1238 | dev_err(dev->dev, "failure adding adapter\n"); | |
d9ebd04d | 1239 | goto err_unuse_clocks; |
010d442c KS |
1240 | } |
1241 | ||
cd10c74a S |
1242 | dev_info(dev->dev, "bus %d rev%d.%d at %d kHz\n", adap->nr, |
1243 | major, minor, dev->speed); | |
c5d3cd6d | 1244 | |
6145197b BC |
1245 | of_i2c_register_devices(adap); |
1246 | ||
6d8451d5 FB |
1247 | pm_runtime_mark_last_busy(dev->dev); |
1248 | pm_runtime_put_autosuspend(dev->dev); | |
62ff2c2b | 1249 | |
010d442c KS |
1250 | return 0; |
1251 | ||
010d442c | 1252 | err_unuse_clocks: |
3e39752d | 1253 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0); |
fab67afb | 1254 | pm_runtime_put(dev->dev); |
24740516 | 1255 | pm_runtime_disable(&pdev->dev); |
010d442c | 1256 | err_free_mem: |
010d442c KS |
1257 | |
1258 | return r; | |
1259 | } | |
1260 | ||
0b255e92 | 1261 | static int omap_i2c_remove(struct platform_device *pdev) |
010d442c KS |
1262 | { |
1263 | struct omap_i2c_dev *dev = platform_get_drvdata(pdev); | |
3b0fb97c | 1264 | int ret; |
010d442c | 1265 | |
010d442c | 1266 | i2c_del_adapter(&dev->adapter); |
3b0fb97c S |
1267 | ret = pm_runtime_get_sync(&pdev->dev); |
1268 | if (IS_ERR_VALUE(ret)) | |
1269 | return ret; | |
1270 | ||
010d442c | 1271 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0); |
0861f430 | 1272 | pm_runtime_put(&pdev->dev); |
24740516 | 1273 | pm_runtime_disable(&pdev->dev); |
010d442c KS |
1274 | return 0; |
1275 | } | |
1276 | ||
5692d2a2 | 1277 | #ifdef CONFIG_PM |
fab67afb KH |
1278 | #ifdef CONFIG_PM_RUNTIME |
1279 | static int omap_i2c_runtime_suspend(struct device *dev) | |
1280 | { | |
1281 | struct platform_device *pdev = to_platform_device(dev); | |
1282 | struct omap_i2c_dev *_dev = platform_get_drvdata(pdev); | |
3dae3efb S |
1283 | |
1284 | _dev->iestate = omap_i2c_read_reg(_dev, OMAP_I2C_IE_REG); | |
bd16c82f S |
1285 | |
1286 | omap_i2c_write_reg(_dev, OMAP_I2C_IE_REG, 0); | |
fab67afb | 1287 | |
3dae3efb | 1288 | if (_dev->rev < OMAP_I2C_OMAP1_REV_2) { |
27e0fbef | 1289 | omap_i2c_read_reg(_dev, OMAP_I2C_IV_REG); /* Read clears */ |
3dae3efb S |
1290 | } else { |
1291 | omap_i2c_write_reg(_dev, OMAP_I2C_STAT_REG, _dev->iestate); | |
fab67afb | 1292 | |
3dae3efb S |
1293 | /* Flush posted write */ |
1294 | omap_i2c_read_reg(_dev, OMAP_I2C_STAT_REG); | |
1295 | } | |
fab67afb KH |
1296 | |
1297 | return 0; | |
1298 | } | |
1299 | ||
1300 | static int omap_i2c_runtime_resume(struct device *dev) | |
1301 | { | |
1302 | struct platform_device *pdev = to_platform_device(dev); | |
1303 | struct omap_i2c_dev *_dev = platform_get_drvdata(pdev); | |
1304 | ||
47dcd016 S |
1305 | if (!_dev->regs) |
1306 | return 0; | |
1307 | ||
554c9674 | 1308 | __omap_i2c_init(_dev); |
fab67afb KH |
1309 | |
1310 | return 0; | |
1311 | } | |
5692d2a2 | 1312 | #endif /* CONFIG_PM_RUNTIME */ |
fab67afb KH |
1313 | |
1314 | static struct dev_pm_ops omap_i2c_pm_ops = { | |
5692d2a2 S |
1315 | SET_RUNTIME_PM_OPS(omap_i2c_runtime_suspend, |
1316 | omap_i2c_runtime_resume, NULL) | |
fab67afb KH |
1317 | }; |
1318 | #define OMAP_I2C_PM_OPS (&omap_i2c_pm_ops) | |
1319 | #else | |
1320 | #define OMAP_I2C_PM_OPS NULL | |
5692d2a2 | 1321 | #endif /* CONFIG_PM */ |
fab67afb | 1322 | |
010d442c KS |
1323 | static struct platform_driver omap_i2c_driver = { |
1324 | .probe = omap_i2c_probe, | |
0b255e92 | 1325 | .remove = omap_i2c_remove, |
010d442c | 1326 | .driver = { |
f7bb0d9a | 1327 | .name = "omap_i2c", |
010d442c | 1328 | .owner = THIS_MODULE, |
fab67afb | 1329 | .pm = OMAP_I2C_PM_OPS, |
6145197b | 1330 | .of_match_table = of_match_ptr(omap_i2c_of_match), |
010d442c KS |
1331 | }, |
1332 | }; | |
1333 | ||
1334 | /* I2C may be needed to bring up other drivers */ | |
1335 | static int __init | |
1336 | omap_i2c_init_driver(void) | |
1337 | { | |
1338 | return platform_driver_register(&omap_i2c_driver); | |
1339 | } | |
1340 | subsys_initcall(omap_i2c_init_driver); | |
1341 | ||
1342 | static void __exit omap_i2c_exit_driver(void) | |
1343 | { | |
1344 | platform_driver_unregister(&omap_i2c_driver); | |
1345 | } | |
1346 | module_exit(omap_i2c_exit_driver); | |
1347 | ||
1348 | MODULE_AUTHOR("MontaVista Software, Inc. (and others)"); | |
1349 | MODULE_DESCRIPTION("TI OMAP I2C bus adapter"); | |
1350 | MODULE_LICENSE("GPL"); | |
f7bb0d9a | 1351 | MODULE_ALIAS("platform:omap_i2c"); |