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i2c: core: only use set_scl for bus recovery after calling prepare_recovery
[deliverable/linux.git] / drivers / i2c / busses / i2c-omap.c
CommitLineData
010d442c
KS		 1/*
2 * TI OMAP I2C master mode driver
3 *
4 * Copyright (C) 2003 MontaVista Software, Inc.
010d442c 5 * Copyright (C) 2005 Nokia Corporation
c1a473bd 6 * Copyright (C) 2004 - 2007 Texas Instruments.
010d442c 7 *
c1a473bd
TL		 8 * Originally written by MontaVista Software, Inc.
9 * Additional contributions by:
10 * Tony Lindgren <tony@atomide.com>
11 * Imre Deak <imre.deak@nokia.com>
12 * Juha Yrjölä <juha.yrjola@solidboot.com>
13 * Syed Khasim <x0khasim@ti.com>
14 * Nishant Menon <nm@ti.com>
010d442c
KS		 15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
010d442c
KS		 25 */
26
27#include <linux/module.h>
28#include <linux/delay.h>
29#include <linux/i2c.h>
30#include <linux/err.h>
31#include <linux/interrupt.h>
32#include <linux/completion.h>
33#include <linux/platform_device.h>
34#include <linux/clk.h>
c1a473bd 35#include <linux/io.h>
6145197b 36#include <linux/of.h>
6145197b 37#include <linux/of_device.h>
5a0e3ad6 38#include <linux/slab.h>
20c9d2c4 39#include <linux/i2c-omap.h>
27b1fec2 40#include <linux/pm_runtime.h>
096ea30c 41#include <linux/pinctrl/consumer.h>
010d442c 42
9c76b878 43/* I2C controller revisions */
4e80f727 44#define OMAP_I2C_OMAP1_REV_2 0x20
9c76b878
PW		 45
46/* I2C controller revisions present on specific hardware */
47dcd016
S		 47#define OMAP_I2C_REV_ON_2430 0x00000036
48#define OMAP_I2C_REV_ON_3430_3530 0x0000003C
49#define OMAP_I2C_REV_ON_3630 0x00000040
50#define OMAP_I2C_REV_ON_4430_PLUS 0x50400002
9c76b878 51
010d442c
KS		 52/* timeout waiting for the controller to respond */
53#define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
54
6d8451d5
FB		 55/* timeout for pm runtime autosuspend */
56#define OMAP_I2C_PM_TIMEOUT 1000 /* ms */
57
0f5768bf
AK		 58/* timeout for making decision on bus free status */
59#define OMAP_I2C_BUS_FREE_TIMEOUT (msecs_to_jiffies(10))
60
5043e9e7 61/* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */
f38e66e0
SS		 62enum {
63 OMAP_I2C_REV_REG = 0,
64 OMAP_I2C_IE_REG,
65 OMAP_I2C_STAT_REG,
66 OMAP_I2C_IV_REG,
67 OMAP_I2C_WE_REG,
68 OMAP_I2C_SYSS_REG,
69 OMAP_I2C_BUF_REG,
70 OMAP_I2C_CNT_REG,
71 OMAP_I2C_DATA_REG,
72 OMAP_I2C_SYSC_REG,
73 OMAP_I2C_CON_REG,
74 OMAP_I2C_OA_REG,
75 OMAP_I2C_SA_REG,
76 OMAP_I2C_PSC_REG,
77 OMAP_I2C_SCLL_REG,
78 OMAP_I2C_SCLH_REG,
79 OMAP_I2C_SYSTEST_REG,
80 OMAP_I2C_BUFSTAT_REG,
b8853088
AG		 81 /* only on OMAP4430 */
82 OMAP_I2C_IP_V2_REVNB_LO,
83 OMAP_I2C_IP_V2_REVNB_HI,
84 OMAP_I2C_IP_V2_IRQSTATUS_RAW,
85 OMAP_I2C_IP_V2_IRQENABLE_SET,
86 OMAP_I2C_IP_V2_IRQENABLE_CLR,
f38e66e0 87};
010d442c
KS		 88
89/* I2C Interrupt Enable Register (OMAP_I2C_IE): */
b6ee52c3
NM		 90#define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */
91#define OMAP_I2C_IE_RDR (1 << 13) /* RX Buffer drain int enable */
010d442c
KS		 92#define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */
93#define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */
94#define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */
95#define OMAP_I2C_IE_NACK (1 << 1) /* No ack interrupt enable */
96#define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */
97
98/* I2C Status Register (OMAP_I2C_STAT): */
b6ee52c3
NM		 99#define OMAP_I2C_STAT_XDR (1 << 14) /* TX Buffer draining */
100#define OMAP_I2C_STAT_RDR (1 << 13) /* RX Buffer draining */
010d442c
KS		 101#define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */
102#define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */
103#define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
104#define OMAP_I2C_STAT_AAS (1 << 9) /* Address as slave */
9fd6ada8 105#define OMAP_I2C_STAT_BF (1 << 8) /* Bus Free */
010d442c
KS		 106#define OMAP_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
107#define OMAP_I2C_STAT_RRDY (1 << 3) /* Receive data ready */
108#define OMAP_I2C_STAT_ARDY (1 << 2) /* Register access ready */
109#define OMAP_I2C_STAT_NACK (1 << 1) /* No ack interrupt enable */
110#define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost int ena */
111
5043e9e7
KJ		 112/* I2C WE wakeup enable register */
113#define OMAP_I2C_WE_XDR_WE (1 << 14) /* TX drain wakup */
114#define OMAP_I2C_WE_RDR_WE (1 << 13) /* RX drain wakeup */
115#define OMAP_I2C_WE_AAS_WE (1 << 9) /* Address as slave wakeup*/
116#define OMAP_I2C_WE_BF_WE (1 << 8) /* Bus free wakeup */
117#define OMAP_I2C_WE_STC_WE (1 << 6) /* Start condition wakeup */
118#define OMAP_I2C_WE_GC_WE (1 << 5) /* General call wakeup */
119#define OMAP_I2C_WE_DRDY_WE (1 << 3) /* TX/RX data ready wakeup */
120#define OMAP_I2C_WE_ARDY_WE (1 << 2) /* Reg access ready wakeup */
121#define OMAP_I2C_WE_NACK_WE (1 << 1) /* No acknowledgment wakeup */
122#define OMAP_I2C_WE_AL_WE (1 << 0) /* Arbitration lost wakeup */
123
124#define OMAP_I2C_WE_ALL (OMAP_I2C_WE_XDR_WE | OMAP_I2C_WE_RDR_WE | \
125 OMAP_I2C_WE_AAS_WE | OMAP_I2C_WE_BF_WE | \
126 OMAP_I2C_WE_STC_WE | OMAP_I2C_WE_GC_WE | \
127 OMAP_I2C_WE_DRDY_WE | OMAP_I2C_WE_ARDY_WE | \
128 OMAP_I2C_WE_NACK_WE | OMAP_I2C_WE_AL_WE)
129
010d442c
KS		 130/* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
131#define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */
b6ee52c3 132#define OMAP_I2C_BUF_RXFIF_CLR (1 << 14) /* RX FIFO Clear */
010d442c 133#define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */
b6ee52c3 134#define OMAP_I2C_BUF_TXFIF_CLR (1 << 6) /* TX FIFO Clear */
010d442c
KS		 135
136/* I2C Configuration Register (OMAP_I2C_CON): */
137#define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */
138#define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */
b6ee52c3 139#define OMAP_I2C_CON_OPMODE_HS (1 << 12) /* High Speed support */
010d442c
KS		 140#define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */
141#define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */
142#define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */
143#define OMAP_I2C_CON_XA (1 << 8) /* Expand address */
144#define OMAP_I2C_CON_RM (1 << 2) /* Repeat mode (master only) */
145#define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */
146#define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */
147
4574eb68
SMK		 148/* I2C SCL time value when Master */
149#define OMAP_I2C_SCLL_HSSCLL 8
150#define OMAP_I2C_SCLH_HSSCLH 8
151
010d442c 152/* I2C System Test Register (OMAP_I2C_SYSTEST): */
010d442c
KS		 153#define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */
154#define OMAP_I2C_SYSTEST_FREE (1 << 14) /* Free running mode */
155#define OMAP_I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */
156#define OMAP_I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */
9fd6ada8
AK		 157/* Functional mode */
158#define OMAP_I2C_SYSTEST_SCL_I_FUNC (1 << 8) /* SCL line input value */
159#define OMAP_I2C_SYSTEST_SCL_O_FUNC (1 << 7) /* SCL line output value */
160#define OMAP_I2C_SYSTEST_SDA_I_FUNC (1 << 6) /* SDA line input value */
161#define OMAP_I2C_SYSTEST_SDA_O_FUNC (1 << 5) /* SDA line output value */
162/* SDA/SCL IO mode */
010d442c
KS		 163#define OMAP_I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense in */
164#define OMAP_I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive out */
165#define OMAP_I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense in */
166#define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */
010d442c 167
fdd07fe6
PW		 168/* OCP_SYSSTATUS bit definitions */
169#define SYSS_RESETDONE_MASK (1 << 0)
170
171/* OCP_SYSCONFIG bit definitions */
172#define SYSC_CLOCKACTIVITY_MASK (0x3 << 8)
173#define SYSC_SIDLEMODE_MASK (0x3 << 3)
174#define SYSC_ENAWAKEUP_MASK (1 << 2)
175#define SYSC_SOFTRESET_MASK (1 << 1)
176#define SYSC_AUTOIDLE_MASK (1 << 0)
177
178#define SYSC_IDLEMODE_SMART 0x2
179#define SYSC_CLOCKACTIVITY_FCLK 0x2
010d442c 180
f3083d92 181/* Errata definitions */
182#define I2C_OMAP_ERRATA_I207 (1 << 0)
c8db38f0 183#define I2C_OMAP_ERRATA_I462 (1 << 1)
010d442c 184
4368de19
OD		 185#define OMAP_I2C_IP_V2_INTERRUPTS_MASK 0x6FFF
186
010d442c 187struct omap_i2c_dev {
3b2f8f82 188 spinlock_t lock; /* IRQ synchronization */
010d442c
KS		 189 struct device *dev;
190 void __iomem *base; /* virtual */
191 int irq;
d84d3ea3 192 int reg_shift; /* bit shift for I2C register addresses */
010d442c
KS		 193 struct completion cmd_complete;
194 struct resource *ioarea;
49839dc9
PW		 195 u32 latency; /* maximum mpu wkup latency */
196 void (*set_mpu_wkup_lat)(struct device *dev,
197 long latency);
6145197b 198 u32 speed; /* Speed of bus in kHz */
6145197b 199 u32 flags;
4368de19 200 u16 scheme;
010d442c
KS		 201 u16 cmd_err;
202 u8 *buf;
f38e66e0 203 u8 *regs;
010d442c
KS		 204 size_t buf_len;
205 struct i2c_adapter adapter;
dd74548d 206 u8 threshold;
b6ee52c3
NM		 207 u8 fifo_size; /* use as flag and value
208 * fifo_size==0 implies no fifo
209 * if set, should be trsh+1
210 */
47dcd016 211 u32 rev;
b6ee52c3 212 unsigned b_hw:1; /* bad h/w fixes */
0f5768bf
AK		 213 unsigned bb_valid:1; /* true when BB-bit reflects
214 * the I2C bus state
215 */
079d8af2 216 unsigned receiver:1; /* true when we're in receiver mode */
f08ac4e7 217 u16 iestate; /* Saved interrupt register */
ef871432
RN		 218 u16 pscstate;
219 u16 scllstate;
220 u16 sclhstate;
ef871432
RN		 221 u16 syscstate;
222 u16 westate;
f3083d92 223 u16 errata;
010d442c
KS		 224};
225
a1295577 226static const u8 reg_map_ip_v1[] = {
f38e66e0
SS		 227 [OMAP_I2C_REV_REG] = 0x00,
228 [OMAP_I2C_IE_REG] = 0x01,
229 [OMAP_I2C_STAT_REG] = 0x02,
230 [OMAP_I2C_IV_REG] = 0x03,
231 [OMAP_I2C_WE_REG] = 0x03,
232 [OMAP_I2C_SYSS_REG] = 0x04,
233 [OMAP_I2C_BUF_REG] = 0x05,
234 [OMAP_I2C_CNT_REG] = 0x06,
235 [OMAP_I2C_DATA_REG] = 0x07,
236 [OMAP_I2C_SYSC_REG] = 0x08,
237 [OMAP_I2C_CON_REG] = 0x09,
238 [OMAP_I2C_OA_REG] = 0x0a,
239 [OMAP_I2C_SA_REG] = 0x0b,
240 [OMAP_I2C_PSC_REG] = 0x0c,
241 [OMAP_I2C_SCLL_REG] = 0x0d,
242 [OMAP_I2C_SCLH_REG] = 0x0e,
243 [OMAP_I2C_SYSTEST_REG] = 0x0f,
244 [OMAP_I2C_BUFSTAT_REG] = 0x10,
245};
246
a1295577 247static const u8 reg_map_ip_v2[] = {
f38e66e0
SS		 248 [OMAP_I2C_REV_REG] = 0x04,
249 [OMAP_I2C_IE_REG] = 0x2c,
250 [OMAP_I2C_STAT_REG] = 0x28,
251 [OMAP_I2C_IV_REG] = 0x34,
252 [OMAP_I2C_WE_REG] = 0x34,
253 [OMAP_I2C_SYSS_REG] = 0x90,
254 [OMAP_I2C_BUF_REG] = 0x94,
255 [OMAP_I2C_CNT_REG] = 0x98,
256 [OMAP_I2C_DATA_REG] = 0x9c,
2727b175 257 [OMAP_I2C_SYSC_REG] = 0x10,
f38e66e0
SS		 258 [OMAP_I2C_CON_REG] = 0xa4,
259 [OMAP_I2C_OA_REG] = 0xa8,
260 [OMAP_I2C_SA_REG] = 0xac,
261 [OMAP_I2C_PSC_REG] = 0xb0,
262 [OMAP_I2C_SCLL_REG] = 0xb4,
263 [OMAP_I2C_SCLH_REG] = 0xb8,
264 [OMAP_I2C_SYSTEST_REG] = 0xbC,
265 [OMAP_I2C_BUFSTAT_REG] = 0xc0,
b8853088
AG		 266 [OMAP_I2C_IP_V2_REVNB_LO] = 0x00,
267 [OMAP_I2C_IP_V2_REVNB_HI] = 0x04,
268 [OMAP_I2C_IP_V2_IRQSTATUS_RAW] = 0x24,
269 [OMAP_I2C_IP_V2_IRQENABLE_SET] = 0x2c,
270 [OMAP_I2C_IP_V2_IRQENABLE_CLR] = 0x30,
f38e66e0
SS		 271};
272
010d442c
KS		 273static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev,
274 int reg, u16 val)
275{
40b13ca8 276 writew_relaxed(val, i2c_dev->base +
f38e66e0 277 (i2c_dev->regs[reg] << i2c_dev->reg_shift));
010d442c
KS		 278}
279
280static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
281{
40b13ca8 282 return readw_relaxed(i2c_dev->base +
f38e66e0 283 (i2c_dev->regs[reg] << i2c_dev->reg_shift));
010d442c
KS		 284}
285
95dd3032
S		 286static void __omap_i2c_init(struct omap_i2c_dev *dev)
287{
288
289 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
290
291 /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
292 omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, dev->pscstate);
293
294 /* SCL low and high time values */
295 omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, dev->scllstate);
296 omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, dev->sclhstate);
297 if (dev->rev >= OMAP_I2C_REV_ON_3430_3530)
298 omap_i2c_write_reg(dev, OMAP_I2C_WE_REG, dev->westate);
299
300 /* Take the I2C module out of reset: */
301 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
302
4f734a3a
AK		 303 /*
304 * NOTE: right after setting CON_EN, STAT_BB could be 0 while the
305 * bus is busy. It will be changed to 1 on the next IP FCLK clock.
306 * udelay(1) will be enough to fix that.
307 */
308
95dd3032
S		 309 /*
310 * Don't write to this register if the IE state is 0 as it can
311 * cause deadlock.
312 */
313 if (dev->iestate)
314 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
315}
316
d6c842ad 317static int omap_i2c_reset(struct omap_i2c_dev *dev)
010d442c 318{
010d442c 319 unsigned long timeout;
ca85e248
S		 320 u16 sysc;
321
4e80f727 322 if (dev->rev >= OMAP_I2C_OMAP1_REV_2) {
ca85e248
S		 323 sysc = omap_i2c_read_reg(dev, OMAP_I2C_SYSC_REG);
324
57eb81b1
MG		 325 /* Disable I2C controller before soft reset */
326 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
327 omap_i2c_read_reg(dev, OMAP_I2C_CON_REG) &
328 ~(OMAP_I2C_CON_EN));
329
fdd07fe6 330 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK);
010d442c
KS		 331 /* For some reason we need to set the EN bit before the
332 * reset done bit gets set. */
333 timeout = jiffies + OMAP_I2C_TIMEOUT;
334 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
335 while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) &
fdd07fe6 336 SYSS_RESETDONE_MASK)) {
010d442c 337 if (time_after(jiffies, timeout)) {
fce3ff03 338 dev_warn(dev->dev, "timeout waiting "
010d442c
KS		 339 "for controller reset\n");
340 return -ETIMEDOUT;
341 }
342 msleep(1);
343 }
fdd07fe6
PW		 344
345 /* SYSC register is cleared by the reset; rewrite it */
ca85e248 346 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, sysc);
fdd07fe6 347
23173eae
AK		 348 if (dev->rev > OMAP_I2C_REV_ON_3430_3530) {
349 /* Schedule I2C-bus monitoring on the next transfer */
350 dev->bb_valid = 0;
351 }
010d442c 352 }
0f5768bf 353
d6c842ad
S		 354 return 0;
355}
356
357static int omap_i2c_init(struct omap_i2c_dev *dev)
358{
359 u16 psc = 0, scll = 0, sclh = 0;
360 u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
361 unsigned long fclk_rate = 12000000;
362 unsigned long internal_clk = 0;
363 struct clk *fclk;
364
365 if (dev->rev >= OMAP_I2C_REV_ON_3430_3530) {
366 /*
367 * Enabling all wakup sources to stop I2C freezing on
368 * WFI instruction.
369 * REVISIT: Some wkup sources might not be needed.
370 */
371 dev->westate = OMAP_I2C_WE_ALL;
372 }
010d442c 373
6145197b 374 if (dev->flags & OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK) {
0e9ae109
RK		 375 /*
376 * The I2C functional clock is the armxor_ck, so there's
377 * no need to get "armxor_ck" separately. Now, if OMAP2420
378 * always returns 12MHz for the functional clock, we can
379 * do this bit unconditionally.
380 */
27b1fec2
RN		 381 fclk = clk_get(dev->dev, "fck");
382 fclk_rate = clk_get_rate(fclk);
383 clk_put(fclk);
0e9ae109 384
010d442c
KS		 385 /* TRM for 5912 says the I2C clock must be prescaled to be
386 * between 7 - 12 MHz. The XOR input clock is typically
387 * 12, 13 or 19.2 MHz. So we should have code that produces:
388 *
389 * XOR MHz Divider Prescaler
390 * 12 1 0
391 * 13 2 1
392 * 19.2 2 1
393 */
d7aef138
JD		 394 if (fclk_rate > 12000000)
395 psc = fclk_rate / 12000000;
010d442c
KS		 396 }
397
6145197b 398 if (!(dev->flags & OMAP_I2C_FLAG_SIMPLE_CLOCK)) {
4574eb68 399
84bf2c86
AK		 400 /*
401 * HSI2C controller internal clk rate should be 19.2 Mhz for
402 * HS and for all modes on 2430. On 34xx we can use lower rate
403 * to get longer filter period for better noise suppression.
404 * The filter is iclk (fclk for HS) period.
405 */
3be0053e 406 if (dev->speed > 400 ||
6145197b 407 dev->flags & OMAP_I2C_FLAG_FORCE_19200_INT_CLK)
84bf2c86
AK		 408 internal_clk = 19200;
409 else if (dev->speed > 100)
410 internal_clk = 9600;
411 else
412 internal_clk = 4000;
27b1fec2
RN		 413 fclk = clk_get(dev->dev, "fck");
414 fclk_rate = clk_get_rate(fclk) / 1000;
415 clk_put(fclk);
4574eb68
SMK		 416
417 /* Compute prescaler divisor */
418 psc = fclk_rate / internal_clk;
419 psc = psc - 1;
420
421 /* If configured for High Speed */
422 if (dev->speed > 400) {
baf46b4e
AK		 423 unsigned long scl;
424
4574eb68 425 /* For first phase of HS mode */
baf46b4e
AK		 426 scl = internal_clk / 400;
427 fsscll = scl - (scl / 3) - 7;
428 fssclh = (scl / 3) - 5;
4574eb68
SMK		 429
430 /* For second phase of HS mode */
baf46b4e
AK		 431 scl = fclk_rate / dev->speed;
432 hsscll = scl - (scl / 3) - 7;
433 hssclh = (scl / 3) - 5;
434 } else if (dev->speed > 100) {
435 unsigned long scl;
436
437 /* Fast mode */
438 scl = internal_clk / dev->speed;
439 fsscll = scl - (scl / 3) - 7;
440 fssclh = (scl / 3) - 5;
4574eb68 441 } else {
baf46b4e
AK		 442 /* Standard mode */
443 fsscll = internal_clk / (dev->speed * 2) - 7;
444 fssclh = internal_clk / (dev->speed * 2) - 5;
4574eb68
SMK		 445 }
446 scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
447 sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
448 } else {
449 /* Program desired operating rate */
450 fclk_rate /= (psc + 1) * 1000;
451 if (psc > 2)
452 psc = 2;
453 scll = fclk_rate / (dev->speed * 2) - 7 + psc;
454 sclh = fclk_rate / (dev->speed * 2) - 7 + psc;
455 }
456
ef871432 457 dev->iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
c1a473bd
TL		 458 OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
459 OMAP_I2C_IE_AL) | ((dev->fifo_size) ?
ef871432 460 (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0);
95dd3032
S		 461
462 dev->pscstate = psc;
463 dev->scllstate = scll;
464 dev->sclhstate = sclh;
465
23173eae 466 if (dev->rev <= OMAP_I2C_REV_ON_3430_3530) {
0f5768bf
AK		 467 /* Not implemented */
468 dev->bb_valid = 1;
469 }
470
95dd3032
S		 471 __omap_i2c_init(dev);
472
010d442c
KS		 473 return 0;
474}
475
476/*
477 * Waiting on Bus Busy
478 */
479static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev)
480{
481 unsigned long timeout;
482
483 timeout = jiffies + OMAP_I2C_TIMEOUT;
484 while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
9dcb0e7b
FB		 485 if (time_after(jiffies, timeout))
486 return i2c_recover_bus(&dev->adapter);
010d442c
KS		 487 msleep(1);
488 }
489
490 return 0;
491}
492
0f5768bf
AK		 493/*
494 * Wait while BB-bit doesn't reflect the I2C bus state
495 *
496 * In a multimaster environment, after IP software reset, BB-bit value doesn't
497 * correspond to the current bus state. It may happen what BB-bit will be 0,
498 * while the bus is busy due to another I2C master activity.
499 * Here are BB-bit values after reset:
500 * SDA SCL BB NOTES
501 * 0 0 0 1, 2
502 * 1 0 0 1, 2
503 * 0 1 1
504 * 1 1 0 3
505 * Later, if IP detect SDA=0 and SCL=1 (ACK) or SDA 1->0 while SCL=1 (START)
506 * combinations on the bus, it set BB-bit to 1.
507 * If IP detect SDA 0->1 while SCL=1 (STOP) combination on the bus,
508 * it set BB-bit to 0 and BF to 1.
509 * BB and BF bits correctly tracks the bus state while IP is suspended
510 * BB bit became valid on the next FCLK clock after CON_EN bit set
511 *
512 * NOTES:
513 * 1. Any transfer started when BB=0 and bus is busy wouldn't be
514 * completed by IP and results in controller timeout.
515 * 2. Any transfer started when BB=0 and SCL=0 results in IP
516 * starting to drive SDA low. In that case IP corrupt data
517 * on the bus.
518 * 3. Any transfer started in the middle of another master's transfer
519 * results in unpredictable results and data corruption
520 */
521static int omap_i2c_wait_for_bb_valid(struct omap_i2c_dev *dev)
522{
523 unsigned long bus_free_timeout = 0;
524 unsigned long timeout;
525 int bus_free = 0;
526 u16 stat, systest;
527
528 if (dev->bb_valid)
529 return 0;
530
531 timeout = jiffies + OMAP_I2C_TIMEOUT;
532 while (1) {
533 stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
534 /*
535 * We will see BB or BF event in a case IP had detected any
536 * activity on the I2C bus. Now IP correctly tracks the bus
537 * state. BB-bit value is valid.
538 */
539 if (stat & (OMAP_I2C_STAT_BB | OMAP_I2C_STAT_BF))
540 break;
541
542 /*
543 * Otherwise, we must look signals on the bus to make
544 * the right decision.
545 */
546 systest = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG);
547 if ((systest & OMAP_I2C_SYSTEST_SCL_I_FUNC) &&
548 (systest & OMAP_I2C_SYSTEST_SDA_I_FUNC)) {
549 if (!bus_free) {
550 bus_free_timeout = jiffies +
551 OMAP_I2C_BUS_FREE_TIMEOUT;
552 bus_free = 1;
553 }
554
555 /*
556 * SDA and SCL lines was high for 10 ms without bus
557 * activity detected. The bus is free. Consider
558 * BB-bit value is valid.
559 */
560 if (time_after(jiffies, bus_free_timeout))
561 break;
562 } else {
563 bus_free = 0;
564 }
565
566 if (time_after(jiffies, timeout)) {
567 dev_warn(dev->dev, "timeout waiting for bus ready\n");
568 return -ETIMEDOUT;
569 }
570
571 msleep(1);
572 }
573
574 dev->bb_valid = 1;
575 return 0;
576}
577
dd74548d
FB		 578static void omap_i2c_resize_fifo(struct omap_i2c_dev *dev, u8 size, bool is_rx)
579{
580 u16 buf;
581
582 if (dev->flags & OMAP_I2C_FLAG_NO_FIFO)
583 return;
584
585 /*
586 * Set up notification threshold based on message size. We're doing
587 * this to try and avoid draining feature as much as possible. Whenever
588 * we have big messages to transfer (bigger than our total fifo size)
589 * then we might use draining feature to transfer the remaining bytes.
590 */
591
592 dev->threshold = clamp(size, (u8) 1, dev->fifo_size);
593
594 buf = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
595
596 if (is_rx) {
597 /* Clear RX Threshold */
598 buf &= ~(0x3f << 8);
599 buf |= ((dev->threshold - 1) << 8) | OMAP_I2C_BUF_RXFIF_CLR;
600 } else {
601 /* Clear TX Threshold */
602 buf &= ~0x3f;
603 buf |= (dev->threshold - 1) | OMAP_I2C_BUF_TXFIF_CLR;
604 }
605
606 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, buf);
607
47dcd016 608 if (dev->rev < OMAP_I2C_REV_ON_3630)
dd74548d
FB		 609 dev->b_hw = 1; /* Enable hardware fixes */
610
611 /* calculate wakeup latency constraint for MPU */
49839dc9
PW		 612 if (dev->set_mpu_wkup_lat != NULL)
613 dev->latency = (1000000 * dev->threshold) /
614 (1000 * dev->speed / 8);
dd74548d
FB		 615}
616
010d442c
KS		 617/*
618 * Low level master read/write transaction.
619 */
620static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
621 struct i2c_msg *msg, int stop)
622{
623 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
33d54985 624 unsigned long timeout;
010d442c
KS		 625 u16 w;
626
627 dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
628 msg->addr, msg->len, msg->flags, stop);
629
630 if (msg->len == 0)
631 return -EINVAL;
632
dd74548d
FB		 633 dev->receiver = !!(msg->flags & I2C_M_RD);
634 omap_i2c_resize_fifo(dev, msg->len, dev->receiver);
635
010d442c
KS		 636 omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);
637
638 /* REVISIT: Could the STB bit of I2C_CON be used with probing? */
639 dev->buf = msg->buf;
640 dev->buf_len = msg->len;
641
d60ece5f
FB		 642 /* make sure writes to dev->buf_len are ordered */
643 barrier();
644
010d442c
KS		 645 omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len);
646
b6ee52c3
NM		 647 /* Clear the FIFO Buffers */
648 w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
649 w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR;
650 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w);
651
16735d02 652 reinit_completion(&dev->cmd_complete);
010d442c
KS		 653 dev->cmd_err = 0;
654
655 w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
4574eb68
SMK		 656
657 /* High speed configuration */
658 if (dev->speed > 400)
b6ee52c3 659 w |= OMAP_I2C_CON_OPMODE_HS;
4574eb68 660
fb604a3d
LP		 661 if (msg->flags & I2C_M_STOP)
662 stop = 1;
010d442c
KS		 663 if (msg->flags & I2C_M_TEN)
664 w |= OMAP_I2C_CON_XA;
665 if (!(msg->flags & I2C_M_RD))
666 w |= OMAP_I2C_CON_TRX;
c1a473bd 667
b6ee52c3 668 if (!dev->b_hw && stop)
010d442c 669 w |= OMAP_I2C_CON_STP;
4f734a3a
AK		 670 /*
671 * NOTE: STAT_BB bit could became 1 here if another master occupy
672 * the bus. IP successfully complete transfer when the bus will be
673 * free again (BB reset to 0).
674 */
010d442c
KS		 675 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
676
b6ee52c3
NM		 677 /*
678 * Don't write stt and stp together on some hardware.
679 */
680 if (dev->b_hw && stop) {
681 unsigned long delay = jiffies + OMAP_I2C_TIMEOUT;
682 u16 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
683 while (con & OMAP_I2C_CON_STT) {
684 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
685
686 /* Let the user know if i2c is in a bad state */
687 if (time_after(jiffies, delay)) {
688 dev_err(dev->dev, "controller timed out "
689 "waiting for start condition to finish\n");
690 return -ETIMEDOUT;
691 }
692 cpu_relax();
693 }
694
695 w |= OMAP_I2C_CON_STP;
696 w &= ~OMAP_I2C_CON_STT;
697 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
698 }
699
b7af349b
JN		 700 /*
701 * REVISIT: We should abort the transfer on signals, but the bus goes
702 * into arbitration and we're currently unable to recover from it.
703 */
33d54985
S		 704 timeout = wait_for_completion_timeout(&dev->cmd_complete,
705 OMAP_I2C_TIMEOUT);
33d54985 706 if (timeout == 0) {
010d442c 707 dev_err(dev->dev, "controller timed out\n");
d6c842ad
S		 708 omap_i2c_reset(dev);
709 __omap_i2c_init(dev);
010d442c
KS		 710 return -ETIMEDOUT;
711 }
712
713 if (likely(!dev->cmd_err))
714 return 0;
715
716 /* We have an error */
b76911d2 717 if (dev->cmd_err & (OMAP_I2C_STAT_ROVR | OMAP_I2C_STAT_XUDF)) {
d6c842ad
S		 718 omap_i2c_reset(dev);
719 __omap_i2c_init(dev);
010d442c
KS		 720 return -EIO;
721 }
722
b76911d2
AK		 723 if (dev->cmd_err & OMAP_I2C_STAT_AL)
724 return -EAGAIN;
725
010d442c
KS		 726 if (dev->cmd_err & OMAP_I2C_STAT_NACK) {
727 if (msg->flags & I2C_M_IGNORE_NAK)
728 return 0;
cda2109a
GS		 729
730 w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
731 w |= OMAP_I2C_CON_STP;
732 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
010d442c
KS		 733 return -EREMOTEIO;
734 }
735 return -EIO;
736}
737
738
739/*
740 * Prepare controller for a transaction and call omap_i2c_xfer_msg
741 * to do the work during IRQ processing.
742 */
743static int
744omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
745{
746 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
747 int i;
748 int r;
749
3b0fb97c 750 r = pm_runtime_get_sync(dev->dev);
ff370257 751 if (r < 0)
33ec5e81 752 goto out;
010d442c 753
0f5768bf
AK		 754 r = omap_i2c_wait_for_bb_valid(dev);
755 if (r < 0)
756 goto out;
757
c1a473bd
TL		 758 r = omap_i2c_wait_for_bb(dev);
759 if (r < 0)
010d442c
KS		 760 goto out;
761
49839dc9
PW		 762 if (dev->set_mpu_wkup_lat != NULL)
763 dev->set_mpu_wkup_lat(dev->dev, dev->latency);
6a91b558 764
010d442c
KS		 765 for (i = 0; i < num; i++) {
766 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));
767 if (r != 0)
768 break;
769 }
770
771 if (r == 0)
772 r = num;
5c64eb26
MN		 773
774 omap_i2c_wait_for_bb(dev);
1ab36045
S		 775
776 if (dev->set_mpu_wkup_lat != NULL)
777 dev->set_mpu_wkup_lat(dev->dev, -1);
778
010d442c 779out:
6d8451d5
FB		 780 pm_runtime_mark_last_busy(dev->dev);
781 pm_runtime_put_autosuspend(dev->dev);
010d442c
KS		 782 return r;
783}
784
785static u32
786omap_i2c_func(struct i2c_adapter *adap)
787{
fb604a3d
LP		 788 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
789 I2C_FUNC_PROTOCOL_MANGLING;
010d442c
KS		 790}
791
792static inline void
793omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err)
794{
795 dev->cmd_err |= err;
796 complete(&dev->cmd_complete);
797}
798
799static inline void
800omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat)
801{
802 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
803}
804
f3083d92 805static inline void i2c_omap_errata_i207(struct omap_i2c_dev *dev, u16 stat)
806{
807 /*
808 * I2C Errata(Errata Nos. OMAP2: 1.67, OMAP3: 1.8)
809 * Not applicable for OMAP4.
810 * Under certain rare conditions, RDR could be set again
811 * when the bus is busy, then ignore the interrupt and
812 * clear the interrupt.
813 */
814 if (stat & OMAP_I2C_STAT_RDR) {
815 /* Step 1: If RDR is set, clear it */
816 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
817
818 /* Step 2: */
819 if (!(omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG)
820 & OMAP_I2C_STAT_BB)) {
821
822 /* Step 3: */
823 if (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG)
824 & OMAP_I2C_STAT_RDR) {
825 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
826 dev_dbg(dev->dev, "RDR when bus is busy.\n");
827 }
828
829 }
830 }
831}
832
43469d8e
PW		 833/* rev1 devices are apparently only on some 15xx */
834#ifdef CONFIG_ARCH_OMAP15XX
835
010d442c 836static irqreturn_t
4e80f727 837omap_i2c_omap1_isr(int this_irq, void *dev_id)
010d442c
KS		 838{
839 struct omap_i2c_dev *dev = dev_id;
840 u16 iv, w;
841
fab67afb 842 if (pm_runtime_suspended(dev->dev))
f08ac4e7
TL		 843 return IRQ_NONE;
844
010d442c
KS		 845 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
846 switch (iv) {
847 case 0x00: /* None */
848 break;
849 case 0x01: /* Arbitration lost */
850 dev_err(dev->dev, "Arbitration lost\n");
851 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
852 break;
853 case 0x02: /* No acknowledgement */
854 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
855 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
856 break;
857 case 0x03: /* Register access ready */
858 omap_i2c_complete_cmd(dev, 0);
859 break;
860 case 0x04: /* Receive data ready */
861 if (dev->buf_len) {
862 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
863 *dev->buf++ = w;
864 dev->buf_len--;
865 if (dev->buf_len) {
866 *dev->buf++ = w >> 8;
867 dev->buf_len--;
868 }
869 } else
870 dev_err(dev->dev, "RRDY IRQ while no data requested\n");
871 break;
872 case 0x05: /* Transmit data ready */
873 if (dev->buf_len) {
874 w = *dev->buf++;
875 dev->buf_len--;
876 if (dev->buf_len) {
877 w |= *dev->buf++ << 8;
878 dev->buf_len--;
879 }
880 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
881 } else
882 dev_err(dev->dev, "XRDY IRQ while no data to send\n");
883 break;
884 default:
885 return IRQ_NONE;
886 }
887
888 return IRQ_HANDLED;
889}
43469d8e 890#else
4e80f727 891#define omap_i2c_omap1_isr NULL
43469d8e 892#endif
010d442c 893
2dd151ab 894/*
c8db38f0 895 * OMAP3430 Errata i462: When an XRDY/XDR is hit, wait for XUDF before writing
2dd151ab
AS		 896 * data to DATA_REG. Otherwise some data bytes can be lost while transferring
897 * them from the memory to the I2C interface.
898 */
4151e741 899static int errata_omap3_i462(struct omap_i2c_dev *dev)
2dd151ab 900{
e9f59b9c 901 unsigned long timeout = 10000;
4151e741 902 u16 stat;
e9f59b9c 903
4151e741
FB		 904 do {
905 stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
906 if (stat & OMAP_I2C_STAT_XUDF)
907 break;
908
909 if (stat & (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) {
540a4790 910 omap_i2c_ack_stat(dev, (OMAP_I2C_STAT_XRDY |
2dd151ab 911 OMAP_I2C_STAT_XDR));
b07be0f3
FB		 912 if (stat & OMAP_I2C_STAT_NACK) {
913 dev->cmd_err |= OMAP_I2C_STAT_NACK;
914 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_NACK);
915 }
916
917 if (stat & OMAP_I2C_STAT_AL) {
918 dev_err(dev->dev, "Arbitration lost\n");
919 dev->cmd_err |= OMAP_I2C_STAT_AL;
2c5de558 920 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_AL);
b07be0f3
FB		 921 }
922
4151e741 923 return -EIO;
2dd151ab 924 }
e9f59b9c 925
2dd151ab 926 cpu_relax();
4151e741 927 } while (--timeout);
2dd151ab 928
e9f59b9c
AS		 929 if (!timeout) {
930 dev_err(dev->dev, "timeout waiting on XUDF bit\n");
931 return 0;
932 }
933
2dd151ab
AS		 934 return 0;
935}
936
3312d25e
FB		 937static void omap_i2c_receive_data(struct omap_i2c_dev *dev, u8 num_bytes,
938 bool is_rdr)
939{
940 u16 w;
941
942 while (num_bytes--) {
3312d25e
FB		 943 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
944 *dev->buf++ = w;
945 dev->buf_len--;
946
947 /*
948 * Data reg in 2430, omap3 and
949 * omap4 is 8 bit wide
950 */
951 if (dev->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) {
dd74548d
FB		 952 *dev->buf++ = w >> 8;
953 dev->buf_len--;
3312d25e
FB		 954 }
955 }
956}
957
958static int omap_i2c_transmit_data(struct omap_i2c_dev *dev, u8 num_bytes,
959 bool is_xdr)
960{
961 u16 w;
962
963 while (num_bytes--) {
3312d25e
FB		 964 w = *dev->buf++;
965 dev->buf_len--;
966
967 /*
968 * Data reg in 2430, omap3 and
969 * omap4 is 8 bit wide
970 */
971 if (dev->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) {
dd74548d
FB		 972 w |= *dev->buf++ << 8;
973 dev->buf_len--;
3312d25e
FB		 974 }
975
976 if (dev->errata & I2C_OMAP_ERRATA_I462) {
977 int ret;
978
979 ret = errata_omap3_i462(dev);
980 if (ret < 0)
981 return ret;
982 }
983
984 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
985 }
986
987 return 0;
988}
989
010d442c 990static irqreturn_t
3b2f8f82 991omap_i2c_isr(int irq, void *dev_id)
010d442c
KS		 992{
993 struct omap_i2c_dev *dev = dev_id;
3b2f8f82
FB		 994 irqreturn_t ret = IRQ_HANDLED;
995 u16 mask;
996 u16 stat;
997
998 spin_lock(&dev->lock);
999 mask = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
1000 stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
1001
1002 if (stat & mask)
1003 ret = IRQ_WAKE_THREAD;
1004
1005 spin_unlock(&dev->lock);
1006
1007 return ret;
1008}
1009
010d442c 1010static irqreturn_t
3b2f8f82 1011omap_i2c_isr_thread(int this_irq, void *dev_id)
010d442c
KS		 1012{
1013 struct omap_i2c_dev *dev = dev_id;
3b2f8f82 1014 unsigned long flags;
010d442c 1015 u16 bits;
3312d25e 1016 u16 stat;
66b92988 1017 int err = 0, count = 0;
010d442c 1018
3b2f8f82 1019 spin_lock_irqsave(&dev->lock, flags);
66b92988
FB		 1020 do {
1021 bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
1022 stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
1023 stat &= bits;
1024
079d8af2
FB		 1025 /* If we're in receiver mode, ignore XDR/XRDY */
1026 if (dev->receiver)
1027 stat &= ~(OMAP_I2C_STAT_XDR | OMAP_I2C_STAT_XRDY);
1028 else
1029 stat &= ~(OMAP_I2C_STAT_RDR | OMAP_I2C_STAT_RRDY);
010d442c 1030
66b92988
FB		 1031 if (!stat) {
1032 /* my work here is done */
0bdfe0cb 1033 goto out;
66b92988 1034 }
f08ac4e7 1035
010d442c
KS		 1036 dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat);
1037 if (count++ == 100) {
1038 dev_warn(dev->dev, "Too much work in one IRQ\n");
1039 break;
1040 }
1041
1d7afc95 1042 if (stat & OMAP_I2C_STAT_NACK) {
b6ee52c3 1043 err |= OMAP_I2C_STAT_NACK;
1d7afc95 1044 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_NACK);
1d7afc95 1045 }
78e1cf42 1046
b6ee52c3
NM		 1047 if (stat & OMAP_I2C_STAT_AL) {
1048 dev_err(dev->dev, "Arbitration lost\n");
1049 err |= OMAP_I2C_STAT_AL;
1d7afc95 1050 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_AL);
b6ee52c3 1051 }
c55edb99 1052
a5a595cc 1053 /*
cb527ede 1054 * ProDB0017052: Clear ARDY bit twice
a5a595cc 1055 */
4cdbf7d3
TK		 1056 if (stat & OMAP_I2C_STAT_ARDY)
1057 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_ARDY);
1058
b6ee52c3 1059 if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
04c688dd 1060 OMAP_I2C_STAT_AL)) {
540a4790
FB		 1061 omap_i2c_ack_stat(dev, (OMAP_I2C_STAT_RRDY |
1062 OMAP_I2C_STAT_RDR |
1063 OMAP_I2C_STAT_XRDY |
1064 OMAP_I2C_STAT_XDR |
1065 OMAP_I2C_STAT_ARDY));
0bdfe0cb 1066 break;
04c688dd 1067 }
c55edb99 1068
6d9939f6 1069 if (stat & OMAP_I2C_STAT_RDR) {
b6ee52c3 1070 u8 num_bytes = 1;
f3083d92 1071
6d9939f6
FB		 1072 if (dev->fifo_size)
1073 num_bytes = dev->buf_len;
1074
ccfc8663 1075 if (dev->errata & I2C_OMAP_ERRATA_I207) {
f3083d92 1076 i2c_omap_errata_i207(dev, stat);
ccfc8663
AK		 1077 num_bytes = (omap_i2c_read_reg(dev,
1078 OMAP_I2C_BUFSTAT_REG) >> 8) & 0x3F;
1079 }
f3083d92 1080
ccfc8663 1081 omap_i2c_receive_data(dev, num_bytes, true);
6d9939f6 1082 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
9eb13cf3 1083 continue;
6d9939f6
FB		 1084 }
1085
1086 if (stat & OMAP_I2C_STAT_RRDY) {
1087 u8 num_bytes = 1;
1088
dd74548d
FB		 1089 if (dev->threshold)
1090 num_bytes = dev->threshold;
6d9939f6 1091
3312d25e 1092 omap_i2c_receive_data(dev, num_bytes, false);
6d9939f6 1093 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RRDY);
010d442c
KS		 1094 continue;
1095 }
c55edb99 1096
6d9939f6 1097 if (stat & OMAP_I2C_STAT_XDR) {
b6ee52c3 1098 u8 num_bytes = 1;
3312d25e 1099 int ret;
6d9939f6
FB		 1100
1101 if (dev->fifo_size)
1102 num_bytes = dev->buf_len;
1103
3312d25e 1104 ret = omap_i2c_transmit_data(dev, num_bytes, true);
3312d25e 1105 if (ret < 0)
0bdfe0cb 1106 break;
6d9939f6
FB		 1107
1108 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XDR);
9eb13cf3 1109 continue;
6d9939f6
FB		 1110 }
1111
1112 if (stat & OMAP_I2C_STAT_XRDY) {
1113 u8 num_bytes = 1;
3312d25e 1114 int ret;
6d9939f6 1115
dd74548d
FB		 1116 if (dev->threshold)
1117 num_bytes = dev->threshold;
6d9939f6 1118
3312d25e 1119 ret = omap_i2c_transmit_data(dev, num_bytes, false);
3312d25e 1120 if (ret < 0)
0bdfe0cb 1121 break;
6d9939f6
FB		 1122
1123 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XRDY);
010d442c
KS		 1124 continue;
1125 }
c55edb99 1126
010d442c
KS		 1127 if (stat & OMAP_I2C_STAT_ROVR) {
1128 dev_err(dev->dev, "Receive overrun\n");
1d7afc95
FB		 1129 err |= OMAP_I2C_STAT_ROVR;
1130 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_ROVR);
0bdfe0cb 1131 break;
010d442c 1132 }
c55edb99 1133
010d442c 1134 if (stat & OMAP_I2C_STAT_XUDF) {
b6ee52c3 1135 dev_err(dev->dev, "Transmit underflow\n");
1d7afc95
FB		 1136 err |= OMAP_I2C_STAT_XUDF;
1137 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XUDF);
0bdfe0cb 1138 break;
010d442c 1139 }
66b92988 1140 } while (stat);
010d442c 1141
4a7ec4ed 1142 omap_i2c_complete_cmd(dev, err);
0bdfe0cb
FB		 1143
1144out:
3b2f8f82 1145 spin_unlock_irqrestore(&dev->lock, flags);
010d442c 1146
6a85ced2 1147 return IRQ_HANDLED;
010d442c
KS		 1148}
1149
8f9082c5 1150static const struct i2c_algorithm omap_i2c_algo = {
010d442c
KS		 1151 .master_xfer = omap_i2c_xfer,
1152 .functionality = omap_i2c_func,
1153};
1154
6145197b 1155#ifdef CONFIG_OF
4c624840
TL		 1156static struct omap_i2c_bus_platform_data omap2420_pdata = {
1157 .rev = OMAP_I2C_IP_VERSION_1,
1158 .flags = OMAP_I2C_FLAG_NO_FIFO |
1159 OMAP_I2C_FLAG_SIMPLE_CLOCK |
1160 OMAP_I2C_FLAG_16BIT_DATA_REG |
1161 OMAP_I2C_FLAG_BUS_SHIFT_2,
1162};
1163
1164static struct omap_i2c_bus_platform_data omap2430_pdata = {
1165 .rev = OMAP_I2C_IP_VERSION_1,
1166 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2 |
1167 OMAP_I2C_FLAG_FORCE_19200_INT_CLK,
1168};
1169
6145197b
BC		 1170static struct omap_i2c_bus_platform_data omap3_pdata = {
1171 .rev = OMAP_I2C_IP_VERSION_1,
972deb4f 1172 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2,
6145197b
BC		 1173};
1174
1175static struct omap_i2c_bus_platform_data omap4_pdata = {
1176 .rev = OMAP_I2C_IP_VERSION_2,
1177};
1178
1179static const struct of_device_id omap_i2c_of_match[] = {
1180 {
1181 .compatible = "ti,omap4-i2c",
1182 .data = &omap4_pdata,
1183 },
1184 {
1185 .compatible = "ti,omap3-i2c",
1186 .data = &omap3_pdata,
1187 },
4c624840
TL		 1188 {
1189 .compatible = "ti,omap2430-i2c",
1190 .data = &omap2430_pdata,
1191 },
1192 {
1193 .compatible = "ti,omap2420-i2c",
1194 .data = &omap2420_pdata,
1195 },
6145197b
BC		 1196 { },
1197};
1198MODULE_DEVICE_TABLE(of, omap_i2c_of_match);
1199#endif
1200
47dcd016
S		 1201#define OMAP_I2C_SCHEME(rev) ((rev & 0xc000) >> 14)
1202
1203#define OMAP_I2C_REV_SCHEME_0_MAJOR(rev) (rev >> 4)
1204#define OMAP_I2C_REV_SCHEME_0_MINOR(rev) (rev & 0xf)
1205
1206#define OMAP_I2C_REV_SCHEME_1_MAJOR(rev) ((rev & 0x0700) >> 7)
1207#define OMAP_I2C_REV_SCHEME_1_MINOR(rev) (rev & 0x1f)
1208#define OMAP_I2C_SCHEME_0 0
1209#define OMAP_I2C_SCHEME_1 1
1210
9dcb0e7b
FB		 1211static int omap_i2c_get_scl(struct i2c_adapter *adap)
1212{
1213 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
1214 u32 reg;
1215
1216 reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG);
1217
1218 return reg & OMAP_I2C_SYSTEST_SCL_I_FUNC;
1219}
1220
1221static int omap_i2c_get_sda(struct i2c_adapter *adap)
1222{
1223 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
1224 u32 reg;
1225
1226 reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG);
1227
1228 return reg & OMAP_I2C_SYSTEST_SDA_I_FUNC;
1229}
1230
1231static void omap_i2c_set_scl(struct i2c_adapter *adap, int val)
1232{
1233 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
1234 u32 reg;
1235
1236 reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG);
1237 if (val)
1238 reg |= OMAP_I2C_SYSTEST_SCL_O;
1239 else
1240 reg &= ~OMAP_I2C_SYSTEST_SCL_O;
1241 omap_i2c_write_reg(dev, OMAP_I2C_SYSTEST_REG, reg);
1242}
1243
1244static void omap_i2c_prepare_recovery(struct i2c_adapter *adap)
1245{
1246 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
1247 u32 reg;
1248
1249 reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG);
1250 reg |= OMAP_I2C_SYSTEST_ST_EN;
1251 omap_i2c_write_reg(dev, OMAP_I2C_SYSTEST_REG, reg);
1252}
1253
1254static void omap_i2c_unprepare_recovery(struct i2c_adapter *adap)
1255{
1256 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
1257 u32 reg;
1258
1259 reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG);
1260 reg &= ~OMAP_I2C_SYSTEST_ST_EN;
1261 omap_i2c_write_reg(dev, OMAP_I2C_SYSTEST_REG, reg);
1262}
1263
1264static struct i2c_bus_recovery_info omap_i2c_bus_recovery_info = {
1265 .get_scl = omap_i2c_get_scl,
1266 .get_sda = omap_i2c_get_sda,
1267 .set_scl = omap_i2c_set_scl,
1268 .prepare_recovery = omap_i2c_prepare_recovery,
1269 .unprepare_recovery = omap_i2c_unprepare_recovery,
1270 .recover_bus = i2c_generic_scl_recovery,
1271};
1272
0b255e92 1273static int
010d442c
KS		 1274omap_i2c_probe(struct platform_device *pdev)
1275{
1276 struct omap_i2c_dev *dev;
1277 struct i2c_adapter *adap;
ac79e4b2 1278 struct resource *mem;
c4dba011 1279 const struct omap_i2c_bus_platform_data *pdata =
6d4028c6 1280 dev_get_platdata(&pdev->dev);
6145197b
BC		 1281 struct device_node *node = pdev->dev.of_node;
1282 const struct of_device_id *match;
ac79e4b2 1283 int irq;
010d442c 1284 int r;
47dcd016 1285 u32 rev;
4368de19 1286 u16 minor, major;
010d442c 1287
ac79e4b2
FB		 1288 irq = platform_get_irq(pdev, 0);
1289 if (irq < 0) {
010d442c 1290 dev_err(&pdev->dev, "no irq resource?\n");
ac79e4b2 1291 return irq;
010d442c
KS		 1292 }
1293
d9ebd04d 1294 dev = devm_kzalloc(&pdev->dev, sizeof(struct omap_i2c_dev), GFP_KERNEL);
46797a2a 1295 if (!dev)
d9ebd04d 1296 return -ENOMEM;
010d442c 1297
3cc2d009 1298 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
84dbf809
TR		 1299 dev->base = devm_ioremap_resource(&pdev->dev, mem);
1300 if (IS_ERR(dev->base))
1301 return PTR_ERR(dev->base);
010d442c 1302
6c5aa407 1303 match = of_match_device(of_match_ptr(omap_i2c_of_match), &pdev->dev);
6145197b
BC		 1304 if (match) {
1305 u32 freq = 100000; /* default to 100000 Hz */
1306
1307 pdata = match->data;
6145197b
BC		 1308 dev->flags = pdata->flags;
1309
1310 of_property_read_u32(node, "clock-frequency", &freq);
1311 /* convert DT freq value in Hz into kHz for speed */
1312 dev->speed = freq / 1000;
1313 } else if (pdata != NULL) {
1314 dev->speed = pdata->clkrate;
1315 dev->flags = pdata->flags;
49839dc9 1316 dev->set_mpu_wkup_lat = pdata->set_mpu_wkup_lat;
20c9d2c4 1317 }
4574eb68 1318
010d442c 1319 dev->dev = &pdev->dev;
ac79e4b2 1320 dev->irq = irq;
55c381e4 1321
3b2f8f82 1322 spin_lock_init(&dev->lock);
55c381e4 1323
010d442c 1324 platform_set_drvdata(pdev, dev);
0e33bbb2 1325 init_completion(&dev->cmd_complete);
010d442c 1326
6145197b 1327 dev->reg_shift = (dev->flags >> OMAP_I2C_FLAG_BUS_SHIFT__SHIFT) & 3;
7c6bd201 1328
7f4b08ee 1329 pm_runtime_enable(dev->dev);
6d8451d5
FB		 1330 pm_runtime_set_autosuspend_delay(dev->dev, OMAP_I2C_PM_TIMEOUT);
1331 pm_runtime_use_autosuspend(dev->dev);
1332
3b0fb97c 1333 r = pm_runtime_get_sync(dev->dev);
ff370257 1334 if (r < 0)
3b0fb97c 1335 goto err_free_mem;
010d442c 1336
47dcd016
S		 1337 /*
1338 * Read the Rev hi bit-[15:14] ie scheme this is 1 indicates ver2.
1339 * On omap1/3/2 Offset 4 is IE Reg the bit [15:14] is 0 at reset.
1340 * Also since the omap_i2c_read_reg uses reg_map_ip_* a
40b13ca8 1341 * readw_relaxed is done.
47dcd016 1342 */
40b13ca8 1343 rev = readw_relaxed(dev->base + 0x04);
47dcd016 1344
4368de19
OD		 1345 dev->scheme = OMAP_I2C_SCHEME(rev);
1346 switch (dev->scheme) {
47dcd016
S		 1347 case OMAP_I2C_SCHEME_0:
1348 dev->regs = (u8 *)reg_map_ip_v1;
1349 dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG);
1350 minor = OMAP_I2C_REV_SCHEME_0_MAJOR(dev->rev);
1351 major = OMAP_I2C_REV_SCHEME_0_MAJOR(dev->rev);
1352 break;
1353 case OMAP_I2C_SCHEME_1:
1354 /* FALLTHROUGH */
1355 default:
1356 dev->regs = (u8 *)reg_map_ip_v2;
1357 rev = (rev << 16) |
1358 omap_i2c_read_reg(dev, OMAP_I2C_IP_V2_REVNB_LO);
1359 minor = OMAP_I2C_REV_SCHEME_1_MINOR(rev);
1360 major = OMAP_I2C_REV_SCHEME_1_MAJOR(rev);
1361 dev->rev = rev;
1362 }
010d442c 1363
9aa8ec67
TK		 1364 dev->errata = 0;
1365
a748021c
S		 1366 if (dev->rev >= OMAP_I2C_REV_ON_2430 &&
1367 dev->rev < OMAP_I2C_REV_ON_4430_PLUS)
9aa8ec67
TK		 1368 dev->errata |= I2C_OMAP_ERRATA_I207;
1369
f518b482 1370 if (dev->rev <= OMAP_I2C_REV_ON_3430_3530)
c8db38f0 1371 dev->errata |= I2C_OMAP_ERRATA_I462;
8a9d97d3 1372
6145197b 1373 if (!(dev->flags & OMAP_I2C_FLAG_NO_FIFO)) {
b6ee52c3
NM		 1374 u16 s;
1375
1376 /* Set up the fifo size - Get total size */
1377 s = (omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3;
1378 dev->fifo_size = 0x8 << s;
1379
1380 /*
1381 * Set up notification threshold as half the total available
1382 * size. This is to ensure that we can handle the status on int
1383 * call back latencies.
1384 */
1d5a34fe
S		 1385
1386 dev->fifo_size = (dev->fifo_size / 2);
1387
47dcd016 1388 if (dev->rev < OMAP_I2C_REV_ON_3630)
f38e66e0 1389 dev->b_hw = 1; /* Enable hardware fixes */
1d5a34fe 1390
20c9d2c4 1391 /* calculate wakeup latency constraint for MPU */
49839dc9
PW		 1392 if (dev->set_mpu_wkup_lat != NULL)
1393 dev->latency = (1000000 * dev->fifo_size) /
1394 (1000 * dev->speed / 8);
b6ee52c3
NM		 1395 }
1396
010d442c
KS		 1397 /* reset ASAP, clearing any IRQs */
1398 omap_i2c_init(dev);
1399
3b2f8f82
FB		 1400 if (dev->rev < OMAP_I2C_OMAP1_REV_2)
1401 r = devm_request_irq(&pdev->dev, dev->irq, omap_i2c_omap1_isr,
1402 IRQF_NO_SUSPEND, pdev->name, dev);
1403 else
1404 r = devm_request_threaded_irq(&pdev->dev, dev->irq,
1405 omap_i2c_isr, omap_i2c_isr_thread,
1406 IRQF_NO_SUSPEND | IRQF_ONESHOT,
1407 pdev->name, dev);
010d442c
KS		 1408
1409 if (r) {
1410 dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
1411 goto err_unuse_clocks;
1412 }
9c76b878 1413
010d442c
KS		 1414 adap = &dev->adapter;
1415 i2c_set_adapdata(adap, dev);
1416 adap->owner = THIS_MODULE;
cfac71d9 1417 adap->class = I2C_CLASS_DEPRECATED;
783fd6fa 1418 strlcpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
010d442c
KS		 1419 adap->algo = &omap_i2c_algo;
1420 adap->dev.parent = &pdev->dev;
6145197b 1421 adap->dev.of_node = pdev->dev.of_node;
9dcb0e7b 1422 adap->bus_recovery_info = &omap_i2c_bus_recovery_info;
010d442c
KS		 1423
1424 /* i2c device drivers may be active on return from add_adapter() */
7c175499
DB		 1425 adap->nr = pdev->id;
1426 r = i2c_add_numbered_adapter(adap);
010d442c
KS		 1427 if (r) {
1428 dev_err(dev->dev, "failure adding adapter\n");
d9ebd04d 1429 goto err_unuse_clocks;
010d442c
KS		 1430 }
1431
cd10c74a
S		 1432 dev_info(dev->dev, "bus %d rev%d.%d at %d kHz\n", adap->nr,
1433 major, minor, dev->speed);
c5d3cd6d 1434
6d8451d5
FB		 1435 pm_runtime_mark_last_busy(dev->dev);
1436 pm_runtime_put_autosuspend(dev->dev);
62ff2c2b 1437
010d442c
KS		 1438 return 0;
1439
010d442c 1440err_unuse_clocks:
3e39752d 1441 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
fab67afb 1442 pm_runtime_put(dev->dev);
24740516 1443 pm_runtime_disable(&pdev->dev);
010d442c 1444err_free_mem:
010d442c
KS		 1445
1446 return r;
1447}
1448
0b255e92 1449static int omap_i2c_remove(struct platform_device *pdev)
010d442c
KS		 1450{
1451 struct omap_i2c_dev *dev = platform_get_drvdata(pdev);
3b0fb97c 1452 int ret;
010d442c 1453
010d442c 1454 i2c_del_adapter(&dev->adapter);
3b0fb97c 1455 ret = pm_runtime_get_sync(&pdev->dev);
ff370257 1456 if (ret < 0)
3b0fb97c
S		 1457 return ret;
1458
010d442c 1459 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
0861f430 1460 pm_runtime_put(&pdev->dev);
24740516 1461 pm_runtime_disable(&pdev->dev);
010d442c
KS		 1462 return 0;
1463}
1464
5692d2a2 1465#ifdef CONFIG_PM
fab67afb
KH		 1466static int omap_i2c_runtime_suspend(struct device *dev)
1467{
1468 struct platform_device *pdev = to_platform_device(dev);
1469 struct omap_i2c_dev *_dev = platform_get_drvdata(pdev);
3dae3efb
S		 1470
1471 _dev->iestate = omap_i2c_read_reg(_dev, OMAP_I2C_IE_REG);
bd16c82f 1472
4368de19
OD		 1473 if (_dev->scheme == OMAP_I2C_SCHEME_0)
1474 omap_i2c_write_reg(_dev, OMAP_I2C_IE_REG, 0);
1475 else
1476 omap_i2c_write_reg(_dev, OMAP_I2C_IP_V2_IRQENABLE_CLR,
1477 OMAP_I2C_IP_V2_INTERRUPTS_MASK);
fab67afb 1478
3dae3efb 1479 if (_dev->rev < OMAP_I2C_OMAP1_REV_2) {
27e0fbef 1480 omap_i2c_read_reg(_dev, OMAP_I2C_IV_REG); /* Read clears */
3dae3efb
S		 1481 } else {
1482 omap_i2c_write_reg(_dev, OMAP_I2C_STAT_REG, _dev->iestate);
fab67afb 1483
3dae3efb
S		 1484 /* Flush posted write */
1485 omap_i2c_read_reg(_dev, OMAP_I2C_STAT_REG);
1486 }
fab67afb 1487
096ea30c
PH		 1488 pinctrl_pm_select_sleep_state(dev);
1489
fab67afb
KH		 1490 return 0;
1491}
1492
1493static int omap_i2c_runtime_resume(struct device *dev)
1494{
1495 struct platform_device *pdev = to_platform_device(dev);
1496 struct omap_i2c_dev *_dev = platform_get_drvdata(pdev);
096ea30c
PH		 1497
1498 pinctrl_pm_select_default_state(dev);
fab67afb 1499
47dcd016
S		 1500 if (!_dev->regs)
1501 return 0;
1502
554c9674 1503 __omap_i2c_init(_dev);
fab67afb
KH		 1504
1505 return 0;
1506}
1507
1508static struct dev_pm_ops omap_i2c_pm_ops = {
5692d2a2
S		 1509 SET_RUNTIME_PM_OPS(omap_i2c_runtime_suspend,
1510 omap_i2c_runtime_resume, NULL)
fab67afb
KH		 1511};
1512#define OMAP_I2C_PM_OPS (&omap_i2c_pm_ops)
1513#else
1514#define OMAP_I2C_PM_OPS NULL
5692d2a2 1515#endif /* CONFIG_PM */
fab67afb 1516
010d442c
KS		 1517static struct platform_driver omap_i2c_driver = {
1518 .probe = omap_i2c_probe,
0b255e92 1519 .remove = omap_i2c_remove,
010d442c 1520 .driver = {
f7bb0d9a 1521 .name = "omap_i2c",
fab67afb 1522 .pm = OMAP_I2C_PM_OPS,
6145197b 1523 .of_match_table = of_match_ptr(omap_i2c_of_match),
010d442c
KS		 1524 },
1525};
1526
1527/* I2C may be needed to bring up other drivers */
1528static int __init
1529omap_i2c_init_driver(void)
1530{
1531 return platform_driver_register(&omap_i2c_driver);
1532}
1533subsys_initcall(omap_i2c_init_driver);
1534
1535static void __exit omap_i2c_exit_driver(void)
1536{
1537 platform_driver_unregister(&omap_i2c_driver);
1538}
1539module_exit(omap_i2c_exit_driver);
1540
1541MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
1542MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
1543MODULE_LICENSE("GPL");
f7bb0d9a 1544MODULE_ALIAS("platform:omap_i2c");
Linux kernel - Deliverables
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