projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
i2c: omap: re-factor omap_i2c_init function
[deliverable/linux.git] / drivers / i2c / busses / i2c-omap.c
CommitLineData
010d442c
KS		 1/*
2 * TI OMAP I2C master mode driver
3 *
4 * Copyright (C) 2003 MontaVista Software, Inc.
010d442c 5 * Copyright (C) 2005 Nokia Corporation
c1a473bd 6 * Copyright (C) 2004 - 2007 Texas Instruments.
010d442c 7 *
c1a473bd
TL		 8 * Originally written by MontaVista Software, Inc.
9 * Additional contributions by:
10 * Tony Lindgren <tony@atomide.com>
11 * Imre Deak <imre.deak@nokia.com>
12 * Juha Yrjölä <juha.yrjola@solidboot.com>
13 * Syed Khasim <x0khasim@ti.com>
14 * Nishant Menon <nm@ti.com>
010d442c
KS		 15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
30
31#include <linux/module.h>
32#include <linux/delay.h>
33#include <linux/i2c.h>
34#include <linux/err.h>
35#include <linux/interrupt.h>
36#include <linux/completion.h>
37#include <linux/platform_device.h>
38#include <linux/clk.h>
c1a473bd 39#include <linux/io.h>
6145197b
BC		 40#include <linux/of.h>
41#include <linux/of_i2c.h>
42#include <linux/of_device.h>
5a0e3ad6 43#include <linux/slab.h>
20c9d2c4 44#include <linux/i2c-omap.h>
27b1fec2 45#include <linux/pm_runtime.h>
2d4b4520 46#include <linux/pinctrl/consumer.h>
010d442c 47
9c76b878 48/* I2C controller revisions */
4e80f727 49#define OMAP_I2C_OMAP1_REV_2 0x20
9c76b878
PW		 50
51/* I2C controller revisions present on specific hardware */
47dcd016
S		 52#define OMAP_I2C_REV_ON_2430 0x00000036
53#define OMAP_I2C_REV_ON_3430_3530 0x0000003C
54#define OMAP_I2C_REV_ON_3630 0x00000040
55#define OMAP_I2C_REV_ON_4430_PLUS 0x50400002
9c76b878 56
010d442c
KS		 57/* timeout waiting for the controller to respond */
58#define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
59
6d8451d5
FB		 60/* timeout for pm runtime autosuspend */
61#define OMAP_I2C_PM_TIMEOUT 1000 /* ms */
62
5043e9e7 63/* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */
f38e66e0
SS		 64enum {
65 OMAP_I2C_REV_REG = 0,
66 OMAP_I2C_IE_REG,
67 OMAP_I2C_STAT_REG,
68 OMAP_I2C_IV_REG,
69 OMAP_I2C_WE_REG,
70 OMAP_I2C_SYSS_REG,
71 OMAP_I2C_BUF_REG,
72 OMAP_I2C_CNT_REG,
73 OMAP_I2C_DATA_REG,
74 OMAP_I2C_SYSC_REG,
75 OMAP_I2C_CON_REG,
76 OMAP_I2C_OA_REG,
77 OMAP_I2C_SA_REG,
78 OMAP_I2C_PSC_REG,
79 OMAP_I2C_SCLL_REG,
80 OMAP_I2C_SCLH_REG,
81 OMAP_I2C_SYSTEST_REG,
82 OMAP_I2C_BUFSTAT_REG,
b8853088
AG		 83 /* only on OMAP4430 */
84 OMAP_I2C_IP_V2_REVNB_LO,
85 OMAP_I2C_IP_V2_REVNB_HI,
86 OMAP_I2C_IP_V2_IRQSTATUS_RAW,
87 OMAP_I2C_IP_V2_IRQENABLE_SET,
88 OMAP_I2C_IP_V2_IRQENABLE_CLR,
f38e66e0 89};
010d442c
KS		 90
91/* I2C Interrupt Enable Register (OMAP_I2C_IE): */
b6ee52c3
NM		 92#define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */
93#define OMAP_I2C_IE_RDR (1 << 13) /* RX Buffer drain int enable */
010d442c
KS		 94#define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */
95#define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */
96#define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */
97#define OMAP_I2C_IE_NACK (1 << 1) /* No ack interrupt enable */
98#define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */
99
100/* I2C Status Register (OMAP_I2C_STAT): */
b6ee52c3
NM		 101#define OMAP_I2C_STAT_XDR (1 << 14) /* TX Buffer draining */
102#define OMAP_I2C_STAT_RDR (1 << 13) /* RX Buffer draining */
010d442c
KS		 103#define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */
104#define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */
105#define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
106#define OMAP_I2C_STAT_AAS (1 << 9) /* Address as slave */
107#define OMAP_I2C_STAT_AD0 (1 << 8) /* Address zero */
108#define OMAP_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
109#define OMAP_I2C_STAT_RRDY (1 << 3) /* Receive data ready */
110#define OMAP_I2C_STAT_ARDY (1 << 2) /* Register access ready */
111#define OMAP_I2C_STAT_NACK (1 << 1) /* No ack interrupt enable */
112#define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost int ena */
113
5043e9e7
KJ		 114/* I2C WE wakeup enable register */
115#define OMAP_I2C_WE_XDR_WE (1 << 14) /* TX drain wakup */
116#define OMAP_I2C_WE_RDR_WE (1 << 13) /* RX drain wakeup */
117#define OMAP_I2C_WE_AAS_WE (1 << 9) /* Address as slave wakeup*/
118#define OMAP_I2C_WE_BF_WE (1 << 8) /* Bus free wakeup */
119#define OMAP_I2C_WE_STC_WE (1 << 6) /* Start condition wakeup */
120#define OMAP_I2C_WE_GC_WE (1 << 5) /* General call wakeup */
121#define OMAP_I2C_WE_DRDY_WE (1 << 3) /* TX/RX data ready wakeup */
122#define OMAP_I2C_WE_ARDY_WE (1 << 2) /* Reg access ready wakeup */
123#define OMAP_I2C_WE_NACK_WE (1 << 1) /* No acknowledgment wakeup */
124#define OMAP_I2C_WE_AL_WE (1 << 0) /* Arbitration lost wakeup */
125
126#define OMAP_I2C_WE_ALL (OMAP_I2C_WE_XDR_WE | OMAP_I2C_WE_RDR_WE | \
127 OMAP_I2C_WE_AAS_WE | OMAP_I2C_WE_BF_WE | \
128 OMAP_I2C_WE_STC_WE | OMAP_I2C_WE_GC_WE | \
129 OMAP_I2C_WE_DRDY_WE | OMAP_I2C_WE_ARDY_WE | \
130 OMAP_I2C_WE_NACK_WE | OMAP_I2C_WE_AL_WE)
131
010d442c
KS		 132/* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
133#define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */
b6ee52c3 134#define OMAP_I2C_BUF_RXFIF_CLR (1 << 14) /* RX FIFO Clear */
010d442c 135#define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */
b6ee52c3 136#define OMAP_I2C_BUF_TXFIF_CLR (1 << 6) /* TX FIFO Clear */
010d442c
KS		 137
138/* I2C Configuration Register (OMAP_I2C_CON): */
139#define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */
140#define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */
b6ee52c3 141#define OMAP_I2C_CON_OPMODE_HS (1 << 12) /* High Speed support */
010d442c
KS		 142#define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */
143#define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */
144#define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */
145#define OMAP_I2C_CON_XA (1 << 8) /* Expand address */
146#define OMAP_I2C_CON_RM (1 << 2) /* Repeat mode (master only) */
147#define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */
148#define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */
149
4574eb68
SMK		 150/* I2C SCL time value when Master */
151#define OMAP_I2C_SCLL_HSSCLL 8
152#define OMAP_I2C_SCLH_HSSCLH 8
153
010d442c
KS		 154/* I2C System Test Register (OMAP_I2C_SYSTEST): */
155#ifdef DEBUG
156#define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */
157#define OMAP_I2C_SYSTEST_FREE (1 << 14) /* Free running mode */
158#define OMAP_I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */
159#define OMAP_I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */
160#define OMAP_I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense in */
161#define OMAP_I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive out */
162#define OMAP_I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense in */
163#define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */
164#endif
165
fdd07fe6
PW		 166/* OCP_SYSSTATUS bit definitions */
167#define SYSS_RESETDONE_MASK (1 << 0)
168
169/* OCP_SYSCONFIG bit definitions */
170#define SYSC_CLOCKACTIVITY_MASK (0x3 << 8)
171#define SYSC_SIDLEMODE_MASK (0x3 << 3)
172#define SYSC_ENAWAKEUP_MASK (1 << 2)
173#define SYSC_SOFTRESET_MASK (1 << 1)
174#define SYSC_AUTOIDLE_MASK (1 << 0)
175
176#define SYSC_IDLEMODE_SMART 0x2
177#define SYSC_CLOCKACTIVITY_FCLK 0x2
010d442c 178
f3083d92 179/* Errata definitions */
180#define I2C_OMAP_ERRATA_I207 (1 << 0)
c8db38f0 181#define I2C_OMAP_ERRATA_I462 (1 << 1)
010d442c 182
010d442c 183struct omap_i2c_dev {
3b2f8f82 184 spinlock_t lock; /* IRQ synchronization */
010d442c
KS		 185 struct device *dev;
186 void __iomem *base; /* virtual */
187 int irq;
d84d3ea3 188 int reg_shift; /* bit shift for I2C register addresses */
010d442c
KS		 189 struct completion cmd_complete;
190 struct resource *ioarea;
49839dc9
PW		 191 u32 latency; /* maximum mpu wkup latency */
192 void (*set_mpu_wkup_lat)(struct device *dev,
193 long latency);
6145197b 194 u32 speed; /* Speed of bus in kHz */
6145197b 195 u32 flags;
010d442c
KS		 196 u16 cmd_err;
197 u8 *buf;
f38e66e0 198 u8 *regs;
010d442c
KS		 199 size_t buf_len;
200 struct i2c_adapter adapter;
dd74548d 201 u8 threshold;
b6ee52c3
NM		 202 u8 fifo_size; /* use as flag and value
203 * fifo_size==0 implies no fifo
204 * if set, should be trsh+1
205 */
47dcd016 206 u32 rev;
b6ee52c3 207 unsigned b_hw:1; /* bad h/w fixes */
079d8af2 208 unsigned receiver:1; /* true when we're in receiver mode */
f08ac4e7 209 u16 iestate; /* Saved interrupt register */
ef871432
RN		 210 u16 pscstate;
211 u16 scllstate;
212 u16 sclhstate;
ef871432
RN		 213 u16 syscstate;
214 u16 westate;
f3083d92 215 u16 errata;
2d4b4520
SG		 216
217 struct pinctrl *pins;
010d442c
KS		 218};
219
a1295577 220static const u8 reg_map_ip_v1[] = {
f38e66e0
SS		 221 [OMAP_I2C_REV_REG] = 0x00,
222 [OMAP_I2C_IE_REG] = 0x01,
223 [OMAP_I2C_STAT_REG] = 0x02,
224 [OMAP_I2C_IV_REG] = 0x03,
225 [OMAP_I2C_WE_REG] = 0x03,
226 [OMAP_I2C_SYSS_REG] = 0x04,
227 [OMAP_I2C_BUF_REG] = 0x05,
228 [OMAP_I2C_CNT_REG] = 0x06,
229 [OMAP_I2C_DATA_REG] = 0x07,
230 [OMAP_I2C_SYSC_REG] = 0x08,
231 [OMAP_I2C_CON_REG] = 0x09,
232 [OMAP_I2C_OA_REG] = 0x0a,
233 [OMAP_I2C_SA_REG] = 0x0b,
234 [OMAP_I2C_PSC_REG] = 0x0c,
235 [OMAP_I2C_SCLL_REG] = 0x0d,
236 [OMAP_I2C_SCLH_REG] = 0x0e,
237 [OMAP_I2C_SYSTEST_REG] = 0x0f,
238 [OMAP_I2C_BUFSTAT_REG] = 0x10,
239};
240
a1295577 241static const u8 reg_map_ip_v2[] = {
f38e66e0
SS		 242 [OMAP_I2C_REV_REG] = 0x04,
243 [OMAP_I2C_IE_REG] = 0x2c,
244 [OMAP_I2C_STAT_REG] = 0x28,
245 [OMAP_I2C_IV_REG] = 0x34,
246 [OMAP_I2C_WE_REG] = 0x34,
247 [OMAP_I2C_SYSS_REG] = 0x90,
248 [OMAP_I2C_BUF_REG] = 0x94,
249 [OMAP_I2C_CNT_REG] = 0x98,
250 [OMAP_I2C_DATA_REG] = 0x9c,
2727b175 251 [OMAP_I2C_SYSC_REG] = 0x10,
f38e66e0
SS		 252 [OMAP_I2C_CON_REG] = 0xa4,
253 [OMAP_I2C_OA_REG] = 0xa8,
254 [OMAP_I2C_SA_REG] = 0xac,
255 [OMAP_I2C_PSC_REG] = 0xb0,
256 [OMAP_I2C_SCLL_REG] = 0xb4,
257 [OMAP_I2C_SCLH_REG] = 0xb8,
258 [OMAP_I2C_SYSTEST_REG] = 0xbC,
259 [OMAP_I2C_BUFSTAT_REG] = 0xc0,
b8853088
AG		 260 [OMAP_I2C_IP_V2_REVNB_LO] = 0x00,
261 [OMAP_I2C_IP_V2_REVNB_HI] = 0x04,
262 [OMAP_I2C_IP_V2_IRQSTATUS_RAW] = 0x24,
263 [OMAP_I2C_IP_V2_IRQENABLE_SET] = 0x2c,
264 [OMAP_I2C_IP_V2_IRQENABLE_CLR] = 0x30,
f38e66e0
SS		 265};
266
010d442c
KS		 267static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev,
268 int reg, u16 val)
269{
f38e66e0
SS		 270 __raw_writew(val, i2c_dev->base +
271 (i2c_dev->regs[reg] << i2c_dev->reg_shift));
010d442c
KS		 272}
273
274static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
275{
f38e66e0
SS		 276 return __raw_readw(i2c_dev->base +
277 (i2c_dev->regs[reg] << i2c_dev->reg_shift));
010d442c
KS		 278}
279
95dd3032
S		 280static void __omap_i2c_init(struct omap_i2c_dev *dev)
281{
282
283 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
284
285 /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
286 omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, dev->pscstate);
287
288 /* SCL low and high time values */
289 omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, dev->scllstate);
290 omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, dev->sclhstate);
291 if (dev->rev >= OMAP_I2C_REV_ON_3430_3530)
292 omap_i2c_write_reg(dev, OMAP_I2C_WE_REG, dev->westate);
293
294 /* Take the I2C module out of reset: */
295 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
296
297 /*
298 * Don't write to this register if the IE state is 0 as it can
299 * cause deadlock.
300 */
301 if (dev->iestate)
302 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
303}
304
010d442c
KS		 305static int omap_i2c_init(struct omap_i2c_dev *dev)
306{
95dd3032 307 u16 psc = 0, scll = 0, sclh = 0;
4574eb68 308 u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
010d442c
KS		 309 unsigned long fclk_rate = 12000000;
310 unsigned long timeout;
4574eb68 311 unsigned long internal_clk = 0;
27b1fec2 312 struct clk *fclk;
010d442c 313
4e80f727 314 if (dev->rev >= OMAP_I2C_OMAP1_REV_2) {
57eb81b1
MG		 315 /* Disable I2C controller before soft reset */
316 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
317 omap_i2c_read_reg(dev, OMAP_I2C_CON_REG) &
318 ~(OMAP_I2C_CON_EN));
319
fdd07fe6 320 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK);
010d442c
KS		 321 /* For some reason we need to set the EN bit before the
322 * reset done bit gets set. */
323 timeout = jiffies + OMAP_I2C_TIMEOUT;
324 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
325 while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) &
fdd07fe6 326 SYSS_RESETDONE_MASK)) {
010d442c 327 if (time_after(jiffies, timeout)) {
fce3ff03 328 dev_warn(dev->dev, "timeout waiting "
010d442c
KS		 329 "for controller reset\n");
330 return -ETIMEDOUT;
331 }
332 msleep(1);
333 }
fdd07fe6
PW		 334
335 /* SYSC register is cleared by the reset; rewrite it */
336 if (dev->rev == OMAP_I2C_REV_ON_2430) {
337
338 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG,
339 SYSC_AUTOIDLE_MASK);
340
f518b482 341 } else if (dev->rev >= OMAP_I2C_REV_ON_3430_3530) {
ef871432
RN		 342 dev->syscstate = SYSC_AUTOIDLE_MASK;
343 dev->syscstate |= SYSC_ENAWAKEUP_MASK;
344 dev->syscstate |= (SYSC_IDLEMODE_SMART <<
fdd07fe6 345 __ffs(SYSC_SIDLEMODE_MASK));
ef871432 346 dev->syscstate |= (SYSC_CLOCKACTIVITY_FCLK <<
fdd07fe6
PW		 347 __ffs(SYSC_CLOCKACTIVITY_MASK));
348
ef871432
RN		 349 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG,
350 dev->syscstate);
5043e9e7
KJ		 351 /*
352 * Enabling all wakup sources to stop I2C freezing on
353 * WFI instruction.
354 * REVISIT: Some wkup sources might not be needed.
355 */
ef871432 356 dev->westate = OMAP_I2C_WE_ALL;
fdd07fe6 357 }
010d442c 358 }
010d442c 359
6145197b 360 if (dev->flags & OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK) {
0e9ae109
RK		 361 /*
362 * The I2C functional clock is the armxor_ck, so there's
363 * no need to get "armxor_ck" separately. Now, if OMAP2420
364 * always returns 12MHz for the functional clock, we can
365 * do this bit unconditionally.
366 */
27b1fec2
RN		 367 fclk = clk_get(dev->dev, "fck");
368 fclk_rate = clk_get_rate(fclk);
369 clk_put(fclk);
0e9ae109 370
010d442c
KS		 371 /* TRM for 5912 says the I2C clock must be prescaled to be
372 * between 7 - 12 MHz. The XOR input clock is typically
373 * 12, 13 or 19.2 MHz. So we should have code that produces:
374 *
375 * XOR MHz Divider Prescaler
376 * 12 1 0
377 * 13 2 1
378 * 19.2 2 1
379 */
d7aef138
JD		 380 if (fclk_rate > 12000000)
381 psc = fclk_rate / 12000000;
010d442c
KS		 382 }
383
6145197b 384 if (!(dev->flags & OMAP_I2C_FLAG_SIMPLE_CLOCK)) {
4574eb68 385
84bf2c86
AK		 386 /*
387 * HSI2C controller internal clk rate should be 19.2 Mhz for
388 * HS and for all modes on 2430. On 34xx we can use lower rate
389 * to get longer filter period for better noise suppression.
390 * The filter is iclk (fclk for HS) period.
391 */
3be0053e 392 if (dev->speed > 400 ||
6145197b 393 dev->flags & OMAP_I2C_FLAG_FORCE_19200_INT_CLK)
84bf2c86
AK		 394 internal_clk = 19200;
395 else if (dev->speed > 100)
396 internal_clk = 9600;
397 else
398 internal_clk = 4000;
27b1fec2
RN		 399 fclk = clk_get(dev->dev, "fck");
400 fclk_rate = clk_get_rate(fclk) / 1000;
401 clk_put(fclk);
4574eb68
SMK		 402
403 /* Compute prescaler divisor */
404 psc = fclk_rate / internal_clk;
405 psc = psc - 1;
406
407 /* If configured for High Speed */
408 if (dev->speed > 400) {
baf46b4e
AK		 409 unsigned long scl;
410
4574eb68 411 /* For first phase of HS mode */
baf46b4e
AK		 412 scl = internal_clk / 400;
413 fsscll = scl - (scl / 3) - 7;
414 fssclh = (scl / 3) - 5;
4574eb68
SMK		 415
416 /* For second phase of HS mode */
baf46b4e
AK		 417 scl = fclk_rate / dev->speed;
418 hsscll = scl - (scl / 3) - 7;
419 hssclh = (scl / 3) - 5;
420 } else if (dev->speed > 100) {
421 unsigned long scl;
422
423 /* Fast mode */
424 scl = internal_clk / dev->speed;
425 fsscll = scl - (scl / 3) - 7;
426 fssclh = (scl / 3) - 5;
4574eb68 427 } else {
baf46b4e
AK		 428 /* Standard mode */
429 fsscll = internal_clk / (dev->speed * 2) - 7;
430 fssclh = internal_clk / (dev->speed * 2) - 5;
4574eb68
SMK		 431 }
432 scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
433 sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
434 } else {
435 /* Program desired operating rate */
436 fclk_rate /= (psc + 1) * 1000;
437 if (psc > 2)
438 psc = 2;
439 scll = fclk_rate / (dev->speed * 2) - 7 + psc;
440 sclh = fclk_rate / (dev->speed * 2) - 7 + psc;
441 }
442
ef871432 443 dev->iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
c1a473bd
TL		 444 OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
445 OMAP_I2C_IE_AL) | ((dev->fifo_size) ?
ef871432 446 (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0);
95dd3032
S		 447
448 dev->pscstate = psc;
449 dev->scllstate = scll;
450 dev->sclhstate = sclh;
451
452 __omap_i2c_init(dev);
453
010d442c
KS		 454 return 0;
455}
456
457/*
458 * Waiting on Bus Busy
459 */
460static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev)
461{
462 unsigned long timeout;
463
464 timeout = jiffies + OMAP_I2C_TIMEOUT;
465 while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
466 if (time_after(jiffies, timeout)) {
467 dev_warn(dev->dev, "timeout waiting for bus ready\n");
468 return -ETIMEDOUT;
469 }
470 msleep(1);
471 }
472
473 return 0;
474}
475
dd74548d
FB		 476static void omap_i2c_resize_fifo(struct omap_i2c_dev *dev, u8 size, bool is_rx)
477{
478 u16 buf;
479
480 if (dev->flags & OMAP_I2C_FLAG_NO_FIFO)
481 return;
482
483 /*
484 * Set up notification threshold based on message size. We're doing
485 * this to try and avoid draining feature as much as possible. Whenever
486 * we have big messages to transfer (bigger than our total fifo size)
487 * then we might use draining feature to transfer the remaining bytes.
488 */
489
490 dev->threshold = clamp(size, (u8) 1, dev->fifo_size);
491
492 buf = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
493
494 if (is_rx) {
495 /* Clear RX Threshold */
496 buf &= ~(0x3f << 8);
497 buf |= ((dev->threshold - 1) << 8) | OMAP_I2C_BUF_RXFIF_CLR;
498 } else {
499 /* Clear TX Threshold */
500 buf &= ~0x3f;
501 buf |= (dev->threshold - 1) | OMAP_I2C_BUF_TXFIF_CLR;
502 }
503
504 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, buf);
505
47dcd016 506 if (dev->rev < OMAP_I2C_REV_ON_3630)
dd74548d
FB		 507 dev->b_hw = 1; /* Enable hardware fixes */
508
509 /* calculate wakeup latency constraint for MPU */
49839dc9
PW		 510 if (dev->set_mpu_wkup_lat != NULL)
511 dev->latency = (1000000 * dev->threshold) /
512 (1000 * dev->speed / 8);
dd74548d
FB		 513}
514
010d442c
KS		 515/*
516 * Low level master read/write transaction.
517 */
518static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
519 struct i2c_msg *msg, int stop)
520{
521 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
33d54985 522 unsigned long timeout;
010d442c
KS		 523 u16 w;
524
525 dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
526 msg->addr, msg->len, msg->flags, stop);
527
528 if (msg->len == 0)
529 return -EINVAL;
530
dd74548d
FB		 531 dev->receiver = !!(msg->flags & I2C_M_RD);
532 omap_i2c_resize_fifo(dev, msg->len, dev->receiver);
533
010d442c
KS		 534 omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);
535
536 /* REVISIT: Could the STB bit of I2C_CON be used with probing? */
537 dev->buf = msg->buf;
538 dev->buf_len = msg->len;
539
d60ece5f
FB		 540 /* make sure writes to dev->buf_len are ordered */
541 barrier();
542
010d442c
KS		 543 omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len);
544
b6ee52c3
NM		 545 /* Clear the FIFO Buffers */
546 w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
547 w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR;
548 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w);
549
0e33bbb2 550 INIT_COMPLETION(dev->cmd_complete);
010d442c
KS		 551 dev->cmd_err = 0;
552
553 w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
4574eb68
SMK		 554
555 /* High speed configuration */
556 if (dev->speed > 400)
b6ee52c3 557 w |= OMAP_I2C_CON_OPMODE_HS;
4574eb68 558
fb604a3d
LP		 559 if (msg->flags & I2C_M_STOP)
560 stop = 1;
010d442c
KS		 561 if (msg->flags & I2C_M_TEN)
562 w |= OMAP_I2C_CON_XA;
563 if (!(msg->flags & I2C_M_RD))
564 w |= OMAP_I2C_CON_TRX;
c1a473bd 565
b6ee52c3 566 if (!dev->b_hw && stop)
010d442c 567 w |= OMAP_I2C_CON_STP;
c1a473bd 568
010d442c
KS		 569 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
570
b6ee52c3
NM		 571 /*
572 * Don't write stt and stp together on some hardware.
573 */
574 if (dev->b_hw && stop) {
575 unsigned long delay = jiffies + OMAP_I2C_TIMEOUT;
576 u16 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
577 while (con & OMAP_I2C_CON_STT) {
578 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
579
580 /* Let the user know if i2c is in a bad state */
581 if (time_after(jiffies, delay)) {
582 dev_err(dev->dev, "controller timed out "
583 "waiting for start condition to finish\n");
584 return -ETIMEDOUT;
585 }
586 cpu_relax();
587 }
588
589 w |= OMAP_I2C_CON_STP;
590 w &= ~OMAP_I2C_CON_STT;
591 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
592 }
593
b7af349b
JN		 594 /*
595 * REVISIT: We should abort the transfer on signals, but the bus goes
596 * into arbitration and we're currently unable to recover from it.
597 */
33d54985
S		 598 timeout = wait_for_completion_timeout(&dev->cmd_complete,
599 OMAP_I2C_TIMEOUT);
33d54985 600 if (timeout == 0) {
010d442c
KS		 601 dev_err(dev->dev, "controller timed out\n");
602 omap_i2c_init(dev);
603 return -ETIMEDOUT;
604 }
605
606 if (likely(!dev->cmd_err))
607 return 0;
608
609 /* We have an error */
610 if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR |
611 OMAP_I2C_STAT_XUDF)) {
612 omap_i2c_init(dev);
613 return -EIO;
614 }
615
616 if (dev->cmd_err & OMAP_I2C_STAT_NACK) {
617 if (msg->flags & I2C_M_IGNORE_NAK)
618 return 0;
619 if (stop) {
620 w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
621 w |= OMAP_I2C_CON_STP;
622 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
623 }
624 return -EREMOTEIO;
625 }
626 return -EIO;
627}
628
629
630/*
631 * Prepare controller for a transaction and call omap_i2c_xfer_msg
632 * to do the work during IRQ processing.
633 */
634static int
635omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
636{
637 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
638 int i;
639 int r;
640
3b0fb97c
S		 641 r = pm_runtime_get_sync(dev->dev);
642 if (IS_ERR_VALUE(r))
33ec5e81 643 goto out;
010d442c 644
c1a473bd
TL		 645 r = omap_i2c_wait_for_bb(dev);
646 if (r < 0)
010d442c
KS		 647 goto out;
648
49839dc9
PW		 649 if (dev->set_mpu_wkup_lat != NULL)
650 dev->set_mpu_wkup_lat(dev->dev, dev->latency);
6a91b558 651
010d442c
KS		 652 for (i = 0; i < num; i++) {
653 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));
654 if (r != 0)
655 break;
656 }
657
49839dc9
PW		 658 if (dev->set_mpu_wkup_lat != NULL)
659 dev->set_mpu_wkup_lat(dev->dev, -1);
6a91b558 660
010d442c
KS		 661 if (r == 0)
662 r = num;
5c64eb26
MN		 663
664 omap_i2c_wait_for_bb(dev);
010d442c 665out:
6d8451d5
FB		 666 pm_runtime_mark_last_busy(dev->dev);
667 pm_runtime_put_autosuspend(dev->dev);
010d442c
KS		 668 return r;
669}
670
671static u32
672omap_i2c_func(struct i2c_adapter *adap)
673{
fb604a3d
LP		 674 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
675 I2C_FUNC_PROTOCOL_MANGLING;
010d442c
KS		 676}
677
678static inline void
679omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err)
680{
681 dev->cmd_err |= err;
682 complete(&dev->cmd_complete);
683}
684
685static inline void
686omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat)
687{
688 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
689}
690
f3083d92 691static inline void i2c_omap_errata_i207(struct omap_i2c_dev *dev, u16 stat)
692{
693 /*
694 * I2C Errata(Errata Nos. OMAP2: 1.67, OMAP3: 1.8)
695 * Not applicable for OMAP4.
696 * Under certain rare conditions, RDR could be set again
697 * when the bus is busy, then ignore the interrupt and
698 * clear the interrupt.
699 */
700 if (stat & OMAP_I2C_STAT_RDR) {
701 /* Step 1: If RDR is set, clear it */
702 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
703
704 /* Step 2: */
705 if (!(omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG)
706 & OMAP_I2C_STAT_BB)) {
707
708 /* Step 3: */
709 if (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG)
710 & OMAP_I2C_STAT_RDR) {
711 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
712 dev_dbg(dev->dev, "RDR when bus is busy.\n");
713 }
714
715 }
716 }
717}
718
43469d8e
PW		 719/* rev1 devices are apparently only on some 15xx */
720#ifdef CONFIG_ARCH_OMAP15XX
721
010d442c 722static irqreturn_t
4e80f727 723omap_i2c_omap1_isr(int this_irq, void *dev_id)
010d442c
KS		 724{
725 struct omap_i2c_dev *dev = dev_id;
726 u16 iv, w;
727
fab67afb 728 if (pm_runtime_suspended(dev->dev))
f08ac4e7
TL		 729 return IRQ_NONE;
730
010d442c
KS		 731 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
732 switch (iv) {
733 case 0x00: /* None */
734 break;
735 case 0x01: /* Arbitration lost */
736 dev_err(dev->dev, "Arbitration lost\n");
737 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
738 break;
739 case 0x02: /* No acknowledgement */
740 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
741 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
742 break;
743 case 0x03: /* Register access ready */
744 omap_i2c_complete_cmd(dev, 0);
745 break;
746 case 0x04: /* Receive data ready */
747 if (dev->buf_len) {
748 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
749 *dev->buf++ = w;
750 dev->buf_len--;
751 if (dev->buf_len) {
752 *dev->buf++ = w >> 8;
753 dev->buf_len--;
754 }
755 } else
756 dev_err(dev->dev, "RRDY IRQ while no data requested\n");
757 break;
758 case 0x05: /* Transmit data ready */
759 if (dev->buf_len) {
760 w = *dev->buf++;
761 dev->buf_len--;
762 if (dev->buf_len) {
763 w |= *dev->buf++ << 8;
764 dev->buf_len--;
765 }
766 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
767 } else
768 dev_err(dev->dev, "XRDY IRQ while no data to send\n");
769 break;
770 default:
771 return IRQ_NONE;
772 }
773
774 return IRQ_HANDLED;
775}
43469d8e 776#else
4e80f727 777#define omap_i2c_omap1_isr NULL
43469d8e 778#endif
010d442c 779
2dd151ab 780/*
c8db38f0 781 * OMAP3430 Errata i462: When an XRDY/XDR is hit, wait for XUDF before writing
2dd151ab
AS		 782 * data to DATA_REG. Otherwise some data bytes can be lost while transferring
783 * them from the memory to the I2C interface.
784 */
4151e741 785static int errata_omap3_i462(struct omap_i2c_dev *dev)
2dd151ab 786{
e9f59b9c 787 unsigned long timeout = 10000;
4151e741 788 u16 stat;
e9f59b9c 789
4151e741
FB		 790 do {
791 stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
792 if (stat & OMAP_I2C_STAT_XUDF)
793 break;
794
795 if (stat & (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) {
540a4790 796 omap_i2c_ack_stat(dev, (OMAP_I2C_STAT_XRDY |
2dd151ab 797 OMAP_I2C_STAT_XDR));
b07be0f3
FB		 798 if (stat & OMAP_I2C_STAT_NACK) {
799 dev->cmd_err |= OMAP_I2C_STAT_NACK;
800 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_NACK);
801 }
802
803 if (stat & OMAP_I2C_STAT_AL) {
804 dev_err(dev->dev, "Arbitration lost\n");
805 dev->cmd_err |= OMAP_I2C_STAT_AL;
806 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_NACK);
807 }
808
4151e741 809 return -EIO;
2dd151ab 810 }
e9f59b9c 811
2dd151ab 812 cpu_relax();
4151e741 813 } while (--timeout);
2dd151ab 814
e9f59b9c
AS		 815 if (!timeout) {
816 dev_err(dev->dev, "timeout waiting on XUDF bit\n");
817 return 0;
818 }
819
2dd151ab
AS		 820 return 0;
821}
822
3312d25e
FB		 823static void omap_i2c_receive_data(struct omap_i2c_dev *dev, u8 num_bytes,
824 bool is_rdr)
825{
826 u16 w;
827
828 while (num_bytes--) {
3312d25e
FB		 829 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
830 *dev->buf++ = w;
831 dev->buf_len--;
832
833 /*
834 * Data reg in 2430, omap3 and
835 * omap4 is 8 bit wide
836 */
837 if (dev->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) {
dd74548d
FB		 838 *dev->buf++ = w >> 8;
839 dev->buf_len--;
3312d25e
FB		 840 }
841 }
842}
843
844static int omap_i2c_transmit_data(struct omap_i2c_dev *dev, u8 num_bytes,
845 bool is_xdr)
846{
847 u16 w;
848
849 while (num_bytes--) {
3312d25e
FB		 850 w = *dev->buf++;
851 dev->buf_len--;
852
853 /*
854 * Data reg in 2430, omap3 and
855 * omap4 is 8 bit wide
856 */
857 if (dev->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) {
dd74548d
FB		 858 w |= *dev->buf++ << 8;
859 dev->buf_len--;
3312d25e
FB		 860 }
861
862 if (dev->errata & I2C_OMAP_ERRATA_I462) {
863 int ret;
864
865 ret = errata_omap3_i462(dev);
866 if (ret < 0)
867 return ret;
868 }
869
870 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
871 }
872
873 return 0;
874}
875
010d442c 876static irqreturn_t
3b2f8f82 877omap_i2c_isr(int irq, void *dev_id)
010d442c
KS		 878{
879 struct omap_i2c_dev *dev = dev_id;
3b2f8f82
FB		 880 irqreturn_t ret = IRQ_HANDLED;
881 u16 mask;
882 u16 stat;
883
884 spin_lock(&dev->lock);
885 mask = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
886 stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
887
888 if (stat & mask)
889 ret = IRQ_WAKE_THREAD;
890
891 spin_unlock(&dev->lock);
892
893 return ret;
894}
895
010d442c 896static irqreturn_t
3b2f8f82 897omap_i2c_isr_thread(int this_irq, void *dev_id)
010d442c
KS		 898{
899 struct omap_i2c_dev *dev = dev_id;
3b2f8f82 900 unsigned long flags;
010d442c 901 u16 bits;
3312d25e 902 u16 stat;
66b92988 903 int err = 0, count = 0;
010d442c 904
3b2f8f82 905 spin_lock_irqsave(&dev->lock, flags);
66b92988
FB		 906 do {
907 bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
908 stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
909 stat &= bits;
910
079d8af2
FB		 911 /* If we're in receiver mode, ignore XDR/XRDY */
912 if (dev->receiver)
913 stat &= ~(OMAP_I2C_STAT_XDR | OMAP_I2C_STAT_XRDY);
914 else
915 stat &= ~(OMAP_I2C_STAT_RDR | OMAP_I2C_STAT_RRDY);
010d442c 916
66b92988
FB		 917 if (!stat) {
918 /* my work here is done */
0bdfe0cb 919 goto out;
66b92988 920 }
f08ac4e7 921
010d442c
KS		 922 dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat);
923 if (count++ == 100) {
924 dev_warn(dev->dev, "Too much work in one IRQ\n");
925 break;
926 }
927
1d7afc95 928 if (stat & OMAP_I2C_STAT_NACK) {
b6ee52c3 929 err |= OMAP_I2C_STAT_NACK;
1d7afc95 930 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_NACK);
0bdfe0cb 931 break;
1d7afc95 932 }
78e1cf42 933
b6ee52c3
NM		 934 if (stat & OMAP_I2C_STAT_AL) {
935 dev_err(dev->dev, "Arbitration lost\n");
936 err |= OMAP_I2C_STAT_AL;
1d7afc95 937 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_AL);
0bdfe0cb 938 break;
b6ee52c3 939 }
c55edb99 940
a5a595cc 941 /*
cb527ede 942 * ProDB0017052: Clear ARDY bit twice
a5a595cc 943 */
b6ee52c3 944 if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
04c688dd 945 OMAP_I2C_STAT_AL)) {
540a4790
FB		 946 omap_i2c_ack_stat(dev, (OMAP_I2C_STAT_RRDY |
947 OMAP_I2C_STAT_RDR |
948 OMAP_I2C_STAT_XRDY |
949 OMAP_I2C_STAT_XDR |
950 OMAP_I2C_STAT_ARDY));
0bdfe0cb 951 break;
04c688dd 952 }
c55edb99 953
6d9939f6 954 if (stat & OMAP_I2C_STAT_RDR) {
b6ee52c3 955 u8 num_bytes = 1;
f3083d92 956
6d9939f6
FB		 957 if (dev->fifo_size)
958 num_bytes = dev->buf_len;
959
3312d25e 960 omap_i2c_receive_data(dev, num_bytes, true);
6d9939f6 961
f3083d92 962 if (dev->errata & I2C_OMAP_ERRATA_I207)
963 i2c_omap_errata_i207(dev, stat);
964
6d9939f6 965 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
0bdfe0cb 966 break;
6d9939f6
FB		 967 }
968
969 if (stat & OMAP_I2C_STAT_RRDY) {
970 u8 num_bytes = 1;
971
dd74548d
FB		 972 if (dev->threshold)
973 num_bytes = dev->threshold;
6d9939f6 974
3312d25e 975 omap_i2c_receive_data(dev, num_bytes, false);
6d9939f6 976 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RRDY);
010d442c
KS		 977 continue;
978 }
c55edb99 979
6d9939f6 980 if (stat & OMAP_I2C_STAT_XDR) {
b6ee52c3 981 u8 num_bytes = 1;
3312d25e 982 int ret;
6d9939f6
FB		 983
984 if (dev->fifo_size)
985 num_bytes = dev->buf_len;
986
3312d25e 987 ret = omap_i2c_transmit_data(dev, num_bytes, true);
3312d25e 988 if (ret < 0)
0bdfe0cb 989 break;
6d9939f6
FB		 990
991 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XDR);
0bdfe0cb 992 break;
6d9939f6
FB		 993 }
994
995 if (stat & OMAP_I2C_STAT_XRDY) {
996 u8 num_bytes = 1;
3312d25e 997 int ret;
6d9939f6 998
dd74548d
FB		 999 if (dev->threshold)
1000 num_bytes = dev->threshold;
6d9939f6 1001
3312d25e 1002 ret = omap_i2c_transmit_data(dev, num_bytes, false);
3312d25e 1003 if (ret < 0)
0bdfe0cb 1004 break;
6d9939f6
FB		 1005
1006 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XRDY);
010d442c
KS		 1007 continue;
1008 }
c55edb99 1009
010d442c
KS		 1010 if (stat & OMAP_I2C_STAT_ROVR) {
1011 dev_err(dev->dev, "Receive overrun\n");
1d7afc95
FB		 1012 err |= OMAP_I2C_STAT_ROVR;
1013 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_ROVR);
0bdfe0cb 1014 break;
010d442c 1015 }
c55edb99 1016
010d442c 1017 if (stat & OMAP_I2C_STAT_XUDF) {
b6ee52c3 1018 dev_err(dev->dev, "Transmit underflow\n");
1d7afc95
FB		 1019 err |= OMAP_I2C_STAT_XUDF;
1020 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XUDF);
0bdfe0cb 1021 break;
010d442c 1022 }
66b92988 1023 } while (stat);
010d442c 1024
4a7ec4ed 1025 omap_i2c_complete_cmd(dev, err);
0bdfe0cb
FB		 1026
1027out:
3b2f8f82 1028 spin_unlock_irqrestore(&dev->lock, flags);
010d442c 1029
6a85ced2 1030 return IRQ_HANDLED;
010d442c
KS		 1031}
1032
8f9082c5 1033static const struct i2c_algorithm omap_i2c_algo = {
010d442c
KS		 1034 .master_xfer = omap_i2c_xfer,
1035 .functionality = omap_i2c_func,
1036};
1037
6145197b
BC		 1038#ifdef CONFIG_OF
1039static struct omap_i2c_bus_platform_data omap3_pdata = {
1040 .rev = OMAP_I2C_IP_VERSION_1,
2c88ab8c 1041 .flags = OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
6145197b
BC		 1042 OMAP_I2C_FLAG_BUS_SHIFT_2,
1043};
1044
1045static struct omap_i2c_bus_platform_data omap4_pdata = {
1046 .rev = OMAP_I2C_IP_VERSION_2,
1047};
1048
1049static const struct of_device_id omap_i2c_of_match[] = {
1050 {
1051 .compatible = "ti,omap4-i2c",
1052 .data = &omap4_pdata,
1053 },
1054 {
1055 .compatible = "ti,omap3-i2c",
1056 .data = &omap3_pdata,
1057 },
1058 { },
1059};
1060MODULE_DEVICE_TABLE(of, omap_i2c_of_match);
1061#endif
1062
47dcd016
S		 1063#define OMAP_I2C_SCHEME(rev) ((rev & 0xc000) >> 14)
1064
1065#define OMAP_I2C_REV_SCHEME_0_MAJOR(rev) (rev >> 4)
1066#define OMAP_I2C_REV_SCHEME_0_MINOR(rev) (rev & 0xf)
1067
1068#define OMAP_I2C_REV_SCHEME_1_MAJOR(rev) ((rev & 0x0700) >> 7)
1069#define OMAP_I2C_REV_SCHEME_1_MINOR(rev) (rev & 0x1f)
1070#define OMAP_I2C_SCHEME_0 0
1071#define OMAP_I2C_SCHEME_1 1
1072
1139aea9 1073static int __devinit
010d442c
KS		 1074omap_i2c_probe(struct platform_device *pdev)
1075{
1076 struct omap_i2c_dev *dev;
1077 struct i2c_adapter *adap;
ac79e4b2 1078 struct resource *mem;
c4dba011
UKK		 1079 const struct omap_i2c_bus_platform_data *pdata =
1080 pdev->dev.platform_data;
6145197b
BC		 1081 struct device_node *node = pdev->dev.of_node;
1082 const struct of_device_id *match;
ac79e4b2 1083 int irq;
010d442c 1084 int r;
47dcd016 1085 u32 rev;
cd10c74a 1086 u16 minor, major, scheme;
010d442c
KS		 1087
1088 /* NOTE: driver uses the static register mapping */
1089 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1090 if (!mem) {
1091 dev_err(&pdev->dev, "no mem resource?\n");
1092 return -ENODEV;
1093 }
ac79e4b2
FB		 1094
1095 irq = platform_get_irq(pdev, 0);
1096 if (irq < 0) {
010d442c 1097 dev_err(&pdev->dev, "no irq resource?\n");
ac79e4b2 1098 return irq;
010d442c
KS		 1099 }
1100
d9ebd04d
FB		 1101 dev = devm_kzalloc(&pdev->dev, sizeof(struct omap_i2c_dev), GFP_KERNEL);
1102 if (!dev) {
1103 dev_err(&pdev->dev, "Menory allocation failed\n");
1104 return -ENOMEM;
010d442c
KS		 1105 }
1106
d9ebd04d
FB		 1107 dev->base = devm_request_and_ioremap(&pdev->dev, mem);
1108 if (!dev->base) {
1109 dev_err(&pdev->dev, "I2C region already claimed\n");
1110 return -ENOMEM;
010d442c
KS		 1111 }
1112
6c5aa407 1113 match = of_match_device(of_match_ptr(omap_i2c_of_match), &pdev->dev);
6145197b
BC		 1114 if (match) {
1115 u32 freq = 100000; /* default to 100000 Hz */
1116
1117 pdata = match->data;
6145197b
BC		 1118 dev->flags = pdata->flags;
1119
1120 of_property_read_u32(node, "clock-frequency", &freq);
1121 /* convert DT freq value in Hz into kHz for speed */
1122 dev->speed = freq / 1000;
1123 } else if (pdata != NULL) {
1124 dev->speed = pdata->clkrate;
1125 dev->flags = pdata->flags;
49839dc9 1126 dev->set_mpu_wkup_lat = pdata->set_mpu_wkup_lat;
20c9d2c4 1127 }
4574eb68 1128
2d4b4520
SG		 1129 dev->pins = devm_pinctrl_get_select_default(&pdev->dev);
1130 if (IS_ERR(dev->pins)) {
1131 if (PTR_ERR(dev->pins) == -EPROBE_DEFER)
1132 return -EPROBE_DEFER;
1133
1134 dev_warn(&pdev->dev, "did not get pins for i2c error: %li\n",
1135 PTR_ERR(dev->pins));
1136 dev->pins = NULL;
1137 }
1138
010d442c 1139 dev->dev = &pdev->dev;
ac79e4b2 1140 dev->irq = irq;
55c381e4 1141
3b2f8f82 1142 spin_lock_init(&dev->lock);
55c381e4 1143
010d442c 1144 platform_set_drvdata(pdev, dev);
0e33bbb2 1145 init_completion(&dev->cmd_complete);
010d442c 1146
6145197b 1147 dev->reg_shift = (dev->flags >> OMAP_I2C_FLAG_BUS_SHIFT__SHIFT) & 3;
7c6bd201 1148
7f4b08ee 1149 pm_runtime_enable(dev->dev);
6d8451d5
FB		 1150 pm_runtime_set_autosuspend_delay(dev->dev, OMAP_I2C_PM_TIMEOUT);
1151 pm_runtime_use_autosuspend(dev->dev);
1152
3b0fb97c
S		 1153 r = pm_runtime_get_sync(dev->dev);
1154 if (IS_ERR_VALUE(r))
1155 goto err_free_mem;
010d442c 1156
47dcd016
S		 1157 /*
1158 * Read the Rev hi bit-[15:14] ie scheme this is 1 indicates ver2.
1159 * On omap1/3/2 Offset 4 is IE Reg the bit [15:14] is 0 at reset.
1160 * Also since the omap_i2c_read_reg uses reg_map_ip_* a
1161 * raw_readw is done.
1162 */
1163 rev = __raw_readw(dev->base + 0x04);
1164
cd10c74a
S		 1165 scheme = OMAP_I2C_SCHEME(rev);
1166 switch (scheme) {
47dcd016
S		 1167 case OMAP_I2C_SCHEME_0:
1168 dev->regs = (u8 *)reg_map_ip_v1;
1169 dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG);
1170 minor = OMAP_I2C_REV_SCHEME_0_MAJOR(dev->rev);
1171 major = OMAP_I2C_REV_SCHEME_0_MAJOR(dev->rev);
1172 break;
1173 case OMAP_I2C_SCHEME_1:
1174 /* FALLTHROUGH */
1175 default:
1176 dev->regs = (u8 *)reg_map_ip_v2;
1177 rev = (rev << 16) |
1178 omap_i2c_read_reg(dev, OMAP_I2C_IP_V2_REVNB_LO);
1179 minor = OMAP_I2C_REV_SCHEME_1_MINOR(rev);
1180 major = OMAP_I2C_REV_SCHEME_1_MAJOR(rev);
1181 dev->rev = rev;
1182 }
010d442c 1183
9aa8ec67
TK		 1184 dev->errata = 0;
1185
a748021c
S		 1186 if (dev->rev >= OMAP_I2C_REV_ON_2430 &&
1187 dev->rev < OMAP_I2C_REV_ON_4430_PLUS)
9aa8ec67
TK		 1188 dev->errata |= I2C_OMAP_ERRATA_I207;
1189
f518b482 1190 if (dev->rev <= OMAP_I2C_REV_ON_3430_3530)
c8db38f0 1191 dev->errata |= I2C_OMAP_ERRATA_I462;
8a9d97d3 1192
6145197b 1193 if (!(dev->flags & OMAP_I2C_FLAG_NO_FIFO)) {
b6ee52c3
NM		 1194 u16 s;
1195
1196 /* Set up the fifo size - Get total size */
1197 s = (omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3;
1198 dev->fifo_size = 0x8 << s;
1199
1200 /*
1201 * Set up notification threshold as half the total available
1202 * size. This is to ensure that we can handle the status on int
1203 * call back latencies.
1204 */
1d5a34fe
S		 1205
1206 dev->fifo_size = (dev->fifo_size / 2);
1207
47dcd016 1208 if (dev->rev < OMAP_I2C_REV_ON_3630)
f38e66e0 1209 dev->b_hw = 1; /* Enable hardware fixes */
1d5a34fe 1210
20c9d2c4 1211 /* calculate wakeup latency constraint for MPU */
49839dc9
PW		 1212 if (dev->set_mpu_wkup_lat != NULL)
1213 dev->latency = (1000000 * dev->fifo_size) /
1214 (1000 * dev->speed / 8);
b6ee52c3
NM		 1215 }
1216
010d442c
KS		 1217 /* reset ASAP, clearing any IRQs */
1218 omap_i2c_init(dev);
1219
3b2f8f82
FB		 1220 if (dev->rev < OMAP_I2C_OMAP1_REV_2)
1221 r = devm_request_irq(&pdev->dev, dev->irq, omap_i2c_omap1_isr,
1222 IRQF_NO_SUSPEND, pdev->name, dev);
1223 else
1224 r = devm_request_threaded_irq(&pdev->dev, dev->irq,
1225 omap_i2c_isr, omap_i2c_isr_thread,
1226 IRQF_NO_SUSPEND | IRQF_ONESHOT,
1227 pdev->name, dev);
010d442c
KS		 1228
1229 if (r) {
1230 dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
1231 goto err_unuse_clocks;
1232 }
9c76b878 1233
010d442c
KS		 1234 adap = &dev->adapter;
1235 i2c_set_adapdata(adap, dev);
1236 adap->owner = THIS_MODULE;
1237 adap->class = I2C_CLASS_HWMON;
783fd6fa 1238 strlcpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
010d442c
KS		 1239 adap->algo = &omap_i2c_algo;
1240 adap->dev.parent = &pdev->dev;
6145197b 1241 adap->dev.of_node = pdev->dev.of_node;
010d442c
KS		 1242
1243 /* i2c device drivers may be active on return from add_adapter() */
7c175499
DB		 1244 adap->nr = pdev->id;
1245 r = i2c_add_numbered_adapter(adap);
010d442c
KS		 1246 if (r) {
1247 dev_err(dev->dev, "failure adding adapter\n");
d9ebd04d 1248 goto err_unuse_clocks;
010d442c
KS		 1249 }
1250
cd10c74a
S		 1251 dev_info(dev->dev, "bus %d rev%d.%d at %d kHz\n", adap->nr,
1252 major, minor, dev->speed);
c5d3cd6d 1253
6145197b
BC		 1254 of_i2c_register_devices(adap);
1255
6d8451d5
FB		 1256 pm_runtime_mark_last_busy(dev->dev);
1257 pm_runtime_put_autosuspend(dev->dev);
62ff2c2b 1258
010d442c
KS		 1259 return 0;
1260
010d442c 1261err_unuse_clocks:
3e39752d 1262 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
fab67afb 1263 pm_runtime_put(dev->dev);
24740516 1264 pm_runtime_disable(&pdev->dev);
010d442c
KS		 1265err_free_mem:
1266 platform_set_drvdata(pdev, NULL);
010d442c
KS		 1267
1268 return r;
1269}
1270
d790aea7 1271static int __devexit omap_i2c_remove(struct platform_device *pdev)
010d442c
KS		 1272{
1273 struct omap_i2c_dev *dev = platform_get_drvdata(pdev);
3b0fb97c 1274 int ret;
010d442c
KS		 1275
1276 platform_set_drvdata(pdev, NULL);
1277
010d442c 1278 i2c_del_adapter(&dev->adapter);
3b0fb97c
S		 1279 ret = pm_runtime_get_sync(&pdev->dev);
1280 if (IS_ERR_VALUE(ret))
1281 return ret;
1282
010d442c 1283 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
0861f430 1284 pm_runtime_put(&pdev->dev);
24740516 1285 pm_runtime_disable(&pdev->dev);
010d442c
KS		 1286 return 0;
1287}
1288
5692d2a2 1289#ifdef CONFIG_PM
fab67afb
KH		 1290#ifdef CONFIG_PM_RUNTIME
1291static int omap_i2c_runtime_suspend(struct device *dev)
1292{
1293 struct platform_device *pdev = to_platform_device(dev);
1294 struct omap_i2c_dev *_dev = platform_get_drvdata(pdev);
3dae3efb
S		 1295 u16 iv;
1296
1297 _dev->iestate = omap_i2c_read_reg(_dev, OMAP_I2C_IE_REG);
bd16c82f
S		 1298
1299 omap_i2c_write_reg(_dev, OMAP_I2C_IE_REG, 0);
fab67afb 1300
3dae3efb
S		 1301 if (_dev->rev < OMAP_I2C_OMAP1_REV_2) {
1302 iv = omap_i2c_read_reg(_dev, OMAP_I2C_IV_REG); /* Read clears */
1303 } else {
1304 omap_i2c_write_reg(_dev, OMAP_I2C_STAT_REG, _dev->iestate);
fab67afb 1305
3dae3efb
S		 1306 /* Flush posted write */
1307 omap_i2c_read_reg(_dev, OMAP_I2C_STAT_REG);
1308 }
fab67afb
KH		 1309
1310 return 0;
1311}
1312
1313static int omap_i2c_runtime_resume(struct device *dev)
1314{
1315 struct platform_device *pdev = to_platform_device(dev);
1316 struct omap_i2c_dev *_dev = platform_get_drvdata(pdev);
1317
47dcd016
S		 1318 if (!_dev->regs)
1319 return 0;
1320
95dd3032
S		 1321 if (_dev->flags & OMAP_I2C_FLAG_RESET_REGS_POSTIDLE)
1322 __omap_i2c_init(_dev);
fab67afb
KH		 1323
1324 return 0;
1325}
5692d2a2 1326#endif /* CONFIG_PM_RUNTIME */
fab67afb
KH		 1327
1328static struct dev_pm_ops omap_i2c_pm_ops = {
5692d2a2
S		 1329 SET_RUNTIME_PM_OPS(omap_i2c_runtime_suspend,
1330 omap_i2c_runtime_resume, NULL)
fab67afb
KH		 1331};
1332#define OMAP_I2C_PM_OPS (&omap_i2c_pm_ops)
1333#else
1334#define OMAP_I2C_PM_OPS NULL
5692d2a2 1335#endif /* CONFIG_PM */
fab67afb 1336
010d442c
KS		 1337static struct platform_driver omap_i2c_driver = {
1338 .probe = omap_i2c_probe,
d790aea7 1339 .remove = __devexit_p(omap_i2c_remove),
010d442c 1340 .driver = {
f7bb0d9a 1341 .name = "omap_i2c",
010d442c 1342 .owner = THIS_MODULE,
fab67afb 1343 .pm = OMAP_I2C_PM_OPS,
6145197b 1344 .of_match_table = of_match_ptr(omap_i2c_of_match),
010d442c
KS		 1345 },
1346};
1347
1348/* I2C may be needed to bring up other drivers */
1349static int __init
1350omap_i2c_init_driver(void)
1351{
1352 return platform_driver_register(&omap_i2c_driver);
1353}
1354subsys_initcall(omap_i2c_init_driver);
1355
1356static void __exit omap_i2c_exit_driver(void)
1357{
1358 platform_driver_unregister(&omap_i2c_driver);
1359}
1360module_exit(omap_i2c_exit_driver);
1361
1362MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
1363MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
1364MODULE_LICENSE("GPL");
f7bb0d9a 1365MODULE_ALIAS("platform:omap_i2c");
Linux kernel - Deliverables
This page took 0.567054 seconds and 5 git commands to generate.