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i2c: s3c2410: Handle i2c sys_cfg register in i2c driver
[deliverable/linux.git] / drivers / i2c / busses / i2c-omap.c
CommitLineData
010d442c
KS		 1/*
2 * TI OMAP I2C master mode driver
3 *
4 * Copyright (C) 2003 MontaVista Software, Inc.
010d442c 5 * Copyright (C) 2005 Nokia Corporation
c1a473bd 6 * Copyright (C) 2004 - 2007 Texas Instruments.
010d442c 7 *
c1a473bd
TL		 8 * Originally written by MontaVista Software, Inc.
9 * Additional contributions by:
10 * Tony Lindgren <tony@atomide.com>
11 * Imre Deak <imre.deak@nokia.com>
12 * Juha Yrjölä <juha.yrjola@solidboot.com>
13 * Syed Khasim <x0khasim@ti.com>
14 * Nishant Menon <nm@ti.com>
010d442c
KS		 15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
010d442c
KS		 25 */
26
27#include <linux/module.h>
28#include <linux/delay.h>
29#include <linux/i2c.h>
30#include <linux/err.h>
31#include <linux/interrupt.h>
32#include <linux/completion.h>
33#include <linux/platform_device.h>
34#include <linux/clk.h>
c1a473bd 35#include <linux/io.h>
6145197b 36#include <linux/of.h>
6145197b 37#include <linux/of_device.h>
5a0e3ad6 38#include <linux/slab.h>
20c9d2c4 39#include <linux/i2c-omap.h>
27b1fec2 40#include <linux/pm_runtime.h>
010d442c 41
9c76b878 42/* I2C controller revisions */
4e80f727 43#define OMAP_I2C_OMAP1_REV_2 0x20
9c76b878
PW		 44
45/* I2C controller revisions present on specific hardware */
47dcd016
S		 46#define OMAP_I2C_REV_ON_2430 0x00000036
47#define OMAP_I2C_REV_ON_3430_3530 0x0000003C
48#define OMAP_I2C_REV_ON_3630 0x00000040
49#define OMAP_I2C_REV_ON_4430_PLUS 0x50400002
9c76b878 50
010d442c
KS		 51/* timeout waiting for the controller to respond */
52#define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
53
6d8451d5
FB		 54/* timeout for pm runtime autosuspend */
55#define OMAP_I2C_PM_TIMEOUT 1000 /* ms */
56
0f5768bf
AK		 57/* timeout for making decision on bus free status */
58#define OMAP_I2C_BUS_FREE_TIMEOUT (msecs_to_jiffies(10))
59
5043e9e7 60/* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */
f38e66e0
SS		 61enum {
62 OMAP_I2C_REV_REG = 0,
63 OMAP_I2C_IE_REG,
64 OMAP_I2C_STAT_REG,
65 OMAP_I2C_IV_REG,
66 OMAP_I2C_WE_REG,
67 OMAP_I2C_SYSS_REG,
68 OMAP_I2C_BUF_REG,
69 OMAP_I2C_CNT_REG,
70 OMAP_I2C_DATA_REG,
71 OMAP_I2C_SYSC_REG,
72 OMAP_I2C_CON_REG,
73 OMAP_I2C_OA_REG,
74 OMAP_I2C_SA_REG,
75 OMAP_I2C_PSC_REG,
76 OMAP_I2C_SCLL_REG,
77 OMAP_I2C_SCLH_REG,
78 OMAP_I2C_SYSTEST_REG,
79 OMAP_I2C_BUFSTAT_REG,
b8853088
AG		 80 /* only on OMAP4430 */
81 OMAP_I2C_IP_V2_REVNB_LO,
82 OMAP_I2C_IP_V2_REVNB_HI,
83 OMAP_I2C_IP_V2_IRQSTATUS_RAW,
84 OMAP_I2C_IP_V2_IRQENABLE_SET,
85 OMAP_I2C_IP_V2_IRQENABLE_CLR,
f38e66e0 86};
010d442c
KS		 87
88/* I2C Interrupt Enable Register (OMAP_I2C_IE): */
b6ee52c3
NM		 89#define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */
90#define OMAP_I2C_IE_RDR (1 << 13) /* RX Buffer drain int enable */
010d442c
KS		 91#define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */
92#define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */
93#define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */
94#define OMAP_I2C_IE_NACK (1 << 1) /* No ack interrupt enable */
95#define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */
96
97/* I2C Status Register (OMAP_I2C_STAT): */
b6ee52c3
NM		 98#define OMAP_I2C_STAT_XDR (1 << 14) /* TX Buffer draining */
99#define OMAP_I2C_STAT_RDR (1 << 13) /* RX Buffer draining */
010d442c
KS		 100#define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */
101#define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */
102#define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
103#define OMAP_I2C_STAT_AAS (1 << 9) /* Address as slave */
9fd6ada8 104#define OMAP_I2C_STAT_BF (1 << 8) /* Bus Free */
010d442c
KS		 105#define OMAP_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
106#define OMAP_I2C_STAT_RRDY (1 << 3) /* Receive data ready */
107#define OMAP_I2C_STAT_ARDY (1 << 2) /* Register access ready */
108#define OMAP_I2C_STAT_NACK (1 << 1) /* No ack interrupt enable */
109#define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost int ena */
110
5043e9e7
KJ		 111/* I2C WE wakeup enable register */
112#define OMAP_I2C_WE_XDR_WE (1 << 14) /* TX drain wakup */
113#define OMAP_I2C_WE_RDR_WE (1 << 13) /* RX drain wakeup */
114#define OMAP_I2C_WE_AAS_WE (1 << 9) /* Address as slave wakeup*/
115#define OMAP_I2C_WE_BF_WE (1 << 8) /* Bus free wakeup */
116#define OMAP_I2C_WE_STC_WE (1 << 6) /* Start condition wakeup */
117#define OMAP_I2C_WE_GC_WE (1 << 5) /* General call wakeup */
118#define OMAP_I2C_WE_DRDY_WE (1 << 3) /* TX/RX data ready wakeup */
119#define OMAP_I2C_WE_ARDY_WE (1 << 2) /* Reg access ready wakeup */
120#define OMAP_I2C_WE_NACK_WE (1 << 1) /* No acknowledgment wakeup */
121#define OMAP_I2C_WE_AL_WE (1 << 0) /* Arbitration lost wakeup */
122
123#define OMAP_I2C_WE_ALL (OMAP_I2C_WE_XDR_WE | OMAP_I2C_WE_RDR_WE | \
124 OMAP_I2C_WE_AAS_WE | OMAP_I2C_WE_BF_WE | \
125 OMAP_I2C_WE_STC_WE | OMAP_I2C_WE_GC_WE | \
126 OMAP_I2C_WE_DRDY_WE | OMAP_I2C_WE_ARDY_WE | \
127 OMAP_I2C_WE_NACK_WE | OMAP_I2C_WE_AL_WE)
128
010d442c
KS		 129/* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
130#define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */
b6ee52c3 131#define OMAP_I2C_BUF_RXFIF_CLR (1 << 14) /* RX FIFO Clear */
010d442c 132#define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */
b6ee52c3 133#define OMAP_I2C_BUF_TXFIF_CLR (1 << 6) /* TX FIFO Clear */
010d442c
KS		 134
135/* I2C Configuration Register (OMAP_I2C_CON): */
136#define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */
137#define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */
b6ee52c3 138#define OMAP_I2C_CON_OPMODE_HS (1 << 12) /* High Speed support */
010d442c
KS		 139#define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */
140#define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */
141#define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */
142#define OMAP_I2C_CON_XA (1 << 8) /* Expand address */
143#define OMAP_I2C_CON_RM (1 << 2) /* Repeat mode (master only) */
144#define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */
145#define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */
146
4574eb68
SMK		 147/* I2C SCL time value when Master */
148#define OMAP_I2C_SCLL_HSSCLL 8
149#define OMAP_I2C_SCLH_HSSCLH 8
150
010d442c 151/* I2C System Test Register (OMAP_I2C_SYSTEST): */
010d442c
KS		 152#define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */
153#define OMAP_I2C_SYSTEST_FREE (1 << 14) /* Free running mode */
154#define OMAP_I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */
155#define OMAP_I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */
9fd6ada8
AK		 156/* Functional mode */
157#define OMAP_I2C_SYSTEST_SCL_I_FUNC (1 << 8) /* SCL line input value */
158#define OMAP_I2C_SYSTEST_SCL_O_FUNC (1 << 7) /* SCL line output value */
159#define OMAP_I2C_SYSTEST_SDA_I_FUNC (1 << 6) /* SDA line input value */
160#define OMAP_I2C_SYSTEST_SDA_O_FUNC (1 << 5) /* SDA line output value */
161/* SDA/SCL IO mode */
010d442c
KS		 162#define OMAP_I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense in */
163#define OMAP_I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive out */
164#define OMAP_I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense in */
165#define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */
010d442c 166
fdd07fe6
PW		 167/* OCP_SYSSTATUS bit definitions */
168#define SYSS_RESETDONE_MASK (1 << 0)
169
170/* OCP_SYSCONFIG bit definitions */
171#define SYSC_CLOCKACTIVITY_MASK (0x3 << 8)
172#define SYSC_SIDLEMODE_MASK (0x3 << 3)
173#define SYSC_ENAWAKEUP_MASK (1 << 2)
174#define SYSC_SOFTRESET_MASK (1 << 1)
175#define SYSC_AUTOIDLE_MASK (1 << 0)
176
177#define SYSC_IDLEMODE_SMART 0x2
178#define SYSC_CLOCKACTIVITY_FCLK 0x2
010d442c 179
f3083d92 180/* Errata definitions */
181#define I2C_OMAP_ERRATA_I207 (1 << 0)
c8db38f0 182#define I2C_OMAP_ERRATA_I462 (1 << 1)
010d442c 183
4368de19
OD		 184#define OMAP_I2C_IP_V2_INTERRUPTS_MASK 0x6FFF
185
010d442c 186struct omap_i2c_dev {
3b2f8f82 187 spinlock_t lock; /* IRQ synchronization */
010d442c
KS		 188 struct device *dev;
189 void __iomem *base; /* virtual */
190 int irq;
d84d3ea3 191 int reg_shift; /* bit shift for I2C register addresses */
010d442c
KS		 192 struct completion cmd_complete;
193 struct resource *ioarea;
49839dc9
PW		 194 u32 latency; /* maximum mpu wkup latency */
195 void (*set_mpu_wkup_lat)(struct device *dev,
196 long latency);
6145197b 197 u32 speed; /* Speed of bus in kHz */
6145197b 198 u32 flags;
4368de19 199 u16 scheme;
010d442c
KS		 200 u16 cmd_err;
201 u8 *buf;
f38e66e0 202 u8 *regs;
010d442c
KS		 203 size_t buf_len;
204 struct i2c_adapter adapter;
dd74548d 205 u8 threshold;
b6ee52c3
NM		 206 u8 fifo_size; /* use as flag and value
207 * fifo_size==0 implies no fifo
208 * if set, should be trsh+1
209 */
47dcd016 210 u32 rev;
b6ee52c3 211 unsigned b_hw:1; /* bad h/w fixes */
0f5768bf
AK		 212 unsigned bb_valid:1; /* true when BB-bit reflects
213 * the I2C bus state
214 */
079d8af2 215 unsigned receiver:1; /* true when we're in receiver mode */
f08ac4e7 216 u16 iestate; /* Saved interrupt register */
ef871432
RN		 217 u16 pscstate;
218 u16 scllstate;
219 u16 sclhstate;
ef871432
RN		 220 u16 syscstate;
221 u16 westate;
f3083d92 222 u16 errata;
010d442c
KS		 223};
224
a1295577 225static const u8 reg_map_ip_v1[] = {
f38e66e0
SS		 226 [OMAP_I2C_REV_REG] = 0x00,
227 [OMAP_I2C_IE_REG] = 0x01,
228 [OMAP_I2C_STAT_REG] = 0x02,
229 [OMAP_I2C_IV_REG] = 0x03,
230 [OMAP_I2C_WE_REG] = 0x03,
231 [OMAP_I2C_SYSS_REG] = 0x04,
232 [OMAP_I2C_BUF_REG] = 0x05,
233 [OMAP_I2C_CNT_REG] = 0x06,
234 [OMAP_I2C_DATA_REG] = 0x07,
235 [OMAP_I2C_SYSC_REG] = 0x08,
236 [OMAP_I2C_CON_REG] = 0x09,
237 [OMAP_I2C_OA_REG] = 0x0a,
238 [OMAP_I2C_SA_REG] = 0x0b,
239 [OMAP_I2C_PSC_REG] = 0x0c,
240 [OMAP_I2C_SCLL_REG] = 0x0d,
241 [OMAP_I2C_SCLH_REG] = 0x0e,
242 [OMAP_I2C_SYSTEST_REG] = 0x0f,
243 [OMAP_I2C_BUFSTAT_REG] = 0x10,
244};
245
a1295577 246static const u8 reg_map_ip_v2[] = {
f38e66e0
SS		 247 [OMAP_I2C_REV_REG] = 0x04,
248 [OMAP_I2C_IE_REG] = 0x2c,
249 [OMAP_I2C_STAT_REG] = 0x28,
250 [OMAP_I2C_IV_REG] = 0x34,
251 [OMAP_I2C_WE_REG] = 0x34,
252 [OMAP_I2C_SYSS_REG] = 0x90,
253 [OMAP_I2C_BUF_REG] = 0x94,
254 [OMAP_I2C_CNT_REG] = 0x98,
255 [OMAP_I2C_DATA_REG] = 0x9c,
2727b175 256 [OMAP_I2C_SYSC_REG] = 0x10,
f38e66e0
SS		 257 [OMAP_I2C_CON_REG] = 0xa4,
258 [OMAP_I2C_OA_REG] = 0xa8,
259 [OMAP_I2C_SA_REG] = 0xac,
260 [OMAP_I2C_PSC_REG] = 0xb0,
261 [OMAP_I2C_SCLL_REG] = 0xb4,
262 [OMAP_I2C_SCLH_REG] = 0xb8,
263 [OMAP_I2C_SYSTEST_REG] = 0xbC,
264 [OMAP_I2C_BUFSTAT_REG] = 0xc0,
b8853088
AG		 265 [OMAP_I2C_IP_V2_REVNB_LO] = 0x00,
266 [OMAP_I2C_IP_V2_REVNB_HI] = 0x04,
267 [OMAP_I2C_IP_V2_IRQSTATUS_RAW] = 0x24,
268 [OMAP_I2C_IP_V2_IRQENABLE_SET] = 0x2c,
269 [OMAP_I2C_IP_V2_IRQENABLE_CLR] = 0x30,
f38e66e0
SS		 270};
271
010d442c
KS		 272static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev,
273 int reg, u16 val)
274{
40b13ca8 275 writew_relaxed(val, i2c_dev->base +
f38e66e0 276 (i2c_dev->regs[reg] << i2c_dev->reg_shift));
010d442c
KS		 277}
278
279static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
280{
40b13ca8 281 return readw_relaxed(i2c_dev->base +
f38e66e0 282 (i2c_dev->regs[reg] << i2c_dev->reg_shift));
010d442c
KS		 283}
284
95dd3032
S		 285static void __omap_i2c_init(struct omap_i2c_dev *dev)
286{
287
288 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
289
290 /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
291 omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, dev->pscstate);
292
293 /* SCL low and high time values */
294 omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, dev->scllstate);
295 omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, dev->sclhstate);
296 if (dev->rev >= OMAP_I2C_REV_ON_3430_3530)
297 omap_i2c_write_reg(dev, OMAP_I2C_WE_REG, dev->westate);
298
299 /* Take the I2C module out of reset: */
300 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
301
4f734a3a
AK		 302 /*
303 * NOTE: right after setting CON_EN, STAT_BB could be 0 while the
304 * bus is busy. It will be changed to 1 on the next IP FCLK clock.
305 * udelay(1) will be enough to fix that.
306 */
307
95dd3032
S		 308 /*
309 * Don't write to this register if the IE state is 0 as it can
310 * cause deadlock.
311 */
312 if (dev->iestate)
313 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
314}
315
d6c842ad 316static int omap_i2c_reset(struct omap_i2c_dev *dev)
010d442c 317{
010d442c 318 unsigned long timeout;
ca85e248
S		 319 u16 sysc;
320
4e80f727 321 if (dev->rev >= OMAP_I2C_OMAP1_REV_2) {
ca85e248
S		 322 sysc = omap_i2c_read_reg(dev, OMAP_I2C_SYSC_REG);
323
57eb81b1
MG		 324 /* Disable I2C controller before soft reset */
325 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
326 omap_i2c_read_reg(dev, OMAP_I2C_CON_REG) &
327 ~(OMAP_I2C_CON_EN));
328
fdd07fe6 329 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK);
010d442c
KS		 330 /* For some reason we need to set the EN bit before the
331 * reset done bit gets set. */
332 timeout = jiffies + OMAP_I2C_TIMEOUT;
333 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
334 while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) &
fdd07fe6 335 SYSS_RESETDONE_MASK)) {
010d442c 336 if (time_after(jiffies, timeout)) {
fce3ff03 337 dev_warn(dev->dev, "timeout waiting "
010d442c
KS		 338 "for controller reset\n");
339 return -ETIMEDOUT;
340 }
341 msleep(1);
342 }
fdd07fe6
PW		 343
344 /* SYSC register is cleared by the reset; rewrite it */
ca85e248 345 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, sysc);
fdd07fe6 346
0f5768bf
AK		 347 /* Schedule I2C-bus monitoring on the next transfer */
348 dev->bb_valid = 0;
010d442c 349 }
0f5768bf 350
d6c842ad
S		 351 return 0;
352}
353
354static int omap_i2c_init(struct omap_i2c_dev *dev)
355{
356 u16 psc = 0, scll = 0, sclh = 0;
357 u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
358 unsigned long fclk_rate = 12000000;
359 unsigned long internal_clk = 0;
360 struct clk *fclk;
361
362 if (dev->rev >= OMAP_I2C_REV_ON_3430_3530) {
363 /*
364 * Enabling all wakup sources to stop I2C freezing on
365 * WFI instruction.
366 * REVISIT: Some wkup sources might not be needed.
367 */
368 dev->westate = OMAP_I2C_WE_ALL;
369 }
010d442c 370
6145197b 371 if (dev->flags & OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK) {
0e9ae109
RK		 372 /*
373 * The I2C functional clock is the armxor_ck, so there's
374 * no need to get "armxor_ck" separately. Now, if OMAP2420
375 * always returns 12MHz for the functional clock, we can
376 * do this bit unconditionally.
377 */
27b1fec2
RN		 378 fclk = clk_get(dev->dev, "fck");
379 fclk_rate = clk_get_rate(fclk);
380 clk_put(fclk);
0e9ae109 381
010d442c
KS		 382 /* TRM for 5912 says the I2C clock must be prescaled to be
383 * between 7 - 12 MHz. The XOR input clock is typically
384 * 12, 13 or 19.2 MHz. So we should have code that produces:
385 *
386 * XOR MHz Divider Prescaler
387 * 12 1 0
388 * 13 2 1
389 * 19.2 2 1
390 */
d7aef138
JD		 391 if (fclk_rate > 12000000)
392 psc = fclk_rate / 12000000;
010d442c
KS		 393 }
394
6145197b 395 if (!(dev->flags & OMAP_I2C_FLAG_SIMPLE_CLOCK)) {
4574eb68 396
84bf2c86
AK		 397 /*
398 * HSI2C controller internal clk rate should be 19.2 Mhz for
399 * HS and for all modes on 2430. On 34xx we can use lower rate
400 * to get longer filter period for better noise suppression.
401 * The filter is iclk (fclk for HS) period.
402 */
3be0053e 403 if (dev->speed > 400 ||
6145197b 404 dev->flags & OMAP_I2C_FLAG_FORCE_19200_INT_CLK)
84bf2c86
AK		 405 internal_clk = 19200;
406 else if (dev->speed > 100)
407 internal_clk = 9600;
408 else
409 internal_clk = 4000;
27b1fec2
RN		 410 fclk = clk_get(dev->dev, "fck");
411 fclk_rate = clk_get_rate(fclk) / 1000;
412 clk_put(fclk);
4574eb68
SMK		 413
414 /* Compute prescaler divisor */
415 psc = fclk_rate / internal_clk;
416 psc = psc - 1;
417
418 /* If configured for High Speed */
419 if (dev->speed > 400) {
baf46b4e
AK		 420 unsigned long scl;
421
4574eb68 422 /* For first phase of HS mode */
baf46b4e
AK		 423 scl = internal_clk / 400;
424 fsscll = scl - (scl / 3) - 7;
425 fssclh = (scl / 3) - 5;
4574eb68
SMK		 426
427 /* For second phase of HS mode */
baf46b4e
AK		 428 scl = fclk_rate / dev->speed;
429 hsscll = scl - (scl / 3) - 7;
430 hssclh = (scl / 3) - 5;
431 } else if (dev->speed > 100) {
432 unsigned long scl;
433
434 /* Fast mode */
435 scl = internal_clk / dev->speed;
436 fsscll = scl - (scl / 3) - 7;
437 fssclh = (scl / 3) - 5;
4574eb68 438 } else {
baf46b4e
AK		 439 /* Standard mode */
440 fsscll = internal_clk / (dev->speed * 2) - 7;
441 fssclh = internal_clk / (dev->speed * 2) - 5;
4574eb68
SMK		 442 }
443 scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
444 sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
445 } else {
446 /* Program desired operating rate */
447 fclk_rate /= (psc + 1) * 1000;
448 if (psc > 2)
449 psc = 2;
450 scll = fclk_rate / (dev->speed * 2) - 7 + psc;
451 sclh = fclk_rate / (dev->speed * 2) - 7 + psc;
452 }
453
ef871432 454 dev->iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
c1a473bd
TL		 455 OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
456 OMAP_I2C_IE_AL) | ((dev->fifo_size) ?
ef871432 457 (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0);
95dd3032
S		 458
459 dev->pscstate = psc;
460 dev->scllstate = scll;
461 dev->sclhstate = sclh;
462
0f5768bf
AK		 463 if (dev->rev < OMAP_I2C_OMAP1_REV_2) {
464 /* Not implemented */
465 dev->bb_valid = 1;
466 }
467
95dd3032
S		 468 __omap_i2c_init(dev);
469
010d442c
KS		 470 return 0;
471}
472
473/*
474 * Waiting on Bus Busy
475 */
476static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev)
477{
478 unsigned long timeout;
479
480 timeout = jiffies + OMAP_I2C_TIMEOUT;
481 while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
482 if (time_after(jiffies, timeout)) {
483 dev_warn(dev->dev, "timeout waiting for bus ready\n");
484 return -ETIMEDOUT;
485 }
486 msleep(1);
487 }
488
489 return 0;
490}
491
0f5768bf
AK		 492/*
493 * Wait while BB-bit doesn't reflect the I2C bus state
494 *
495 * In a multimaster environment, after IP software reset, BB-bit value doesn't
496 * correspond to the current bus state. It may happen what BB-bit will be 0,
497 * while the bus is busy due to another I2C master activity.
498 * Here are BB-bit values after reset:
499 * SDA SCL BB NOTES
500 * 0 0 0 1, 2
501 * 1 0 0 1, 2
502 * 0 1 1
503 * 1 1 0 3
504 * Later, if IP detect SDA=0 and SCL=1 (ACK) or SDA 1->0 while SCL=1 (START)
505 * combinations on the bus, it set BB-bit to 1.
506 * If IP detect SDA 0->1 while SCL=1 (STOP) combination on the bus,
507 * it set BB-bit to 0 and BF to 1.
508 * BB and BF bits correctly tracks the bus state while IP is suspended
509 * BB bit became valid on the next FCLK clock after CON_EN bit set
510 *
511 * NOTES:
512 * 1. Any transfer started when BB=0 and bus is busy wouldn't be
513 * completed by IP and results in controller timeout.
514 * 2. Any transfer started when BB=0 and SCL=0 results in IP
515 * starting to drive SDA low. In that case IP corrupt data
516 * on the bus.
517 * 3. Any transfer started in the middle of another master's transfer
518 * results in unpredictable results and data corruption
519 */
520static int omap_i2c_wait_for_bb_valid(struct omap_i2c_dev *dev)
521{
522 unsigned long bus_free_timeout = 0;
523 unsigned long timeout;
524 int bus_free = 0;
525 u16 stat, systest;
526
527 if (dev->bb_valid)
528 return 0;
529
530 timeout = jiffies + OMAP_I2C_TIMEOUT;
531 while (1) {
532 stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
533 /*
534 * We will see BB or BF event in a case IP had detected any
535 * activity on the I2C bus. Now IP correctly tracks the bus
536 * state. BB-bit value is valid.
537 */
538 if (stat & (OMAP_I2C_STAT_BB | OMAP_I2C_STAT_BF))
539 break;
540
541 /*
542 * Otherwise, we must look signals on the bus to make
543 * the right decision.
544 */
545 systest = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG);
546 if ((systest & OMAP_I2C_SYSTEST_SCL_I_FUNC) &&
547 (systest & OMAP_I2C_SYSTEST_SDA_I_FUNC)) {
548 if (!bus_free) {
549 bus_free_timeout = jiffies +
550 OMAP_I2C_BUS_FREE_TIMEOUT;
551 bus_free = 1;
552 }
553
554 /*
555 * SDA and SCL lines was high for 10 ms without bus
556 * activity detected. The bus is free. Consider
557 * BB-bit value is valid.
558 */
559 if (time_after(jiffies, bus_free_timeout))
560 break;
561 } else {
562 bus_free = 0;
563 }
564
565 if (time_after(jiffies, timeout)) {
566 dev_warn(dev->dev, "timeout waiting for bus ready\n");
567 return -ETIMEDOUT;
568 }
569
570 msleep(1);
571 }
572
573 dev->bb_valid = 1;
574 return 0;
575}
576
dd74548d
FB		 577static void omap_i2c_resize_fifo(struct omap_i2c_dev *dev, u8 size, bool is_rx)
578{
579 u16 buf;
580
581 if (dev->flags & OMAP_I2C_FLAG_NO_FIFO)
582 return;
583
584 /*
585 * Set up notification threshold based on message size. We're doing
586 * this to try and avoid draining feature as much as possible. Whenever
587 * we have big messages to transfer (bigger than our total fifo size)
588 * then we might use draining feature to transfer the remaining bytes.
589 */
590
591 dev->threshold = clamp(size, (u8) 1, dev->fifo_size);
592
593 buf = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
594
595 if (is_rx) {
596 /* Clear RX Threshold */
597 buf &= ~(0x3f << 8);
598 buf |= ((dev->threshold - 1) << 8) | OMAP_I2C_BUF_RXFIF_CLR;
599 } else {
600 /* Clear TX Threshold */
601 buf &= ~0x3f;
602 buf |= (dev->threshold - 1) | OMAP_I2C_BUF_TXFIF_CLR;
603 }
604
605 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, buf);
606
47dcd016 607 if (dev->rev < OMAP_I2C_REV_ON_3630)
dd74548d
FB		 608 dev->b_hw = 1; /* Enable hardware fixes */
609
610 /* calculate wakeup latency constraint for MPU */
49839dc9
PW		 611 if (dev->set_mpu_wkup_lat != NULL)
612 dev->latency = (1000000 * dev->threshold) /
613 (1000 * dev->speed / 8);
dd74548d
FB		 614}
615
010d442c
KS		 616/*
617 * Low level master read/write transaction.
618 */
619static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
620 struct i2c_msg *msg, int stop)
621{
622 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
33d54985 623 unsigned long timeout;
010d442c
KS		 624 u16 w;
625
626 dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
627 msg->addr, msg->len, msg->flags, stop);
628
629 if (msg->len == 0)
630 return -EINVAL;
631
dd74548d
FB		 632 dev->receiver = !!(msg->flags & I2C_M_RD);
633 omap_i2c_resize_fifo(dev, msg->len, dev->receiver);
634
010d442c
KS		 635 omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);
636
637 /* REVISIT: Could the STB bit of I2C_CON be used with probing? */
638 dev->buf = msg->buf;
639 dev->buf_len = msg->len;
640
d60ece5f
FB		 641 /* make sure writes to dev->buf_len are ordered */
642 barrier();
643
010d442c
KS		 644 omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len);
645
b6ee52c3
NM		 646 /* Clear the FIFO Buffers */
647 w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
648 w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR;
649 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w);
650
16735d02 651 reinit_completion(&dev->cmd_complete);
010d442c
KS		 652 dev->cmd_err = 0;
653
654 w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
4574eb68
SMK		 655
656 /* High speed configuration */
657 if (dev->speed > 400)
b6ee52c3 658 w |= OMAP_I2C_CON_OPMODE_HS;
4574eb68 659
fb604a3d
LP		 660 if (msg->flags & I2C_M_STOP)
661 stop = 1;
010d442c
KS		 662 if (msg->flags & I2C_M_TEN)
663 w |= OMAP_I2C_CON_XA;
664 if (!(msg->flags & I2C_M_RD))
665 w |= OMAP_I2C_CON_TRX;
c1a473bd 666
b6ee52c3 667 if (!dev->b_hw && stop)
010d442c 668 w |= OMAP_I2C_CON_STP;
4f734a3a
AK		 669 /*
670 * NOTE: STAT_BB bit could became 1 here if another master occupy
671 * the bus. IP successfully complete transfer when the bus will be
672 * free again (BB reset to 0).
673 */
010d442c
KS		 674 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
675
b6ee52c3
NM		 676 /*
677 * Don't write stt and stp together on some hardware.
678 */
679 if (dev->b_hw && stop) {
680 unsigned long delay = jiffies + OMAP_I2C_TIMEOUT;
681 u16 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
682 while (con & OMAP_I2C_CON_STT) {
683 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
684
685 /* Let the user know if i2c is in a bad state */
686 if (time_after(jiffies, delay)) {
687 dev_err(dev->dev, "controller timed out "
688 "waiting for start condition to finish\n");
689 return -ETIMEDOUT;
690 }
691 cpu_relax();
692 }
693
694 w |= OMAP_I2C_CON_STP;
695 w &= ~OMAP_I2C_CON_STT;
696 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
697 }
698
b7af349b
JN		 699 /*
700 * REVISIT: We should abort the transfer on signals, but the bus goes
701 * into arbitration and we're currently unable to recover from it.
702 */
33d54985
S		 703 timeout = wait_for_completion_timeout(&dev->cmd_complete,
704 OMAP_I2C_TIMEOUT);
33d54985 705 if (timeout == 0) {
010d442c 706 dev_err(dev->dev, "controller timed out\n");
d6c842ad
S		 707 omap_i2c_reset(dev);
708 __omap_i2c_init(dev);
010d442c
KS		 709 return -ETIMEDOUT;
710 }
711
712 if (likely(!dev->cmd_err))
713 return 0;
714
715 /* We have an error */
b76911d2 716 if (dev->cmd_err & (OMAP_I2C_STAT_ROVR | OMAP_I2C_STAT_XUDF)) {
d6c842ad
S		 717 omap_i2c_reset(dev);
718 __omap_i2c_init(dev);
010d442c
KS		 719 return -EIO;
720 }
721
b76911d2
AK		 722 if (dev->cmd_err & OMAP_I2C_STAT_AL)
723 return -EAGAIN;
724
010d442c
KS		 725 if (dev->cmd_err & OMAP_I2C_STAT_NACK) {
726 if (msg->flags & I2C_M_IGNORE_NAK)
727 return 0;
cda2109a
GS		 728
729 w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
730 w |= OMAP_I2C_CON_STP;
731 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
010d442c
KS		 732 return -EREMOTEIO;
733 }
734 return -EIO;
735}
736
737
738/*
739 * Prepare controller for a transaction and call omap_i2c_xfer_msg
740 * to do the work during IRQ processing.
741 */
742static int
743omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
744{
745 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
746 int i;
747 int r;
748
3b0fb97c 749 r = pm_runtime_get_sync(dev->dev);
ff370257 750 if (r < 0)
33ec5e81 751 goto out;
010d442c 752
0f5768bf
AK		 753 r = omap_i2c_wait_for_bb_valid(dev);
754 if (r < 0)
755 goto out;
756
c1a473bd
TL		 757 r = omap_i2c_wait_for_bb(dev);
758 if (r < 0)
010d442c
KS		 759 goto out;
760
49839dc9
PW		 761 if (dev->set_mpu_wkup_lat != NULL)
762 dev->set_mpu_wkup_lat(dev->dev, dev->latency);
6a91b558 763
010d442c
KS		 764 for (i = 0; i < num; i++) {
765 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));
766 if (r != 0)
767 break;
768 }
769
770 if (r == 0)
771 r = num;
5c64eb26
MN		 772
773 omap_i2c_wait_for_bb(dev);
1ab36045
S		 774
775 if (dev->set_mpu_wkup_lat != NULL)
776 dev->set_mpu_wkup_lat(dev->dev, -1);
777
010d442c 778out:
6d8451d5
FB		 779 pm_runtime_mark_last_busy(dev->dev);
780 pm_runtime_put_autosuspend(dev->dev);
010d442c
KS		 781 return r;
782}
783
784static u32
785omap_i2c_func(struct i2c_adapter *adap)
786{
fb604a3d
LP		 787 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
788 I2C_FUNC_PROTOCOL_MANGLING;
010d442c
KS		 789}
790
791static inline void
792omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err)
793{
794 dev->cmd_err |= err;
795 complete(&dev->cmd_complete);
796}
797
798static inline void
799omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat)
800{
801 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
802}
803
f3083d92 804static inline void i2c_omap_errata_i207(struct omap_i2c_dev *dev, u16 stat)
805{
806 /*
807 * I2C Errata(Errata Nos. OMAP2: 1.67, OMAP3: 1.8)
808 * Not applicable for OMAP4.
809 * Under certain rare conditions, RDR could be set again
810 * when the bus is busy, then ignore the interrupt and
811 * clear the interrupt.
812 */
813 if (stat & OMAP_I2C_STAT_RDR) {
814 /* Step 1: If RDR is set, clear it */
815 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
816
817 /* Step 2: */
818 if (!(omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG)
819 & OMAP_I2C_STAT_BB)) {
820
821 /* Step 3: */
822 if (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG)
823 & OMAP_I2C_STAT_RDR) {
824 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
825 dev_dbg(dev->dev, "RDR when bus is busy.\n");
826 }
827
828 }
829 }
830}
831
43469d8e
PW		 832/* rev1 devices are apparently only on some 15xx */
833#ifdef CONFIG_ARCH_OMAP15XX
834
010d442c 835static irqreturn_t
4e80f727 836omap_i2c_omap1_isr(int this_irq, void *dev_id)
010d442c
KS		 837{
838 struct omap_i2c_dev *dev = dev_id;
839 u16 iv, w;
840
fab67afb 841 if (pm_runtime_suspended(dev->dev))
f08ac4e7
TL		 842 return IRQ_NONE;
843
010d442c
KS		 844 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
845 switch (iv) {
846 case 0x00: /* None */
847 break;
848 case 0x01: /* Arbitration lost */
849 dev_err(dev->dev, "Arbitration lost\n");
850 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
851 break;
852 case 0x02: /* No acknowledgement */
853 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
854 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
855 break;
856 case 0x03: /* Register access ready */
857 omap_i2c_complete_cmd(dev, 0);
858 break;
859 case 0x04: /* Receive data ready */
860 if (dev->buf_len) {
861 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
862 *dev->buf++ = w;
863 dev->buf_len--;
864 if (dev->buf_len) {
865 *dev->buf++ = w >> 8;
866 dev->buf_len--;
867 }
868 } else
869 dev_err(dev->dev, "RRDY IRQ while no data requested\n");
870 break;
871 case 0x05: /* Transmit data ready */
872 if (dev->buf_len) {
873 w = *dev->buf++;
874 dev->buf_len--;
875 if (dev->buf_len) {
876 w |= *dev->buf++ << 8;
877 dev->buf_len--;
878 }
879 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
880 } else
881 dev_err(dev->dev, "XRDY IRQ while no data to send\n");
882 break;
883 default:
884 return IRQ_NONE;
885 }
886
887 return IRQ_HANDLED;
888}
43469d8e 889#else
4e80f727 890#define omap_i2c_omap1_isr NULL
43469d8e 891#endif
010d442c 892
2dd151ab 893/*
c8db38f0 894 * OMAP3430 Errata i462: When an XRDY/XDR is hit, wait for XUDF before writing
2dd151ab
AS		 895 * data to DATA_REG. Otherwise some data bytes can be lost while transferring
896 * them from the memory to the I2C interface.
897 */
4151e741 898static int errata_omap3_i462(struct omap_i2c_dev *dev)
2dd151ab 899{
e9f59b9c 900 unsigned long timeout = 10000;
4151e741 901 u16 stat;
e9f59b9c 902
4151e741
FB		 903 do {
904 stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
905 if (stat & OMAP_I2C_STAT_XUDF)
906 break;
907
908 if (stat & (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) {
540a4790 909 omap_i2c_ack_stat(dev, (OMAP_I2C_STAT_XRDY |
2dd151ab 910 OMAP_I2C_STAT_XDR));
b07be0f3
FB		 911 if (stat & OMAP_I2C_STAT_NACK) {
912 dev->cmd_err |= OMAP_I2C_STAT_NACK;
913 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_NACK);
914 }
915
916 if (stat & OMAP_I2C_STAT_AL) {
917 dev_err(dev->dev, "Arbitration lost\n");
918 dev->cmd_err |= OMAP_I2C_STAT_AL;
2c5de558 919 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_AL);
b07be0f3
FB		 920 }
921
4151e741 922 return -EIO;
2dd151ab 923 }
e9f59b9c 924
2dd151ab 925 cpu_relax();
4151e741 926 } while (--timeout);
2dd151ab 927
e9f59b9c
AS		 928 if (!timeout) {
929 dev_err(dev->dev, "timeout waiting on XUDF bit\n");
930 return 0;
931 }
932
2dd151ab
AS		 933 return 0;
934}
935
3312d25e
FB		 936static void omap_i2c_receive_data(struct omap_i2c_dev *dev, u8 num_bytes,
937 bool is_rdr)
938{
939 u16 w;
940
941 while (num_bytes--) {
3312d25e
FB		 942 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
943 *dev->buf++ = w;
944 dev->buf_len--;
945
946 /*
947 * Data reg in 2430, omap3 and
948 * omap4 is 8 bit wide
949 */
950 if (dev->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) {
dd74548d
FB		 951 *dev->buf++ = w >> 8;
952 dev->buf_len--;
3312d25e
FB		 953 }
954 }
955}
956
957static int omap_i2c_transmit_data(struct omap_i2c_dev *dev, u8 num_bytes,
958 bool is_xdr)
959{
960 u16 w;
961
962 while (num_bytes--) {
3312d25e
FB		 963 w = *dev->buf++;
964 dev->buf_len--;
965
966 /*
967 * Data reg in 2430, omap3 and
968 * omap4 is 8 bit wide
969 */
970 if (dev->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) {
dd74548d
FB		 971 w |= *dev->buf++ << 8;
972 dev->buf_len--;
3312d25e
FB		 973 }
974
975 if (dev->errata & I2C_OMAP_ERRATA_I462) {
976 int ret;
977
978 ret = errata_omap3_i462(dev);
979 if (ret < 0)
980 return ret;
981 }
982
983 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
984 }
985
986 return 0;
987}
988
010d442c 989static irqreturn_t
3b2f8f82 990omap_i2c_isr(int irq, void *dev_id)
010d442c
KS		 991{
992 struct omap_i2c_dev *dev = dev_id;
3b2f8f82
FB		 993 irqreturn_t ret = IRQ_HANDLED;
994 u16 mask;
995 u16 stat;
996
997 spin_lock(&dev->lock);
998 mask = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
999 stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
1000
1001 if (stat & mask)
1002 ret = IRQ_WAKE_THREAD;
1003
1004 spin_unlock(&dev->lock);
1005
1006 return ret;
1007}
1008
010d442c 1009static irqreturn_t
3b2f8f82 1010omap_i2c_isr_thread(int this_irq, void *dev_id)
010d442c
KS		 1011{
1012 struct omap_i2c_dev *dev = dev_id;
3b2f8f82 1013 unsigned long flags;
010d442c 1014 u16 bits;
3312d25e 1015 u16 stat;
66b92988 1016 int err = 0, count = 0;
010d442c 1017
3b2f8f82 1018 spin_lock_irqsave(&dev->lock, flags);
66b92988
FB		 1019 do {
1020 bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
1021 stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
1022 stat &= bits;
1023
079d8af2
FB		 1024 /* If we're in receiver mode, ignore XDR/XRDY */
1025 if (dev->receiver)
1026 stat &= ~(OMAP_I2C_STAT_XDR | OMAP_I2C_STAT_XRDY);
1027 else
1028 stat &= ~(OMAP_I2C_STAT_RDR | OMAP_I2C_STAT_RRDY);
010d442c 1029
66b92988
FB		 1030 if (!stat) {
1031 /* my work here is done */
0bdfe0cb 1032 goto out;
66b92988 1033 }
f08ac4e7 1034
010d442c
KS		 1035 dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat);
1036 if (count++ == 100) {
1037 dev_warn(dev->dev, "Too much work in one IRQ\n");
1038 break;
1039 }
1040
1d7afc95 1041 if (stat & OMAP_I2C_STAT_NACK) {
b6ee52c3 1042 err |= OMAP_I2C_STAT_NACK;
1d7afc95 1043 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_NACK);
0bdfe0cb 1044 break;
1d7afc95 1045 }
78e1cf42 1046
b6ee52c3
NM		 1047 if (stat & OMAP_I2C_STAT_AL) {
1048 dev_err(dev->dev, "Arbitration lost\n");
1049 err |= OMAP_I2C_STAT_AL;
1d7afc95 1050 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_AL);
0bdfe0cb 1051 break;
b6ee52c3 1052 }
c55edb99 1053
a5a595cc 1054 /*
cb527ede 1055 * ProDB0017052: Clear ARDY bit twice
a5a595cc 1056 */
4cdbf7d3
TK		 1057 if (stat & OMAP_I2C_STAT_ARDY)
1058 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_ARDY);
1059
b6ee52c3 1060 if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
04c688dd 1061 OMAP_I2C_STAT_AL)) {
540a4790
FB		 1062 omap_i2c_ack_stat(dev, (OMAP_I2C_STAT_RRDY |
1063 OMAP_I2C_STAT_RDR |
1064 OMAP_I2C_STAT_XRDY |
1065 OMAP_I2C_STAT_XDR |
1066 OMAP_I2C_STAT_ARDY));
0bdfe0cb 1067 break;
04c688dd 1068 }
c55edb99 1069
6d9939f6 1070 if (stat & OMAP_I2C_STAT_RDR) {
b6ee52c3 1071 u8 num_bytes = 1;
f3083d92 1072
6d9939f6
FB		 1073 if (dev->fifo_size)
1074 num_bytes = dev->buf_len;
1075
3312d25e 1076 omap_i2c_receive_data(dev, num_bytes, true);
6d9939f6 1077
f3083d92 1078 if (dev->errata & I2C_OMAP_ERRATA_I207)
1079 i2c_omap_errata_i207(dev, stat);
1080
6d9939f6 1081 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
9eb13cf3 1082 continue;
6d9939f6
FB		 1083 }
1084
1085 if (stat & OMAP_I2C_STAT_RRDY) {
1086 u8 num_bytes = 1;
1087
dd74548d
FB		 1088 if (dev->threshold)
1089 num_bytes = dev->threshold;
6d9939f6 1090
3312d25e 1091 omap_i2c_receive_data(dev, num_bytes, false);
6d9939f6 1092 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RRDY);
010d442c
KS		 1093 continue;
1094 }
c55edb99 1095
6d9939f6 1096 if (stat & OMAP_I2C_STAT_XDR) {
b6ee52c3 1097 u8 num_bytes = 1;
3312d25e 1098 int ret;
6d9939f6
FB		 1099
1100 if (dev->fifo_size)
1101 num_bytes = dev->buf_len;
1102
3312d25e 1103 ret = omap_i2c_transmit_data(dev, num_bytes, true);
3312d25e 1104 if (ret < 0)
0bdfe0cb 1105 break;
6d9939f6
FB		 1106
1107 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XDR);
9eb13cf3 1108 continue;
6d9939f6
FB		 1109 }
1110
1111 if (stat & OMAP_I2C_STAT_XRDY) {
1112 u8 num_bytes = 1;
3312d25e 1113 int ret;
6d9939f6 1114
dd74548d
FB		 1115 if (dev->threshold)
1116 num_bytes = dev->threshold;
6d9939f6 1117
3312d25e 1118 ret = omap_i2c_transmit_data(dev, num_bytes, false);
3312d25e 1119 if (ret < 0)
0bdfe0cb 1120 break;
6d9939f6
FB		 1121
1122 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XRDY);
010d442c
KS		 1123 continue;
1124 }
c55edb99 1125
010d442c
KS		 1126 if (stat & OMAP_I2C_STAT_ROVR) {
1127 dev_err(dev->dev, "Receive overrun\n");
1d7afc95
FB		 1128 err |= OMAP_I2C_STAT_ROVR;
1129 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_ROVR);
0bdfe0cb 1130 break;
010d442c 1131 }
c55edb99 1132
010d442c 1133 if (stat & OMAP_I2C_STAT_XUDF) {
b6ee52c3 1134 dev_err(dev->dev, "Transmit underflow\n");
1d7afc95
FB		 1135 err |= OMAP_I2C_STAT_XUDF;
1136 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XUDF);
0bdfe0cb 1137 break;
010d442c 1138 }
66b92988 1139 } while (stat);
010d442c 1140
4a7ec4ed 1141 omap_i2c_complete_cmd(dev, err);
0bdfe0cb
FB		 1142
1143out:
3b2f8f82 1144 spin_unlock_irqrestore(&dev->lock, flags);
010d442c 1145
6a85ced2 1146 return IRQ_HANDLED;
010d442c
KS		 1147}
1148
8f9082c5 1149static const struct i2c_algorithm omap_i2c_algo = {
010d442c
KS		 1150 .master_xfer = omap_i2c_xfer,
1151 .functionality = omap_i2c_func,
1152};
1153
6145197b 1154#ifdef CONFIG_OF
4c624840
TL		 1155static struct omap_i2c_bus_platform_data omap2420_pdata = {
1156 .rev = OMAP_I2C_IP_VERSION_1,
1157 .flags = OMAP_I2C_FLAG_NO_FIFO |
1158 OMAP_I2C_FLAG_SIMPLE_CLOCK |
1159 OMAP_I2C_FLAG_16BIT_DATA_REG |
1160 OMAP_I2C_FLAG_BUS_SHIFT_2,
1161};
1162
1163static struct omap_i2c_bus_platform_data omap2430_pdata = {
1164 .rev = OMAP_I2C_IP_VERSION_1,
1165 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2 |
1166 OMAP_I2C_FLAG_FORCE_19200_INT_CLK,
1167};
1168
6145197b
BC		 1169static struct omap_i2c_bus_platform_data omap3_pdata = {
1170 .rev = OMAP_I2C_IP_VERSION_1,
972deb4f 1171 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2,
6145197b
BC		 1172};
1173
1174static struct omap_i2c_bus_platform_data omap4_pdata = {
1175 .rev = OMAP_I2C_IP_VERSION_2,
1176};
1177
1178static const struct of_device_id omap_i2c_of_match[] = {
1179 {
1180 .compatible = "ti,omap4-i2c",
1181 .data = &omap4_pdata,
1182 },
1183 {
1184 .compatible = "ti,omap3-i2c",
1185 .data = &omap3_pdata,
1186 },
4c624840
TL		 1187 {
1188 .compatible = "ti,omap2430-i2c",
1189 .data = &omap2430_pdata,
1190 },
1191 {
1192 .compatible = "ti,omap2420-i2c",
1193 .data = &omap2420_pdata,
1194 },
6145197b
BC		 1195 { },
1196};
1197MODULE_DEVICE_TABLE(of, omap_i2c_of_match);
1198#endif
1199
47dcd016
S		 1200#define OMAP_I2C_SCHEME(rev) ((rev & 0xc000) >> 14)
1201
1202#define OMAP_I2C_REV_SCHEME_0_MAJOR(rev) (rev >> 4)
1203#define OMAP_I2C_REV_SCHEME_0_MINOR(rev) (rev & 0xf)
1204
1205#define OMAP_I2C_REV_SCHEME_1_MAJOR(rev) ((rev & 0x0700) >> 7)
1206#define OMAP_I2C_REV_SCHEME_1_MINOR(rev) (rev & 0x1f)
1207#define OMAP_I2C_SCHEME_0 0
1208#define OMAP_I2C_SCHEME_1 1
1209
0b255e92 1210static int
010d442c
KS		 1211omap_i2c_probe(struct platform_device *pdev)
1212{
1213 struct omap_i2c_dev *dev;
1214 struct i2c_adapter *adap;
ac79e4b2 1215 struct resource *mem;
c4dba011 1216 const struct omap_i2c_bus_platform_data *pdata =
6d4028c6 1217 dev_get_platdata(&pdev->dev);
6145197b
BC		 1218 struct device_node *node = pdev->dev.of_node;
1219 const struct of_device_id *match;
ac79e4b2 1220 int irq;
010d442c 1221 int r;
47dcd016 1222 u32 rev;
4368de19 1223 u16 minor, major;
010d442c 1224
ac79e4b2
FB		 1225 irq = platform_get_irq(pdev, 0);
1226 if (irq < 0) {
010d442c 1227 dev_err(&pdev->dev, "no irq resource?\n");
ac79e4b2 1228 return irq;
010d442c
KS		 1229 }
1230
d9ebd04d 1231 dev = devm_kzalloc(&pdev->dev, sizeof(struct omap_i2c_dev), GFP_KERNEL);
46797a2a 1232 if (!dev)
d9ebd04d 1233 return -ENOMEM;
010d442c 1234
3cc2d009 1235 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
84dbf809
TR		 1236 dev->base = devm_ioremap_resource(&pdev->dev, mem);
1237 if (IS_ERR(dev->base))
1238 return PTR_ERR(dev->base);
010d442c 1239
6c5aa407 1240 match = of_match_device(of_match_ptr(omap_i2c_of_match), &pdev->dev);
6145197b
BC		 1241 if (match) {
1242 u32 freq = 100000; /* default to 100000 Hz */
1243
1244 pdata = match->data;
6145197b
BC		 1245 dev->flags = pdata->flags;
1246
1247 of_property_read_u32(node, "clock-frequency", &freq);
1248 /* convert DT freq value in Hz into kHz for speed */
1249 dev->speed = freq / 1000;
1250 } else if (pdata != NULL) {
1251 dev->speed = pdata->clkrate;
1252 dev->flags = pdata->flags;
49839dc9 1253 dev->set_mpu_wkup_lat = pdata->set_mpu_wkup_lat;
20c9d2c4 1254 }
4574eb68 1255
010d442c 1256 dev->dev = &pdev->dev;
ac79e4b2 1257 dev->irq = irq;
55c381e4 1258
3b2f8f82 1259 spin_lock_init(&dev->lock);
55c381e4 1260
010d442c 1261 platform_set_drvdata(pdev, dev);
0e33bbb2 1262 init_completion(&dev->cmd_complete);
010d442c 1263
6145197b 1264 dev->reg_shift = (dev->flags >> OMAP_I2C_FLAG_BUS_SHIFT__SHIFT) & 3;
7c6bd201 1265
7f4b08ee 1266 pm_runtime_enable(dev->dev);
6d8451d5
FB		 1267 pm_runtime_set_autosuspend_delay(dev->dev, OMAP_I2C_PM_TIMEOUT);
1268 pm_runtime_use_autosuspend(dev->dev);
1269
3b0fb97c 1270 r = pm_runtime_get_sync(dev->dev);
ff370257 1271 if (r < 0)
3b0fb97c 1272 goto err_free_mem;
010d442c 1273
47dcd016
S		 1274 /*
1275 * Read the Rev hi bit-[15:14] ie scheme this is 1 indicates ver2.
1276 * On omap1/3/2 Offset 4 is IE Reg the bit [15:14] is 0 at reset.
1277 * Also since the omap_i2c_read_reg uses reg_map_ip_* a
40b13ca8 1278 * readw_relaxed is done.
47dcd016 1279 */
40b13ca8 1280 rev = readw_relaxed(dev->base + 0x04);
47dcd016 1281
4368de19
OD		 1282 dev->scheme = OMAP_I2C_SCHEME(rev);
1283 switch (dev->scheme) {
47dcd016
S		 1284 case OMAP_I2C_SCHEME_0:
1285 dev->regs = (u8 *)reg_map_ip_v1;
1286 dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG);
1287 minor = OMAP_I2C_REV_SCHEME_0_MAJOR(dev->rev);
1288 major = OMAP_I2C_REV_SCHEME_0_MAJOR(dev->rev);
1289 break;
1290 case OMAP_I2C_SCHEME_1:
1291 /* FALLTHROUGH */
1292 default:
1293 dev->regs = (u8 *)reg_map_ip_v2;
1294 rev = (rev << 16) |
1295 omap_i2c_read_reg(dev, OMAP_I2C_IP_V2_REVNB_LO);
1296 minor = OMAP_I2C_REV_SCHEME_1_MINOR(rev);
1297 major = OMAP_I2C_REV_SCHEME_1_MAJOR(rev);
1298 dev->rev = rev;
1299 }
010d442c 1300
9aa8ec67
TK		 1301 dev->errata = 0;
1302
a748021c
S		 1303 if (dev->rev >= OMAP_I2C_REV_ON_2430 &&
1304 dev->rev < OMAP_I2C_REV_ON_4430_PLUS)
9aa8ec67
TK		 1305 dev->errata |= I2C_OMAP_ERRATA_I207;
1306
f518b482 1307 if (dev->rev <= OMAP_I2C_REV_ON_3430_3530)
c8db38f0 1308 dev->errata |= I2C_OMAP_ERRATA_I462;
8a9d97d3 1309
6145197b 1310 if (!(dev->flags & OMAP_I2C_FLAG_NO_FIFO)) {
b6ee52c3
NM		 1311 u16 s;
1312
1313 /* Set up the fifo size - Get total size */
1314 s = (omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3;
1315 dev->fifo_size = 0x8 << s;
1316
1317 /*
1318 * Set up notification threshold as half the total available
1319 * size. This is to ensure that we can handle the status on int
1320 * call back latencies.
1321 */
1d5a34fe
S		 1322
1323 dev->fifo_size = (dev->fifo_size / 2);
1324
47dcd016 1325 if (dev->rev < OMAP_I2C_REV_ON_3630)
f38e66e0 1326 dev->b_hw = 1; /* Enable hardware fixes */
1d5a34fe 1327
20c9d2c4 1328 /* calculate wakeup latency constraint for MPU */
49839dc9
PW		 1329 if (dev->set_mpu_wkup_lat != NULL)
1330 dev->latency = (1000000 * dev->fifo_size) /
1331 (1000 * dev->speed / 8);
b6ee52c3
NM		 1332 }
1333
010d442c
KS		 1334 /* reset ASAP, clearing any IRQs */
1335 omap_i2c_init(dev);
1336
3b2f8f82
FB		 1337 if (dev->rev < OMAP_I2C_OMAP1_REV_2)
1338 r = devm_request_irq(&pdev->dev, dev->irq, omap_i2c_omap1_isr,
1339 IRQF_NO_SUSPEND, pdev->name, dev);
1340 else
1341 r = devm_request_threaded_irq(&pdev->dev, dev->irq,
1342 omap_i2c_isr, omap_i2c_isr_thread,
1343 IRQF_NO_SUSPEND | IRQF_ONESHOT,
1344 pdev->name, dev);
010d442c
KS		 1345
1346 if (r) {
1347 dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
1348 goto err_unuse_clocks;
1349 }
9c76b878 1350
010d442c
KS		 1351 adap = &dev->adapter;
1352 i2c_set_adapdata(adap, dev);
1353 adap->owner = THIS_MODULE;
cfac71d9 1354 adap->class = I2C_CLASS_DEPRECATED;
783fd6fa 1355 strlcpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
010d442c
KS		 1356 adap->algo = &omap_i2c_algo;
1357 adap->dev.parent = &pdev->dev;
6145197b 1358 adap->dev.of_node = pdev->dev.of_node;
010d442c
KS		 1359
1360 /* i2c device drivers may be active on return from add_adapter() */
7c175499
DB		 1361 adap->nr = pdev->id;
1362 r = i2c_add_numbered_adapter(adap);
010d442c
KS		 1363 if (r) {
1364 dev_err(dev->dev, "failure adding adapter\n");
d9ebd04d 1365 goto err_unuse_clocks;
010d442c
KS		 1366 }
1367
cd10c74a
S		 1368 dev_info(dev->dev, "bus %d rev%d.%d at %d kHz\n", adap->nr,
1369 major, minor, dev->speed);
c5d3cd6d 1370
6d8451d5
FB		 1371 pm_runtime_mark_last_busy(dev->dev);
1372 pm_runtime_put_autosuspend(dev->dev);
62ff2c2b 1373
010d442c
KS		 1374 return 0;
1375
010d442c 1376err_unuse_clocks:
3e39752d 1377 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
fab67afb 1378 pm_runtime_put(dev->dev);
24740516 1379 pm_runtime_disable(&pdev->dev);
010d442c 1380err_free_mem:
010d442c
KS		 1381
1382 return r;
1383}
1384
0b255e92 1385static int omap_i2c_remove(struct platform_device *pdev)
010d442c
KS		 1386{
1387 struct omap_i2c_dev *dev = platform_get_drvdata(pdev);
3b0fb97c 1388 int ret;
010d442c 1389
010d442c 1390 i2c_del_adapter(&dev->adapter);
3b0fb97c 1391 ret = pm_runtime_get_sync(&pdev->dev);
ff370257 1392 if (ret < 0)
3b0fb97c
S		 1393 return ret;
1394
010d442c 1395 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
0861f430 1396 pm_runtime_put(&pdev->dev);
24740516 1397 pm_runtime_disable(&pdev->dev);
010d442c
KS		 1398 return 0;
1399}
1400
5692d2a2 1401#ifdef CONFIG_PM
fab67afb
KH		 1402#ifdef CONFIG_PM_RUNTIME
1403static int omap_i2c_runtime_suspend(struct device *dev)
1404{
1405 struct platform_device *pdev = to_platform_device(dev);
1406 struct omap_i2c_dev *_dev = platform_get_drvdata(pdev);
3dae3efb
S		 1407
1408 _dev->iestate = omap_i2c_read_reg(_dev, OMAP_I2C_IE_REG);
bd16c82f 1409
4368de19
OD		 1410 if (_dev->scheme == OMAP_I2C_SCHEME_0)
1411 omap_i2c_write_reg(_dev, OMAP_I2C_IE_REG, 0);
1412 else
1413 omap_i2c_write_reg(_dev, OMAP_I2C_IP_V2_IRQENABLE_CLR,
1414 OMAP_I2C_IP_V2_INTERRUPTS_MASK);
fab67afb 1415
3dae3efb 1416 if (_dev->rev < OMAP_I2C_OMAP1_REV_2) {
27e0fbef 1417 omap_i2c_read_reg(_dev, OMAP_I2C_IV_REG); /* Read clears */
3dae3efb
S		 1418 } else {
1419 omap_i2c_write_reg(_dev, OMAP_I2C_STAT_REG, _dev->iestate);
fab67afb 1420
3dae3efb
S		 1421 /* Flush posted write */
1422 omap_i2c_read_reg(_dev, OMAP_I2C_STAT_REG);
1423 }
fab67afb
KH		 1424
1425 return 0;
1426}
1427
1428static int omap_i2c_runtime_resume(struct device *dev)
1429{
1430 struct platform_device *pdev = to_platform_device(dev);
1431 struct omap_i2c_dev *_dev = platform_get_drvdata(pdev);
1432
47dcd016
S		 1433 if (!_dev->regs)
1434 return 0;
1435
554c9674 1436 __omap_i2c_init(_dev);
fab67afb
KH		 1437
1438 return 0;
1439}
5692d2a2 1440#endif /* CONFIG_PM_RUNTIME */
fab67afb
KH		 1441
1442static struct dev_pm_ops omap_i2c_pm_ops = {
5692d2a2
S		 1443 SET_RUNTIME_PM_OPS(omap_i2c_runtime_suspend,
1444 omap_i2c_runtime_resume, NULL)
fab67afb
KH		 1445};
1446#define OMAP_I2C_PM_OPS (&omap_i2c_pm_ops)
1447#else
1448#define OMAP_I2C_PM_OPS NULL
5692d2a2 1449#endif /* CONFIG_PM */
fab67afb 1450
010d442c
KS		 1451static struct platform_driver omap_i2c_driver = {
1452 .probe = omap_i2c_probe,
0b255e92 1453 .remove = omap_i2c_remove,
010d442c 1454 .driver = {
f7bb0d9a 1455 .name = "omap_i2c",
010d442c 1456 .owner = THIS_MODULE,
fab67afb 1457 .pm = OMAP_I2C_PM_OPS,
6145197b 1458 .of_match_table = of_match_ptr(omap_i2c_of_match),
010d442c
KS		 1459 },
1460};
1461
1462/* I2C may be needed to bring up other drivers */
1463static int __init
1464omap_i2c_init_driver(void)
1465{
1466 return platform_driver_register(&omap_i2c_driver);
1467}
1468subsys_initcall(omap_i2c_init_driver);
1469
1470static void __exit omap_i2c_exit_driver(void)
1471{
1472 platform_driver_unregister(&omap_i2c_driver);
1473}
1474module_exit(omap_i2c_exit_driver);
1475
1476MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
1477MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
1478MODULE_LICENSE("GPL");
f7bb0d9a 1479MODULE_ALIAS("platform:omap_i2c");
Linux kernel - Deliverables
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