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i2c: OMAP2/3: Fix scll/sclh calculations
[deliverable/linux.git] / drivers / i2c / busses / i2c-omap.c
CommitLineData
010d442c
KS		 1/*
2 * TI OMAP I2C master mode driver
3 *
4 * Copyright (C) 2003 MontaVista Software, Inc.
010d442c 5 * Copyright (C) 2005 Nokia Corporation
c1a473bd 6 * Copyright (C) 2004 - 2007 Texas Instruments.
010d442c 7 *
c1a473bd
TL		 8 * Originally written by MontaVista Software, Inc.
9 * Additional contributions by:
10 * Tony Lindgren <tony@atomide.com>
11 * Imre Deak <imre.deak@nokia.com>
12 * Juha Yrjölä <juha.yrjola@solidboot.com>
13 * Syed Khasim <x0khasim@ti.com>
14 * Nishant Menon <nm@ti.com>
010d442c
KS		 15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
30
31#include <linux/module.h>
32#include <linux/delay.h>
33#include <linux/i2c.h>
34#include <linux/err.h>
35#include <linux/interrupt.h>
36#include <linux/completion.h>
37#include <linux/platform_device.h>
38#include <linux/clk.h>
c1a473bd 39#include <linux/io.h>
010d442c 40
9c76b878
PW		 41/* I2C controller revisions */
42#define OMAP_I2C_REV_2 0x20
43
44/* I2C controller revisions present on specific hardware */
45#define OMAP_I2C_REV_ON_2430 0x36
46#define OMAP_I2C_REV_ON_3430 0x3C
47
010d442c
KS		 48/* timeout waiting for the controller to respond */
49#define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
50
51#define OMAP_I2C_REV_REG 0x00
52#define OMAP_I2C_IE_REG 0x04
53#define OMAP_I2C_STAT_REG 0x08
54#define OMAP_I2C_IV_REG 0x0c
5043e9e7
KJ		 55/* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */
56#define OMAP_I2C_WE_REG 0x0c
010d442c
KS		 57#define OMAP_I2C_SYSS_REG 0x10
58#define OMAP_I2C_BUF_REG 0x14
59#define OMAP_I2C_CNT_REG 0x18
60#define OMAP_I2C_DATA_REG 0x1c
61#define OMAP_I2C_SYSC_REG 0x20
62#define OMAP_I2C_CON_REG 0x24
63#define OMAP_I2C_OA_REG 0x28
64#define OMAP_I2C_SA_REG 0x2c
65#define OMAP_I2C_PSC_REG 0x30
66#define OMAP_I2C_SCLL_REG 0x34
67#define OMAP_I2C_SCLH_REG 0x38
68#define OMAP_I2C_SYSTEST_REG 0x3c
b6ee52c3 69#define OMAP_I2C_BUFSTAT_REG 0x40
010d442c
KS		 70
71/* I2C Interrupt Enable Register (OMAP_I2C_IE): */
b6ee52c3
NM		 72#define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */
73#define OMAP_I2C_IE_RDR (1 << 13) /* RX Buffer drain int enable */
010d442c
KS		 74#define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */
75#define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */
76#define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */
77#define OMAP_I2C_IE_NACK (1 << 1) /* No ack interrupt enable */
78#define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */
79
80/* I2C Status Register (OMAP_I2C_STAT): */
b6ee52c3
NM		 81#define OMAP_I2C_STAT_XDR (1 << 14) /* TX Buffer draining */
82#define OMAP_I2C_STAT_RDR (1 << 13) /* RX Buffer draining */
010d442c
KS		 83#define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */
84#define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */
85#define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
86#define OMAP_I2C_STAT_AAS (1 << 9) /* Address as slave */
87#define OMAP_I2C_STAT_AD0 (1 << 8) /* Address zero */
88#define OMAP_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
89#define OMAP_I2C_STAT_RRDY (1 << 3) /* Receive data ready */
90#define OMAP_I2C_STAT_ARDY (1 << 2) /* Register access ready */
91#define OMAP_I2C_STAT_NACK (1 << 1) /* No ack interrupt enable */
92#define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost int ena */
93
5043e9e7
KJ		 94/* I2C WE wakeup enable register */
95#define OMAP_I2C_WE_XDR_WE (1 << 14) /* TX drain wakup */
96#define OMAP_I2C_WE_RDR_WE (1 << 13) /* RX drain wakeup */
97#define OMAP_I2C_WE_AAS_WE (1 << 9) /* Address as slave wakeup*/
98#define OMAP_I2C_WE_BF_WE (1 << 8) /* Bus free wakeup */
99#define OMAP_I2C_WE_STC_WE (1 << 6) /* Start condition wakeup */
100#define OMAP_I2C_WE_GC_WE (1 << 5) /* General call wakeup */
101#define OMAP_I2C_WE_DRDY_WE (1 << 3) /* TX/RX data ready wakeup */
102#define OMAP_I2C_WE_ARDY_WE (1 << 2) /* Reg access ready wakeup */
103#define OMAP_I2C_WE_NACK_WE (1 << 1) /* No acknowledgment wakeup */
104#define OMAP_I2C_WE_AL_WE (1 << 0) /* Arbitration lost wakeup */
105
106#define OMAP_I2C_WE_ALL (OMAP_I2C_WE_XDR_WE | OMAP_I2C_WE_RDR_WE | \
107 OMAP_I2C_WE_AAS_WE | OMAP_I2C_WE_BF_WE | \
108 OMAP_I2C_WE_STC_WE | OMAP_I2C_WE_GC_WE | \
109 OMAP_I2C_WE_DRDY_WE | OMAP_I2C_WE_ARDY_WE | \
110 OMAP_I2C_WE_NACK_WE | OMAP_I2C_WE_AL_WE)
111
010d442c
KS		 112/* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
113#define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */
b6ee52c3 114#define OMAP_I2C_BUF_RXFIF_CLR (1 << 14) /* RX FIFO Clear */
010d442c 115#define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */
b6ee52c3 116#define OMAP_I2C_BUF_TXFIF_CLR (1 << 6) /* TX FIFO Clear */
010d442c
KS		 117
118/* I2C Configuration Register (OMAP_I2C_CON): */
119#define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */
120#define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */
b6ee52c3 121#define OMAP_I2C_CON_OPMODE_HS (1 << 12) /* High Speed support */
010d442c
KS		 122#define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */
123#define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */
124#define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */
125#define OMAP_I2C_CON_XA (1 << 8) /* Expand address */
126#define OMAP_I2C_CON_RM (1 << 2) /* Repeat mode (master only) */
127#define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */
128#define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */
129
4574eb68
SMK		 130/* I2C SCL time value when Master */
131#define OMAP_I2C_SCLL_HSSCLL 8
132#define OMAP_I2C_SCLH_HSSCLH 8
133
010d442c
KS		 134/* I2C System Test Register (OMAP_I2C_SYSTEST): */
135#ifdef DEBUG
136#define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */
137#define OMAP_I2C_SYSTEST_FREE (1 << 14) /* Free running mode */
138#define OMAP_I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */
139#define OMAP_I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */
140#define OMAP_I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense in */
141#define OMAP_I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive out */
142#define OMAP_I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense in */
143#define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */
144#endif
145
fdd07fe6
PW		 146/* OCP_SYSSTATUS bit definitions */
147#define SYSS_RESETDONE_MASK (1 << 0)
148
149/* OCP_SYSCONFIG bit definitions */
150#define SYSC_CLOCKACTIVITY_MASK (0x3 << 8)
151#define SYSC_SIDLEMODE_MASK (0x3 << 3)
152#define SYSC_ENAWAKEUP_MASK (1 << 2)
153#define SYSC_SOFTRESET_MASK (1 << 1)
154#define SYSC_AUTOIDLE_MASK (1 << 0)
155
156#define SYSC_IDLEMODE_SMART 0x2
157#define SYSC_CLOCKACTIVITY_FCLK 0x2
010d442c 158
010d442c 159
010d442c
KS		 160struct omap_i2c_dev {
161 struct device *dev;
162 void __iomem *base; /* virtual */
163 int irq;
164 struct clk *iclk; /* Interface clock */
165 struct clk *fclk; /* Functional clock */
166 struct completion cmd_complete;
167 struct resource *ioarea;
4574eb68 168 u32 speed; /* Speed of bus in Khz */
010d442c
KS		 169 u16 cmd_err;
170 u8 *buf;
171 size_t buf_len;
172 struct i2c_adapter adapter;
b6ee52c3
NM		 173 u8 fifo_size; /* use as flag and value
174 * fifo_size==0 implies no fifo
175 * if set, should be trsh+1
176 */
9c76b878 177 u8 rev;
b6ee52c3 178 unsigned b_hw:1; /* bad h/w fixes */
f08ac4e7
TL		 179 unsigned idle:1;
180 u16 iestate; /* Saved interrupt register */
010d442c
KS		 181};
182
183static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev,
184 int reg, u16 val)
185{
186 __raw_writew(val, i2c_dev->base + reg);
187}
188
189static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
190{
191 return __raw_readw(i2c_dev->base + reg);
192}
193
510be9c9 194static int __init omap_i2c_get_clocks(struct omap_i2c_dev *dev)
010d442c 195{
5fe23380
RK		 196 int ret;
197
198 dev->iclk = clk_get(dev->dev, "ick");
199 if (IS_ERR(dev->iclk)) {
200 ret = PTR_ERR(dev->iclk);
201 dev->iclk = NULL;
202 return ret;
010d442c
KS		 203 }
204
1d14de08 205 dev->fclk = clk_get(dev->dev, "fck");
010d442c 206 if (IS_ERR(dev->fclk)) {
5fe23380 207 ret = PTR_ERR(dev->fclk);
010d442c
KS		 208 if (dev->iclk != NULL) {
209 clk_put(dev->iclk);
210 dev->iclk = NULL;
211 }
212 dev->fclk = NULL;
5fe23380 213 return ret;
010d442c
KS		 214 }
215
216 return 0;
217}
218
219static void omap_i2c_put_clocks(struct omap_i2c_dev *dev)
220{
221 clk_put(dev->fclk);
222 dev->fclk = NULL;
5fe23380
RK		 223 clk_put(dev->iclk);
224 dev->iclk = NULL;
010d442c
KS		 225}
226
f08ac4e7 227static void omap_i2c_unidle(struct omap_i2c_dev *dev)
010d442c 228{
3831f154
PW		 229 WARN_ON(!dev->idle);
230
5fe23380 231 clk_enable(dev->iclk);
010d442c 232 clk_enable(dev->fclk);
0cbbcffd 233 dev->idle = 0;
f08ac4e7
TL		 234 if (dev->iestate)
235 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
010d442c
KS		 236}
237
f08ac4e7 238static void omap_i2c_idle(struct omap_i2c_dev *dev)
010d442c 239{
f08ac4e7
TL		 240 u16 iv;
241
3831f154
PW		 242 WARN_ON(dev->idle);
243
f08ac4e7
TL		 244 dev->iestate = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
245 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, 0);
9c76b878 246 if (dev->rev < OMAP_I2C_REV_2) {
c1a473bd 247 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG); /* Read clears */
0cbbcffd 248 } else {
f08ac4e7 249 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, dev->iestate);
0cbbcffd
PW		 250
251 /* Flush posted write before the dev->idle store occurs */
252 omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
253 }
254 dev->idle = 1;
f08ac4e7 255 clk_disable(dev->fclk);
5fe23380 256 clk_disable(dev->iclk);
010d442c
KS		 257}
258
259static int omap_i2c_init(struct omap_i2c_dev *dev)
260{
4574eb68
SMK		 261 u16 psc = 0, scll = 0, sclh = 0;
262 u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
010d442c
KS		 263 unsigned long fclk_rate = 12000000;
264 unsigned long timeout;
4574eb68 265 unsigned long internal_clk = 0;
010d442c 266
9c76b878 267 if (dev->rev >= OMAP_I2C_REV_2) {
fdd07fe6 268 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK);
010d442c
KS		 269 /* For some reason we need to set the EN bit before the
270 * reset done bit gets set. */
271 timeout = jiffies + OMAP_I2C_TIMEOUT;
272 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
273 while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) &
fdd07fe6 274 SYSS_RESETDONE_MASK)) {
010d442c 275 if (time_after(jiffies, timeout)) {
fce3ff03 276 dev_warn(dev->dev, "timeout waiting "
010d442c
KS		 277 "for controller reset\n");
278 return -ETIMEDOUT;
279 }
280 msleep(1);
281 }
fdd07fe6
PW		 282
283 /* SYSC register is cleared by the reset; rewrite it */
284 if (dev->rev == OMAP_I2C_REV_ON_2430) {
285
286 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG,
287 SYSC_AUTOIDLE_MASK);
288
289 } else if (dev->rev >= OMAP_I2C_REV_ON_3430) {
290 u32 v;
291
292 v = SYSC_AUTOIDLE_MASK;
293 v |= SYSC_ENAWAKEUP_MASK;
294 v |= (SYSC_IDLEMODE_SMART <<
295 __ffs(SYSC_SIDLEMODE_MASK));
296 v |= (SYSC_CLOCKACTIVITY_FCLK <<
297 __ffs(SYSC_CLOCKACTIVITY_MASK));
298
299 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, v);
5043e9e7
KJ		 300 /*
301 * Enabling all wakup sources to stop I2C freezing on
302 * WFI instruction.
303 * REVISIT: Some wkup sources might not be needed.
304 */
305 omap_i2c_write_reg(dev, OMAP_I2C_WE_REG,
306 OMAP_I2C_WE_ALL);
fdd07fe6
PW		 307
308 }
010d442c
KS		 309 }
310 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
311
312 if (cpu_class_is_omap1()) {
0e9ae109
RK		 313 /*
314 * The I2C functional clock is the armxor_ck, so there's
315 * no need to get "armxor_ck" separately. Now, if OMAP2420
316 * always returns 12MHz for the functional clock, we can
317 * do this bit unconditionally.
318 */
319 fclk_rate = clk_get_rate(dev->fclk);
320
010d442c
KS		 321 /* TRM for 5912 says the I2C clock must be prescaled to be
322 * between 7 - 12 MHz. The XOR input clock is typically
323 * 12, 13 or 19.2 MHz. So we should have code that produces:
324 *
325 * XOR MHz Divider Prescaler
326 * 12 1 0
327 * 13 2 1
328 * 19.2 2 1
329 */
d7aef138
JD		 330 if (fclk_rate > 12000000)
331 psc = fclk_rate / 12000000;
010d442c
KS		 332 }
333
3d522fb4 334 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
4574eb68
SMK		 335
336 /* HSI2C controller internal clk rate should be 19.2 Mhz */
337 internal_clk = 19200;
338 fclk_rate = clk_get_rate(dev->fclk) / 1000;
339
340 /* Compute prescaler divisor */
341 psc = fclk_rate / internal_clk;
342 psc = psc - 1;
343
344 /* If configured for High Speed */
345 if (dev->speed > 400) {
baf46b4e
AK		 346 unsigned long scl;
347
4574eb68 348 /* For first phase of HS mode */
baf46b4e
AK		 349 scl = internal_clk / 400;
350 fsscll = scl - (scl / 3) - 7;
351 fssclh = (scl / 3) - 5;
4574eb68
SMK		 352
353 /* For second phase of HS mode */
baf46b4e
AK		 354 scl = fclk_rate / dev->speed;
355 hsscll = scl - (scl / 3) - 7;
356 hssclh = (scl / 3) - 5;
357 } else if (dev->speed > 100) {
358 unsigned long scl;
359
360 /* Fast mode */
361 scl = internal_clk / dev->speed;
362 fsscll = scl - (scl / 3) - 7;
363 fssclh = (scl / 3) - 5;
4574eb68 364 } else {
baf46b4e
AK		 365 /* Standard mode */
366 fsscll = internal_clk / (dev->speed * 2) - 7;
367 fssclh = internal_clk / (dev->speed * 2) - 5;
4574eb68
SMK		 368 }
369 scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
370 sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
371 } else {
372 /* Program desired operating rate */
373 fclk_rate /= (psc + 1) * 1000;
374 if (psc > 2)
375 psc = 2;
376 scll = fclk_rate / (dev->speed * 2) - 7 + psc;
377 sclh = fclk_rate / (dev->speed * 2) - 7 + psc;
378 }
379
010d442c
KS		 380 /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
381 omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc);
382
4574eb68
SMK		 383 /* SCL low and high time values */
384 omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, scll);
385 omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, sclh);
010d442c 386
b6ee52c3
NM		 387 if (dev->fifo_size)
388 /* Note: setup required fifo size - 1 */
389 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG,
390 (dev->fifo_size - 1) << 8 | /* RTRSH */
391 OMAP_I2C_BUF_RXFIF_CLR |
392 (dev->fifo_size - 1) | /* XTRSH */
393 OMAP_I2C_BUF_TXFIF_CLR);
394
010d442c
KS		 395 /* Take the I2C module out of reset: */
396 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
397
398 /* Enable interrupts */
399 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG,
c1a473bd
TL		 400 (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
401 OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
402 OMAP_I2C_IE_AL) | ((dev->fifo_size) ?
b6ee52c3 403 (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0));
010d442c
KS		 404 return 0;
405}
406
407/*
408 * Waiting on Bus Busy
409 */
410static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev)
411{
412 unsigned long timeout;
413
414 timeout = jiffies + OMAP_I2C_TIMEOUT;
415 while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
416 if (time_after(jiffies, timeout)) {
417 dev_warn(dev->dev, "timeout waiting for bus ready\n");
418 return -ETIMEDOUT;
419 }
420 msleep(1);
421 }
422
423 return 0;
424}
425
426/*
427 * Low level master read/write transaction.
428 */
429static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
430 struct i2c_msg *msg, int stop)
431{
432 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
433 int r;
434 u16 w;
435
436 dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
437 msg->addr, msg->len, msg->flags, stop);
438
439 if (msg->len == 0)
440 return -EINVAL;
441
442 omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);
443
444 /* REVISIT: Could the STB bit of I2C_CON be used with probing? */
445 dev->buf = msg->buf;
446 dev->buf_len = msg->len;
447
448 omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len);
449
b6ee52c3
NM		 450 /* Clear the FIFO Buffers */
451 w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
452 w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR;
453 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w);
454
010d442c
KS		 455 init_completion(&dev->cmd_complete);
456 dev->cmd_err = 0;
457
458 w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
4574eb68
SMK		 459
460 /* High speed configuration */
461 if (dev->speed > 400)
b6ee52c3 462 w |= OMAP_I2C_CON_OPMODE_HS;
4574eb68 463
010d442c
KS		 464 if (msg->flags & I2C_M_TEN)
465 w |= OMAP_I2C_CON_XA;
466 if (!(msg->flags & I2C_M_RD))
467 w |= OMAP_I2C_CON_TRX;
c1a473bd 468
b6ee52c3 469 if (!dev->b_hw && stop)
010d442c 470 w |= OMAP_I2C_CON_STP;
c1a473bd 471
010d442c
KS		 472 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
473
b6ee52c3
NM		 474 /*
475 * Don't write stt and stp together on some hardware.
476 */
477 if (dev->b_hw && stop) {
478 unsigned long delay = jiffies + OMAP_I2C_TIMEOUT;
479 u16 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
480 while (con & OMAP_I2C_CON_STT) {
481 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
482
483 /* Let the user know if i2c is in a bad state */
484 if (time_after(jiffies, delay)) {
485 dev_err(dev->dev, "controller timed out "
486 "waiting for start condition to finish\n");
487 return -ETIMEDOUT;
488 }
489 cpu_relax();
490 }
491
492 w |= OMAP_I2C_CON_STP;
493 w &= ~OMAP_I2C_CON_STT;
494 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
495 }
496
b7af349b
JN		 497 /*
498 * REVISIT: We should abort the transfer on signals, but the bus goes
499 * into arbitration and we're currently unable to recover from it.
500 */
501 r = wait_for_completion_timeout(&dev->cmd_complete,
502 OMAP_I2C_TIMEOUT);
010d442c
KS		 503 dev->buf_len = 0;
504 if (r < 0)
505 return r;
506 if (r == 0) {
507 dev_err(dev->dev, "controller timed out\n");
508 omap_i2c_init(dev);
509 return -ETIMEDOUT;
510 }
511
512 if (likely(!dev->cmd_err))
513 return 0;
514
515 /* We have an error */
516 if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR |
517 OMAP_I2C_STAT_XUDF)) {
518 omap_i2c_init(dev);
519 return -EIO;
520 }
521
522 if (dev->cmd_err & OMAP_I2C_STAT_NACK) {
523 if (msg->flags & I2C_M_IGNORE_NAK)
524 return 0;
525 if (stop) {
526 w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
527 w |= OMAP_I2C_CON_STP;
528 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
529 }
530 return -EREMOTEIO;
531 }
532 return -EIO;
533}
534
535
536/*
537 * Prepare controller for a transaction and call omap_i2c_xfer_msg
538 * to do the work during IRQ processing.
539 */
540static int
541omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
542{
543 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
544 int i;
545 int r;
546
f08ac4e7 547 omap_i2c_unidle(dev);
010d442c 548
c1a473bd
TL		 549 r = omap_i2c_wait_for_bb(dev);
550 if (r < 0)
010d442c
KS		 551 goto out;
552
553 for (i = 0; i < num; i++) {
554 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));
555 if (r != 0)
556 break;
557 }
558
559 if (r == 0)
560 r = num;
561out:
f08ac4e7 562 omap_i2c_idle(dev);
010d442c
KS		 563 return r;
564}
565
566static u32
567omap_i2c_func(struct i2c_adapter *adap)
568{
569 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
570}
571
572static inline void
573omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err)
574{
575 dev->cmd_err |= err;
576 complete(&dev->cmd_complete);
577}
578
579static inline void
580omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat)
581{
582 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
583}
584
43469d8e
PW		 585/* rev1 devices are apparently only on some 15xx */
586#ifdef CONFIG_ARCH_OMAP15XX
587
010d442c 588static irqreturn_t
7d12e780 589omap_i2c_rev1_isr(int this_irq, void *dev_id)
010d442c
KS		 590{
591 struct omap_i2c_dev *dev = dev_id;
592 u16 iv, w;
593
f08ac4e7
TL		 594 if (dev->idle)
595 return IRQ_NONE;
596
010d442c
KS		 597 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
598 switch (iv) {
599 case 0x00: /* None */
600 break;
601 case 0x01: /* Arbitration lost */
602 dev_err(dev->dev, "Arbitration lost\n");
603 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
604 break;
605 case 0x02: /* No acknowledgement */
606 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
607 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
608 break;
609 case 0x03: /* Register access ready */
610 omap_i2c_complete_cmd(dev, 0);
611 break;
612 case 0x04: /* Receive data ready */
613 if (dev->buf_len) {
614 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
615 *dev->buf++ = w;
616 dev->buf_len--;
617 if (dev->buf_len) {
618 *dev->buf++ = w >> 8;
619 dev->buf_len--;
620 }
621 } else
622 dev_err(dev->dev, "RRDY IRQ while no data requested\n");
623 break;
624 case 0x05: /* Transmit data ready */
625 if (dev->buf_len) {
626 w = *dev->buf++;
627 dev->buf_len--;
628 if (dev->buf_len) {
629 w |= *dev->buf++ << 8;
630 dev->buf_len--;
631 }
632 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
633 } else
634 dev_err(dev->dev, "XRDY IRQ while no data to send\n");
635 break;
636 default:
637 return IRQ_NONE;
638 }
639
640 return IRQ_HANDLED;
641}
43469d8e 642#else
c1a473bd 643#define omap_i2c_rev1_isr NULL
43469d8e 644#endif
010d442c
KS		 645
646static irqreturn_t
7d12e780 647omap_i2c_isr(int this_irq, void *dev_id)
010d442c
KS		 648{
649 struct omap_i2c_dev *dev = dev_id;
650 u16 bits;
651 u16 stat, w;
b6ee52c3 652 int err, count = 0;
010d442c 653
f08ac4e7
TL		 654 if (dev->idle)
655 return IRQ_NONE;
656
010d442c
KS		 657 bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
658 while ((stat = (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG))) & bits) {
659 dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat);
660 if (count++ == 100) {
661 dev_warn(dev->dev, "Too much work in one IRQ\n");
662 break;
663 }
664
665 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
666
b6ee52c3
NM		 667 err = 0;
668 if (stat & OMAP_I2C_STAT_NACK) {
669 err |= OMAP_I2C_STAT_NACK;
670 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
671 OMAP_I2C_CON_STP);
010d442c 672 }
b6ee52c3
NM		 673 if (stat & OMAP_I2C_STAT_AL) {
674 dev_err(dev->dev, "Arbitration lost\n");
675 err |= OMAP_I2C_STAT_AL;
676 }
677 if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
678 OMAP_I2C_STAT_AL))
679 omap_i2c_complete_cmd(dev, err);
680 if (stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR)) {
681 u8 num_bytes = 1;
682 if (dev->fifo_size) {
683 if (stat & OMAP_I2C_STAT_RRDY)
684 num_bytes = dev->fifo_size;
685 else
686 num_bytes = omap_i2c_read_reg(dev,
687 OMAP_I2C_BUFSTAT_REG);
688 }
689 while (num_bytes) {
690 num_bytes--;
691 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
010d442c 692 if (dev->buf_len) {
b6ee52c3 693 *dev->buf++ = w;
010d442c 694 dev->buf_len--;
b6ee52c3 695 /* Data reg from 2430 is 8 bit wide */
3d522fb4
C		 696 if (!cpu_is_omap2430() &&
697 !cpu_is_omap34xx()) {
b6ee52c3
NM		 698 if (dev->buf_len) {
699 *dev->buf++ = w >> 8;
700 dev->buf_len--;
701 }
702 }
703 } else {
704 if (stat & OMAP_I2C_STAT_RRDY)
705 dev_err(dev->dev,
706 "RRDY IRQ while no data"
707 " requested\n");
708 if (stat & OMAP_I2C_STAT_RDR)
709 dev_err(dev->dev,
710 "RDR IRQ while no data"
711 " requested\n");
712 break;
010d442c 713 }
b6ee52c3
NM		 714 }
715 omap_i2c_ack_stat(dev,
716 stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR));
010d442c
KS		 717 continue;
718 }
b6ee52c3
NM		 719 if (stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR)) {
720 u8 num_bytes = 1;
721 if (dev->fifo_size) {
722 if (stat & OMAP_I2C_STAT_XRDY)
723 num_bytes = dev->fifo_size;
724 else
725 num_bytes = omap_i2c_read_reg(dev,
726 OMAP_I2C_BUFSTAT_REG);
727 }
728 while (num_bytes) {
729 num_bytes--;
730 w = 0;
010d442c 731 if (dev->buf_len) {
b6ee52c3 732 w = *dev->buf++;
010d442c 733 dev->buf_len--;
b6ee52c3 734 /* Data reg from 2430 is 8 bit wide */
3d522fb4
C		 735 if (!cpu_is_omap2430() &&
736 !cpu_is_omap34xx()) {
b6ee52c3
NM		 737 if (dev->buf_len) {
738 w |= *dev->buf++ << 8;
739 dev->buf_len--;
740 }
741 }
742 } else {
743 if (stat & OMAP_I2C_STAT_XRDY)
744 dev_err(dev->dev,
745 "XRDY IRQ while no "
746 "data to send\n");
747 if (stat & OMAP_I2C_STAT_XDR)
748 dev_err(dev->dev,
749 "XDR IRQ while no "
750 "data to send\n");
751 break;
010d442c 752 }
b6ee52c3
NM		 753 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
754 }
755 omap_i2c_ack_stat(dev,
756 stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
010d442c
KS		 757 continue;
758 }
759 if (stat & OMAP_I2C_STAT_ROVR) {
760 dev_err(dev->dev, "Receive overrun\n");
761 dev->cmd_err |= OMAP_I2C_STAT_ROVR;
762 }
763 if (stat & OMAP_I2C_STAT_XUDF) {
b6ee52c3 764 dev_err(dev->dev, "Transmit underflow\n");
010d442c
KS		 765 dev->cmd_err |= OMAP_I2C_STAT_XUDF;
766 }
010d442c
KS		 767 }
768
769 return count ? IRQ_HANDLED : IRQ_NONE;
770}
771
8f9082c5 772static const struct i2c_algorithm omap_i2c_algo = {
010d442c
KS		 773 .master_xfer = omap_i2c_xfer,
774 .functionality = omap_i2c_func,
775};
776
510be9c9 777static int __init
010d442c
KS		 778omap_i2c_probe(struct platform_device *pdev)
779{
780 struct omap_i2c_dev *dev;
781 struct i2c_adapter *adap;
782 struct resource *mem, *irq, *ioarea;
e355204e 783 irq_handler_t isr;
010d442c 784 int r;
3d522fb4 785 u32 speed = 0;
010d442c
KS		 786
787 /* NOTE: driver uses the static register mapping */
788 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
789 if (!mem) {
790 dev_err(&pdev->dev, "no mem resource?\n");
791 return -ENODEV;
792 }
793 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
794 if (!irq) {
795 dev_err(&pdev->dev, "no irq resource?\n");
796 return -ENODEV;
797 }
798
799 ioarea = request_mem_region(mem->start, (mem->end - mem->start) + 1,
800 pdev->name);
801 if (!ioarea) {
802 dev_err(&pdev->dev, "I2C region already claimed\n");
803 return -EBUSY;
804 }
805
010d442c
KS		 806 dev = kzalloc(sizeof(struct omap_i2c_dev), GFP_KERNEL);
807 if (!dev) {
808 r = -ENOMEM;
809 goto err_release_region;
810 }
811
4574eb68 812 if (pdev->dev.platform_data != NULL)
3d522fb4 813 speed = *(u32 *)pdev->dev.platform_data;
4574eb68 814 else
3d522fb4 815 speed = 100; /* Defualt speed */
4574eb68 816
3d522fb4 817 dev->speed = speed;
3831f154 818 dev->idle = 1;
010d442c
KS		 819 dev->dev = &pdev->dev;
820 dev->irq = irq->start;
55c381e4
RK		 821 dev->base = ioremap(mem->start, mem->end - mem->start + 1);
822 if (!dev->base) {
823 r = -ENOMEM;
824 goto err_free_mem;
825 }
826
010d442c
KS		 827 platform_set_drvdata(pdev, dev);
828
829 if ((r = omap_i2c_get_clocks(dev)) != 0)
55c381e4 830 goto err_iounmap;
010d442c 831
f08ac4e7 832 omap_i2c_unidle(dev);
010d442c 833
9c76b878 834 dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff;
010d442c 835
3d522fb4 836 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
b6ee52c3
NM		 837 u16 s;
838
839 /* Set up the fifo size - Get total size */
840 s = (omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3;
841 dev->fifo_size = 0x8 << s;
842
843 /*
844 * Set up notification threshold as half the total available
845 * size. This is to ensure that we can handle the status on int
846 * call back latencies.
847 */
848 dev->fifo_size = (dev->fifo_size / 2);
849 dev->b_hw = 1; /* Enable hardware fixes */
850 }
851
010d442c
KS		 852 /* reset ASAP, clearing any IRQs */
853 omap_i2c_init(dev);
854
9c76b878
PW		 855 isr = (dev->rev < OMAP_I2C_REV_2) ? omap_i2c_rev1_isr : omap_i2c_isr;
856 r = request_irq(dev->irq, isr, 0, pdev->name, dev);
010d442c
KS		 857
858 if (r) {
859 dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
860 goto err_unuse_clocks;
861 }
9c76b878 862
010d442c 863 dev_info(dev->dev, "bus %d rev%d.%d at %d kHz\n",
9c76b878 864 pdev->id, dev->rev >> 4, dev->rev & 0xf, dev->speed);
010d442c 865
3831f154
PW		 866 omap_i2c_idle(dev);
867
010d442c
KS		 868 adap = &dev->adapter;
869 i2c_set_adapdata(adap, dev);
870 adap->owner = THIS_MODULE;
871 adap->class = I2C_CLASS_HWMON;
872 strncpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
873 adap->algo = &omap_i2c_algo;
874 adap->dev.parent = &pdev->dev;
875
876 /* i2c device drivers may be active on return from add_adapter() */
7c175499
DB		 877 adap->nr = pdev->id;
878 r = i2c_add_numbered_adapter(adap);
010d442c
KS		 879 if (r) {
880 dev_err(dev->dev, "failure adding adapter\n");
881 goto err_free_irq;
882 }
883
010d442c
KS		 884 return 0;
885
886err_free_irq:
887 free_irq(dev->irq, dev);
888err_unuse_clocks:
3e39752d 889 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
f08ac4e7 890 omap_i2c_idle(dev);
010d442c 891 omap_i2c_put_clocks(dev);
55c381e4
RK		 892err_iounmap:
893 iounmap(dev->base);
010d442c
KS		 894err_free_mem:
895 platform_set_drvdata(pdev, NULL);
896 kfree(dev);
897err_release_region:
010d442c
KS		 898 release_mem_region(mem->start, (mem->end - mem->start) + 1);
899
900 return r;
901}
902
903static int
904omap_i2c_remove(struct platform_device *pdev)
905{
906 struct omap_i2c_dev *dev = platform_get_drvdata(pdev);
907 struct resource *mem;
908
909 platform_set_drvdata(pdev, NULL);
910
911 free_irq(dev->irq, dev);
912 i2c_del_adapter(&dev->adapter);
913 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
914 omap_i2c_put_clocks(dev);
55c381e4 915 iounmap(dev->base);
010d442c
KS		 916 kfree(dev);
917 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
918 release_mem_region(mem->start, (mem->end - mem->start) + 1);
919 return 0;
920}
921
922static struct platform_driver omap_i2c_driver = {
923 .probe = omap_i2c_probe,
924 .remove = omap_i2c_remove,
925 .driver = {
926 .name = "i2c_omap",
927 .owner = THIS_MODULE,
928 },
929};
930
931/* I2C may be needed to bring up other drivers */
932static int __init
933omap_i2c_init_driver(void)
934{
935 return platform_driver_register(&omap_i2c_driver);
936}
937subsys_initcall(omap_i2c_init_driver);
938
939static void __exit omap_i2c_exit_driver(void)
940{
941 platform_driver_unregister(&omap_i2c_driver);
942}
943module_exit(omap_i2c_exit_driver);
944
945MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
946MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
947MODULE_LICENSE("GPL");
add8eda7 948MODULE_ALIAS("platform:i2c_omap");
Linux kernel - Deliverables
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