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i2c: omap: resize fifos before each message
[deliverable/linux.git] / drivers / i2c / busses / i2c-omap.c
CommitLineData
010d442c
KS		 1/*
2 * TI OMAP I2C master mode driver
3 *
4 * Copyright (C) 2003 MontaVista Software, Inc.
010d442c 5 * Copyright (C) 2005 Nokia Corporation
c1a473bd 6 * Copyright (C) 2004 - 2007 Texas Instruments.
010d442c 7 *
c1a473bd
TL		 8 * Originally written by MontaVista Software, Inc.
9 * Additional contributions by:
10 * Tony Lindgren <tony@atomide.com>
11 * Imre Deak <imre.deak@nokia.com>
12 * Juha Yrjölä <juha.yrjola@solidboot.com>
13 * Syed Khasim <x0khasim@ti.com>
14 * Nishant Menon <nm@ti.com>
010d442c
KS		 15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
30
31#include <linux/module.h>
32#include <linux/delay.h>
33#include <linux/i2c.h>
34#include <linux/err.h>
35#include <linux/interrupt.h>
36#include <linux/completion.h>
37#include <linux/platform_device.h>
38#include <linux/clk.h>
c1a473bd 39#include <linux/io.h>
6145197b
BC		 40#include <linux/of.h>
41#include <linux/of_i2c.h>
42#include <linux/of_device.h>
5a0e3ad6 43#include <linux/slab.h>
20c9d2c4 44#include <linux/i2c-omap.h>
27b1fec2 45#include <linux/pm_runtime.h>
010d442c 46
9c76b878 47/* I2C controller revisions */
4e80f727 48#define OMAP_I2C_OMAP1_REV_2 0x20
9c76b878
PW		 49
50/* I2C controller revisions present on specific hardware */
51#define OMAP_I2C_REV_ON_2430 0x36
f518b482
JH		 52#define OMAP_I2C_REV_ON_3430_3530 0x3C
53#define OMAP_I2C_REV_ON_3630_4430 0x40
9c76b878 54
010d442c
KS		 55/* timeout waiting for the controller to respond */
56#define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
57
5043e9e7 58/* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */
f38e66e0
SS		 59enum {
60 OMAP_I2C_REV_REG = 0,
61 OMAP_I2C_IE_REG,
62 OMAP_I2C_STAT_REG,
63 OMAP_I2C_IV_REG,
64 OMAP_I2C_WE_REG,
65 OMAP_I2C_SYSS_REG,
66 OMAP_I2C_BUF_REG,
67 OMAP_I2C_CNT_REG,
68 OMAP_I2C_DATA_REG,
69 OMAP_I2C_SYSC_REG,
70 OMAP_I2C_CON_REG,
71 OMAP_I2C_OA_REG,
72 OMAP_I2C_SA_REG,
73 OMAP_I2C_PSC_REG,
74 OMAP_I2C_SCLL_REG,
75 OMAP_I2C_SCLH_REG,
76 OMAP_I2C_SYSTEST_REG,
77 OMAP_I2C_BUFSTAT_REG,
b8853088
AG		 78 /* only on OMAP4430 */
79 OMAP_I2C_IP_V2_REVNB_LO,
80 OMAP_I2C_IP_V2_REVNB_HI,
81 OMAP_I2C_IP_V2_IRQSTATUS_RAW,
82 OMAP_I2C_IP_V2_IRQENABLE_SET,
83 OMAP_I2C_IP_V2_IRQENABLE_CLR,
f38e66e0 84};
010d442c
KS		 85
86/* I2C Interrupt Enable Register (OMAP_I2C_IE): */
b6ee52c3
NM		 87#define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */
88#define OMAP_I2C_IE_RDR (1 << 13) /* RX Buffer drain int enable */
010d442c
KS		 89#define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */
90#define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */
91#define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */
92#define OMAP_I2C_IE_NACK (1 << 1) /* No ack interrupt enable */
93#define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */
94
95/* I2C Status Register (OMAP_I2C_STAT): */
b6ee52c3
NM		 96#define OMAP_I2C_STAT_XDR (1 << 14) /* TX Buffer draining */
97#define OMAP_I2C_STAT_RDR (1 << 13) /* RX Buffer draining */
010d442c
KS		 98#define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */
99#define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */
100#define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
101#define OMAP_I2C_STAT_AAS (1 << 9) /* Address as slave */
102#define OMAP_I2C_STAT_AD0 (1 << 8) /* Address zero */
103#define OMAP_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
104#define OMAP_I2C_STAT_RRDY (1 << 3) /* Receive data ready */
105#define OMAP_I2C_STAT_ARDY (1 << 2) /* Register access ready */
106#define OMAP_I2C_STAT_NACK (1 << 1) /* No ack interrupt enable */
107#define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost int ena */
108
5043e9e7
KJ		 109/* I2C WE wakeup enable register */
110#define OMAP_I2C_WE_XDR_WE (1 << 14) /* TX drain wakup */
111#define OMAP_I2C_WE_RDR_WE (1 << 13) /* RX drain wakeup */
112#define OMAP_I2C_WE_AAS_WE (1 << 9) /* Address as slave wakeup*/
113#define OMAP_I2C_WE_BF_WE (1 << 8) /* Bus free wakeup */
114#define OMAP_I2C_WE_STC_WE (1 << 6) /* Start condition wakeup */
115#define OMAP_I2C_WE_GC_WE (1 << 5) /* General call wakeup */
116#define OMAP_I2C_WE_DRDY_WE (1 << 3) /* TX/RX data ready wakeup */
117#define OMAP_I2C_WE_ARDY_WE (1 << 2) /* Reg access ready wakeup */
118#define OMAP_I2C_WE_NACK_WE (1 << 1) /* No acknowledgment wakeup */
119#define OMAP_I2C_WE_AL_WE (1 << 0) /* Arbitration lost wakeup */
120
121#define OMAP_I2C_WE_ALL (OMAP_I2C_WE_XDR_WE | OMAP_I2C_WE_RDR_WE | \
122 OMAP_I2C_WE_AAS_WE | OMAP_I2C_WE_BF_WE | \
123 OMAP_I2C_WE_STC_WE | OMAP_I2C_WE_GC_WE | \
124 OMAP_I2C_WE_DRDY_WE | OMAP_I2C_WE_ARDY_WE | \
125 OMAP_I2C_WE_NACK_WE | OMAP_I2C_WE_AL_WE)
126
010d442c
KS		 127/* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
128#define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */
b6ee52c3 129#define OMAP_I2C_BUF_RXFIF_CLR (1 << 14) /* RX FIFO Clear */
010d442c 130#define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */
b6ee52c3 131#define OMAP_I2C_BUF_TXFIF_CLR (1 << 6) /* TX FIFO Clear */
010d442c
KS		 132
133/* I2C Configuration Register (OMAP_I2C_CON): */
134#define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */
135#define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */
b6ee52c3 136#define OMAP_I2C_CON_OPMODE_HS (1 << 12) /* High Speed support */
010d442c
KS		 137#define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */
138#define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */
139#define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */
140#define OMAP_I2C_CON_XA (1 << 8) /* Expand address */
141#define OMAP_I2C_CON_RM (1 << 2) /* Repeat mode (master only) */
142#define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */
143#define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */
144
4574eb68
SMK		 145/* I2C SCL time value when Master */
146#define OMAP_I2C_SCLL_HSSCLL 8
147#define OMAP_I2C_SCLH_HSSCLH 8
148
010d442c
KS		 149/* I2C System Test Register (OMAP_I2C_SYSTEST): */
150#ifdef DEBUG
151#define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */
152#define OMAP_I2C_SYSTEST_FREE (1 << 14) /* Free running mode */
153#define OMAP_I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */
154#define OMAP_I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */
155#define OMAP_I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense in */
156#define OMAP_I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive out */
157#define OMAP_I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense in */
158#define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */
159#endif
160
fdd07fe6
PW		 161/* OCP_SYSSTATUS bit definitions */
162#define SYSS_RESETDONE_MASK (1 << 0)
163
164/* OCP_SYSCONFIG bit definitions */
165#define SYSC_CLOCKACTIVITY_MASK (0x3 << 8)
166#define SYSC_SIDLEMODE_MASK (0x3 << 3)
167#define SYSC_ENAWAKEUP_MASK (1 << 2)
168#define SYSC_SOFTRESET_MASK (1 << 1)
169#define SYSC_AUTOIDLE_MASK (1 << 0)
170
171#define SYSC_IDLEMODE_SMART 0x2
172#define SYSC_CLOCKACTIVITY_FCLK 0x2
010d442c 173
f3083d92 174/* Errata definitions */
175#define I2C_OMAP_ERRATA_I207 (1 << 0)
c8db38f0 176#define I2C_OMAP_ERRATA_I462 (1 << 1)
010d442c 177
010d442c
KS		 178struct omap_i2c_dev {
179 struct device *dev;
180 void __iomem *base; /* virtual */
181 int irq;
d84d3ea3 182 int reg_shift; /* bit shift for I2C register addresses */
010d442c
KS		 183 struct completion cmd_complete;
184 struct resource *ioarea;
20c9d2c4
KJ		 185 u32 latency; /* maximum mpu wkup latency */
186 void (*set_mpu_wkup_lat)(struct device *dev,
187 long latency);
6145197b
BC		 188 u32 speed; /* Speed of bus in kHz */
189 u32 dtrev; /* extra revision from DT */
190 u32 flags;
010d442c
KS		 191 u16 cmd_err;
192 u8 *buf;
f38e66e0 193 u8 *regs;
010d442c
KS		 194 size_t buf_len;
195 struct i2c_adapter adapter;
dd74548d 196 u8 threshold;
b6ee52c3
NM		 197 u8 fifo_size; /* use as flag and value
198 * fifo_size==0 implies no fifo
199 * if set, should be trsh+1
200 */
9c76b878 201 u8 rev;
b6ee52c3 202 unsigned b_hw:1; /* bad h/w fixes */
079d8af2 203 unsigned receiver:1; /* true when we're in receiver mode */
f08ac4e7 204 u16 iestate; /* Saved interrupt register */
ef871432
RN		 205 u16 pscstate;
206 u16 scllstate;
207 u16 sclhstate;
208 u16 bufstate;
209 u16 syscstate;
210 u16 westate;
f3083d92 211 u16 errata;
010d442c
KS		 212};
213
a1295577 214static const u8 reg_map_ip_v1[] = {
f38e66e0
SS		 215 [OMAP_I2C_REV_REG] = 0x00,
216 [OMAP_I2C_IE_REG] = 0x01,
217 [OMAP_I2C_STAT_REG] = 0x02,
218 [OMAP_I2C_IV_REG] = 0x03,
219 [OMAP_I2C_WE_REG] = 0x03,
220 [OMAP_I2C_SYSS_REG] = 0x04,
221 [OMAP_I2C_BUF_REG] = 0x05,
222 [OMAP_I2C_CNT_REG] = 0x06,
223 [OMAP_I2C_DATA_REG] = 0x07,
224 [OMAP_I2C_SYSC_REG] = 0x08,
225 [OMAP_I2C_CON_REG] = 0x09,
226 [OMAP_I2C_OA_REG] = 0x0a,
227 [OMAP_I2C_SA_REG] = 0x0b,
228 [OMAP_I2C_PSC_REG] = 0x0c,
229 [OMAP_I2C_SCLL_REG] = 0x0d,
230 [OMAP_I2C_SCLH_REG] = 0x0e,
231 [OMAP_I2C_SYSTEST_REG] = 0x0f,
232 [OMAP_I2C_BUFSTAT_REG] = 0x10,
233};
234
a1295577 235static const u8 reg_map_ip_v2[] = {
f38e66e0
SS		 236 [OMAP_I2C_REV_REG] = 0x04,
237 [OMAP_I2C_IE_REG] = 0x2c,
238 [OMAP_I2C_STAT_REG] = 0x28,
239 [OMAP_I2C_IV_REG] = 0x34,
240 [OMAP_I2C_WE_REG] = 0x34,
241 [OMAP_I2C_SYSS_REG] = 0x90,
242 [OMAP_I2C_BUF_REG] = 0x94,
243 [OMAP_I2C_CNT_REG] = 0x98,
244 [OMAP_I2C_DATA_REG] = 0x9c,
2727b175 245 [OMAP_I2C_SYSC_REG] = 0x10,
f38e66e0
SS		 246 [OMAP_I2C_CON_REG] = 0xa4,
247 [OMAP_I2C_OA_REG] = 0xa8,
248 [OMAP_I2C_SA_REG] = 0xac,
249 [OMAP_I2C_PSC_REG] = 0xb0,
250 [OMAP_I2C_SCLL_REG] = 0xb4,
251 [OMAP_I2C_SCLH_REG] = 0xb8,
252 [OMAP_I2C_SYSTEST_REG] = 0xbC,
253 [OMAP_I2C_BUFSTAT_REG] = 0xc0,
b8853088
AG		 254 [OMAP_I2C_IP_V2_REVNB_LO] = 0x00,
255 [OMAP_I2C_IP_V2_REVNB_HI] = 0x04,
256 [OMAP_I2C_IP_V2_IRQSTATUS_RAW] = 0x24,
257 [OMAP_I2C_IP_V2_IRQENABLE_SET] = 0x2c,
258 [OMAP_I2C_IP_V2_IRQENABLE_CLR] = 0x30,
f38e66e0
SS		 259};
260
010d442c
KS		 261static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev,
262 int reg, u16 val)
263{
f38e66e0
SS		 264 __raw_writew(val, i2c_dev->base +
265 (i2c_dev->regs[reg] << i2c_dev->reg_shift));
010d442c
KS		 266}
267
268static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
269{
f38e66e0
SS		 270 return __raw_readw(i2c_dev->base +
271 (i2c_dev->regs[reg] << i2c_dev->reg_shift));
010d442c
KS		 272}
273
010d442c
KS		 274static int omap_i2c_init(struct omap_i2c_dev *dev)
275{
ef871432 276 u16 psc = 0, scll = 0, sclh = 0, buf = 0;
4574eb68 277 u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
010d442c
KS		 278 unsigned long fclk_rate = 12000000;
279 unsigned long timeout;
4574eb68 280 unsigned long internal_clk = 0;
27b1fec2 281 struct clk *fclk;
010d442c 282
4e80f727 283 if (dev->rev >= OMAP_I2C_OMAP1_REV_2) {
57eb81b1
MG		 284 /* Disable I2C controller before soft reset */
285 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
286 omap_i2c_read_reg(dev, OMAP_I2C_CON_REG) &
287 ~(OMAP_I2C_CON_EN));
288
fdd07fe6 289 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK);
010d442c
KS		 290 /* For some reason we need to set the EN bit before the
291 * reset done bit gets set. */
292 timeout = jiffies + OMAP_I2C_TIMEOUT;
293 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
294 while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) &
fdd07fe6 295 SYSS_RESETDONE_MASK)) {
010d442c 296 if (time_after(jiffies, timeout)) {
fce3ff03 297 dev_warn(dev->dev, "timeout waiting "
010d442c
KS		 298 "for controller reset\n");
299 return -ETIMEDOUT;
300 }
301 msleep(1);
302 }
fdd07fe6
PW		 303
304 /* SYSC register is cleared by the reset; rewrite it */
305 if (dev->rev == OMAP_I2C_REV_ON_2430) {
306
307 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG,
308 SYSC_AUTOIDLE_MASK);
309
f518b482 310 } else if (dev->rev >= OMAP_I2C_REV_ON_3430_3530) {
ef871432
RN		 311 dev->syscstate = SYSC_AUTOIDLE_MASK;
312 dev->syscstate |= SYSC_ENAWAKEUP_MASK;
313 dev->syscstate |= (SYSC_IDLEMODE_SMART <<
fdd07fe6 314 __ffs(SYSC_SIDLEMODE_MASK));
ef871432 315 dev->syscstate |= (SYSC_CLOCKACTIVITY_FCLK <<
fdd07fe6
PW		 316 __ffs(SYSC_CLOCKACTIVITY_MASK));
317
ef871432
RN		 318 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG,
319 dev->syscstate);
5043e9e7
KJ		 320 /*
321 * Enabling all wakup sources to stop I2C freezing on
322 * WFI instruction.
323 * REVISIT: Some wkup sources might not be needed.
324 */
ef871432 325 dev->westate = OMAP_I2C_WE_ALL;
cb28e582
S		 326 omap_i2c_write_reg(dev, OMAP_I2C_WE_REG,
327 dev->westate);
fdd07fe6 328 }
010d442c
KS		 329 }
330 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
331
6145197b 332 if (dev->flags & OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK) {
0e9ae109
RK		 333 /*
334 * The I2C functional clock is the armxor_ck, so there's
335 * no need to get "armxor_ck" separately. Now, if OMAP2420
336 * always returns 12MHz for the functional clock, we can
337 * do this bit unconditionally.
338 */
27b1fec2
RN		 339 fclk = clk_get(dev->dev, "fck");
340 fclk_rate = clk_get_rate(fclk);
341 clk_put(fclk);
0e9ae109 342
010d442c
KS		 343 /* TRM for 5912 says the I2C clock must be prescaled to be
344 * between 7 - 12 MHz. The XOR input clock is typically
345 * 12, 13 or 19.2 MHz. So we should have code that produces:
346 *
347 * XOR MHz Divider Prescaler
348 * 12 1 0
349 * 13 2 1
350 * 19.2 2 1
351 */
d7aef138
JD		 352 if (fclk_rate > 12000000)
353 psc = fclk_rate / 12000000;
010d442c
KS		 354 }
355
6145197b 356 if (!(dev->flags & OMAP_I2C_FLAG_SIMPLE_CLOCK)) {
4574eb68 357
84bf2c86
AK		 358 /*
359 * HSI2C controller internal clk rate should be 19.2 Mhz for
360 * HS and for all modes on 2430. On 34xx we can use lower rate
361 * to get longer filter period for better noise suppression.
362 * The filter is iclk (fclk for HS) period.
363 */
3be0053e 364 if (dev->speed > 400 ||
6145197b 365 dev->flags & OMAP_I2C_FLAG_FORCE_19200_INT_CLK)
84bf2c86
AK		 366 internal_clk = 19200;
367 else if (dev->speed > 100)
368 internal_clk = 9600;
369 else
370 internal_clk = 4000;
27b1fec2
RN		 371 fclk = clk_get(dev->dev, "fck");
372 fclk_rate = clk_get_rate(fclk) / 1000;
373 clk_put(fclk);
4574eb68
SMK		 374
375 /* Compute prescaler divisor */
376 psc = fclk_rate / internal_clk;
377 psc = psc - 1;
378
379 /* If configured for High Speed */
380 if (dev->speed > 400) {
baf46b4e
AK		 381 unsigned long scl;
382
4574eb68 383 /* For first phase of HS mode */
baf46b4e
AK		 384 scl = internal_clk / 400;
385 fsscll = scl - (scl / 3) - 7;
386 fssclh = (scl / 3) - 5;
4574eb68
SMK		 387
388 /* For second phase of HS mode */
baf46b4e
AK		 389 scl = fclk_rate / dev->speed;
390 hsscll = scl - (scl / 3) - 7;
391 hssclh = (scl / 3) - 5;
392 } else if (dev->speed > 100) {
393 unsigned long scl;
394
395 /* Fast mode */
396 scl = internal_clk / dev->speed;
397 fsscll = scl - (scl / 3) - 7;
398 fssclh = (scl / 3) - 5;
4574eb68 399 } else {
baf46b4e
AK		 400 /* Standard mode */
401 fsscll = internal_clk / (dev->speed * 2) - 7;
402 fssclh = internal_clk / (dev->speed * 2) - 5;
4574eb68
SMK		 403 }
404 scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
405 sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
406 } else {
407 /* Program desired operating rate */
408 fclk_rate /= (psc + 1) * 1000;
409 if (psc > 2)
410 psc = 2;
411 scll = fclk_rate / (dev->speed * 2) - 7 + psc;
412 sclh = fclk_rate / (dev->speed * 2) - 7 + psc;
413 }
414
010d442c
KS		 415 /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
416 omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc);
417
4574eb68
SMK		 418 /* SCL low and high time values */
419 omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, scll);
420 omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, sclh);
010d442c
KS		 421
422 /* Take the I2C module out of reset: */
423 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
424
425 /* Enable interrupts */
ef871432 426 dev->iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
c1a473bd
TL		 427 OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
428 OMAP_I2C_IE_AL) | ((dev->fifo_size) ?
ef871432
RN		 429 (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0);
430 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
6145197b 431 if (dev->flags & OMAP_I2C_FLAG_RESET_REGS_POSTIDLE) {
ef871432
RN		 432 dev->pscstate = psc;
433 dev->scllstate = scll;
434 dev->sclhstate = sclh;
435 dev->bufstate = buf;
436 }
010d442c
KS		 437 return 0;
438}
439
440/*
441 * Waiting on Bus Busy
442 */
443static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev)
444{
445 unsigned long timeout;
446
447 timeout = jiffies + OMAP_I2C_TIMEOUT;
448 while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
449 if (time_after(jiffies, timeout)) {
450 dev_warn(dev->dev, "timeout waiting for bus ready\n");
451 return -ETIMEDOUT;
452 }
453 msleep(1);
454 }
455
456 return 0;
457}
458
dd74548d
FB		 459static void omap_i2c_resize_fifo(struct omap_i2c_dev *dev, u8 size, bool is_rx)
460{
461 u16 buf;
462
463 if (dev->flags & OMAP_I2C_FLAG_NO_FIFO)
464 return;
465
466 /*
467 * Set up notification threshold based on message size. We're doing
468 * this to try and avoid draining feature as much as possible. Whenever
469 * we have big messages to transfer (bigger than our total fifo size)
470 * then we might use draining feature to transfer the remaining bytes.
471 */
472
473 dev->threshold = clamp(size, (u8) 1, dev->fifo_size);
474
475 buf = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
476
477 if (is_rx) {
478 /* Clear RX Threshold */
479 buf &= ~(0x3f << 8);
480 buf |= ((dev->threshold - 1) << 8) | OMAP_I2C_BUF_RXFIF_CLR;
481 } else {
482 /* Clear TX Threshold */
483 buf &= ~0x3f;
484 buf |= (dev->threshold - 1) | OMAP_I2C_BUF_TXFIF_CLR;
485 }
486
487 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, buf);
488
489 if (dev->rev < OMAP_I2C_REV_ON_3630_4430)
490 dev->b_hw = 1; /* Enable hardware fixes */
491
492 /* calculate wakeup latency constraint for MPU */
493 if (dev->set_mpu_wkup_lat != NULL)
494 dev->latency = (1000000 * dev->threshold) /
495 (1000 * dev->speed / 8);
496}
497
010d442c
KS		 498/*
499 * Low level master read/write transaction.
500 */
501static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
502 struct i2c_msg *msg, int stop)
503{
504 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
33d54985 505 unsigned long timeout;
010d442c
KS		 506 u16 w;
507
508 dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
509 msg->addr, msg->len, msg->flags, stop);
510
511 if (msg->len == 0)
512 return -EINVAL;
513
dd74548d
FB		 514 dev->receiver = !!(msg->flags & I2C_M_RD);
515 omap_i2c_resize_fifo(dev, msg->len, dev->receiver);
516
010d442c
KS		 517 omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);
518
519 /* REVISIT: Could the STB bit of I2C_CON be used with probing? */
520 dev->buf = msg->buf;
521 dev->buf_len = msg->len;
522
523 omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len);
524
b6ee52c3
NM		 525 /* Clear the FIFO Buffers */
526 w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
527 w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR;
528 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w);
529
0e33bbb2 530 INIT_COMPLETION(dev->cmd_complete);
010d442c
KS		 531 dev->cmd_err = 0;
532
533 w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
4574eb68
SMK		 534
535 /* High speed configuration */
536 if (dev->speed > 400)
b6ee52c3 537 w |= OMAP_I2C_CON_OPMODE_HS;
4574eb68 538
fb604a3d
LP		 539 if (msg->flags & I2C_M_STOP)
540 stop = 1;
010d442c
KS		 541 if (msg->flags & I2C_M_TEN)
542 w |= OMAP_I2C_CON_XA;
543 if (!(msg->flags & I2C_M_RD))
544 w |= OMAP_I2C_CON_TRX;
c1a473bd 545
b6ee52c3 546 if (!dev->b_hw && stop)
010d442c 547 w |= OMAP_I2C_CON_STP;
c1a473bd 548
010d442c
KS		 549 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
550
b6ee52c3
NM		 551 /*
552 * Don't write stt and stp together on some hardware.
553 */
554 if (dev->b_hw && stop) {
555 unsigned long delay = jiffies + OMAP_I2C_TIMEOUT;
556 u16 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
557 while (con & OMAP_I2C_CON_STT) {
558 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
559
560 /* Let the user know if i2c is in a bad state */
561 if (time_after(jiffies, delay)) {
562 dev_err(dev->dev, "controller timed out "
563 "waiting for start condition to finish\n");
564 return -ETIMEDOUT;
565 }
566 cpu_relax();
567 }
568
569 w |= OMAP_I2C_CON_STP;
570 w &= ~OMAP_I2C_CON_STT;
571 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
572 }
573
b7af349b
JN		 574 /*
575 * REVISIT: We should abort the transfer on signals, but the bus goes
576 * into arbitration and we're currently unable to recover from it.
577 */
33d54985
S		 578 timeout = wait_for_completion_timeout(&dev->cmd_complete,
579 OMAP_I2C_TIMEOUT);
010d442c 580 dev->buf_len = 0;
33d54985 581 if (timeout == 0) {
010d442c
KS		 582 dev_err(dev->dev, "controller timed out\n");
583 omap_i2c_init(dev);
584 return -ETIMEDOUT;
585 }
586
587 if (likely(!dev->cmd_err))
588 return 0;
589
590 /* We have an error */
591 if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR |
592 OMAP_I2C_STAT_XUDF)) {
593 omap_i2c_init(dev);
594 return -EIO;
595 }
596
597 if (dev->cmd_err & OMAP_I2C_STAT_NACK) {
598 if (msg->flags & I2C_M_IGNORE_NAK)
599 return 0;
600 if (stop) {
601 w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
602 w |= OMAP_I2C_CON_STP;
603 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
604 }
605 return -EREMOTEIO;
606 }
607 return -EIO;
608}
609
610
611/*
612 * Prepare controller for a transaction and call omap_i2c_xfer_msg
613 * to do the work during IRQ processing.
614 */
615static int
616omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
617{
618 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
619 int i;
620 int r;
621
3b0fb97c
S		 622 r = pm_runtime_get_sync(dev->dev);
623 if (IS_ERR_VALUE(r))
33ec5e81 624 goto out;
010d442c 625
c1a473bd
TL		 626 r = omap_i2c_wait_for_bb(dev);
627 if (r < 0)
010d442c
KS		 628 goto out;
629
6a91b558
SO		 630 if (dev->set_mpu_wkup_lat != NULL)
631 dev->set_mpu_wkup_lat(dev->dev, dev->latency);
632
010d442c
KS		 633 for (i = 0; i < num; i++) {
634 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));
635 if (r != 0)
636 break;
637 }
638
6a91b558
SO		 639 if (dev->set_mpu_wkup_lat != NULL)
640 dev->set_mpu_wkup_lat(dev->dev, -1);
641
010d442c
KS		 642 if (r == 0)
643 r = num;
5c64eb26
MN		 644
645 omap_i2c_wait_for_bb(dev);
010d442c 646out:
fab67afb 647 pm_runtime_put(dev->dev);
010d442c
KS		 648 return r;
649}
650
651static u32
652omap_i2c_func(struct i2c_adapter *adap)
653{
fb604a3d
LP		 654 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
655 I2C_FUNC_PROTOCOL_MANGLING;
010d442c
KS		 656}
657
658static inline void
659omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err)
660{
661 dev->cmd_err |= err;
662 complete(&dev->cmd_complete);
663}
664
665static inline void
666omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat)
667{
668 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
669}
670
f3083d92 671static inline void i2c_omap_errata_i207(struct omap_i2c_dev *dev, u16 stat)
672{
673 /*
674 * I2C Errata(Errata Nos. OMAP2: 1.67, OMAP3: 1.8)
675 * Not applicable for OMAP4.
676 * Under certain rare conditions, RDR could be set again
677 * when the bus is busy, then ignore the interrupt and
678 * clear the interrupt.
679 */
680 if (stat & OMAP_I2C_STAT_RDR) {
681 /* Step 1: If RDR is set, clear it */
682 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
683
684 /* Step 2: */
685 if (!(omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG)
686 & OMAP_I2C_STAT_BB)) {
687
688 /* Step 3: */
689 if (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG)
690 & OMAP_I2C_STAT_RDR) {
691 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
692 dev_dbg(dev->dev, "RDR when bus is busy.\n");
693 }
694
695 }
696 }
697}
698
43469d8e
PW		 699/* rev1 devices are apparently only on some 15xx */
700#ifdef CONFIG_ARCH_OMAP15XX
701
010d442c 702static irqreturn_t
4e80f727 703omap_i2c_omap1_isr(int this_irq, void *dev_id)
010d442c
KS		 704{
705 struct omap_i2c_dev *dev = dev_id;
706 u16 iv, w;
707
fab67afb 708 if (pm_runtime_suspended(dev->dev))
f08ac4e7
TL		 709 return IRQ_NONE;
710
010d442c
KS		 711 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
712 switch (iv) {
713 case 0x00: /* None */
714 break;
715 case 0x01: /* Arbitration lost */
716 dev_err(dev->dev, "Arbitration lost\n");
717 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
718 break;
719 case 0x02: /* No acknowledgement */
720 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
721 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
722 break;
723 case 0x03: /* Register access ready */
724 omap_i2c_complete_cmd(dev, 0);
725 break;
726 case 0x04: /* Receive data ready */
727 if (dev->buf_len) {
728 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
729 *dev->buf++ = w;
730 dev->buf_len--;
731 if (dev->buf_len) {
732 *dev->buf++ = w >> 8;
733 dev->buf_len--;
734 }
735 } else
736 dev_err(dev->dev, "RRDY IRQ while no data requested\n");
737 break;
738 case 0x05: /* Transmit data ready */
739 if (dev->buf_len) {
740 w = *dev->buf++;
741 dev->buf_len--;
742 if (dev->buf_len) {
743 w |= *dev->buf++ << 8;
744 dev->buf_len--;
745 }
746 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
747 } else
748 dev_err(dev->dev, "XRDY IRQ while no data to send\n");
749 break;
750 default:
751 return IRQ_NONE;
752 }
753
754 return IRQ_HANDLED;
755}
43469d8e 756#else
4e80f727 757#define omap_i2c_omap1_isr NULL
43469d8e 758#endif
010d442c 759
2dd151ab 760/*
c8db38f0 761 * OMAP3430 Errata i462: When an XRDY/XDR is hit, wait for XUDF before writing
2dd151ab
AS		 762 * data to DATA_REG. Otherwise some data bytes can be lost while transferring
763 * them from the memory to the I2C interface.
764 */
4151e741 765static int errata_omap3_i462(struct omap_i2c_dev *dev)
2dd151ab 766{
e9f59b9c 767 unsigned long timeout = 10000;
4151e741 768 u16 stat;
e9f59b9c 769
4151e741
FB		 770 do {
771 stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
772 if (stat & OMAP_I2C_STAT_XUDF)
773 break;
774
775 if (stat & (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) {
540a4790 776 omap_i2c_ack_stat(dev, (OMAP_I2C_STAT_XRDY |
2dd151ab 777 OMAP_I2C_STAT_XDR));
4151e741 778 return -EIO;
2dd151ab 779 }
e9f59b9c 780
2dd151ab 781 cpu_relax();
4151e741 782 } while (--timeout);
2dd151ab 783
e9f59b9c
AS		 784 if (!timeout) {
785 dev_err(dev->dev, "timeout waiting on XUDF bit\n");
786 return 0;
787 }
788
2dd151ab
AS		 789 return 0;
790}
791
3312d25e
FB		 792static void omap_i2c_receive_data(struct omap_i2c_dev *dev, u8 num_bytes,
793 bool is_rdr)
794{
795 u16 w;
796
797 while (num_bytes--) {
3312d25e
FB		 798 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
799 *dev->buf++ = w;
800 dev->buf_len--;
801
802 /*
803 * Data reg in 2430, omap3 and
804 * omap4 is 8 bit wide
805 */
806 if (dev->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) {
dd74548d
FB		 807 *dev->buf++ = w >> 8;
808 dev->buf_len--;
3312d25e
FB		 809 }
810 }
811}
812
813static int omap_i2c_transmit_data(struct omap_i2c_dev *dev, u8 num_bytes,
814 bool is_xdr)
815{
816 u16 w;
817
818 while (num_bytes--) {
3312d25e
FB		 819 w = *dev->buf++;
820 dev->buf_len--;
821
822 /*
823 * Data reg in 2430, omap3 and
824 * omap4 is 8 bit wide
825 */
826 if (dev->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) {
dd74548d
FB		 827 w |= *dev->buf++ << 8;
828 dev->buf_len--;
3312d25e
FB		 829 }
830
831 if (dev->errata & I2C_OMAP_ERRATA_I462) {
832 int ret;
833
834 ret = errata_omap3_i462(dev);
835 if (ret < 0)
836 return ret;
837 }
838
839 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
840 }
841
842 return 0;
843}
844
010d442c 845static irqreturn_t
7d12e780 846omap_i2c_isr(int this_irq, void *dev_id)
010d442c
KS		 847{
848 struct omap_i2c_dev *dev = dev_id;
849 u16 bits;
3312d25e 850 u16 stat;
66b92988 851 int err = 0, count = 0;
010d442c 852
fab67afb 853 if (pm_runtime_suspended(dev->dev))
f08ac4e7
TL		 854 return IRQ_NONE;
855
66b92988
FB		 856 do {
857 bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
858 stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
859 stat &= bits;
860
079d8af2
FB		 861 /* If we're in receiver mode, ignore XDR/XRDY */
862 if (dev->receiver)
863 stat &= ~(OMAP_I2C_STAT_XDR | OMAP_I2C_STAT_XRDY);
864 else
865 stat &= ~(OMAP_I2C_STAT_RDR | OMAP_I2C_STAT_RRDY);
866
66b92988
FB		 867 if (!stat) {
868 /* my work here is done */
869 return IRQ_HANDLED;
870 }
871
010d442c
KS		 872 dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat);
873 if (count++ == 100) {
874 dev_warn(dev->dev, "Too much work in one IRQ\n");
4a7ec4ed 875 goto out;
010d442c
KS		 876 }
877
cd086d3a 878complete:
1d7afc95 879 if (stat & OMAP_I2C_STAT_NACK) {
b6ee52c3 880 err |= OMAP_I2C_STAT_NACK;
1d7afc95 881 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_NACK);
4a7ec4ed 882 goto out;
1d7afc95 883 }
78e1cf42 884
b6ee52c3
NM		 885 if (stat & OMAP_I2C_STAT_AL) {
886 dev_err(dev->dev, "Arbitration lost\n");
887 err |= OMAP_I2C_STAT_AL;
1d7afc95 888 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_AL);
4a7ec4ed 889 goto out;
b6ee52c3 890 }
c55edb99 891
a5a595cc 892 /*
cb527ede 893 * ProDB0017052: Clear ARDY bit twice
a5a595cc 894 */
b6ee52c3 895 if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
04c688dd 896 OMAP_I2C_STAT_AL)) {
540a4790
FB		 897 omap_i2c_ack_stat(dev, (OMAP_I2C_STAT_RRDY |
898 OMAP_I2C_STAT_RDR |
899 OMAP_I2C_STAT_XRDY |
900 OMAP_I2C_STAT_XDR |
901 OMAP_I2C_STAT_ARDY));
4a7ec4ed 902 goto out;
04c688dd 903 }
c55edb99 904
6d9939f6 905 if (stat & OMAP_I2C_STAT_RDR) {
b6ee52c3 906 u8 num_bytes = 1;
f3083d92 907
6d9939f6
FB		 908 if (dev->fifo_size)
909 num_bytes = dev->buf_len;
910
3312d25e 911 omap_i2c_receive_data(dev, num_bytes, true);
6d9939f6 912
f3083d92 913 if (dev->errata & I2C_OMAP_ERRATA_I207)
914 i2c_omap_errata_i207(dev, stat);
915
6d9939f6
FB		 916 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
917 continue;
918 }
919
920 if (stat & OMAP_I2C_STAT_RRDY) {
921 u8 num_bytes = 1;
922
dd74548d
FB		 923 if (dev->threshold)
924 num_bytes = dev->threshold;
6d9939f6 925
3312d25e 926 omap_i2c_receive_data(dev, num_bytes, false);
6d9939f6 927 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RRDY);
010d442c
KS		 928 continue;
929 }
c55edb99 930
6d9939f6 931 if (stat & OMAP_I2C_STAT_XDR) {
b6ee52c3 932 u8 num_bytes = 1;
3312d25e 933 int ret;
6d9939f6
FB		 934
935 if (dev->fifo_size)
936 num_bytes = dev->buf_len;
937
3312d25e
FB		 938 ret = omap_i2c_transmit_data(dev, num_bytes, true);
939 stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
940 if (ret < 0)
941 goto complete;
6d9939f6
FB		 942
943 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XDR);
944 continue;
945 }
946
947 if (stat & OMAP_I2C_STAT_XRDY) {
948 u8 num_bytes = 1;
3312d25e 949 int ret;
6d9939f6 950
dd74548d
FB		 951 if (dev->threshold)
952 num_bytes = dev->threshold;
6d9939f6 953
3312d25e
FB		 954 ret = omap_i2c_transmit_data(dev, num_bytes, false);
955 stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
956 if (ret < 0)
957 goto complete;
6d9939f6
FB		 958
959 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XRDY);
010d442c
KS		 960 continue;
961 }
c55edb99 962
010d442c
KS		 963 if (stat & OMAP_I2C_STAT_ROVR) {
964 dev_err(dev->dev, "Receive overrun\n");
1d7afc95
FB		 965 err |= OMAP_I2C_STAT_ROVR;
966 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_ROVR);
4a7ec4ed 967 goto out;
010d442c 968 }
c55edb99 969
010d442c 970 if (stat & OMAP_I2C_STAT_XUDF) {
b6ee52c3 971 dev_err(dev->dev, "Transmit underflow\n");
1d7afc95
FB		 972 err |= OMAP_I2C_STAT_XUDF;
973 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XUDF);
4a7ec4ed 974 goto out;
010d442c 975 }
66b92988 976 } while (stat);
010d442c 977
4a7ec4ed
FB		 978out:
979 omap_i2c_complete_cmd(dev, err);
6a85ced2 980 return IRQ_HANDLED;
010d442c
KS		 981}
982
8f9082c5 983static const struct i2c_algorithm omap_i2c_algo = {
010d442c
KS		 984 .master_xfer = omap_i2c_xfer,
985 .functionality = omap_i2c_func,
986};
987
6145197b
BC		 988#ifdef CONFIG_OF
989static struct omap_i2c_bus_platform_data omap3_pdata = {
990 .rev = OMAP_I2C_IP_VERSION_1,
991 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
992 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
993 OMAP_I2C_FLAG_BUS_SHIFT_2,
994};
995
996static struct omap_i2c_bus_platform_data omap4_pdata = {
997 .rev = OMAP_I2C_IP_VERSION_2,
998};
999
1000static const struct of_device_id omap_i2c_of_match[] = {
1001 {
1002 .compatible = "ti,omap4-i2c",
1003 .data = &omap4_pdata,
1004 },
1005 {
1006 .compatible = "ti,omap3-i2c",
1007 .data = &omap3_pdata,
1008 },
1009 { },
1010};
1011MODULE_DEVICE_TABLE(of, omap_i2c_of_match);
1012#endif
1013
1139aea9 1014static int __devinit
010d442c
KS		 1015omap_i2c_probe(struct platform_device *pdev)
1016{
1017 struct omap_i2c_dev *dev;
1018 struct i2c_adapter *adap;
ac79e4b2 1019 struct resource *mem;
20c9d2c4 1020 struct omap_i2c_bus_platform_data *pdata = pdev->dev.platform_data;
6145197b
BC		 1021 struct device_node *node = pdev->dev.of_node;
1022 const struct of_device_id *match;
e355204e 1023 irq_handler_t isr;
ac79e4b2 1024 int irq;
010d442c
KS		 1025 int r;
1026
1027 /* NOTE: driver uses the static register mapping */
1028 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1029 if (!mem) {
1030 dev_err(&pdev->dev, "no mem resource?\n");
1031 return -ENODEV;
1032 }
ac79e4b2
FB		 1033
1034 irq = platform_get_irq(pdev, 0);
1035 if (irq < 0) {
010d442c 1036 dev_err(&pdev->dev, "no irq resource?\n");
ac79e4b2 1037 return irq;
010d442c
KS		 1038 }
1039
d9ebd04d
FB		 1040 dev = devm_kzalloc(&pdev->dev, sizeof(struct omap_i2c_dev), GFP_KERNEL);
1041 if (!dev) {
1042 dev_err(&pdev->dev, "Menory allocation failed\n");
1043 return -ENOMEM;
010d442c
KS		 1044 }
1045
d9ebd04d
FB		 1046 dev->base = devm_request_and_ioremap(&pdev->dev, mem);
1047 if (!dev->base) {
1048 dev_err(&pdev->dev, "I2C region already claimed\n");
1049 return -ENOMEM;
010d442c
KS		 1050 }
1051
6c5aa407 1052 match = of_match_device(of_match_ptr(omap_i2c_of_match), &pdev->dev);
6145197b
BC		 1053 if (match) {
1054 u32 freq = 100000; /* default to 100000 Hz */
1055
1056 pdata = match->data;
1057 dev->dtrev = pdata->rev;
1058 dev->flags = pdata->flags;
1059
1060 of_property_read_u32(node, "clock-frequency", &freq);
1061 /* convert DT freq value in Hz into kHz for speed */
1062 dev->speed = freq / 1000;
1063 } else if (pdata != NULL) {
1064 dev->speed = pdata->clkrate;
1065 dev->flags = pdata->flags;
20c9d2c4 1066 dev->set_mpu_wkup_lat = pdata->set_mpu_wkup_lat;
6145197b 1067 dev->dtrev = pdata->rev;
20c9d2c4 1068 }
4574eb68 1069
010d442c 1070 dev->dev = &pdev->dev;
ac79e4b2 1071 dev->irq = irq;
55c381e4 1072
010d442c 1073 platform_set_drvdata(pdev, dev);
0e33bbb2 1074 init_completion(&dev->cmd_complete);
010d442c 1075
6145197b 1076 dev->reg_shift = (dev->flags >> OMAP_I2C_FLAG_BUS_SHIFT__SHIFT) & 3;
7c6bd201 1077
6145197b 1078 if (dev->dtrev == OMAP_I2C_IP_VERSION_2)
a1295577 1079 dev->regs = (u8 *)reg_map_ip_v2;
f38e66e0 1080 else
a1295577 1081 dev->regs = (u8 *)reg_map_ip_v1;
f38e66e0 1082
7f4b08ee 1083 pm_runtime_enable(dev->dev);
3b0fb97c
S		 1084 r = pm_runtime_get_sync(dev->dev);
1085 if (IS_ERR_VALUE(r))
1086 goto err_free_mem;
010d442c 1087
9c76b878 1088 dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff;
010d442c 1089
9aa8ec67
TK		 1090 dev->errata = 0;
1091
1092 if (dev->flags & OMAP_I2C_FLAG_APPLY_ERRATA_I207)
1093 dev->errata |= I2C_OMAP_ERRATA_I207;
1094
f518b482 1095 if (dev->rev <= OMAP_I2C_REV_ON_3430_3530)
c8db38f0 1096 dev->errata |= I2C_OMAP_ERRATA_I462;
8a9d97d3 1097
6145197b 1098 if (!(dev->flags & OMAP_I2C_FLAG_NO_FIFO)) {
b6ee52c3
NM		 1099 u16 s;
1100
1101 /* Set up the fifo size - Get total size */
1102 s = (omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3;
1103 dev->fifo_size = 0x8 << s;
1104
1105 /*
1106 * Set up notification threshold as half the total available
1107 * size. This is to ensure that we can handle the status on int
1108 * call back latencies.
1109 */
1d5a34fe
S		 1110
1111 dev->fifo_size = (dev->fifo_size / 2);
1112
3ff4443f 1113 if (dev->rev < OMAP_I2C_REV_ON_3630_4430)
f38e66e0 1114 dev->b_hw = 1; /* Enable hardware fixes */
1d5a34fe 1115
20c9d2c4
KJ		 1116 /* calculate wakeup latency constraint for MPU */
1117 if (dev->set_mpu_wkup_lat != NULL)
1118 dev->latency = (1000000 * dev->fifo_size) /
6145197b 1119 (1000 * dev->speed / 8);
b6ee52c3
NM		 1120 }
1121
010d442c
KS		 1122 /* reset ASAP, clearing any IRQs */
1123 omap_i2c_init(dev);
1124
4e80f727
AG		 1125 isr = (dev->rev < OMAP_I2C_OMAP1_REV_2) ? omap_i2c_omap1_isr :
1126 omap_i2c_isr;
d9ebd04d
FB		 1127 r = devm_request_irq(&pdev->dev, dev->irq, isr, IRQF_NO_SUSPEND,
1128 pdev->name, dev);
010d442c
KS		 1129
1130 if (r) {
1131 dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
1132 goto err_unuse_clocks;
1133 }
9c76b878 1134
9550d4d7 1135 dev_info(dev->dev, "bus %d rev%d.%d.%d at %d kHz\n", pdev->id,
6145197b 1136 dev->dtrev, dev->rev >> 4, dev->rev & 0xf, dev->speed);
010d442c
KS		 1137
1138 adap = &dev->adapter;
1139 i2c_set_adapdata(adap, dev);
1140 adap->owner = THIS_MODULE;
1141 adap->class = I2C_CLASS_HWMON;
783fd6fa 1142 strlcpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
010d442c
KS		 1143 adap->algo = &omap_i2c_algo;
1144 adap->dev.parent = &pdev->dev;
6145197b 1145 adap->dev.of_node = pdev->dev.of_node;
010d442c
KS		 1146
1147 /* i2c device drivers may be active on return from add_adapter() */
7c175499
DB		 1148 adap->nr = pdev->id;
1149 r = i2c_add_numbered_adapter(adap);
010d442c
KS		 1150 if (r) {
1151 dev_err(dev->dev, "failure adding adapter\n");
d9ebd04d 1152 goto err_unuse_clocks;
010d442c
KS		 1153 }
1154
6145197b
BC		 1155 of_i2c_register_devices(adap);
1156
62ff2c2b
S		 1157 pm_runtime_put(dev->dev);
1158
010d442c
KS		 1159 return 0;
1160
010d442c 1161err_unuse_clocks:
3e39752d 1162 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
fab67afb 1163 pm_runtime_put(dev->dev);
24740516 1164 pm_runtime_disable(&pdev->dev);
010d442c
KS		 1165err_free_mem:
1166 platform_set_drvdata(pdev, NULL);
010d442c
KS		 1167
1168 return r;
1169}
1170
d790aea7 1171static int __devexit omap_i2c_remove(struct platform_device *pdev)
010d442c
KS		 1172{
1173 struct omap_i2c_dev *dev = platform_get_drvdata(pdev);
3b0fb97c 1174 int ret;
010d442c
KS		 1175
1176 platform_set_drvdata(pdev, NULL);
1177
010d442c 1178 i2c_del_adapter(&dev->adapter);
3b0fb97c
S		 1179 ret = pm_runtime_get_sync(&pdev->dev);
1180 if (IS_ERR_VALUE(ret))
1181 return ret;
1182
010d442c 1183 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
0861f430 1184 pm_runtime_put(&pdev->dev);
24740516 1185 pm_runtime_disable(&pdev->dev);
010d442c
KS		 1186 return 0;
1187}
1188
5692d2a2 1189#ifdef CONFIG_PM
fab67afb
KH		 1190#ifdef CONFIG_PM_RUNTIME
1191static int omap_i2c_runtime_suspend(struct device *dev)
1192{
1193 struct platform_device *pdev = to_platform_device(dev);
1194 struct omap_i2c_dev *_dev = platform_get_drvdata(pdev);
3dae3efb
S		 1195 u16 iv;
1196
1197 _dev->iestate = omap_i2c_read_reg(_dev, OMAP_I2C_IE_REG);
bd16c82f
S		 1198
1199 omap_i2c_write_reg(_dev, OMAP_I2C_IE_REG, 0);
fab67afb 1200
3dae3efb
S		 1201 if (_dev->rev < OMAP_I2C_OMAP1_REV_2) {
1202 iv = omap_i2c_read_reg(_dev, OMAP_I2C_IV_REG); /* Read clears */
1203 } else {
1204 omap_i2c_write_reg(_dev, OMAP_I2C_STAT_REG, _dev->iestate);
fab67afb 1205
3dae3efb
S		 1206 /* Flush posted write */
1207 omap_i2c_read_reg(_dev, OMAP_I2C_STAT_REG);
1208 }
fab67afb
KH		 1209
1210 return 0;
1211}
1212
1213static int omap_i2c_runtime_resume(struct device *dev)
1214{
1215 struct platform_device *pdev = to_platform_device(dev);
1216 struct omap_i2c_dev *_dev = platform_get_drvdata(pdev);
1217
3dae3efb
S		 1218 if (_dev->flags & OMAP_I2C_FLAG_RESET_REGS_POSTIDLE) {
1219 omap_i2c_write_reg(_dev, OMAP_I2C_CON_REG, 0);
1220 omap_i2c_write_reg(_dev, OMAP_I2C_PSC_REG, _dev->pscstate);
1221 omap_i2c_write_reg(_dev, OMAP_I2C_SCLL_REG, _dev->scllstate);
1222 omap_i2c_write_reg(_dev, OMAP_I2C_SCLH_REG, _dev->sclhstate);
1223 omap_i2c_write_reg(_dev, OMAP_I2C_BUF_REG, _dev->bufstate);
1224 omap_i2c_write_reg(_dev, OMAP_I2C_SYSC_REG, _dev->syscstate);
1225 omap_i2c_write_reg(_dev, OMAP_I2C_WE_REG, _dev->westate);
1226 omap_i2c_write_reg(_dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
1227 }
1228
1229 /*
1230 * Don't write to this register if the IE state is 0 as it can
1231 * cause deadlock.
1232 */
1233 if (_dev->iestate)
1234 omap_i2c_write_reg(_dev, OMAP_I2C_IE_REG, _dev->iestate);
fab67afb
KH		 1235
1236 return 0;
1237}
5692d2a2 1238#endif /* CONFIG_PM_RUNTIME */
fab67afb
KH		 1239
1240static struct dev_pm_ops omap_i2c_pm_ops = {
5692d2a2
S		 1241 SET_RUNTIME_PM_OPS(omap_i2c_runtime_suspend,
1242 omap_i2c_runtime_resume, NULL)
fab67afb
KH		 1243};
1244#define OMAP_I2C_PM_OPS (&omap_i2c_pm_ops)
1245#else
1246#define OMAP_I2C_PM_OPS NULL
5692d2a2 1247#endif /* CONFIG_PM */
fab67afb 1248
010d442c
KS		 1249static struct platform_driver omap_i2c_driver = {
1250 .probe = omap_i2c_probe,
d790aea7 1251 .remove = __devexit_p(omap_i2c_remove),
010d442c 1252 .driver = {
f7bb0d9a 1253 .name = "omap_i2c",
010d442c 1254 .owner = THIS_MODULE,
fab67afb 1255 .pm = OMAP_I2C_PM_OPS,
6145197b 1256 .of_match_table = of_match_ptr(omap_i2c_of_match),
010d442c
KS		 1257 },
1258};
1259
1260/* I2C may be needed to bring up other drivers */
1261static int __init
1262omap_i2c_init_driver(void)
1263{
1264 return platform_driver_register(&omap_i2c_driver);
1265}
1266subsys_initcall(omap_i2c_init_driver);
1267
1268static void __exit omap_i2c_exit_driver(void)
1269{
1270 platform_driver_unregister(&omap_i2c_driver);
1271}
1272module_exit(omap_i2c_exit_driver);
1273
1274MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
1275MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
1276MODULE_LICENSE("GPL");
f7bb0d9a 1277MODULE_ALIAS("platform:omap_i2c");
Linux kernel - Deliverables
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