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010d442c KS |
1 | /* |
2 | * TI OMAP I2C master mode driver | |
3 | * | |
4 | * Copyright (C) 2003 MontaVista Software, Inc. | |
010d442c | 5 | * Copyright (C) 2005 Nokia Corporation |
c1a473bd | 6 | * Copyright (C) 2004 - 2007 Texas Instruments. |
010d442c | 7 | * |
c1a473bd TL |
8 | * Originally written by MontaVista Software, Inc. |
9 | * Additional contributions by: | |
10 | * Tony Lindgren <tony@atomide.com> | |
11 | * Imre Deak <imre.deak@nokia.com> | |
12 | * Juha Yrjölä <juha.yrjola@solidboot.com> | |
13 | * Syed Khasim <x0khasim@ti.com> | |
14 | * Nishant Menon <nm@ti.com> | |
010d442c KS |
15 | * |
16 | * This program is free software; you can redistribute it and/or modify | |
17 | * it under the terms of the GNU General Public License as published by | |
18 | * the Free Software Foundation; either version 2 of the License, or | |
19 | * (at your option) any later version. | |
20 | * | |
21 | * This program is distributed in the hope that it will be useful, | |
22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
24 | * GNU General Public License for more details. | |
25 | * | |
26 | * You should have received a copy of the GNU General Public License | |
27 | * along with this program; if not, write to the Free Software | |
28 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
29 | */ | |
30 | ||
31 | #include <linux/module.h> | |
32 | #include <linux/delay.h> | |
33 | #include <linux/i2c.h> | |
34 | #include <linux/err.h> | |
35 | #include <linux/interrupt.h> | |
36 | #include <linux/completion.h> | |
37 | #include <linux/platform_device.h> | |
38 | #include <linux/clk.h> | |
c1a473bd | 39 | #include <linux/io.h> |
6145197b BC |
40 | #include <linux/of.h> |
41 | #include <linux/of_i2c.h> | |
42 | #include <linux/of_device.h> | |
5a0e3ad6 | 43 | #include <linux/slab.h> |
20c9d2c4 | 44 | #include <linux/i2c-omap.h> |
27b1fec2 | 45 | #include <linux/pm_runtime.h> |
010d442c | 46 | |
9c76b878 | 47 | /* I2C controller revisions */ |
4e80f727 | 48 | #define OMAP_I2C_OMAP1_REV_2 0x20 |
9c76b878 PW |
49 | |
50 | /* I2C controller revisions present on specific hardware */ | |
51 | #define OMAP_I2C_REV_ON_2430 0x36 | |
52 | #define OMAP_I2C_REV_ON_3430 0x3C | |
4e80f727 | 53 | #define OMAP_I2C_REV_ON_3530_4430 0x40 |
9c76b878 | 54 | |
010d442c KS |
55 | /* timeout waiting for the controller to respond */ |
56 | #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000)) | |
57 | ||
5043e9e7 | 58 | /* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */ |
f38e66e0 SS |
59 | enum { |
60 | OMAP_I2C_REV_REG = 0, | |
61 | OMAP_I2C_IE_REG, | |
62 | OMAP_I2C_STAT_REG, | |
63 | OMAP_I2C_IV_REG, | |
64 | OMAP_I2C_WE_REG, | |
65 | OMAP_I2C_SYSS_REG, | |
66 | OMAP_I2C_BUF_REG, | |
67 | OMAP_I2C_CNT_REG, | |
68 | OMAP_I2C_DATA_REG, | |
69 | OMAP_I2C_SYSC_REG, | |
70 | OMAP_I2C_CON_REG, | |
71 | OMAP_I2C_OA_REG, | |
72 | OMAP_I2C_SA_REG, | |
73 | OMAP_I2C_PSC_REG, | |
74 | OMAP_I2C_SCLL_REG, | |
75 | OMAP_I2C_SCLH_REG, | |
76 | OMAP_I2C_SYSTEST_REG, | |
77 | OMAP_I2C_BUFSTAT_REG, | |
b8853088 AG |
78 | /* only on OMAP4430 */ |
79 | OMAP_I2C_IP_V2_REVNB_LO, | |
80 | OMAP_I2C_IP_V2_REVNB_HI, | |
81 | OMAP_I2C_IP_V2_IRQSTATUS_RAW, | |
82 | OMAP_I2C_IP_V2_IRQENABLE_SET, | |
83 | OMAP_I2C_IP_V2_IRQENABLE_CLR, | |
f38e66e0 | 84 | }; |
010d442c KS |
85 | |
86 | /* I2C Interrupt Enable Register (OMAP_I2C_IE): */ | |
b6ee52c3 NM |
87 | #define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */ |
88 | #define OMAP_I2C_IE_RDR (1 << 13) /* RX Buffer drain int enable */ | |
010d442c KS |
89 | #define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */ |
90 | #define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */ | |
91 | #define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */ | |
92 | #define OMAP_I2C_IE_NACK (1 << 1) /* No ack interrupt enable */ | |
93 | #define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */ | |
94 | ||
95 | /* I2C Status Register (OMAP_I2C_STAT): */ | |
b6ee52c3 NM |
96 | #define OMAP_I2C_STAT_XDR (1 << 14) /* TX Buffer draining */ |
97 | #define OMAP_I2C_STAT_RDR (1 << 13) /* RX Buffer draining */ | |
010d442c KS |
98 | #define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */ |
99 | #define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */ | |
100 | #define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ | |
101 | #define OMAP_I2C_STAT_AAS (1 << 9) /* Address as slave */ | |
102 | #define OMAP_I2C_STAT_AD0 (1 << 8) /* Address zero */ | |
103 | #define OMAP_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ | |
104 | #define OMAP_I2C_STAT_RRDY (1 << 3) /* Receive data ready */ | |
105 | #define OMAP_I2C_STAT_ARDY (1 << 2) /* Register access ready */ | |
106 | #define OMAP_I2C_STAT_NACK (1 << 1) /* No ack interrupt enable */ | |
107 | #define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost int ena */ | |
108 | ||
5043e9e7 KJ |
109 | /* I2C WE wakeup enable register */ |
110 | #define OMAP_I2C_WE_XDR_WE (1 << 14) /* TX drain wakup */ | |
111 | #define OMAP_I2C_WE_RDR_WE (1 << 13) /* RX drain wakeup */ | |
112 | #define OMAP_I2C_WE_AAS_WE (1 << 9) /* Address as slave wakeup*/ | |
113 | #define OMAP_I2C_WE_BF_WE (1 << 8) /* Bus free wakeup */ | |
114 | #define OMAP_I2C_WE_STC_WE (1 << 6) /* Start condition wakeup */ | |
115 | #define OMAP_I2C_WE_GC_WE (1 << 5) /* General call wakeup */ | |
116 | #define OMAP_I2C_WE_DRDY_WE (1 << 3) /* TX/RX data ready wakeup */ | |
117 | #define OMAP_I2C_WE_ARDY_WE (1 << 2) /* Reg access ready wakeup */ | |
118 | #define OMAP_I2C_WE_NACK_WE (1 << 1) /* No acknowledgment wakeup */ | |
119 | #define OMAP_I2C_WE_AL_WE (1 << 0) /* Arbitration lost wakeup */ | |
120 | ||
121 | #define OMAP_I2C_WE_ALL (OMAP_I2C_WE_XDR_WE | OMAP_I2C_WE_RDR_WE | \ | |
122 | OMAP_I2C_WE_AAS_WE | OMAP_I2C_WE_BF_WE | \ | |
123 | OMAP_I2C_WE_STC_WE | OMAP_I2C_WE_GC_WE | \ | |
124 | OMAP_I2C_WE_DRDY_WE | OMAP_I2C_WE_ARDY_WE | \ | |
125 | OMAP_I2C_WE_NACK_WE | OMAP_I2C_WE_AL_WE) | |
126 | ||
010d442c KS |
127 | /* I2C Buffer Configuration Register (OMAP_I2C_BUF): */ |
128 | #define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */ | |
b6ee52c3 | 129 | #define OMAP_I2C_BUF_RXFIF_CLR (1 << 14) /* RX FIFO Clear */ |
010d442c | 130 | #define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */ |
b6ee52c3 | 131 | #define OMAP_I2C_BUF_TXFIF_CLR (1 << 6) /* TX FIFO Clear */ |
010d442c KS |
132 | |
133 | /* I2C Configuration Register (OMAP_I2C_CON): */ | |
134 | #define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */ | |
135 | #define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */ | |
b6ee52c3 | 136 | #define OMAP_I2C_CON_OPMODE_HS (1 << 12) /* High Speed support */ |
010d442c KS |
137 | #define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */ |
138 | #define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */ | |
139 | #define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */ | |
140 | #define OMAP_I2C_CON_XA (1 << 8) /* Expand address */ | |
141 | #define OMAP_I2C_CON_RM (1 << 2) /* Repeat mode (master only) */ | |
142 | #define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */ | |
143 | #define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */ | |
144 | ||
4574eb68 SMK |
145 | /* I2C SCL time value when Master */ |
146 | #define OMAP_I2C_SCLL_HSSCLL 8 | |
147 | #define OMAP_I2C_SCLH_HSSCLH 8 | |
148 | ||
010d442c KS |
149 | /* I2C System Test Register (OMAP_I2C_SYSTEST): */ |
150 | #ifdef DEBUG | |
151 | #define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */ | |
152 | #define OMAP_I2C_SYSTEST_FREE (1 << 14) /* Free running mode */ | |
153 | #define OMAP_I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */ | |
154 | #define OMAP_I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */ | |
155 | #define OMAP_I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense in */ | |
156 | #define OMAP_I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive out */ | |
157 | #define OMAP_I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense in */ | |
158 | #define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */ | |
159 | #endif | |
160 | ||
fdd07fe6 PW |
161 | /* OCP_SYSSTATUS bit definitions */ |
162 | #define SYSS_RESETDONE_MASK (1 << 0) | |
163 | ||
164 | /* OCP_SYSCONFIG bit definitions */ | |
165 | #define SYSC_CLOCKACTIVITY_MASK (0x3 << 8) | |
166 | #define SYSC_SIDLEMODE_MASK (0x3 << 3) | |
167 | #define SYSC_ENAWAKEUP_MASK (1 << 2) | |
168 | #define SYSC_SOFTRESET_MASK (1 << 1) | |
169 | #define SYSC_AUTOIDLE_MASK (1 << 0) | |
170 | ||
171 | #define SYSC_IDLEMODE_SMART 0x2 | |
172 | #define SYSC_CLOCKACTIVITY_FCLK 0x2 | |
010d442c | 173 | |
f3083d92 | 174 | /* Errata definitions */ |
175 | #define I2C_OMAP_ERRATA_I207 (1 << 0) | |
8a9d97d3 | 176 | #define I2C_OMAP3_1P153 (1 << 1) |
010d442c | 177 | |
010d442c KS |
178 | struct omap_i2c_dev { |
179 | struct device *dev; | |
180 | void __iomem *base; /* virtual */ | |
181 | int irq; | |
d84d3ea3 | 182 | int reg_shift; /* bit shift for I2C register addresses */ |
010d442c KS |
183 | struct completion cmd_complete; |
184 | struct resource *ioarea; | |
20c9d2c4 KJ |
185 | u32 latency; /* maximum mpu wkup latency */ |
186 | void (*set_mpu_wkup_lat)(struct device *dev, | |
187 | long latency); | |
6145197b BC |
188 | u32 speed; /* Speed of bus in kHz */ |
189 | u32 dtrev; /* extra revision from DT */ | |
190 | u32 flags; | |
010d442c KS |
191 | u16 cmd_err; |
192 | u8 *buf; | |
f38e66e0 | 193 | u8 *regs; |
010d442c KS |
194 | size_t buf_len; |
195 | struct i2c_adapter adapter; | |
b6ee52c3 NM |
196 | u8 fifo_size; /* use as flag and value |
197 | * fifo_size==0 implies no fifo | |
198 | * if set, should be trsh+1 | |
199 | */ | |
9c76b878 | 200 | u8 rev; |
b6ee52c3 | 201 | unsigned b_hw:1; /* bad h/w fixes */ |
f08ac4e7 | 202 | u16 iestate; /* Saved interrupt register */ |
ef871432 RN |
203 | u16 pscstate; |
204 | u16 scllstate; | |
205 | u16 sclhstate; | |
206 | u16 bufstate; | |
207 | u16 syscstate; | |
208 | u16 westate; | |
f3083d92 | 209 | u16 errata; |
010d442c KS |
210 | }; |
211 | ||
a1295577 | 212 | static const u8 reg_map_ip_v1[] = { |
f38e66e0 SS |
213 | [OMAP_I2C_REV_REG] = 0x00, |
214 | [OMAP_I2C_IE_REG] = 0x01, | |
215 | [OMAP_I2C_STAT_REG] = 0x02, | |
216 | [OMAP_I2C_IV_REG] = 0x03, | |
217 | [OMAP_I2C_WE_REG] = 0x03, | |
218 | [OMAP_I2C_SYSS_REG] = 0x04, | |
219 | [OMAP_I2C_BUF_REG] = 0x05, | |
220 | [OMAP_I2C_CNT_REG] = 0x06, | |
221 | [OMAP_I2C_DATA_REG] = 0x07, | |
222 | [OMAP_I2C_SYSC_REG] = 0x08, | |
223 | [OMAP_I2C_CON_REG] = 0x09, | |
224 | [OMAP_I2C_OA_REG] = 0x0a, | |
225 | [OMAP_I2C_SA_REG] = 0x0b, | |
226 | [OMAP_I2C_PSC_REG] = 0x0c, | |
227 | [OMAP_I2C_SCLL_REG] = 0x0d, | |
228 | [OMAP_I2C_SCLH_REG] = 0x0e, | |
229 | [OMAP_I2C_SYSTEST_REG] = 0x0f, | |
230 | [OMAP_I2C_BUFSTAT_REG] = 0x10, | |
231 | }; | |
232 | ||
a1295577 | 233 | static const u8 reg_map_ip_v2[] = { |
f38e66e0 SS |
234 | [OMAP_I2C_REV_REG] = 0x04, |
235 | [OMAP_I2C_IE_REG] = 0x2c, | |
236 | [OMAP_I2C_STAT_REG] = 0x28, | |
237 | [OMAP_I2C_IV_REG] = 0x34, | |
238 | [OMAP_I2C_WE_REG] = 0x34, | |
239 | [OMAP_I2C_SYSS_REG] = 0x90, | |
240 | [OMAP_I2C_BUF_REG] = 0x94, | |
241 | [OMAP_I2C_CNT_REG] = 0x98, | |
242 | [OMAP_I2C_DATA_REG] = 0x9c, | |
2727b175 | 243 | [OMAP_I2C_SYSC_REG] = 0x10, |
f38e66e0 SS |
244 | [OMAP_I2C_CON_REG] = 0xa4, |
245 | [OMAP_I2C_OA_REG] = 0xa8, | |
246 | [OMAP_I2C_SA_REG] = 0xac, | |
247 | [OMAP_I2C_PSC_REG] = 0xb0, | |
248 | [OMAP_I2C_SCLL_REG] = 0xb4, | |
249 | [OMAP_I2C_SCLH_REG] = 0xb8, | |
250 | [OMAP_I2C_SYSTEST_REG] = 0xbC, | |
251 | [OMAP_I2C_BUFSTAT_REG] = 0xc0, | |
b8853088 AG |
252 | [OMAP_I2C_IP_V2_REVNB_LO] = 0x00, |
253 | [OMAP_I2C_IP_V2_REVNB_HI] = 0x04, | |
254 | [OMAP_I2C_IP_V2_IRQSTATUS_RAW] = 0x24, | |
255 | [OMAP_I2C_IP_V2_IRQENABLE_SET] = 0x2c, | |
256 | [OMAP_I2C_IP_V2_IRQENABLE_CLR] = 0x30, | |
f38e66e0 SS |
257 | }; |
258 | ||
010d442c KS |
259 | static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev, |
260 | int reg, u16 val) | |
261 | { | |
f38e66e0 SS |
262 | __raw_writew(val, i2c_dev->base + |
263 | (i2c_dev->regs[reg] << i2c_dev->reg_shift)); | |
010d442c KS |
264 | } |
265 | ||
266 | static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg) | |
267 | { | |
f38e66e0 SS |
268 | return __raw_readw(i2c_dev->base + |
269 | (i2c_dev->regs[reg] << i2c_dev->reg_shift)); | |
010d442c KS |
270 | } |
271 | ||
010d442c KS |
272 | static int omap_i2c_init(struct omap_i2c_dev *dev) |
273 | { | |
ef871432 | 274 | u16 psc = 0, scll = 0, sclh = 0, buf = 0; |
4574eb68 | 275 | u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0; |
010d442c KS |
276 | unsigned long fclk_rate = 12000000; |
277 | unsigned long timeout; | |
4574eb68 | 278 | unsigned long internal_clk = 0; |
27b1fec2 | 279 | struct clk *fclk; |
010d442c | 280 | |
4e80f727 | 281 | if (dev->rev >= OMAP_I2C_OMAP1_REV_2) { |
57eb81b1 MG |
282 | /* Disable I2C controller before soft reset */ |
283 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, | |
284 | omap_i2c_read_reg(dev, OMAP_I2C_CON_REG) & | |
285 | ~(OMAP_I2C_CON_EN)); | |
286 | ||
fdd07fe6 | 287 | omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK); |
010d442c KS |
288 | /* For some reason we need to set the EN bit before the |
289 | * reset done bit gets set. */ | |
290 | timeout = jiffies + OMAP_I2C_TIMEOUT; | |
291 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN); | |
292 | while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) & | |
fdd07fe6 | 293 | SYSS_RESETDONE_MASK)) { |
010d442c | 294 | if (time_after(jiffies, timeout)) { |
fce3ff03 | 295 | dev_warn(dev->dev, "timeout waiting " |
010d442c KS |
296 | "for controller reset\n"); |
297 | return -ETIMEDOUT; | |
298 | } | |
299 | msleep(1); | |
300 | } | |
fdd07fe6 PW |
301 | |
302 | /* SYSC register is cleared by the reset; rewrite it */ | |
303 | if (dev->rev == OMAP_I2C_REV_ON_2430) { | |
304 | ||
305 | omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, | |
306 | SYSC_AUTOIDLE_MASK); | |
307 | ||
308 | } else if (dev->rev >= OMAP_I2C_REV_ON_3430) { | |
ef871432 RN |
309 | dev->syscstate = SYSC_AUTOIDLE_MASK; |
310 | dev->syscstate |= SYSC_ENAWAKEUP_MASK; | |
311 | dev->syscstate |= (SYSC_IDLEMODE_SMART << | |
fdd07fe6 | 312 | __ffs(SYSC_SIDLEMODE_MASK)); |
ef871432 | 313 | dev->syscstate |= (SYSC_CLOCKACTIVITY_FCLK << |
fdd07fe6 PW |
314 | __ffs(SYSC_CLOCKACTIVITY_MASK)); |
315 | ||
ef871432 RN |
316 | omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, |
317 | dev->syscstate); | |
5043e9e7 KJ |
318 | /* |
319 | * Enabling all wakup sources to stop I2C freezing on | |
320 | * WFI instruction. | |
321 | * REVISIT: Some wkup sources might not be needed. | |
322 | */ | |
ef871432 | 323 | dev->westate = OMAP_I2C_WE_ALL; |
cb28e582 S |
324 | omap_i2c_write_reg(dev, OMAP_I2C_WE_REG, |
325 | dev->westate); | |
fdd07fe6 | 326 | } |
010d442c KS |
327 | } |
328 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0); | |
329 | ||
6145197b | 330 | if (dev->flags & OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK) { |
0e9ae109 RK |
331 | /* |
332 | * The I2C functional clock is the armxor_ck, so there's | |
333 | * no need to get "armxor_ck" separately. Now, if OMAP2420 | |
334 | * always returns 12MHz for the functional clock, we can | |
335 | * do this bit unconditionally. | |
336 | */ | |
27b1fec2 RN |
337 | fclk = clk_get(dev->dev, "fck"); |
338 | fclk_rate = clk_get_rate(fclk); | |
339 | clk_put(fclk); | |
0e9ae109 | 340 | |
010d442c KS |
341 | /* TRM for 5912 says the I2C clock must be prescaled to be |
342 | * between 7 - 12 MHz. The XOR input clock is typically | |
343 | * 12, 13 or 19.2 MHz. So we should have code that produces: | |
344 | * | |
345 | * XOR MHz Divider Prescaler | |
346 | * 12 1 0 | |
347 | * 13 2 1 | |
348 | * 19.2 2 1 | |
349 | */ | |
d7aef138 JD |
350 | if (fclk_rate > 12000000) |
351 | psc = fclk_rate / 12000000; | |
010d442c KS |
352 | } |
353 | ||
6145197b | 354 | if (!(dev->flags & OMAP_I2C_FLAG_SIMPLE_CLOCK)) { |
4574eb68 | 355 | |
84bf2c86 AK |
356 | /* |
357 | * HSI2C controller internal clk rate should be 19.2 Mhz for | |
358 | * HS and for all modes on 2430. On 34xx we can use lower rate | |
359 | * to get longer filter period for better noise suppression. | |
360 | * The filter is iclk (fclk for HS) period. | |
361 | */ | |
3be0053e | 362 | if (dev->speed > 400 || |
6145197b | 363 | dev->flags & OMAP_I2C_FLAG_FORCE_19200_INT_CLK) |
84bf2c86 AK |
364 | internal_clk = 19200; |
365 | else if (dev->speed > 100) | |
366 | internal_clk = 9600; | |
367 | else | |
368 | internal_clk = 4000; | |
27b1fec2 RN |
369 | fclk = clk_get(dev->dev, "fck"); |
370 | fclk_rate = clk_get_rate(fclk) / 1000; | |
371 | clk_put(fclk); | |
4574eb68 SMK |
372 | |
373 | /* Compute prescaler divisor */ | |
374 | psc = fclk_rate / internal_clk; | |
375 | psc = psc - 1; | |
376 | ||
377 | /* If configured for High Speed */ | |
378 | if (dev->speed > 400) { | |
baf46b4e AK |
379 | unsigned long scl; |
380 | ||
4574eb68 | 381 | /* For first phase of HS mode */ |
baf46b4e AK |
382 | scl = internal_clk / 400; |
383 | fsscll = scl - (scl / 3) - 7; | |
384 | fssclh = (scl / 3) - 5; | |
4574eb68 SMK |
385 | |
386 | /* For second phase of HS mode */ | |
baf46b4e AK |
387 | scl = fclk_rate / dev->speed; |
388 | hsscll = scl - (scl / 3) - 7; | |
389 | hssclh = (scl / 3) - 5; | |
390 | } else if (dev->speed > 100) { | |
391 | unsigned long scl; | |
392 | ||
393 | /* Fast mode */ | |
394 | scl = internal_clk / dev->speed; | |
395 | fsscll = scl - (scl / 3) - 7; | |
396 | fssclh = (scl / 3) - 5; | |
4574eb68 | 397 | } else { |
baf46b4e AK |
398 | /* Standard mode */ |
399 | fsscll = internal_clk / (dev->speed * 2) - 7; | |
400 | fssclh = internal_clk / (dev->speed * 2) - 5; | |
4574eb68 SMK |
401 | } |
402 | scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll; | |
403 | sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh; | |
404 | } else { | |
405 | /* Program desired operating rate */ | |
406 | fclk_rate /= (psc + 1) * 1000; | |
407 | if (psc > 2) | |
408 | psc = 2; | |
409 | scll = fclk_rate / (dev->speed * 2) - 7 + psc; | |
410 | sclh = fclk_rate / (dev->speed * 2) - 7 + psc; | |
411 | } | |
412 | ||
010d442c KS |
413 | /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */ |
414 | omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc); | |
415 | ||
4574eb68 SMK |
416 | /* SCL low and high time values */ |
417 | omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, scll); | |
418 | omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, sclh); | |
010d442c | 419 | |
ef871432 RN |
420 | if (dev->fifo_size) { |
421 | /* Note: setup required fifo size - 1. RTRSH and XTRSH */ | |
422 | buf = (dev->fifo_size - 1) << 8 | OMAP_I2C_BUF_RXFIF_CLR | | |
423 | (dev->fifo_size - 1) | OMAP_I2C_BUF_TXFIF_CLR; | |
424 | omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, buf); | |
425 | } | |
b6ee52c3 | 426 | |
010d442c KS |
427 | /* Take the I2C module out of reset: */ |
428 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN); | |
429 | ||
430 | /* Enable interrupts */ | |
ef871432 | 431 | dev->iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY | |
c1a473bd TL |
432 | OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK | |
433 | OMAP_I2C_IE_AL) | ((dev->fifo_size) ? | |
ef871432 RN |
434 | (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0); |
435 | omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate); | |
6145197b | 436 | if (dev->flags & OMAP_I2C_FLAG_RESET_REGS_POSTIDLE) { |
ef871432 RN |
437 | dev->pscstate = psc; |
438 | dev->scllstate = scll; | |
439 | dev->sclhstate = sclh; | |
440 | dev->bufstate = buf; | |
441 | } | |
010d442c KS |
442 | return 0; |
443 | } | |
444 | ||
445 | /* | |
446 | * Waiting on Bus Busy | |
447 | */ | |
448 | static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev) | |
449 | { | |
450 | unsigned long timeout; | |
451 | ||
452 | timeout = jiffies + OMAP_I2C_TIMEOUT; | |
453 | while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) { | |
454 | if (time_after(jiffies, timeout)) { | |
455 | dev_warn(dev->dev, "timeout waiting for bus ready\n"); | |
456 | return -ETIMEDOUT; | |
457 | } | |
458 | msleep(1); | |
459 | } | |
460 | ||
461 | return 0; | |
462 | } | |
463 | ||
464 | /* | |
465 | * Low level master read/write transaction. | |
466 | */ | |
467 | static int omap_i2c_xfer_msg(struct i2c_adapter *adap, | |
468 | struct i2c_msg *msg, int stop) | |
469 | { | |
470 | struct omap_i2c_dev *dev = i2c_get_adapdata(adap); | |
33d54985 | 471 | unsigned long timeout; |
010d442c KS |
472 | u16 w; |
473 | ||
474 | dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n", | |
475 | msg->addr, msg->len, msg->flags, stop); | |
476 | ||
477 | if (msg->len == 0) | |
478 | return -EINVAL; | |
479 | ||
480 | omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr); | |
481 | ||
482 | /* REVISIT: Could the STB bit of I2C_CON be used with probing? */ | |
483 | dev->buf = msg->buf; | |
484 | dev->buf_len = msg->len; | |
485 | ||
486 | omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len); | |
487 | ||
b6ee52c3 NM |
488 | /* Clear the FIFO Buffers */ |
489 | w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG); | |
490 | w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR; | |
491 | omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w); | |
492 | ||
010d442c KS |
493 | init_completion(&dev->cmd_complete); |
494 | dev->cmd_err = 0; | |
495 | ||
496 | w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT; | |
4574eb68 SMK |
497 | |
498 | /* High speed configuration */ | |
499 | if (dev->speed > 400) | |
b6ee52c3 | 500 | w |= OMAP_I2C_CON_OPMODE_HS; |
4574eb68 | 501 | |
010d442c KS |
502 | if (msg->flags & I2C_M_TEN) |
503 | w |= OMAP_I2C_CON_XA; | |
504 | if (!(msg->flags & I2C_M_RD)) | |
505 | w |= OMAP_I2C_CON_TRX; | |
c1a473bd | 506 | |
b6ee52c3 | 507 | if (!dev->b_hw && stop) |
010d442c | 508 | w |= OMAP_I2C_CON_STP; |
c1a473bd | 509 | |
010d442c KS |
510 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w); |
511 | ||
b6ee52c3 NM |
512 | /* |
513 | * Don't write stt and stp together on some hardware. | |
514 | */ | |
515 | if (dev->b_hw && stop) { | |
516 | unsigned long delay = jiffies + OMAP_I2C_TIMEOUT; | |
517 | u16 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG); | |
518 | while (con & OMAP_I2C_CON_STT) { | |
519 | con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG); | |
520 | ||
521 | /* Let the user know if i2c is in a bad state */ | |
522 | if (time_after(jiffies, delay)) { | |
523 | dev_err(dev->dev, "controller timed out " | |
524 | "waiting for start condition to finish\n"); | |
525 | return -ETIMEDOUT; | |
526 | } | |
527 | cpu_relax(); | |
528 | } | |
529 | ||
530 | w |= OMAP_I2C_CON_STP; | |
531 | w &= ~OMAP_I2C_CON_STT; | |
532 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w); | |
533 | } | |
534 | ||
b7af349b JN |
535 | /* |
536 | * REVISIT: We should abort the transfer on signals, but the bus goes | |
537 | * into arbitration and we're currently unable to recover from it. | |
538 | */ | |
33d54985 S |
539 | timeout = wait_for_completion_timeout(&dev->cmd_complete, |
540 | OMAP_I2C_TIMEOUT); | |
010d442c | 541 | dev->buf_len = 0; |
33d54985 | 542 | if (timeout == 0) { |
010d442c KS |
543 | dev_err(dev->dev, "controller timed out\n"); |
544 | omap_i2c_init(dev); | |
545 | return -ETIMEDOUT; | |
546 | } | |
547 | ||
548 | if (likely(!dev->cmd_err)) | |
549 | return 0; | |
550 | ||
551 | /* We have an error */ | |
552 | if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR | | |
553 | OMAP_I2C_STAT_XUDF)) { | |
554 | omap_i2c_init(dev); | |
555 | return -EIO; | |
556 | } | |
557 | ||
558 | if (dev->cmd_err & OMAP_I2C_STAT_NACK) { | |
559 | if (msg->flags & I2C_M_IGNORE_NAK) | |
560 | return 0; | |
561 | if (stop) { | |
562 | w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG); | |
563 | w |= OMAP_I2C_CON_STP; | |
564 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w); | |
565 | } | |
566 | return -EREMOTEIO; | |
567 | } | |
568 | return -EIO; | |
569 | } | |
570 | ||
571 | ||
572 | /* | |
573 | * Prepare controller for a transaction and call omap_i2c_xfer_msg | |
574 | * to do the work during IRQ processing. | |
575 | */ | |
576 | static int | |
577 | omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) | |
578 | { | |
579 | struct omap_i2c_dev *dev = i2c_get_adapdata(adap); | |
580 | int i; | |
581 | int r; | |
582 | ||
3b0fb97c S |
583 | r = pm_runtime_get_sync(dev->dev); |
584 | if (IS_ERR_VALUE(r)) | |
585 | return r; | |
010d442c | 586 | |
c1a473bd TL |
587 | r = omap_i2c_wait_for_bb(dev); |
588 | if (r < 0) | |
010d442c KS |
589 | goto out; |
590 | ||
6a91b558 SO |
591 | if (dev->set_mpu_wkup_lat != NULL) |
592 | dev->set_mpu_wkup_lat(dev->dev, dev->latency); | |
593 | ||
010d442c KS |
594 | for (i = 0; i < num; i++) { |
595 | r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1))); | |
596 | if (r != 0) | |
597 | break; | |
598 | } | |
599 | ||
6a91b558 SO |
600 | if (dev->set_mpu_wkup_lat != NULL) |
601 | dev->set_mpu_wkup_lat(dev->dev, -1); | |
602 | ||
010d442c KS |
603 | if (r == 0) |
604 | r = num; | |
5c64eb26 MN |
605 | |
606 | omap_i2c_wait_for_bb(dev); | |
010d442c | 607 | out: |
fab67afb | 608 | pm_runtime_put(dev->dev); |
010d442c KS |
609 | return r; |
610 | } | |
611 | ||
612 | static u32 | |
613 | omap_i2c_func(struct i2c_adapter *adap) | |
614 | { | |
615 | return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); | |
616 | } | |
617 | ||
618 | static inline void | |
619 | omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err) | |
620 | { | |
621 | dev->cmd_err |= err; | |
622 | complete(&dev->cmd_complete); | |
623 | } | |
624 | ||
625 | static inline void | |
626 | omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat) | |
627 | { | |
628 | omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat); | |
629 | } | |
630 | ||
f3083d92 | 631 | static inline void i2c_omap_errata_i207(struct omap_i2c_dev *dev, u16 stat) |
632 | { | |
633 | /* | |
634 | * I2C Errata(Errata Nos. OMAP2: 1.67, OMAP3: 1.8) | |
635 | * Not applicable for OMAP4. | |
636 | * Under certain rare conditions, RDR could be set again | |
637 | * when the bus is busy, then ignore the interrupt and | |
638 | * clear the interrupt. | |
639 | */ | |
640 | if (stat & OMAP_I2C_STAT_RDR) { | |
641 | /* Step 1: If RDR is set, clear it */ | |
642 | omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR); | |
643 | ||
644 | /* Step 2: */ | |
645 | if (!(omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) | |
646 | & OMAP_I2C_STAT_BB)) { | |
647 | ||
648 | /* Step 3: */ | |
649 | if (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) | |
650 | & OMAP_I2C_STAT_RDR) { | |
651 | omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR); | |
652 | dev_dbg(dev->dev, "RDR when bus is busy.\n"); | |
653 | } | |
654 | ||
655 | } | |
656 | } | |
657 | } | |
658 | ||
43469d8e PW |
659 | /* rev1 devices are apparently only on some 15xx */ |
660 | #ifdef CONFIG_ARCH_OMAP15XX | |
661 | ||
010d442c | 662 | static irqreturn_t |
4e80f727 | 663 | omap_i2c_omap1_isr(int this_irq, void *dev_id) |
010d442c KS |
664 | { |
665 | struct omap_i2c_dev *dev = dev_id; | |
666 | u16 iv, w; | |
667 | ||
fab67afb | 668 | if (pm_runtime_suspended(dev->dev)) |
f08ac4e7 TL |
669 | return IRQ_NONE; |
670 | ||
010d442c KS |
671 | iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG); |
672 | switch (iv) { | |
673 | case 0x00: /* None */ | |
674 | break; | |
675 | case 0x01: /* Arbitration lost */ | |
676 | dev_err(dev->dev, "Arbitration lost\n"); | |
677 | omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL); | |
678 | break; | |
679 | case 0x02: /* No acknowledgement */ | |
680 | omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK); | |
681 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP); | |
682 | break; | |
683 | case 0x03: /* Register access ready */ | |
684 | omap_i2c_complete_cmd(dev, 0); | |
685 | break; | |
686 | case 0x04: /* Receive data ready */ | |
687 | if (dev->buf_len) { | |
688 | w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG); | |
689 | *dev->buf++ = w; | |
690 | dev->buf_len--; | |
691 | if (dev->buf_len) { | |
692 | *dev->buf++ = w >> 8; | |
693 | dev->buf_len--; | |
694 | } | |
695 | } else | |
696 | dev_err(dev->dev, "RRDY IRQ while no data requested\n"); | |
697 | break; | |
698 | case 0x05: /* Transmit data ready */ | |
699 | if (dev->buf_len) { | |
700 | w = *dev->buf++; | |
701 | dev->buf_len--; | |
702 | if (dev->buf_len) { | |
703 | w |= *dev->buf++ << 8; | |
704 | dev->buf_len--; | |
705 | } | |
706 | omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w); | |
707 | } else | |
708 | dev_err(dev->dev, "XRDY IRQ while no data to send\n"); | |
709 | break; | |
710 | default: | |
711 | return IRQ_NONE; | |
712 | } | |
713 | ||
714 | return IRQ_HANDLED; | |
715 | } | |
43469d8e | 716 | #else |
4e80f727 | 717 | #define omap_i2c_omap1_isr NULL |
43469d8e | 718 | #endif |
010d442c | 719 | |
2dd151ab AS |
720 | /* |
721 | * OMAP3430 Errata 1.153: When an XRDY/XDR is hit, wait for XUDF before writing | |
722 | * data to DATA_REG. Otherwise some data bytes can be lost while transferring | |
723 | * them from the memory to the I2C interface. | |
724 | */ | |
725 | static int errata_omap3_1p153(struct omap_i2c_dev *dev, u16 *stat, int *err) | |
726 | { | |
e9f59b9c AS |
727 | unsigned long timeout = 10000; |
728 | ||
729 | while (--timeout && !(*stat & OMAP_I2C_STAT_XUDF)) { | |
2dd151ab AS |
730 | if (*stat & (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) { |
731 | omap_i2c_ack_stat(dev, *stat & (OMAP_I2C_STAT_XRDY | | |
732 | OMAP_I2C_STAT_XDR)); | |
2dd151ab AS |
733 | return -ETIMEDOUT; |
734 | } | |
e9f59b9c | 735 | |
2dd151ab AS |
736 | cpu_relax(); |
737 | *stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG); | |
738 | } | |
739 | ||
e9f59b9c AS |
740 | if (!timeout) { |
741 | dev_err(dev->dev, "timeout waiting on XUDF bit\n"); | |
742 | return 0; | |
743 | } | |
744 | ||
e7e62df0 | 745 | *err |= OMAP_I2C_STAT_XUDF; |
2dd151ab AS |
746 | return 0; |
747 | } | |
748 | ||
010d442c | 749 | static irqreturn_t |
7d12e780 | 750 | omap_i2c_isr(int this_irq, void *dev_id) |
010d442c KS |
751 | { |
752 | struct omap_i2c_dev *dev = dev_id; | |
753 | u16 bits; | |
754 | u16 stat, w; | |
b6ee52c3 | 755 | int err, count = 0; |
010d442c | 756 | |
fab67afb | 757 | if (pm_runtime_suspended(dev->dev)) |
f08ac4e7 TL |
758 | return IRQ_NONE; |
759 | ||
010d442c KS |
760 | bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG); |
761 | while ((stat = (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG))) & bits) { | |
762 | dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat); | |
763 | if (count++ == 100) { | |
764 | dev_warn(dev->dev, "Too much work in one IRQ\n"); | |
765 | break; | |
766 | } | |
767 | ||
cd086d3a SM |
768 | err = 0; |
769 | complete: | |
dcc4ec26 NM |
770 | /* |
771 | * Ack the stat in one go, but [R/X]DR and [R/X]RDY should be | |
772 | * acked after the data operation is complete. | |
773 | * Ref: TRM SWPU114Q Figure 18-31 | |
774 | */ | |
775 | omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat & | |
776 | ~(OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR | | |
777 | OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR)); | |
010d442c | 778 | |
78e1cf42 | 779 | if (stat & OMAP_I2C_STAT_NACK) |
b6ee52c3 | 780 | err |= OMAP_I2C_STAT_NACK; |
78e1cf42 | 781 | |
b6ee52c3 NM |
782 | if (stat & OMAP_I2C_STAT_AL) { |
783 | dev_err(dev->dev, "Arbitration lost\n"); | |
784 | err |= OMAP_I2C_STAT_AL; | |
785 | } | |
a5a595cc | 786 | /* |
cb527ede | 787 | * ProDB0017052: Clear ARDY bit twice |
a5a595cc | 788 | */ |
b6ee52c3 | 789 | if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK | |
04c688dd | 790 | OMAP_I2C_STAT_AL)) { |
dd11976a MS |
791 | omap_i2c_ack_stat(dev, stat & |
792 | (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR | | |
cb527ede R |
793 | OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR | |
794 | OMAP_I2C_STAT_ARDY)); | |
b6ee52c3 | 795 | omap_i2c_complete_cmd(dev, err); |
04c688dd SM |
796 | return IRQ_HANDLED; |
797 | } | |
b6ee52c3 NM |
798 | if (stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR)) { |
799 | u8 num_bytes = 1; | |
f3083d92 | 800 | |
801 | if (dev->errata & I2C_OMAP_ERRATA_I207) | |
802 | i2c_omap_errata_i207(dev, stat); | |
803 | ||
b6ee52c3 NM |
804 | if (dev->fifo_size) { |
805 | if (stat & OMAP_I2C_STAT_RRDY) | |
806 | num_bytes = dev->fifo_size; | |
bfb6b658 SM |
807 | else /* read RXSTAT on RDR interrupt */ |
808 | num_bytes = (omap_i2c_read_reg(dev, | |
809 | OMAP_I2C_BUFSTAT_REG) | |
810 | >> 8) & 0x3F; | |
b6ee52c3 NM |
811 | } |
812 | while (num_bytes) { | |
813 | num_bytes--; | |
814 | w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG); | |
010d442c | 815 | if (dev->buf_len) { |
b6ee52c3 | 816 | *dev->buf++ = w; |
010d442c | 817 | dev->buf_len--; |
f38e66e0 SS |
818 | /* |
819 | * Data reg in 2430, omap3 and | |
820 | * omap4 is 8 bit wide | |
821 | */ | |
6145197b | 822 | if (dev->flags & |
3be0053e | 823 | OMAP_I2C_FLAG_16BIT_DATA_REG) { |
b6ee52c3 NM |
824 | if (dev->buf_len) { |
825 | *dev->buf++ = w >> 8; | |
826 | dev->buf_len--; | |
827 | } | |
828 | } | |
829 | } else { | |
830 | if (stat & OMAP_I2C_STAT_RRDY) | |
831 | dev_err(dev->dev, | |
832 | "RRDY IRQ while no data" | |
833 | " requested\n"); | |
834 | if (stat & OMAP_I2C_STAT_RDR) | |
835 | dev_err(dev->dev, | |
836 | "RDR IRQ while no data" | |
837 | " requested\n"); | |
838 | break; | |
010d442c | 839 | } |
b6ee52c3 NM |
840 | } |
841 | omap_i2c_ack_stat(dev, | |
842 | stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR)); | |
010d442c KS |
843 | continue; |
844 | } | |
b6ee52c3 NM |
845 | if (stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR)) { |
846 | u8 num_bytes = 1; | |
847 | if (dev->fifo_size) { | |
848 | if (stat & OMAP_I2C_STAT_XRDY) | |
849 | num_bytes = dev->fifo_size; | |
bfb6b658 | 850 | else /* read TXSTAT on XDR interrupt */ |
b6ee52c3 | 851 | num_bytes = omap_i2c_read_reg(dev, |
bfb6b658 SM |
852 | OMAP_I2C_BUFSTAT_REG) |
853 | & 0x3F; | |
b6ee52c3 NM |
854 | } |
855 | while (num_bytes) { | |
856 | num_bytes--; | |
857 | w = 0; | |
010d442c | 858 | if (dev->buf_len) { |
b6ee52c3 | 859 | w = *dev->buf++; |
010d442c | 860 | dev->buf_len--; |
f38e66e0 SS |
861 | /* |
862 | * Data reg in 2430, omap3 and | |
863 | * omap4 is 8 bit wide | |
864 | */ | |
6145197b | 865 | if (dev->flags & |
3be0053e | 866 | OMAP_I2C_FLAG_16BIT_DATA_REG) { |
b6ee52c3 NM |
867 | if (dev->buf_len) { |
868 | w |= *dev->buf++ << 8; | |
869 | dev->buf_len--; | |
870 | } | |
871 | } | |
872 | } else { | |
873 | if (stat & OMAP_I2C_STAT_XRDY) | |
874 | dev_err(dev->dev, | |
875 | "XRDY IRQ while no " | |
876 | "data to send\n"); | |
877 | if (stat & OMAP_I2C_STAT_XDR) | |
878 | dev_err(dev->dev, | |
879 | "XDR IRQ while no " | |
880 | "data to send\n"); | |
881 | break; | |
010d442c | 882 | } |
cd086d3a | 883 | |
8a9d97d3 | 884 | if ((dev->errata & I2C_OMAP3_1P153) && |
2dd151ab AS |
885 | errata_omap3_1p153(dev, &stat, &err)) |
886 | goto complete; | |
cd086d3a | 887 | |
b6ee52c3 NM |
888 | omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w); |
889 | } | |
890 | omap_i2c_ack_stat(dev, | |
891 | stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR)); | |
010d442c KS |
892 | continue; |
893 | } | |
894 | if (stat & OMAP_I2C_STAT_ROVR) { | |
895 | dev_err(dev->dev, "Receive overrun\n"); | |
896 | dev->cmd_err |= OMAP_I2C_STAT_ROVR; | |
897 | } | |
898 | if (stat & OMAP_I2C_STAT_XUDF) { | |
b6ee52c3 | 899 | dev_err(dev->dev, "Transmit underflow\n"); |
010d442c KS |
900 | dev->cmd_err |= OMAP_I2C_STAT_XUDF; |
901 | } | |
010d442c KS |
902 | } |
903 | ||
904 | return count ? IRQ_HANDLED : IRQ_NONE; | |
905 | } | |
906 | ||
8f9082c5 | 907 | static const struct i2c_algorithm omap_i2c_algo = { |
010d442c KS |
908 | .master_xfer = omap_i2c_xfer, |
909 | .functionality = omap_i2c_func, | |
910 | }; | |
911 | ||
6145197b BC |
912 | #ifdef CONFIG_OF |
913 | static struct omap_i2c_bus_platform_data omap3_pdata = { | |
914 | .rev = OMAP_I2C_IP_VERSION_1, | |
915 | .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | | |
916 | OMAP_I2C_FLAG_RESET_REGS_POSTIDLE | | |
917 | OMAP_I2C_FLAG_BUS_SHIFT_2, | |
918 | }; | |
919 | ||
920 | static struct omap_i2c_bus_platform_data omap4_pdata = { | |
921 | .rev = OMAP_I2C_IP_VERSION_2, | |
922 | }; | |
923 | ||
924 | static const struct of_device_id omap_i2c_of_match[] = { | |
925 | { | |
926 | .compatible = "ti,omap4-i2c", | |
927 | .data = &omap4_pdata, | |
928 | }, | |
929 | { | |
930 | .compatible = "ti,omap3-i2c", | |
931 | .data = &omap3_pdata, | |
932 | }, | |
933 | { }, | |
934 | }; | |
935 | MODULE_DEVICE_TABLE(of, omap_i2c_of_match); | |
936 | #endif | |
937 | ||
1139aea9 | 938 | static int __devinit |
010d442c KS |
939 | omap_i2c_probe(struct platform_device *pdev) |
940 | { | |
941 | struct omap_i2c_dev *dev; | |
942 | struct i2c_adapter *adap; | |
943 | struct resource *mem, *irq, *ioarea; | |
20c9d2c4 | 944 | struct omap_i2c_bus_platform_data *pdata = pdev->dev.platform_data; |
6145197b BC |
945 | struct device_node *node = pdev->dev.of_node; |
946 | const struct of_device_id *match; | |
e355204e | 947 | irq_handler_t isr; |
010d442c KS |
948 | int r; |
949 | ||
950 | /* NOTE: driver uses the static register mapping */ | |
951 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
952 | if (!mem) { | |
953 | dev_err(&pdev->dev, "no mem resource?\n"); | |
954 | return -ENODEV; | |
955 | } | |
956 | irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
957 | if (!irq) { | |
958 | dev_err(&pdev->dev, "no irq resource?\n"); | |
959 | return -ENODEV; | |
960 | } | |
961 | ||
59330825 | 962 | ioarea = request_mem_region(mem->start, resource_size(mem), |
010d442c KS |
963 | pdev->name); |
964 | if (!ioarea) { | |
965 | dev_err(&pdev->dev, "I2C region already claimed\n"); | |
966 | return -EBUSY; | |
967 | } | |
968 | ||
010d442c KS |
969 | dev = kzalloc(sizeof(struct omap_i2c_dev), GFP_KERNEL); |
970 | if (!dev) { | |
971 | r = -ENOMEM; | |
972 | goto err_release_region; | |
973 | } | |
974 | ||
6c5aa407 | 975 | match = of_match_device(of_match_ptr(omap_i2c_of_match), &pdev->dev); |
6145197b BC |
976 | if (match) { |
977 | u32 freq = 100000; /* default to 100000 Hz */ | |
978 | ||
979 | pdata = match->data; | |
980 | dev->dtrev = pdata->rev; | |
981 | dev->flags = pdata->flags; | |
982 | ||
983 | of_property_read_u32(node, "clock-frequency", &freq); | |
984 | /* convert DT freq value in Hz into kHz for speed */ | |
985 | dev->speed = freq / 1000; | |
986 | } else if (pdata != NULL) { | |
987 | dev->speed = pdata->clkrate; | |
988 | dev->flags = pdata->flags; | |
20c9d2c4 | 989 | dev->set_mpu_wkup_lat = pdata->set_mpu_wkup_lat; |
6145197b | 990 | dev->dtrev = pdata->rev; |
20c9d2c4 | 991 | } |
4574eb68 | 992 | |
010d442c KS |
993 | dev->dev = &pdev->dev; |
994 | dev->irq = irq->start; | |
c6ffddea | 995 | dev->base = ioremap(mem->start, resource_size(mem)); |
55c381e4 RK |
996 | if (!dev->base) { |
997 | r = -ENOMEM; | |
998 | goto err_free_mem; | |
999 | } | |
1000 | ||
010d442c KS |
1001 | platform_set_drvdata(pdev, dev); |
1002 | ||
6145197b | 1003 | dev->reg_shift = (dev->flags >> OMAP_I2C_FLAG_BUS_SHIFT__SHIFT) & 3; |
7c6bd201 | 1004 | |
6145197b | 1005 | if (dev->dtrev == OMAP_I2C_IP_VERSION_2) |
a1295577 | 1006 | dev->regs = (u8 *)reg_map_ip_v2; |
f38e66e0 | 1007 | else |
a1295577 | 1008 | dev->regs = (u8 *)reg_map_ip_v1; |
f38e66e0 | 1009 | |
7f4b08ee | 1010 | pm_runtime_enable(dev->dev); |
3b0fb97c S |
1011 | r = pm_runtime_get_sync(dev->dev); |
1012 | if (IS_ERR_VALUE(r)) | |
1013 | goto err_free_mem; | |
010d442c | 1014 | |
9c76b878 | 1015 | dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff; |
010d442c | 1016 | |
9aa8ec67 TK |
1017 | dev->errata = 0; |
1018 | ||
1019 | if (dev->flags & OMAP_I2C_FLAG_APPLY_ERRATA_I207) | |
1020 | dev->errata |= I2C_OMAP_ERRATA_I207; | |
1021 | ||
8a9d97d3 | 1022 | if (dev->rev <= OMAP_I2C_REV_ON_3430) |
1023 | dev->errata |= I2C_OMAP3_1P153; | |
1024 | ||
6145197b | 1025 | if (!(dev->flags & OMAP_I2C_FLAG_NO_FIFO)) { |
b6ee52c3 NM |
1026 | u16 s; |
1027 | ||
1028 | /* Set up the fifo size - Get total size */ | |
1029 | s = (omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3; | |
1030 | dev->fifo_size = 0x8 << s; | |
1031 | ||
1032 | /* | |
1033 | * Set up notification threshold as half the total available | |
1034 | * size. This is to ensure that we can handle the status on int | |
1035 | * call back latencies. | |
1036 | */ | |
1d5a34fe S |
1037 | |
1038 | dev->fifo_size = (dev->fifo_size / 2); | |
1039 | ||
1040 | if (dev->rev >= OMAP_I2C_REV_ON_3530_4430) | |
f38e66e0 | 1041 | dev->b_hw = 0; /* Disable hardware fixes */ |
1d5a34fe | 1042 | else |
f38e66e0 | 1043 | dev->b_hw = 1; /* Enable hardware fixes */ |
1d5a34fe | 1044 | |
20c9d2c4 KJ |
1045 | /* calculate wakeup latency constraint for MPU */ |
1046 | if (dev->set_mpu_wkup_lat != NULL) | |
1047 | dev->latency = (1000000 * dev->fifo_size) / | |
6145197b | 1048 | (1000 * dev->speed / 8); |
b6ee52c3 NM |
1049 | } |
1050 | ||
010d442c KS |
1051 | /* reset ASAP, clearing any IRQs */ |
1052 | omap_i2c_init(dev); | |
1053 | ||
4e80f727 AG |
1054 | isr = (dev->rev < OMAP_I2C_OMAP1_REV_2) ? omap_i2c_omap1_isr : |
1055 | omap_i2c_isr; | |
9c76b878 | 1056 | r = request_irq(dev->irq, isr, 0, pdev->name, dev); |
010d442c KS |
1057 | |
1058 | if (r) { | |
1059 | dev_err(dev->dev, "failure requesting irq %i\n", dev->irq); | |
1060 | goto err_unuse_clocks; | |
1061 | } | |
9c76b878 | 1062 | |
9550d4d7 | 1063 | dev_info(dev->dev, "bus %d rev%d.%d.%d at %d kHz\n", pdev->id, |
6145197b | 1064 | dev->dtrev, dev->rev >> 4, dev->rev & 0xf, dev->speed); |
010d442c KS |
1065 | |
1066 | adap = &dev->adapter; | |
1067 | i2c_set_adapdata(adap, dev); | |
1068 | adap->owner = THIS_MODULE; | |
1069 | adap->class = I2C_CLASS_HWMON; | |
783fd6fa | 1070 | strlcpy(adap->name, "OMAP I2C adapter", sizeof(adap->name)); |
010d442c KS |
1071 | adap->algo = &omap_i2c_algo; |
1072 | adap->dev.parent = &pdev->dev; | |
6145197b | 1073 | adap->dev.of_node = pdev->dev.of_node; |
010d442c KS |
1074 | |
1075 | /* i2c device drivers may be active on return from add_adapter() */ | |
7c175499 DB |
1076 | adap->nr = pdev->id; |
1077 | r = i2c_add_numbered_adapter(adap); | |
010d442c KS |
1078 | if (r) { |
1079 | dev_err(dev->dev, "failure adding adapter\n"); | |
1080 | goto err_free_irq; | |
1081 | } | |
1082 | ||
6145197b BC |
1083 | of_i2c_register_devices(adap); |
1084 | ||
62ff2c2b S |
1085 | pm_runtime_put(dev->dev); |
1086 | ||
010d442c KS |
1087 | return 0; |
1088 | ||
1089 | err_free_irq: | |
1090 | free_irq(dev->irq, dev); | |
1091 | err_unuse_clocks: | |
3e39752d | 1092 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0); |
fab67afb | 1093 | pm_runtime_put(dev->dev); |
55c381e4 | 1094 | iounmap(dev->base); |
24740516 | 1095 | pm_runtime_disable(&pdev->dev); |
010d442c KS |
1096 | err_free_mem: |
1097 | platform_set_drvdata(pdev, NULL); | |
1098 | kfree(dev); | |
1099 | err_release_region: | |
59330825 | 1100 | release_mem_region(mem->start, resource_size(mem)); |
010d442c KS |
1101 | |
1102 | return r; | |
1103 | } | |
1104 | ||
1105 | static int | |
1106 | omap_i2c_remove(struct platform_device *pdev) | |
1107 | { | |
1108 | struct omap_i2c_dev *dev = platform_get_drvdata(pdev); | |
1109 | struct resource *mem; | |
3b0fb97c | 1110 | int ret; |
010d442c KS |
1111 | |
1112 | platform_set_drvdata(pdev, NULL); | |
1113 | ||
1114 | free_irq(dev->irq, dev); | |
1115 | i2c_del_adapter(&dev->adapter); | |
3b0fb97c S |
1116 | ret = pm_runtime_get_sync(&pdev->dev); |
1117 | if (IS_ERR_VALUE(ret)) | |
1118 | return ret; | |
1119 | ||
010d442c | 1120 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0); |
0861f430 | 1121 | pm_runtime_put(&pdev->dev); |
24740516 | 1122 | pm_runtime_disable(&pdev->dev); |
55c381e4 | 1123 | iounmap(dev->base); |
010d442c KS |
1124 | kfree(dev); |
1125 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
59330825 | 1126 | release_mem_region(mem->start, resource_size(mem)); |
010d442c KS |
1127 | return 0; |
1128 | } | |
1129 | ||
fab67afb KH |
1130 | #ifdef CONFIG_PM_RUNTIME |
1131 | static int omap_i2c_runtime_suspend(struct device *dev) | |
1132 | { | |
1133 | struct platform_device *pdev = to_platform_device(dev); | |
1134 | struct omap_i2c_dev *_dev = platform_get_drvdata(pdev); | |
3dae3efb S |
1135 | u16 iv; |
1136 | ||
1137 | _dev->iestate = omap_i2c_read_reg(_dev, OMAP_I2C_IE_REG); | |
bd16c82f S |
1138 | |
1139 | omap_i2c_write_reg(_dev, OMAP_I2C_IE_REG, 0); | |
3dae3efb S |
1140 | |
1141 | if (_dev->rev < OMAP_I2C_OMAP1_REV_2) { | |
1142 | iv = omap_i2c_read_reg(_dev, OMAP_I2C_IV_REG); /* Read clears */ | |
1143 | } else { | |
1144 | omap_i2c_write_reg(_dev, OMAP_I2C_STAT_REG, _dev->iestate); | |
fab67afb | 1145 | |
3dae3efb S |
1146 | /* Flush posted write */ |
1147 | omap_i2c_read_reg(_dev, OMAP_I2C_STAT_REG); | |
1148 | } | |
fab67afb KH |
1149 | |
1150 | return 0; | |
1151 | } | |
1152 | ||
1153 | static int omap_i2c_runtime_resume(struct device *dev) | |
1154 | { | |
1155 | struct platform_device *pdev = to_platform_device(dev); | |
1156 | struct omap_i2c_dev *_dev = platform_get_drvdata(pdev); | |
1157 | ||
3dae3efb S |
1158 | if (_dev->flags & OMAP_I2C_FLAG_RESET_REGS_POSTIDLE) { |
1159 | omap_i2c_write_reg(_dev, OMAP_I2C_CON_REG, 0); | |
1160 | omap_i2c_write_reg(_dev, OMAP_I2C_PSC_REG, _dev->pscstate); | |
1161 | omap_i2c_write_reg(_dev, OMAP_I2C_SCLL_REG, _dev->scllstate); | |
1162 | omap_i2c_write_reg(_dev, OMAP_I2C_SCLH_REG, _dev->sclhstate); | |
1163 | omap_i2c_write_reg(_dev, OMAP_I2C_BUF_REG, _dev->bufstate); | |
1164 | omap_i2c_write_reg(_dev, OMAP_I2C_SYSC_REG, _dev->syscstate); | |
1165 | omap_i2c_write_reg(_dev, OMAP_I2C_WE_REG, _dev->westate); | |
1166 | omap_i2c_write_reg(_dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN); | |
1167 | } | |
1168 | ||
1169 | /* | |
1170 | * Don't write to this register if the IE state is 0 as it can | |
1171 | * cause deadlock. | |
1172 | */ | |
1173 | if (_dev->iestate) | |
1174 | omap_i2c_write_reg(_dev, OMAP_I2C_IE_REG, _dev->iestate); | |
fab67afb KH |
1175 | |
1176 | return 0; | |
1177 | } | |
1178 | ||
1179 | static struct dev_pm_ops omap_i2c_pm_ops = { | |
1180 | .runtime_suspend = omap_i2c_runtime_suspend, | |
1181 | .runtime_resume = omap_i2c_runtime_resume, | |
1182 | }; | |
1183 | #define OMAP_I2C_PM_OPS (&omap_i2c_pm_ops) | |
1184 | #else | |
1185 | #define OMAP_I2C_PM_OPS NULL | |
1186 | #endif | |
1187 | ||
010d442c KS |
1188 | static struct platform_driver omap_i2c_driver = { |
1189 | .probe = omap_i2c_probe, | |
1190 | .remove = omap_i2c_remove, | |
1191 | .driver = { | |
f7bb0d9a | 1192 | .name = "omap_i2c", |
010d442c | 1193 | .owner = THIS_MODULE, |
fab67afb | 1194 | .pm = OMAP_I2C_PM_OPS, |
6145197b | 1195 | .of_match_table = of_match_ptr(omap_i2c_of_match), |
010d442c KS |
1196 | }, |
1197 | }; | |
1198 | ||
1199 | /* I2C may be needed to bring up other drivers */ | |
1200 | static int __init | |
1201 | omap_i2c_init_driver(void) | |
1202 | { | |
1203 | return platform_driver_register(&omap_i2c_driver); | |
1204 | } | |
1205 | subsys_initcall(omap_i2c_init_driver); | |
1206 | ||
1207 | static void __exit omap_i2c_exit_driver(void) | |
1208 | { | |
1209 | platform_driver_unregister(&omap_i2c_driver); | |
1210 | } | |
1211 | module_exit(omap_i2c_exit_driver); | |
1212 | ||
1213 | MODULE_AUTHOR("MontaVista Software, Inc. (and others)"); | |
1214 | MODULE_DESCRIPTION("TI OMAP I2C bus adapter"); | |
1215 | MODULE_LICENSE("GPL"); | |
f7bb0d9a | 1216 | MODULE_ALIAS("platform:omap_i2c"); |