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i2c: constify platform_device_id
[deliverable/linux.git] / drivers / i2c / busses / i2c-omap.c
CommitLineData
010d442c
KS		 1/*
2 * TI OMAP I2C master mode driver
3 *
4 * Copyright (C) 2003 MontaVista Software, Inc.
010d442c 5 * Copyright (C) 2005 Nokia Corporation
c1a473bd 6 * Copyright (C) 2004 - 2007 Texas Instruments.
010d442c 7 *
c1a473bd
TL		 8 * Originally written by MontaVista Software, Inc.
9 * Additional contributions by:
10 * Tony Lindgren <tony@atomide.com>
11 * Imre Deak <imre.deak@nokia.com>
12 * Juha Yrjölä <juha.yrjola@solidboot.com>
13 * Syed Khasim <x0khasim@ti.com>
14 * Nishant Menon <nm@ti.com>
010d442c
KS		 15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
010d442c
KS		 25 */
26
27#include <linux/module.h>
28#include <linux/delay.h>
29#include <linux/i2c.h>
30#include <linux/err.h>
31#include <linux/interrupt.h>
32#include <linux/completion.h>
33#include <linux/platform_device.h>
34#include <linux/clk.h>
c1a473bd 35#include <linux/io.h>
6145197b 36#include <linux/of.h>
6145197b 37#include <linux/of_device.h>
5a0e3ad6 38#include <linux/slab.h>
20c9d2c4 39#include <linux/i2c-omap.h>
27b1fec2 40#include <linux/pm_runtime.h>
096ea30c 41#include <linux/pinctrl/consumer.h>
010d442c 42
9c76b878 43/* I2C controller revisions */
4e80f727 44#define OMAP_I2C_OMAP1_REV_2 0x20
9c76b878
PW		 45
46/* I2C controller revisions present on specific hardware */
47dcd016
S		 47#define OMAP_I2C_REV_ON_2430 0x00000036
48#define OMAP_I2C_REV_ON_3430_3530 0x0000003C
49#define OMAP_I2C_REV_ON_3630 0x00000040
50#define OMAP_I2C_REV_ON_4430_PLUS 0x50400002
9c76b878 51
010d442c
KS		 52/* timeout waiting for the controller to respond */
53#define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
54
6d8451d5
FB		 55/* timeout for pm runtime autosuspend */
56#define OMAP_I2C_PM_TIMEOUT 1000 /* ms */
57
0f5768bf
AK		 58/* timeout for making decision on bus free status */
59#define OMAP_I2C_BUS_FREE_TIMEOUT (msecs_to_jiffies(10))
60
5043e9e7 61/* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */
f38e66e0
SS		 62enum {
63 OMAP_I2C_REV_REG = 0,
64 OMAP_I2C_IE_REG,
65 OMAP_I2C_STAT_REG,
66 OMAP_I2C_IV_REG,
67 OMAP_I2C_WE_REG,
68 OMAP_I2C_SYSS_REG,
69 OMAP_I2C_BUF_REG,
70 OMAP_I2C_CNT_REG,
71 OMAP_I2C_DATA_REG,
72 OMAP_I2C_SYSC_REG,
73 OMAP_I2C_CON_REG,
74 OMAP_I2C_OA_REG,
75 OMAP_I2C_SA_REG,
76 OMAP_I2C_PSC_REG,
77 OMAP_I2C_SCLL_REG,
78 OMAP_I2C_SCLH_REG,
79 OMAP_I2C_SYSTEST_REG,
80 OMAP_I2C_BUFSTAT_REG,
b8853088
AG		 81 /* only on OMAP4430 */
82 OMAP_I2C_IP_V2_REVNB_LO,
83 OMAP_I2C_IP_V2_REVNB_HI,
84 OMAP_I2C_IP_V2_IRQSTATUS_RAW,
85 OMAP_I2C_IP_V2_IRQENABLE_SET,
86 OMAP_I2C_IP_V2_IRQENABLE_CLR,
f38e66e0 87};
010d442c
KS		 88
89/* I2C Interrupt Enable Register (OMAP_I2C_IE): */
b6ee52c3
NM		 90#define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */
91#define OMAP_I2C_IE_RDR (1 << 13) /* RX Buffer drain int enable */
010d442c
KS		 92#define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */
93#define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */
94#define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */
95#define OMAP_I2C_IE_NACK (1 << 1) /* No ack interrupt enable */
96#define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */
97
98/* I2C Status Register (OMAP_I2C_STAT): */
b6ee52c3
NM		 99#define OMAP_I2C_STAT_XDR (1 << 14) /* TX Buffer draining */
100#define OMAP_I2C_STAT_RDR (1 << 13) /* RX Buffer draining */
010d442c
KS		 101#define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */
102#define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */
103#define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
104#define OMAP_I2C_STAT_AAS (1 << 9) /* Address as slave */
9fd6ada8 105#define OMAP_I2C_STAT_BF (1 << 8) /* Bus Free */
010d442c
KS		 106#define OMAP_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
107#define OMAP_I2C_STAT_RRDY (1 << 3) /* Receive data ready */
108#define OMAP_I2C_STAT_ARDY (1 << 2) /* Register access ready */
109#define OMAP_I2C_STAT_NACK (1 << 1) /* No ack interrupt enable */
110#define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost int ena */
111
5043e9e7
KJ		 112/* I2C WE wakeup enable register */
113#define OMAP_I2C_WE_XDR_WE (1 << 14) /* TX drain wakup */
114#define OMAP_I2C_WE_RDR_WE (1 << 13) /* RX drain wakeup */
115#define OMAP_I2C_WE_AAS_WE (1 << 9) /* Address as slave wakeup*/
116#define OMAP_I2C_WE_BF_WE (1 << 8) /* Bus free wakeup */
117#define OMAP_I2C_WE_STC_WE (1 << 6) /* Start condition wakeup */
118#define OMAP_I2C_WE_GC_WE (1 << 5) /* General call wakeup */
119#define OMAP_I2C_WE_DRDY_WE (1 << 3) /* TX/RX data ready wakeup */
120#define OMAP_I2C_WE_ARDY_WE (1 << 2) /* Reg access ready wakeup */
121#define OMAP_I2C_WE_NACK_WE (1 << 1) /* No acknowledgment wakeup */
122#define OMAP_I2C_WE_AL_WE (1 << 0) /* Arbitration lost wakeup */
123
124#define OMAP_I2C_WE_ALL (OMAP_I2C_WE_XDR_WE | OMAP_I2C_WE_RDR_WE | \
125 OMAP_I2C_WE_AAS_WE | OMAP_I2C_WE_BF_WE | \
126 OMAP_I2C_WE_STC_WE | OMAP_I2C_WE_GC_WE | \
127 OMAP_I2C_WE_DRDY_WE | OMAP_I2C_WE_ARDY_WE | \
128 OMAP_I2C_WE_NACK_WE | OMAP_I2C_WE_AL_WE)
129
010d442c
KS		 130/* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
131#define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */
b6ee52c3 132#define OMAP_I2C_BUF_RXFIF_CLR (1 << 14) /* RX FIFO Clear */
010d442c 133#define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */
b6ee52c3 134#define OMAP_I2C_BUF_TXFIF_CLR (1 << 6) /* TX FIFO Clear */
010d442c
KS		 135
136/* I2C Configuration Register (OMAP_I2C_CON): */
137#define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */
138#define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */
b6ee52c3 139#define OMAP_I2C_CON_OPMODE_HS (1 << 12) /* High Speed support */
010d442c
KS		 140#define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */
141#define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */
142#define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */
143#define OMAP_I2C_CON_XA (1 << 8) /* Expand address */
144#define OMAP_I2C_CON_RM (1 << 2) /* Repeat mode (master only) */
145#define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */
146#define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */
147
4574eb68
SMK		 148/* I2C SCL time value when Master */
149#define OMAP_I2C_SCLL_HSSCLL 8
150#define OMAP_I2C_SCLH_HSSCLH 8
151
010d442c 152/* I2C System Test Register (OMAP_I2C_SYSTEST): */
010d442c
KS		 153#define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */
154#define OMAP_I2C_SYSTEST_FREE (1 << 14) /* Free running mode */
155#define OMAP_I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */
156#define OMAP_I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */
9fd6ada8
AK		 157/* Functional mode */
158#define OMAP_I2C_SYSTEST_SCL_I_FUNC (1 << 8) /* SCL line input value */
159#define OMAP_I2C_SYSTEST_SCL_O_FUNC (1 << 7) /* SCL line output value */
160#define OMAP_I2C_SYSTEST_SDA_I_FUNC (1 << 6) /* SDA line input value */
161#define OMAP_I2C_SYSTEST_SDA_O_FUNC (1 << 5) /* SDA line output value */
162/* SDA/SCL IO mode */
010d442c
KS		 163#define OMAP_I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense in */
164#define OMAP_I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive out */
165#define OMAP_I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense in */
166#define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */
010d442c 167
fdd07fe6
PW		 168/* OCP_SYSSTATUS bit definitions */
169#define SYSS_RESETDONE_MASK (1 << 0)
170
171/* OCP_SYSCONFIG bit definitions */
172#define SYSC_CLOCKACTIVITY_MASK (0x3 << 8)
173#define SYSC_SIDLEMODE_MASK (0x3 << 3)
174#define SYSC_ENAWAKEUP_MASK (1 << 2)
175#define SYSC_SOFTRESET_MASK (1 << 1)
176#define SYSC_AUTOIDLE_MASK (1 << 0)
177
178#define SYSC_IDLEMODE_SMART 0x2
179#define SYSC_CLOCKACTIVITY_FCLK 0x2
010d442c 180
f3083d92 181/* Errata definitions */
182#define I2C_OMAP_ERRATA_I207 (1 << 0)
c8db38f0 183#define I2C_OMAP_ERRATA_I462 (1 << 1)
010d442c 184
4368de19
OD		 185#define OMAP_I2C_IP_V2_INTERRUPTS_MASK 0x6FFF
186
010d442c 187struct omap_i2c_dev {
3b2f8f82 188 spinlock_t lock; /* IRQ synchronization */
010d442c
KS		 189 struct device *dev;
190 void __iomem *base; /* virtual */
191 int irq;
d84d3ea3 192 int reg_shift; /* bit shift for I2C register addresses */
010d442c
KS		 193 struct completion cmd_complete;
194 struct resource *ioarea;
49839dc9
PW		 195 u32 latency; /* maximum mpu wkup latency */
196 void (*set_mpu_wkup_lat)(struct device *dev,
197 long latency);
6145197b 198 u32 speed; /* Speed of bus in kHz */
6145197b 199 u32 flags;
4368de19 200 u16 scheme;
010d442c
KS		 201 u16 cmd_err;
202 u8 *buf;
f38e66e0 203 u8 *regs;
010d442c
KS		 204 size_t buf_len;
205 struct i2c_adapter adapter;
dd74548d 206 u8 threshold;
b6ee52c3
NM		 207 u8 fifo_size; /* use as flag and value
208 * fifo_size==0 implies no fifo
209 * if set, should be trsh+1
210 */
47dcd016 211 u32 rev;
b6ee52c3 212 unsigned b_hw:1; /* bad h/w fixes */
0f5768bf
AK		 213 unsigned bb_valid:1; /* true when BB-bit reflects
214 * the I2C bus state
215 */
079d8af2 216 unsigned receiver:1; /* true when we're in receiver mode */
f08ac4e7 217 u16 iestate; /* Saved interrupt register */
ef871432
RN		 218 u16 pscstate;
219 u16 scllstate;
220 u16 sclhstate;
ef871432
RN		 221 u16 syscstate;
222 u16 westate;
f3083d92 223 u16 errata;
010d442c
KS		 224};
225
a1295577 226static const u8 reg_map_ip_v1[] = {
f38e66e0
SS		 227 [OMAP_I2C_REV_REG] = 0x00,
228 [OMAP_I2C_IE_REG] = 0x01,
229 [OMAP_I2C_STAT_REG] = 0x02,
230 [OMAP_I2C_IV_REG] = 0x03,
231 [OMAP_I2C_WE_REG] = 0x03,
232 [OMAP_I2C_SYSS_REG] = 0x04,
233 [OMAP_I2C_BUF_REG] = 0x05,
234 [OMAP_I2C_CNT_REG] = 0x06,
235 [OMAP_I2C_DATA_REG] = 0x07,
236 [OMAP_I2C_SYSC_REG] = 0x08,
237 [OMAP_I2C_CON_REG] = 0x09,
238 [OMAP_I2C_OA_REG] = 0x0a,
239 [OMAP_I2C_SA_REG] = 0x0b,
240 [OMAP_I2C_PSC_REG] = 0x0c,
241 [OMAP_I2C_SCLL_REG] = 0x0d,
242 [OMAP_I2C_SCLH_REG] = 0x0e,
243 [OMAP_I2C_SYSTEST_REG] = 0x0f,
244 [OMAP_I2C_BUFSTAT_REG] = 0x10,
245};
246
a1295577 247static const u8 reg_map_ip_v2[] = {
f38e66e0
SS		 248 [OMAP_I2C_REV_REG] = 0x04,
249 [OMAP_I2C_IE_REG] = 0x2c,
250 [OMAP_I2C_STAT_REG] = 0x28,
251 [OMAP_I2C_IV_REG] = 0x34,
252 [OMAP_I2C_WE_REG] = 0x34,
253 [OMAP_I2C_SYSS_REG] = 0x90,
254 [OMAP_I2C_BUF_REG] = 0x94,
255 [OMAP_I2C_CNT_REG] = 0x98,
256 [OMAP_I2C_DATA_REG] = 0x9c,
2727b175 257 [OMAP_I2C_SYSC_REG] = 0x10,
f38e66e0
SS		 258 [OMAP_I2C_CON_REG] = 0xa4,
259 [OMAP_I2C_OA_REG] = 0xa8,
260 [OMAP_I2C_SA_REG] = 0xac,
261 [OMAP_I2C_PSC_REG] = 0xb0,
262 [OMAP_I2C_SCLL_REG] = 0xb4,
263 [OMAP_I2C_SCLH_REG] = 0xb8,
264 [OMAP_I2C_SYSTEST_REG] = 0xbC,
265 [OMAP_I2C_BUFSTAT_REG] = 0xc0,
b8853088
AG		 266 [OMAP_I2C_IP_V2_REVNB_LO] = 0x00,
267 [OMAP_I2C_IP_V2_REVNB_HI] = 0x04,
268 [OMAP_I2C_IP_V2_IRQSTATUS_RAW] = 0x24,
269 [OMAP_I2C_IP_V2_IRQENABLE_SET] = 0x2c,
270 [OMAP_I2C_IP_V2_IRQENABLE_CLR] = 0x30,
f38e66e0
SS		 271};
272
010d442c
KS		 273static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev,
274 int reg, u16 val)
275{
40b13ca8 276 writew_relaxed(val, i2c_dev->base +
f38e66e0 277 (i2c_dev->regs[reg] << i2c_dev->reg_shift));
010d442c
KS		 278}
279
280static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
281{
40b13ca8 282 return readw_relaxed(i2c_dev->base +
f38e66e0 283 (i2c_dev->regs[reg] << i2c_dev->reg_shift));
010d442c
KS		 284}
285
95dd3032
S		 286static void __omap_i2c_init(struct omap_i2c_dev *dev)
287{
288
289 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
290
291 /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
292 omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, dev->pscstate);
293
294 /* SCL low and high time values */
295 omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, dev->scllstate);
296 omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, dev->sclhstate);
297 if (dev->rev >= OMAP_I2C_REV_ON_3430_3530)
298 omap_i2c_write_reg(dev, OMAP_I2C_WE_REG, dev->westate);
299
300 /* Take the I2C module out of reset: */
301 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
302
4f734a3a
AK		 303 /*
304 * NOTE: right after setting CON_EN, STAT_BB could be 0 while the
305 * bus is busy. It will be changed to 1 on the next IP FCLK clock.
306 * udelay(1) will be enough to fix that.
307 */
308
95dd3032
S		 309 /*
310 * Don't write to this register if the IE state is 0 as it can
311 * cause deadlock.
312 */
313 if (dev->iestate)
314 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
315}
316
d6c842ad 317static int omap_i2c_reset(struct omap_i2c_dev *dev)
010d442c 318{
010d442c 319 unsigned long timeout;
ca85e248
S		 320 u16 sysc;
321
4e80f727 322 if (dev->rev >= OMAP_I2C_OMAP1_REV_2) {
ca85e248
S		 323 sysc = omap_i2c_read_reg(dev, OMAP_I2C_SYSC_REG);
324
57eb81b1
MG		 325 /* Disable I2C controller before soft reset */
326 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
327 omap_i2c_read_reg(dev, OMAP_I2C_CON_REG) &
328 ~(OMAP_I2C_CON_EN));
329
fdd07fe6 330 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK);
010d442c
KS		 331 /* For some reason we need to set the EN bit before the
332 * reset done bit gets set. */
333 timeout = jiffies + OMAP_I2C_TIMEOUT;
334 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
335 while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) &
fdd07fe6 336 SYSS_RESETDONE_MASK)) {
010d442c 337 if (time_after(jiffies, timeout)) {
fce3ff03 338 dev_warn(dev->dev, "timeout waiting "
010d442c
KS		 339 "for controller reset\n");
340 return -ETIMEDOUT;
341 }
342 msleep(1);
343 }
fdd07fe6
PW		 344
345 /* SYSC register is cleared by the reset; rewrite it */
ca85e248 346 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, sysc);
fdd07fe6 347
23173eae
AK		 348 if (dev->rev > OMAP_I2C_REV_ON_3430_3530) {
349 /* Schedule I2C-bus monitoring on the next transfer */
350 dev->bb_valid = 0;
351 }
010d442c 352 }
0f5768bf 353
d6c842ad
S		 354 return 0;
355}
356
357static int omap_i2c_init(struct omap_i2c_dev *dev)
358{
359 u16 psc = 0, scll = 0, sclh = 0;
360 u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
361 unsigned long fclk_rate = 12000000;
362 unsigned long internal_clk = 0;
363 struct clk *fclk;
364
365 if (dev->rev >= OMAP_I2C_REV_ON_3430_3530) {
366 /*
367 * Enabling all wakup sources to stop I2C freezing on
368 * WFI instruction.
369 * REVISIT: Some wkup sources might not be needed.
370 */
371 dev->westate = OMAP_I2C_WE_ALL;
372 }
010d442c 373
6145197b 374 if (dev->flags & OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK) {
0e9ae109
RK		 375 /*
376 * The I2C functional clock is the armxor_ck, so there's
377 * no need to get "armxor_ck" separately. Now, if OMAP2420
378 * always returns 12MHz for the functional clock, we can
379 * do this bit unconditionally.
380 */
27b1fec2
RN		 381 fclk = clk_get(dev->dev, "fck");
382 fclk_rate = clk_get_rate(fclk);
383 clk_put(fclk);
0e9ae109 384
010d442c
KS		 385 /* TRM for 5912 says the I2C clock must be prescaled to be
386 * between 7 - 12 MHz. The XOR input clock is typically
387 * 12, 13 or 19.2 MHz. So we should have code that produces:
388 *
389 * XOR MHz Divider Prescaler
390 * 12 1 0
391 * 13 2 1
392 * 19.2 2 1
393 */
d7aef138
JD		 394 if (fclk_rate > 12000000)
395 psc = fclk_rate / 12000000;
010d442c
KS		 396 }
397
6145197b 398 if (!(dev->flags & OMAP_I2C_FLAG_SIMPLE_CLOCK)) {
4574eb68 399
84bf2c86
AK		 400 /*
401 * HSI2C controller internal clk rate should be 19.2 Mhz for
402 * HS and for all modes on 2430. On 34xx we can use lower rate
403 * to get longer filter period for better noise suppression.
404 * The filter is iclk (fclk for HS) period.
405 */
3be0053e 406 if (dev->speed > 400 ||
6145197b 407 dev->flags & OMAP_I2C_FLAG_FORCE_19200_INT_CLK)
84bf2c86
AK		 408 internal_clk = 19200;
409 else if (dev->speed > 100)
410 internal_clk = 9600;
411 else
412 internal_clk = 4000;
27b1fec2
RN		 413 fclk = clk_get(dev->dev, "fck");
414 fclk_rate = clk_get_rate(fclk) / 1000;
415 clk_put(fclk);
4574eb68
SMK		 416
417 /* Compute prescaler divisor */
418 psc = fclk_rate / internal_clk;
419 psc = psc - 1;
420
421 /* If configured for High Speed */
422 if (dev->speed > 400) {
baf46b4e
AK		 423 unsigned long scl;
424
4574eb68 425 /* For first phase of HS mode */
baf46b4e
AK		 426 scl = internal_clk / 400;
427 fsscll = scl - (scl / 3) - 7;
428 fssclh = (scl / 3) - 5;
4574eb68
SMK		 429
430 /* For second phase of HS mode */
baf46b4e
AK		 431 scl = fclk_rate / dev->speed;
432 hsscll = scl - (scl / 3) - 7;
433 hssclh = (scl / 3) - 5;
434 } else if (dev->speed > 100) {
435 unsigned long scl;
436
437 /* Fast mode */
438 scl = internal_clk / dev->speed;
439 fsscll = scl - (scl / 3) - 7;
440 fssclh = (scl / 3) - 5;
4574eb68 441 } else {
baf46b4e
AK		 442 /* Standard mode */
443 fsscll = internal_clk / (dev->speed * 2) - 7;
444 fssclh = internal_clk / (dev->speed * 2) - 5;
4574eb68
SMK		 445 }
446 scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
447 sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
448 } else {
449 /* Program desired operating rate */
450 fclk_rate /= (psc + 1) * 1000;
451 if (psc > 2)
452 psc = 2;
453 scll = fclk_rate / (dev->speed * 2) - 7 + psc;
454 sclh = fclk_rate / (dev->speed * 2) - 7 + psc;
455 }
456
ef871432 457 dev->iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
c1a473bd
TL		 458 OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
459 OMAP_I2C_IE_AL) | ((dev->fifo_size) ?
ef871432 460 (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0);
95dd3032
S		 461
462 dev->pscstate = psc;
463 dev->scllstate = scll;
464 dev->sclhstate = sclh;
465
23173eae 466 if (dev->rev <= OMAP_I2C_REV_ON_3430_3530) {
0f5768bf
AK		 467 /* Not implemented */
468 dev->bb_valid = 1;
469 }
470
95dd3032
S		 471 __omap_i2c_init(dev);
472
010d442c
KS		 473 return 0;
474}
475
476/*
477 * Waiting on Bus Busy
478 */
479static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev)
480{
481 unsigned long timeout;
482
483 timeout = jiffies + OMAP_I2C_TIMEOUT;
484 while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
485 if (time_after(jiffies, timeout)) {
486 dev_warn(dev->dev, "timeout waiting for bus ready\n");
487 return -ETIMEDOUT;
488 }
489 msleep(1);
490 }
491
492 return 0;
493}
494
0f5768bf
AK		 495/*
496 * Wait while BB-bit doesn't reflect the I2C bus state
497 *
498 * In a multimaster environment, after IP software reset, BB-bit value doesn't
499 * correspond to the current bus state. It may happen what BB-bit will be 0,
500 * while the bus is busy due to another I2C master activity.
501 * Here are BB-bit values after reset:
502 * SDA SCL BB NOTES
503 * 0 0 0 1, 2
504 * 1 0 0 1, 2
505 * 0 1 1
506 * 1 1 0 3
507 * Later, if IP detect SDA=0 and SCL=1 (ACK) or SDA 1->0 while SCL=1 (START)
508 * combinations on the bus, it set BB-bit to 1.
509 * If IP detect SDA 0->1 while SCL=1 (STOP) combination on the bus,
510 * it set BB-bit to 0 and BF to 1.
511 * BB and BF bits correctly tracks the bus state while IP is suspended
512 * BB bit became valid on the next FCLK clock after CON_EN bit set
513 *
514 * NOTES:
515 * 1. Any transfer started when BB=0 and bus is busy wouldn't be
516 * completed by IP and results in controller timeout.
517 * 2. Any transfer started when BB=0 and SCL=0 results in IP
518 * starting to drive SDA low. In that case IP corrupt data
519 * on the bus.
520 * 3. Any transfer started in the middle of another master's transfer
521 * results in unpredictable results and data corruption
522 */
523static int omap_i2c_wait_for_bb_valid(struct omap_i2c_dev *dev)
524{
525 unsigned long bus_free_timeout = 0;
526 unsigned long timeout;
527 int bus_free = 0;
528 u16 stat, systest;
529
530 if (dev->bb_valid)
531 return 0;
532
533 timeout = jiffies + OMAP_I2C_TIMEOUT;
534 while (1) {
535 stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
536 /*
537 * We will see BB or BF event in a case IP had detected any
538 * activity on the I2C bus. Now IP correctly tracks the bus
539 * state. BB-bit value is valid.
540 */
541 if (stat & (OMAP_I2C_STAT_BB | OMAP_I2C_STAT_BF))
542 break;
543
544 /*
545 * Otherwise, we must look signals on the bus to make
546 * the right decision.
547 */
548 systest = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG);
549 if ((systest & OMAP_I2C_SYSTEST_SCL_I_FUNC) &&
550 (systest & OMAP_I2C_SYSTEST_SDA_I_FUNC)) {
551 if (!bus_free) {
552 bus_free_timeout = jiffies +
553 OMAP_I2C_BUS_FREE_TIMEOUT;
554 bus_free = 1;
555 }
556
557 /*
558 * SDA and SCL lines was high for 10 ms without bus
559 * activity detected. The bus is free. Consider
560 * BB-bit value is valid.
561 */
562 if (time_after(jiffies, bus_free_timeout))
563 break;
564 } else {
565 bus_free = 0;
566 }
567
568 if (time_after(jiffies, timeout)) {
569 dev_warn(dev->dev, "timeout waiting for bus ready\n");
570 return -ETIMEDOUT;
571 }
572
573 msleep(1);
574 }
575
576 dev->bb_valid = 1;
577 return 0;
578}
579
dd74548d
FB		 580static void omap_i2c_resize_fifo(struct omap_i2c_dev *dev, u8 size, bool is_rx)
581{
582 u16 buf;
583
584 if (dev->flags & OMAP_I2C_FLAG_NO_FIFO)
585 return;
586
587 /*
588 * Set up notification threshold based on message size. We're doing
589 * this to try and avoid draining feature as much as possible. Whenever
590 * we have big messages to transfer (bigger than our total fifo size)
591 * then we might use draining feature to transfer the remaining bytes.
592 */
593
594 dev->threshold = clamp(size, (u8) 1, dev->fifo_size);
595
596 buf = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
597
598 if (is_rx) {
599 /* Clear RX Threshold */
600 buf &= ~(0x3f << 8);
601 buf |= ((dev->threshold - 1) << 8) | OMAP_I2C_BUF_RXFIF_CLR;
602 } else {
603 /* Clear TX Threshold */
604 buf &= ~0x3f;
605 buf |= (dev->threshold - 1) | OMAP_I2C_BUF_TXFIF_CLR;
606 }
607
608 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, buf);
609
47dcd016 610 if (dev->rev < OMAP_I2C_REV_ON_3630)
dd74548d
FB		 611 dev->b_hw = 1; /* Enable hardware fixes */
612
613 /* calculate wakeup latency constraint for MPU */
49839dc9
PW		 614 if (dev->set_mpu_wkup_lat != NULL)
615 dev->latency = (1000000 * dev->threshold) /
616 (1000 * dev->speed / 8);
dd74548d
FB		 617}
618
010d442c
KS		 619/*
620 * Low level master read/write transaction.
621 */
622static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
623 struct i2c_msg *msg, int stop)
624{
625 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
33d54985 626 unsigned long timeout;
010d442c
KS		 627 u16 w;
628
629 dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
630 msg->addr, msg->len, msg->flags, stop);
631
632 if (msg->len == 0)
633 return -EINVAL;
634
dd74548d
FB		 635 dev->receiver = !!(msg->flags & I2C_M_RD);
636 omap_i2c_resize_fifo(dev, msg->len, dev->receiver);
637
010d442c
KS		 638 omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);
639
640 /* REVISIT: Could the STB bit of I2C_CON be used with probing? */
641 dev->buf = msg->buf;
642 dev->buf_len = msg->len;
643
d60ece5f
FB		 644 /* make sure writes to dev->buf_len are ordered */
645 barrier();
646
010d442c
KS		 647 omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len);
648
b6ee52c3
NM		 649 /* Clear the FIFO Buffers */
650 w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
651 w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR;
652 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w);
653
16735d02 654 reinit_completion(&dev->cmd_complete);
010d442c
KS		 655 dev->cmd_err = 0;
656
657 w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
4574eb68
SMK		 658
659 /* High speed configuration */
660 if (dev->speed > 400)
b6ee52c3 661 w |= OMAP_I2C_CON_OPMODE_HS;
4574eb68 662
fb604a3d
LP		 663 if (msg->flags & I2C_M_STOP)
664 stop = 1;
010d442c
KS		 665 if (msg->flags & I2C_M_TEN)
666 w |= OMAP_I2C_CON_XA;
667 if (!(msg->flags & I2C_M_RD))
668 w |= OMAP_I2C_CON_TRX;
c1a473bd 669
b6ee52c3 670 if (!dev->b_hw && stop)
010d442c 671 w |= OMAP_I2C_CON_STP;
4f734a3a
AK		 672 /*
673 * NOTE: STAT_BB bit could became 1 here if another master occupy
674 * the bus. IP successfully complete transfer when the bus will be
675 * free again (BB reset to 0).
676 */
010d442c
KS		 677 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
678
b6ee52c3
NM		 679 /*
680 * Don't write stt and stp together on some hardware.
681 */
682 if (dev->b_hw && stop) {
683 unsigned long delay = jiffies + OMAP_I2C_TIMEOUT;
684 u16 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
685 while (con & OMAP_I2C_CON_STT) {
686 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
687
688 /* Let the user know if i2c is in a bad state */
689 if (time_after(jiffies, delay)) {
690 dev_err(dev->dev, "controller timed out "
691 "waiting for start condition to finish\n");
692 return -ETIMEDOUT;
693 }
694 cpu_relax();
695 }
696
697 w |= OMAP_I2C_CON_STP;
698 w &= ~OMAP_I2C_CON_STT;
699 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
700 }
701
b7af349b
JN		 702 /*
703 * REVISIT: We should abort the transfer on signals, but the bus goes
704 * into arbitration and we're currently unable to recover from it.
705 */
33d54985
S		 706 timeout = wait_for_completion_timeout(&dev->cmd_complete,
707 OMAP_I2C_TIMEOUT);
33d54985 708 if (timeout == 0) {
010d442c 709 dev_err(dev->dev, "controller timed out\n");
d6c842ad
S		 710 omap_i2c_reset(dev);
711 __omap_i2c_init(dev);
010d442c
KS		 712 return -ETIMEDOUT;
713 }
714
715 if (likely(!dev->cmd_err))
716 return 0;
717
718 /* We have an error */
b76911d2 719 if (dev->cmd_err & (OMAP_I2C_STAT_ROVR | OMAP_I2C_STAT_XUDF)) {
d6c842ad
S		 720 omap_i2c_reset(dev);
721 __omap_i2c_init(dev);
010d442c
KS		 722 return -EIO;
723 }
724
b76911d2
AK		 725 if (dev->cmd_err & OMAP_I2C_STAT_AL)
726 return -EAGAIN;
727
010d442c
KS		 728 if (dev->cmd_err & OMAP_I2C_STAT_NACK) {
729 if (msg->flags & I2C_M_IGNORE_NAK)
730 return 0;
cda2109a
GS		 731
732 w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
733 w |= OMAP_I2C_CON_STP;
734 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
010d442c
KS		 735 return -EREMOTEIO;
736 }
737 return -EIO;
738}
739
740
741/*
742 * Prepare controller for a transaction and call omap_i2c_xfer_msg
743 * to do the work during IRQ processing.
744 */
745static int
746omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
747{
748 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
749 int i;
750 int r;
751
3b0fb97c 752 r = pm_runtime_get_sync(dev->dev);
ff370257 753 if (r < 0)
33ec5e81 754 goto out;
010d442c 755
0f5768bf
AK		 756 r = omap_i2c_wait_for_bb_valid(dev);
757 if (r < 0)
758 goto out;
759
c1a473bd
TL		 760 r = omap_i2c_wait_for_bb(dev);
761 if (r < 0)
010d442c
KS		 762 goto out;
763
49839dc9
PW		 764 if (dev->set_mpu_wkup_lat != NULL)
765 dev->set_mpu_wkup_lat(dev->dev, dev->latency);
6a91b558 766
010d442c
KS		 767 for (i = 0; i < num; i++) {
768 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));
769 if (r != 0)
770 break;
771 }
772
773 if (r == 0)
774 r = num;
5c64eb26
MN		 775
776 omap_i2c_wait_for_bb(dev);
1ab36045
S		 777
778 if (dev->set_mpu_wkup_lat != NULL)
779 dev->set_mpu_wkup_lat(dev->dev, -1);
780
010d442c 781out:
6d8451d5
FB		 782 pm_runtime_mark_last_busy(dev->dev);
783 pm_runtime_put_autosuspend(dev->dev);
010d442c
KS		 784 return r;
785}
786
787static u32
788omap_i2c_func(struct i2c_adapter *adap)
789{
fb604a3d
LP		 790 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
791 I2C_FUNC_PROTOCOL_MANGLING;
010d442c
KS		 792}
793
794static inline void
795omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err)
796{
797 dev->cmd_err |= err;
798 complete(&dev->cmd_complete);
799}
800
801static inline void
802omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat)
803{
804 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
805}
806
f3083d92 807static inline void i2c_omap_errata_i207(struct omap_i2c_dev *dev, u16 stat)
808{
809 /*
810 * I2C Errata(Errata Nos. OMAP2: 1.67, OMAP3: 1.8)
811 * Not applicable for OMAP4.
812 * Under certain rare conditions, RDR could be set again
813 * when the bus is busy, then ignore the interrupt and
814 * clear the interrupt.
815 */
816 if (stat & OMAP_I2C_STAT_RDR) {
817 /* Step 1: If RDR is set, clear it */
818 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
819
820 /* Step 2: */
821 if (!(omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG)
822 & OMAP_I2C_STAT_BB)) {
823
824 /* Step 3: */
825 if (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG)
826 & OMAP_I2C_STAT_RDR) {
827 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
828 dev_dbg(dev->dev, "RDR when bus is busy.\n");
829 }
830
831 }
832 }
833}
834
43469d8e
PW		 835/* rev1 devices are apparently only on some 15xx */
836#ifdef CONFIG_ARCH_OMAP15XX
837
010d442c 838static irqreturn_t
4e80f727 839omap_i2c_omap1_isr(int this_irq, void *dev_id)
010d442c
KS		 840{
841 struct omap_i2c_dev *dev = dev_id;
842 u16 iv, w;
843
fab67afb 844 if (pm_runtime_suspended(dev->dev))
f08ac4e7
TL		 845 return IRQ_NONE;
846
010d442c
KS		 847 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
848 switch (iv) {
849 case 0x00: /* None */
850 break;
851 case 0x01: /* Arbitration lost */
852 dev_err(dev->dev, "Arbitration lost\n");
853 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
854 break;
855 case 0x02: /* No acknowledgement */
856 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
857 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
858 break;
859 case 0x03: /* Register access ready */
860 omap_i2c_complete_cmd(dev, 0);
861 break;
862 case 0x04: /* Receive data ready */
863 if (dev->buf_len) {
864 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
865 *dev->buf++ = w;
866 dev->buf_len--;
867 if (dev->buf_len) {
868 *dev->buf++ = w >> 8;
869 dev->buf_len--;
870 }
871 } else
872 dev_err(dev->dev, "RRDY IRQ while no data requested\n");
873 break;
874 case 0x05: /* Transmit data ready */
875 if (dev->buf_len) {
876 w = *dev->buf++;
877 dev->buf_len--;
878 if (dev->buf_len) {
879 w |= *dev->buf++ << 8;
880 dev->buf_len--;
881 }
882 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
883 } else
884 dev_err(dev->dev, "XRDY IRQ while no data to send\n");
885 break;
886 default:
887 return IRQ_NONE;
888 }
889
890 return IRQ_HANDLED;
891}
43469d8e 892#else
4e80f727 893#define omap_i2c_omap1_isr NULL
43469d8e 894#endif
010d442c 895
2dd151ab 896/*
c8db38f0 897 * OMAP3430 Errata i462: When an XRDY/XDR is hit, wait for XUDF before writing
2dd151ab
AS		 898 * data to DATA_REG. Otherwise some data bytes can be lost while transferring
899 * them from the memory to the I2C interface.
900 */
4151e741 901static int errata_omap3_i462(struct omap_i2c_dev *dev)
2dd151ab 902{
e9f59b9c 903 unsigned long timeout = 10000;
4151e741 904 u16 stat;
e9f59b9c 905
4151e741
FB		 906 do {
907 stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
908 if (stat & OMAP_I2C_STAT_XUDF)
909 break;
910
911 if (stat & (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) {
540a4790 912 omap_i2c_ack_stat(dev, (OMAP_I2C_STAT_XRDY |
2dd151ab 913 OMAP_I2C_STAT_XDR));
b07be0f3
FB		 914 if (stat & OMAP_I2C_STAT_NACK) {
915 dev->cmd_err |= OMAP_I2C_STAT_NACK;
916 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_NACK);
917 }
918
919 if (stat & OMAP_I2C_STAT_AL) {
920 dev_err(dev->dev, "Arbitration lost\n");
921 dev->cmd_err |= OMAP_I2C_STAT_AL;
2c5de558 922 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_AL);
b07be0f3
FB		 923 }
924
4151e741 925 return -EIO;
2dd151ab 926 }
e9f59b9c 927
2dd151ab 928 cpu_relax();
4151e741 929 } while (--timeout);
2dd151ab 930
e9f59b9c
AS		 931 if (!timeout) {
932 dev_err(dev->dev, "timeout waiting on XUDF bit\n");
933 return 0;
934 }
935
2dd151ab
AS		 936 return 0;
937}
938
3312d25e
FB		 939static void omap_i2c_receive_data(struct omap_i2c_dev *dev, u8 num_bytes,
940 bool is_rdr)
941{
942 u16 w;
943
944 while (num_bytes--) {
3312d25e
FB		 945 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
946 *dev->buf++ = w;
947 dev->buf_len--;
948
949 /*
950 * Data reg in 2430, omap3 and
951 * omap4 is 8 bit wide
952 */
953 if (dev->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) {
dd74548d
FB		 954 *dev->buf++ = w >> 8;
955 dev->buf_len--;
3312d25e
FB		 956 }
957 }
958}
959
960static int omap_i2c_transmit_data(struct omap_i2c_dev *dev, u8 num_bytes,
961 bool is_xdr)
962{
963 u16 w;
964
965 while (num_bytes--) {
3312d25e
FB		 966 w = *dev->buf++;
967 dev->buf_len--;
968
969 /*
970 * Data reg in 2430, omap3 and
971 * omap4 is 8 bit wide
972 */
973 if (dev->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) {
dd74548d
FB		 974 w |= *dev->buf++ << 8;
975 dev->buf_len--;
3312d25e
FB		 976 }
977
978 if (dev->errata & I2C_OMAP_ERRATA_I462) {
979 int ret;
980
981 ret = errata_omap3_i462(dev);
982 if (ret < 0)
983 return ret;
984 }
985
986 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
987 }
988
989 return 0;
990}
991
010d442c 992static irqreturn_t
3b2f8f82 993omap_i2c_isr(int irq, void *dev_id)
010d442c
KS		 994{
995 struct omap_i2c_dev *dev = dev_id;
3b2f8f82
FB		 996 irqreturn_t ret = IRQ_HANDLED;
997 u16 mask;
998 u16 stat;
999
1000 spin_lock(&dev->lock);
1001 mask = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
1002 stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
1003
1004 if (stat & mask)
1005 ret = IRQ_WAKE_THREAD;
1006
1007 spin_unlock(&dev->lock);
1008
1009 return ret;
1010}
1011
010d442c 1012static irqreturn_t
3b2f8f82 1013omap_i2c_isr_thread(int this_irq, void *dev_id)
010d442c
KS		 1014{
1015 struct omap_i2c_dev *dev = dev_id;
3b2f8f82 1016 unsigned long flags;
010d442c 1017 u16 bits;
3312d25e 1018 u16 stat;
66b92988 1019 int err = 0, count = 0;
010d442c 1020
3b2f8f82 1021 spin_lock_irqsave(&dev->lock, flags);
66b92988
FB		 1022 do {
1023 bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
1024 stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
1025 stat &= bits;
1026
079d8af2
FB		 1027 /* If we're in receiver mode, ignore XDR/XRDY */
1028 if (dev->receiver)
1029 stat &= ~(OMAP_I2C_STAT_XDR | OMAP_I2C_STAT_XRDY);
1030 else
1031 stat &= ~(OMAP_I2C_STAT_RDR | OMAP_I2C_STAT_RRDY);
010d442c 1032
66b92988
FB		 1033 if (!stat) {
1034 /* my work here is done */
0bdfe0cb 1035 goto out;
66b92988 1036 }
f08ac4e7 1037
010d442c
KS		 1038 dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat);
1039 if (count++ == 100) {
1040 dev_warn(dev->dev, "Too much work in one IRQ\n");
1041 break;
1042 }
1043
1d7afc95 1044 if (stat & OMAP_I2C_STAT_NACK) {
b6ee52c3 1045 err |= OMAP_I2C_STAT_NACK;
1d7afc95 1046 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_NACK);
1d7afc95 1047 }
78e1cf42 1048
b6ee52c3
NM		 1049 if (stat & OMAP_I2C_STAT_AL) {
1050 dev_err(dev->dev, "Arbitration lost\n");
1051 err |= OMAP_I2C_STAT_AL;
1d7afc95 1052 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_AL);
b6ee52c3 1053 }
c55edb99 1054
a5a595cc 1055 /*
cb527ede 1056 * ProDB0017052: Clear ARDY bit twice
a5a595cc 1057 */
4cdbf7d3
TK		 1058 if (stat & OMAP_I2C_STAT_ARDY)
1059 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_ARDY);
1060
b6ee52c3 1061 if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
04c688dd 1062 OMAP_I2C_STAT_AL)) {
540a4790
FB		 1063 omap_i2c_ack_stat(dev, (OMAP_I2C_STAT_RRDY |
1064 OMAP_I2C_STAT_RDR |
1065 OMAP_I2C_STAT_XRDY |
1066 OMAP_I2C_STAT_XDR |
1067 OMAP_I2C_STAT_ARDY));
0bdfe0cb 1068 break;
04c688dd 1069 }
c55edb99 1070
6d9939f6 1071 if (stat & OMAP_I2C_STAT_RDR) {
b6ee52c3 1072 u8 num_bytes = 1;
f3083d92 1073
6d9939f6
FB		 1074 if (dev->fifo_size)
1075 num_bytes = dev->buf_len;
1076
ccfc8663 1077 if (dev->errata & I2C_OMAP_ERRATA_I207) {
f3083d92 1078 i2c_omap_errata_i207(dev, stat);
ccfc8663
AK		 1079 num_bytes = (omap_i2c_read_reg(dev,
1080 OMAP_I2C_BUFSTAT_REG) >> 8) & 0x3F;
1081 }
f3083d92 1082
ccfc8663 1083 omap_i2c_receive_data(dev, num_bytes, true);
6d9939f6 1084 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
9eb13cf3 1085 continue;
6d9939f6
FB		 1086 }
1087
1088 if (stat & OMAP_I2C_STAT_RRDY) {
1089 u8 num_bytes = 1;
1090
dd74548d
FB		 1091 if (dev->threshold)
1092 num_bytes = dev->threshold;
6d9939f6 1093
3312d25e 1094 omap_i2c_receive_data(dev, num_bytes, false);
6d9939f6 1095 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RRDY);
010d442c
KS		 1096 continue;
1097 }
c55edb99 1098
6d9939f6 1099 if (stat & OMAP_I2C_STAT_XDR) {
b6ee52c3 1100 u8 num_bytes = 1;
3312d25e 1101 int ret;
6d9939f6
FB		 1102
1103 if (dev->fifo_size)
1104 num_bytes = dev->buf_len;
1105
3312d25e 1106 ret = omap_i2c_transmit_data(dev, num_bytes, true);
3312d25e 1107 if (ret < 0)
0bdfe0cb 1108 break;
6d9939f6
FB		 1109
1110 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XDR);
9eb13cf3 1111 continue;
6d9939f6
FB		 1112 }
1113
1114 if (stat & OMAP_I2C_STAT_XRDY) {
1115 u8 num_bytes = 1;
3312d25e 1116 int ret;
6d9939f6 1117
dd74548d
FB		 1118 if (dev->threshold)
1119 num_bytes = dev->threshold;
6d9939f6 1120
3312d25e 1121 ret = omap_i2c_transmit_data(dev, num_bytes, false);
3312d25e 1122 if (ret < 0)
0bdfe0cb 1123 break;
6d9939f6
FB		 1124
1125 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XRDY);
010d442c
KS		 1126 continue;
1127 }
c55edb99 1128
010d442c
KS		 1129 if (stat & OMAP_I2C_STAT_ROVR) {
1130 dev_err(dev->dev, "Receive overrun\n");
1d7afc95
FB		 1131 err |= OMAP_I2C_STAT_ROVR;
1132 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_ROVR);
0bdfe0cb 1133 break;
010d442c 1134 }
c55edb99 1135
010d442c 1136 if (stat & OMAP_I2C_STAT_XUDF) {
b6ee52c3 1137 dev_err(dev->dev, "Transmit underflow\n");
1d7afc95
FB		 1138 err |= OMAP_I2C_STAT_XUDF;
1139 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XUDF);
0bdfe0cb 1140 break;
010d442c 1141 }
66b92988 1142 } while (stat);
010d442c 1143
4a7ec4ed 1144 omap_i2c_complete_cmd(dev, err);
0bdfe0cb
FB		 1145
1146out:
3b2f8f82 1147 spin_unlock_irqrestore(&dev->lock, flags);
010d442c 1148
6a85ced2 1149 return IRQ_HANDLED;
010d442c
KS		 1150}
1151
8f9082c5 1152static const struct i2c_algorithm omap_i2c_algo = {
010d442c
KS		 1153 .master_xfer = omap_i2c_xfer,
1154 .functionality = omap_i2c_func,
1155};
1156
6145197b 1157#ifdef CONFIG_OF
4c624840
TL		 1158static struct omap_i2c_bus_platform_data omap2420_pdata = {
1159 .rev = OMAP_I2C_IP_VERSION_1,
1160 .flags = OMAP_I2C_FLAG_NO_FIFO |
1161 OMAP_I2C_FLAG_SIMPLE_CLOCK |
1162 OMAP_I2C_FLAG_16BIT_DATA_REG |
1163 OMAP_I2C_FLAG_BUS_SHIFT_2,
1164};
1165
1166static struct omap_i2c_bus_platform_data omap2430_pdata = {
1167 .rev = OMAP_I2C_IP_VERSION_1,
1168 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2 |
1169 OMAP_I2C_FLAG_FORCE_19200_INT_CLK,
1170};
1171
6145197b
BC		 1172static struct omap_i2c_bus_platform_data omap3_pdata = {
1173 .rev = OMAP_I2C_IP_VERSION_1,
972deb4f 1174 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2,
6145197b
BC		 1175};
1176
1177static struct omap_i2c_bus_platform_data omap4_pdata = {
1178 .rev = OMAP_I2C_IP_VERSION_2,
1179};
1180
1181static const struct of_device_id omap_i2c_of_match[] = {
1182 {
1183 .compatible = "ti,omap4-i2c",
1184 .data = &omap4_pdata,
1185 },
1186 {
1187 .compatible = "ti,omap3-i2c",
1188 .data = &omap3_pdata,
1189 },
4c624840
TL		 1190 {
1191 .compatible = "ti,omap2430-i2c",
1192 .data = &omap2430_pdata,
1193 },
1194 {
1195 .compatible = "ti,omap2420-i2c",
1196 .data = &omap2420_pdata,
1197 },
6145197b
BC		 1198 { },
1199};
1200MODULE_DEVICE_TABLE(of, omap_i2c_of_match);
1201#endif
1202
47dcd016
S		 1203#define OMAP_I2C_SCHEME(rev) ((rev & 0xc000) >> 14)
1204
1205#define OMAP_I2C_REV_SCHEME_0_MAJOR(rev) (rev >> 4)
1206#define OMAP_I2C_REV_SCHEME_0_MINOR(rev) (rev & 0xf)
1207
1208#define OMAP_I2C_REV_SCHEME_1_MAJOR(rev) ((rev & 0x0700) >> 7)
1209#define OMAP_I2C_REV_SCHEME_1_MINOR(rev) (rev & 0x1f)
1210#define OMAP_I2C_SCHEME_0 0
1211#define OMAP_I2C_SCHEME_1 1
1212
0b255e92 1213static int
010d442c
KS		 1214omap_i2c_probe(struct platform_device *pdev)
1215{
1216 struct omap_i2c_dev *dev;
1217 struct i2c_adapter *adap;
ac79e4b2 1218 struct resource *mem;
c4dba011 1219 const struct omap_i2c_bus_platform_data *pdata =
6d4028c6 1220 dev_get_platdata(&pdev->dev);
6145197b
BC		 1221 struct device_node *node = pdev->dev.of_node;
1222 const struct of_device_id *match;
ac79e4b2 1223 int irq;
010d442c 1224 int r;
47dcd016 1225 u32 rev;
4368de19 1226 u16 minor, major;
010d442c 1227
ac79e4b2
FB		 1228 irq = platform_get_irq(pdev, 0);
1229 if (irq < 0) {
010d442c 1230 dev_err(&pdev->dev, "no irq resource?\n");
ac79e4b2 1231 return irq;
010d442c
KS		 1232 }
1233
d9ebd04d 1234 dev = devm_kzalloc(&pdev->dev, sizeof(struct omap_i2c_dev), GFP_KERNEL);
46797a2a 1235 if (!dev)
d9ebd04d 1236 return -ENOMEM;
010d442c 1237
3cc2d009 1238 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
84dbf809
TR		 1239 dev->base = devm_ioremap_resource(&pdev->dev, mem);
1240 if (IS_ERR(dev->base))
1241 return PTR_ERR(dev->base);
010d442c 1242
6c5aa407 1243 match = of_match_device(of_match_ptr(omap_i2c_of_match), &pdev->dev);
6145197b
BC		 1244 if (match) {
1245 u32 freq = 100000; /* default to 100000 Hz */
1246
1247 pdata = match->data;
6145197b
BC		 1248 dev->flags = pdata->flags;
1249
1250 of_property_read_u32(node, "clock-frequency", &freq);
1251 /* convert DT freq value in Hz into kHz for speed */
1252 dev->speed = freq / 1000;
1253 } else if (pdata != NULL) {
1254 dev->speed = pdata->clkrate;
1255 dev->flags = pdata->flags;
49839dc9 1256 dev->set_mpu_wkup_lat = pdata->set_mpu_wkup_lat;
20c9d2c4 1257 }
4574eb68 1258
010d442c 1259 dev->dev = &pdev->dev;
ac79e4b2 1260 dev->irq = irq;
55c381e4 1261
3b2f8f82 1262 spin_lock_init(&dev->lock);
55c381e4 1263
010d442c 1264 platform_set_drvdata(pdev, dev);
0e33bbb2 1265 init_completion(&dev->cmd_complete);
010d442c 1266
6145197b 1267 dev->reg_shift = (dev->flags >> OMAP_I2C_FLAG_BUS_SHIFT__SHIFT) & 3;
7c6bd201 1268
7f4b08ee 1269 pm_runtime_enable(dev->dev);
6d8451d5
FB		 1270 pm_runtime_set_autosuspend_delay(dev->dev, OMAP_I2C_PM_TIMEOUT);
1271 pm_runtime_use_autosuspend(dev->dev);
1272
3b0fb97c 1273 r = pm_runtime_get_sync(dev->dev);
ff370257 1274 if (r < 0)
3b0fb97c 1275 goto err_free_mem;
010d442c 1276
47dcd016
S		 1277 /*
1278 * Read the Rev hi bit-[15:14] ie scheme this is 1 indicates ver2.
1279 * On omap1/3/2 Offset 4 is IE Reg the bit [15:14] is 0 at reset.
1280 * Also since the omap_i2c_read_reg uses reg_map_ip_* a
40b13ca8 1281 * readw_relaxed is done.
47dcd016 1282 */
40b13ca8 1283 rev = readw_relaxed(dev->base + 0x04);
47dcd016 1284
4368de19
OD		 1285 dev->scheme = OMAP_I2C_SCHEME(rev);
1286 switch (dev->scheme) {
47dcd016
S		 1287 case OMAP_I2C_SCHEME_0:
1288 dev->regs = (u8 *)reg_map_ip_v1;
1289 dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG);
1290 minor = OMAP_I2C_REV_SCHEME_0_MAJOR(dev->rev);
1291 major = OMAP_I2C_REV_SCHEME_0_MAJOR(dev->rev);
1292 break;
1293 case OMAP_I2C_SCHEME_1:
1294 /* FALLTHROUGH */
1295 default:
1296 dev->regs = (u8 *)reg_map_ip_v2;
1297 rev = (rev << 16) |
1298 omap_i2c_read_reg(dev, OMAP_I2C_IP_V2_REVNB_LO);
1299 minor = OMAP_I2C_REV_SCHEME_1_MINOR(rev);
1300 major = OMAP_I2C_REV_SCHEME_1_MAJOR(rev);
1301 dev->rev = rev;
1302 }
010d442c 1303
9aa8ec67
TK		 1304 dev->errata = 0;
1305
a748021c
S		 1306 if (dev->rev >= OMAP_I2C_REV_ON_2430 &&
1307 dev->rev < OMAP_I2C_REV_ON_4430_PLUS)
9aa8ec67
TK		 1308 dev->errata |= I2C_OMAP_ERRATA_I207;
1309
f518b482 1310 if (dev->rev <= OMAP_I2C_REV_ON_3430_3530)
c8db38f0 1311 dev->errata |= I2C_OMAP_ERRATA_I462;
8a9d97d3 1312
6145197b 1313 if (!(dev->flags & OMAP_I2C_FLAG_NO_FIFO)) {
b6ee52c3
NM		 1314 u16 s;
1315
1316 /* Set up the fifo size - Get total size */
1317 s = (omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3;
1318 dev->fifo_size = 0x8 << s;
1319
1320 /*
1321 * Set up notification threshold as half the total available
1322 * size. This is to ensure that we can handle the status on int
1323 * call back latencies.
1324 */
1d5a34fe
S		 1325
1326 dev->fifo_size = (dev->fifo_size / 2);
1327
47dcd016 1328 if (dev->rev < OMAP_I2C_REV_ON_3630)
f38e66e0 1329 dev->b_hw = 1; /* Enable hardware fixes */
1d5a34fe 1330
20c9d2c4 1331 /* calculate wakeup latency constraint for MPU */
49839dc9
PW		 1332 if (dev->set_mpu_wkup_lat != NULL)
1333 dev->latency = (1000000 * dev->fifo_size) /
1334 (1000 * dev->speed / 8);
b6ee52c3
NM		 1335 }
1336
010d442c
KS		 1337 /* reset ASAP, clearing any IRQs */
1338 omap_i2c_init(dev);
1339
3b2f8f82
FB		 1340 if (dev->rev < OMAP_I2C_OMAP1_REV_2)
1341 r = devm_request_irq(&pdev->dev, dev->irq, omap_i2c_omap1_isr,
1342 IRQF_NO_SUSPEND, pdev->name, dev);
1343 else
1344 r = devm_request_threaded_irq(&pdev->dev, dev->irq,
1345 omap_i2c_isr, omap_i2c_isr_thread,
1346 IRQF_NO_SUSPEND | IRQF_ONESHOT,
1347 pdev->name, dev);
010d442c
KS		 1348
1349 if (r) {
1350 dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
1351 goto err_unuse_clocks;
1352 }
9c76b878 1353
010d442c
KS		 1354 adap = &dev->adapter;
1355 i2c_set_adapdata(adap, dev);
1356 adap->owner = THIS_MODULE;
cfac71d9 1357 adap->class = I2C_CLASS_DEPRECATED;
783fd6fa 1358 strlcpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
010d442c
KS		 1359 adap->algo = &omap_i2c_algo;
1360 adap->dev.parent = &pdev->dev;
6145197b 1361 adap->dev.of_node = pdev->dev.of_node;
010d442c
KS		 1362
1363 /* i2c device drivers may be active on return from add_adapter() */
7c175499
DB		 1364 adap->nr = pdev->id;
1365 r = i2c_add_numbered_adapter(adap);
010d442c
KS		 1366 if (r) {
1367 dev_err(dev->dev, "failure adding adapter\n");
d9ebd04d 1368 goto err_unuse_clocks;
010d442c
KS		 1369 }
1370
cd10c74a
S		 1371 dev_info(dev->dev, "bus %d rev%d.%d at %d kHz\n", adap->nr,
1372 major, minor, dev->speed);
c5d3cd6d 1373
6d8451d5
FB		 1374 pm_runtime_mark_last_busy(dev->dev);
1375 pm_runtime_put_autosuspend(dev->dev);
62ff2c2b 1376
010d442c
KS		 1377 return 0;
1378
010d442c 1379err_unuse_clocks:
3e39752d 1380 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
fab67afb 1381 pm_runtime_put(dev->dev);
24740516 1382 pm_runtime_disable(&pdev->dev);
010d442c 1383err_free_mem:
010d442c
KS		 1384
1385 return r;
1386}
1387
0b255e92 1388static int omap_i2c_remove(struct platform_device *pdev)
010d442c
KS		 1389{
1390 struct omap_i2c_dev *dev = platform_get_drvdata(pdev);
3b0fb97c 1391 int ret;
010d442c 1392
010d442c 1393 i2c_del_adapter(&dev->adapter);
3b0fb97c 1394 ret = pm_runtime_get_sync(&pdev->dev);
ff370257 1395 if (ret < 0)
3b0fb97c
S		 1396 return ret;
1397
010d442c 1398 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
0861f430 1399 pm_runtime_put(&pdev->dev);
24740516 1400 pm_runtime_disable(&pdev->dev);
010d442c
KS		 1401 return 0;
1402}
1403
5692d2a2 1404#ifdef CONFIG_PM
fab67afb
KH		 1405static int omap_i2c_runtime_suspend(struct device *dev)
1406{
1407 struct platform_device *pdev = to_platform_device(dev);
1408 struct omap_i2c_dev *_dev = platform_get_drvdata(pdev);
3dae3efb
S		 1409
1410 _dev->iestate = omap_i2c_read_reg(_dev, OMAP_I2C_IE_REG);
bd16c82f 1411
4368de19
OD		 1412 if (_dev->scheme == OMAP_I2C_SCHEME_0)
1413 omap_i2c_write_reg(_dev, OMAP_I2C_IE_REG, 0);
1414 else
1415 omap_i2c_write_reg(_dev, OMAP_I2C_IP_V2_IRQENABLE_CLR,
1416 OMAP_I2C_IP_V2_INTERRUPTS_MASK);
fab67afb 1417
3dae3efb 1418 if (_dev->rev < OMAP_I2C_OMAP1_REV_2) {
27e0fbef 1419 omap_i2c_read_reg(_dev, OMAP_I2C_IV_REG); /* Read clears */
3dae3efb
S		 1420 } else {
1421 omap_i2c_write_reg(_dev, OMAP_I2C_STAT_REG, _dev->iestate);
fab67afb 1422
3dae3efb
S		 1423 /* Flush posted write */
1424 omap_i2c_read_reg(_dev, OMAP_I2C_STAT_REG);
1425 }
fab67afb 1426
096ea30c
PH		 1427 pinctrl_pm_select_sleep_state(dev);
1428
fab67afb
KH		 1429 return 0;
1430}
1431
1432static int omap_i2c_runtime_resume(struct device *dev)
1433{
1434 struct platform_device *pdev = to_platform_device(dev);
1435 struct omap_i2c_dev *_dev = platform_get_drvdata(pdev);
096ea30c
PH		 1436
1437 pinctrl_pm_select_default_state(dev);
fab67afb 1438
47dcd016
S		 1439 if (!_dev->regs)
1440 return 0;
1441
554c9674 1442 __omap_i2c_init(_dev);
fab67afb
KH		 1443
1444 return 0;
1445}
1446
1447static struct dev_pm_ops omap_i2c_pm_ops = {
5692d2a2
S		 1448 SET_RUNTIME_PM_OPS(omap_i2c_runtime_suspend,
1449 omap_i2c_runtime_resume, NULL)
fab67afb
KH		 1450};
1451#define OMAP_I2C_PM_OPS (&omap_i2c_pm_ops)
1452#else
1453#define OMAP_I2C_PM_OPS NULL
5692d2a2 1454#endif /* CONFIG_PM */
fab67afb 1455
010d442c
KS		 1456static struct platform_driver omap_i2c_driver = {
1457 .probe = omap_i2c_probe,
0b255e92 1458 .remove = omap_i2c_remove,
010d442c 1459 .driver = {
f7bb0d9a 1460 .name = "omap_i2c",
fab67afb 1461 .pm = OMAP_I2C_PM_OPS,
6145197b 1462 .of_match_table = of_match_ptr(omap_i2c_of_match),
010d442c
KS		 1463 },
1464};
1465
1466/* I2C may be needed to bring up other drivers */
1467static int __init
1468omap_i2c_init_driver(void)
1469{
1470 return platform_driver_register(&omap_i2c_driver);
1471}
1472subsys_initcall(omap_i2c_init_driver);
1473
1474static void __exit omap_i2c_exit_driver(void)
1475{
1476 platform_driver_unregister(&omap_i2c_driver);
1477}
1478module_exit(omap_i2c_exit_driver);
1479
1480MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
1481MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
1482MODULE_LICENSE("GPL");
f7bb0d9a 1483MODULE_ALIAS("platform:omap_i2c");
Linux kernel - Deliverables
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