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010d442c KS |
1 | /* |
2 | * TI OMAP I2C master mode driver | |
3 | * | |
4 | * Copyright (C) 2003 MontaVista Software, Inc. | |
010d442c | 5 | * Copyright (C) 2005 Nokia Corporation |
c1a473bd | 6 | * Copyright (C) 2004 - 2007 Texas Instruments. |
010d442c | 7 | * |
c1a473bd TL |
8 | * Originally written by MontaVista Software, Inc. |
9 | * Additional contributions by: | |
10 | * Tony Lindgren <tony@atomide.com> | |
11 | * Imre Deak <imre.deak@nokia.com> | |
12 | * Juha Yrjölä <juha.yrjola@solidboot.com> | |
13 | * Syed Khasim <x0khasim@ti.com> | |
14 | * Nishant Menon <nm@ti.com> | |
010d442c KS |
15 | * |
16 | * This program is free software; you can redistribute it and/or modify | |
17 | * it under the terms of the GNU General Public License as published by | |
18 | * the Free Software Foundation; either version 2 of the License, or | |
19 | * (at your option) any later version. | |
20 | * | |
21 | * This program is distributed in the hope that it will be useful, | |
22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
24 | * GNU General Public License for more details. | |
25 | * | |
26 | * You should have received a copy of the GNU General Public License | |
27 | * along with this program; if not, write to the Free Software | |
28 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
29 | */ | |
30 | ||
31 | #include <linux/module.h> | |
32 | #include <linux/delay.h> | |
33 | #include <linux/i2c.h> | |
34 | #include <linux/err.h> | |
35 | #include <linux/interrupt.h> | |
36 | #include <linux/completion.h> | |
37 | #include <linux/platform_device.h> | |
38 | #include <linux/clk.h> | |
c1a473bd | 39 | #include <linux/io.h> |
5a0e3ad6 | 40 | #include <linux/slab.h> |
010d442c | 41 | |
9c76b878 PW |
42 | /* I2C controller revisions */ |
43 | #define OMAP_I2C_REV_2 0x20 | |
44 | ||
45 | /* I2C controller revisions present on specific hardware */ | |
46 | #define OMAP_I2C_REV_ON_2430 0x36 | |
47 | #define OMAP_I2C_REV_ON_3430 0x3C | |
48 | ||
010d442c KS |
49 | /* timeout waiting for the controller to respond */ |
50 | #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000)) | |
51 | ||
52 | #define OMAP_I2C_REV_REG 0x00 | |
d84d3ea3 CM |
53 | #define OMAP_I2C_IE_REG 0x01 |
54 | #define OMAP_I2C_STAT_REG 0x02 | |
55 | #define OMAP_I2C_IV_REG 0x03 | |
5043e9e7 | 56 | /* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */ |
d84d3ea3 CM |
57 | #define OMAP_I2C_WE_REG 0x03 |
58 | #define OMAP_I2C_SYSS_REG 0x04 | |
59 | #define OMAP_I2C_BUF_REG 0x05 | |
60 | #define OMAP_I2C_CNT_REG 0x06 | |
61 | #define OMAP_I2C_DATA_REG 0x07 | |
62 | #define OMAP_I2C_SYSC_REG 0x08 | |
63 | #define OMAP_I2C_CON_REG 0x09 | |
64 | #define OMAP_I2C_OA_REG 0x0a | |
65 | #define OMAP_I2C_SA_REG 0x0b | |
66 | #define OMAP_I2C_PSC_REG 0x0c | |
67 | #define OMAP_I2C_SCLL_REG 0x0d | |
68 | #define OMAP_I2C_SCLH_REG 0x0e | |
69 | #define OMAP_I2C_SYSTEST_REG 0x0f | |
70 | #define OMAP_I2C_BUFSTAT_REG 0x10 | |
010d442c KS |
71 | |
72 | /* I2C Interrupt Enable Register (OMAP_I2C_IE): */ | |
b6ee52c3 NM |
73 | #define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */ |
74 | #define OMAP_I2C_IE_RDR (1 << 13) /* RX Buffer drain int enable */ | |
010d442c KS |
75 | #define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */ |
76 | #define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */ | |
77 | #define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */ | |
78 | #define OMAP_I2C_IE_NACK (1 << 1) /* No ack interrupt enable */ | |
79 | #define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */ | |
80 | ||
81 | /* I2C Status Register (OMAP_I2C_STAT): */ | |
b6ee52c3 NM |
82 | #define OMAP_I2C_STAT_XDR (1 << 14) /* TX Buffer draining */ |
83 | #define OMAP_I2C_STAT_RDR (1 << 13) /* RX Buffer draining */ | |
010d442c KS |
84 | #define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */ |
85 | #define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */ | |
86 | #define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ | |
87 | #define OMAP_I2C_STAT_AAS (1 << 9) /* Address as slave */ | |
88 | #define OMAP_I2C_STAT_AD0 (1 << 8) /* Address zero */ | |
89 | #define OMAP_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ | |
90 | #define OMAP_I2C_STAT_RRDY (1 << 3) /* Receive data ready */ | |
91 | #define OMAP_I2C_STAT_ARDY (1 << 2) /* Register access ready */ | |
92 | #define OMAP_I2C_STAT_NACK (1 << 1) /* No ack interrupt enable */ | |
93 | #define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost int ena */ | |
94 | ||
5043e9e7 KJ |
95 | /* I2C WE wakeup enable register */ |
96 | #define OMAP_I2C_WE_XDR_WE (1 << 14) /* TX drain wakup */ | |
97 | #define OMAP_I2C_WE_RDR_WE (1 << 13) /* RX drain wakeup */ | |
98 | #define OMAP_I2C_WE_AAS_WE (1 << 9) /* Address as slave wakeup*/ | |
99 | #define OMAP_I2C_WE_BF_WE (1 << 8) /* Bus free wakeup */ | |
100 | #define OMAP_I2C_WE_STC_WE (1 << 6) /* Start condition wakeup */ | |
101 | #define OMAP_I2C_WE_GC_WE (1 << 5) /* General call wakeup */ | |
102 | #define OMAP_I2C_WE_DRDY_WE (1 << 3) /* TX/RX data ready wakeup */ | |
103 | #define OMAP_I2C_WE_ARDY_WE (1 << 2) /* Reg access ready wakeup */ | |
104 | #define OMAP_I2C_WE_NACK_WE (1 << 1) /* No acknowledgment wakeup */ | |
105 | #define OMAP_I2C_WE_AL_WE (1 << 0) /* Arbitration lost wakeup */ | |
106 | ||
107 | #define OMAP_I2C_WE_ALL (OMAP_I2C_WE_XDR_WE | OMAP_I2C_WE_RDR_WE | \ | |
108 | OMAP_I2C_WE_AAS_WE | OMAP_I2C_WE_BF_WE | \ | |
109 | OMAP_I2C_WE_STC_WE | OMAP_I2C_WE_GC_WE | \ | |
110 | OMAP_I2C_WE_DRDY_WE | OMAP_I2C_WE_ARDY_WE | \ | |
111 | OMAP_I2C_WE_NACK_WE | OMAP_I2C_WE_AL_WE) | |
112 | ||
010d442c KS |
113 | /* I2C Buffer Configuration Register (OMAP_I2C_BUF): */ |
114 | #define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */ | |
b6ee52c3 | 115 | #define OMAP_I2C_BUF_RXFIF_CLR (1 << 14) /* RX FIFO Clear */ |
010d442c | 116 | #define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */ |
b6ee52c3 | 117 | #define OMAP_I2C_BUF_TXFIF_CLR (1 << 6) /* TX FIFO Clear */ |
010d442c KS |
118 | |
119 | /* I2C Configuration Register (OMAP_I2C_CON): */ | |
120 | #define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */ | |
121 | #define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */ | |
b6ee52c3 | 122 | #define OMAP_I2C_CON_OPMODE_HS (1 << 12) /* High Speed support */ |
010d442c KS |
123 | #define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */ |
124 | #define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */ | |
125 | #define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */ | |
126 | #define OMAP_I2C_CON_XA (1 << 8) /* Expand address */ | |
127 | #define OMAP_I2C_CON_RM (1 << 2) /* Repeat mode (master only) */ | |
128 | #define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */ | |
129 | #define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */ | |
130 | ||
4574eb68 SMK |
131 | /* I2C SCL time value when Master */ |
132 | #define OMAP_I2C_SCLL_HSSCLL 8 | |
133 | #define OMAP_I2C_SCLH_HSSCLH 8 | |
134 | ||
010d442c KS |
135 | /* I2C System Test Register (OMAP_I2C_SYSTEST): */ |
136 | #ifdef DEBUG | |
137 | #define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */ | |
138 | #define OMAP_I2C_SYSTEST_FREE (1 << 14) /* Free running mode */ | |
139 | #define OMAP_I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */ | |
140 | #define OMAP_I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */ | |
141 | #define OMAP_I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense in */ | |
142 | #define OMAP_I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive out */ | |
143 | #define OMAP_I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense in */ | |
144 | #define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */ | |
145 | #endif | |
146 | ||
fdd07fe6 PW |
147 | /* OCP_SYSSTATUS bit definitions */ |
148 | #define SYSS_RESETDONE_MASK (1 << 0) | |
149 | ||
150 | /* OCP_SYSCONFIG bit definitions */ | |
151 | #define SYSC_CLOCKACTIVITY_MASK (0x3 << 8) | |
152 | #define SYSC_SIDLEMODE_MASK (0x3 << 3) | |
153 | #define SYSC_ENAWAKEUP_MASK (1 << 2) | |
154 | #define SYSC_SOFTRESET_MASK (1 << 1) | |
155 | #define SYSC_AUTOIDLE_MASK (1 << 0) | |
156 | ||
157 | #define SYSC_IDLEMODE_SMART 0x2 | |
158 | #define SYSC_CLOCKACTIVITY_FCLK 0x2 | |
010d442c | 159 | |
010d442c | 160 | |
010d442c KS |
161 | struct omap_i2c_dev { |
162 | struct device *dev; | |
163 | void __iomem *base; /* virtual */ | |
164 | int irq; | |
d84d3ea3 | 165 | int reg_shift; /* bit shift for I2C register addresses */ |
010d442c KS |
166 | struct clk *iclk; /* Interface clock */ |
167 | struct clk *fclk; /* Functional clock */ | |
168 | struct completion cmd_complete; | |
169 | struct resource *ioarea; | |
4574eb68 | 170 | u32 speed; /* Speed of bus in Khz */ |
010d442c KS |
171 | u16 cmd_err; |
172 | u8 *buf; | |
173 | size_t buf_len; | |
174 | struct i2c_adapter adapter; | |
b6ee52c3 NM |
175 | u8 fifo_size; /* use as flag and value |
176 | * fifo_size==0 implies no fifo | |
177 | * if set, should be trsh+1 | |
178 | */ | |
9c76b878 | 179 | u8 rev; |
b6ee52c3 | 180 | unsigned b_hw:1; /* bad h/w fixes */ |
f08ac4e7 TL |
181 | unsigned idle:1; |
182 | u16 iestate; /* Saved interrupt register */ | |
ef871432 RN |
183 | u16 pscstate; |
184 | u16 scllstate; | |
185 | u16 sclhstate; | |
186 | u16 bufstate; | |
187 | u16 syscstate; | |
188 | u16 westate; | |
010d442c KS |
189 | }; |
190 | ||
191 | static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev, | |
192 | int reg, u16 val) | |
193 | { | |
d84d3ea3 | 194 | __raw_writew(val, i2c_dev->base + (reg << i2c_dev->reg_shift)); |
010d442c KS |
195 | } |
196 | ||
197 | static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg) | |
198 | { | |
d84d3ea3 | 199 | return __raw_readw(i2c_dev->base + (reg << i2c_dev->reg_shift)); |
010d442c KS |
200 | } |
201 | ||
510be9c9 | 202 | static int __init omap_i2c_get_clocks(struct omap_i2c_dev *dev) |
010d442c | 203 | { |
5fe23380 RK |
204 | int ret; |
205 | ||
206 | dev->iclk = clk_get(dev->dev, "ick"); | |
207 | if (IS_ERR(dev->iclk)) { | |
208 | ret = PTR_ERR(dev->iclk); | |
209 | dev->iclk = NULL; | |
210 | return ret; | |
010d442c KS |
211 | } |
212 | ||
1d14de08 | 213 | dev->fclk = clk_get(dev->dev, "fck"); |
010d442c | 214 | if (IS_ERR(dev->fclk)) { |
5fe23380 | 215 | ret = PTR_ERR(dev->fclk); |
010d442c KS |
216 | if (dev->iclk != NULL) { |
217 | clk_put(dev->iclk); | |
218 | dev->iclk = NULL; | |
219 | } | |
220 | dev->fclk = NULL; | |
5fe23380 | 221 | return ret; |
010d442c KS |
222 | } |
223 | ||
224 | return 0; | |
225 | } | |
226 | ||
227 | static void omap_i2c_put_clocks(struct omap_i2c_dev *dev) | |
228 | { | |
229 | clk_put(dev->fclk); | |
230 | dev->fclk = NULL; | |
5fe23380 RK |
231 | clk_put(dev->iclk); |
232 | dev->iclk = NULL; | |
010d442c KS |
233 | } |
234 | ||
f08ac4e7 | 235 | static void omap_i2c_unidle(struct omap_i2c_dev *dev) |
010d442c | 236 | { |
3831f154 PW |
237 | WARN_ON(!dev->idle); |
238 | ||
5fe23380 | 239 | clk_enable(dev->iclk); |
010d442c | 240 | clk_enable(dev->fclk); |
ef871432 RN |
241 | if (cpu_is_omap34xx()) { |
242 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0); | |
243 | omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, dev->pscstate); | |
244 | omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, dev->scllstate); | |
245 | omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, dev->sclhstate); | |
246 | omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, dev->bufstate); | |
247 | omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, dev->syscstate); | |
248 | omap_i2c_write_reg(dev, OMAP_I2C_WE_REG, dev->westate); | |
249 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN); | |
250 | } | |
0cbbcffd | 251 | dev->idle = 0; |
07ac31f6 CM |
252 | |
253 | /* | |
254 | * Don't write to this register if the IE state is 0 as it can | |
255 | * cause deadlock. | |
256 | */ | |
257 | if (dev->iestate) | |
258 | omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate); | |
010d442c KS |
259 | } |
260 | ||
f08ac4e7 | 261 | static void omap_i2c_idle(struct omap_i2c_dev *dev) |
010d442c | 262 | { |
f08ac4e7 TL |
263 | u16 iv; |
264 | ||
3831f154 PW |
265 | WARN_ON(dev->idle); |
266 | ||
f08ac4e7 TL |
267 | dev->iestate = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG); |
268 | omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, 0); | |
9c76b878 | 269 | if (dev->rev < OMAP_I2C_REV_2) { |
c1a473bd | 270 | iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG); /* Read clears */ |
0cbbcffd | 271 | } else { |
f08ac4e7 | 272 | omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, dev->iestate); |
0cbbcffd PW |
273 | |
274 | /* Flush posted write before the dev->idle store occurs */ | |
275 | omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG); | |
276 | } | |
277 | dev->idle = 1; | |
f08ac4e7 | 278 | clk_disable(dev->fclk); |
5fe23380 | 279 | clk_disable(dev->iclk); |
010d442c KS |
280 | } |
281 | ||
282 | static int omap_i2c_init(struct omap_i2c_dev *dev) | |
283 | { | |
ef871432 | 284 | u16 psc = 0, scll = 0, sclh = 0, buf = 0; |
4574eb68 | 285 | u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0; |
010d442c KS |
286 | unsigned long fclk_rate = 12000000; |
287 | unsigned long timeout; | |
4574eb68 | 288 | unsigned long internal_clk = 0; |
010d442c | 289 | |
9c76b878 | 290 | if (dev->rev >= OMAP_I2C_REV_2) { |
57eb81b1 MG |
291 | /* Disable I2C controller before soft reset */ |
292 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, | |
293 | omap_i2c_read_reg(dev, OMAP_I2C_CON_REG) & | |
294 | ~(OMAP_I2C_CON_EN)); | |
295 | ||
fdd07fe6 | 296 | omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK); |
010d442c KS |
297 | /* For some reason we need to set the EN bit before the |
298 | * reset done bit gets set. */ | |
299 | timeout = jiffies + OMAP_I2C_TIMEOUT; | |
300 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN); | |
301 | while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) & | |
fdd07fe6 | 302 | SYSS_RESETDONE_MASK)) { |
010d442c | 303 | if (time_after(jiffies, timeout)) { |
fce3ff03 | 304 | dev_warn(dev->dev, "timeout waiting " |
010d442c KS |
305 | "for controller reset\n"); |
306 | return -ETIMEDOUT; | |
307 | } | |
308 | msleep(1); | |
309 | } | |
fdd07fe6 PW |
310 | |
311 | /* SYSC register is cleared by the reset; rewrite it */ | |
312 | if (dev->rev == OMAP_I2C_REV_ON_2430) { | |
313 | ||
314 | omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, | |
315 | SYSC_AUTOIDLE_MASK); | |
316 | ||
317 | } else if (dev->rev >= OMAP_I2C_REV_ON_3430) { | |
ef871432 RN |
318 | dev->syscstate = SYSC_AUTOIDLE_MASK; |
319 | dev->syscstate |= SYSC_ENAWAKEUP_MASK; | |
320 | dev->syscstate |= (SYSC_IDLEMODE_SMART << | |
fdd07fe6 | 321 | __ffs(SYSC_SIDLEMODE_MASK)); |
ef871432 | 322 | dev->syscstate |= (SYSC_CLOCKACTIVITY_FCLK << |
fdd07fe6 PW |
323 | __ffs(SYSC_CLOCKACTIVITY_MASK)); |
324 | ||
ef871432 RN |
325 | omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, |
326 | dev->syscstate); | |
5043e9e7 KJ |
327 | /* |
328 | * Enabling all wakup sources to stop I2C freezing on | |
329 | * WFI instruction. | |
330 | * REVISIT: Some wkup sources might not be needed. | |
331 | */ | |
ef871432 RN |
332 | dev->westate = OMAP_I2C_WE_ALL; |
333 | omap_i2c_write_reg(dev, OMAP_I2C_WE_REG, dev->westate); | |
fdd07fe6 | 334 | } |
010d442c KS |
335 | } |
336 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0); | |
337 | ||
338 | if (cpu_class_is_omap1()) { | |
0e9ae109 RK |
339 | /* |
340 | * The I2C functional clock is the armxor_ck, so there's | |
341 | * no need to get "armxor_ck" separately. Now, if OMAP2420 | |
342 | * always returns 12MHz for the functional clock, we can | |
343 | * do this bit unconditionally. | |
344 | */ | |
345 | fclk_rate = clk_get_rate(dev->fclk); | |
346 | ||
010d442c KS |
347 | /* TRM for 5912 says the I2C clock must be prescaled to be |
348 | * between 7 - 12 MHz. The XOR input clock is typically | |
349 | * 12, 13 or 19.2 MHz. So we should have code that produces: | |
350 | * | |
351 | * XOR MHz Divider Prescaler | |
352 | * 12 1 0 | |
353 | * 13 2 1 | |
354 | * 19.2 2 1 | |
355 | */ | |
d7aef138 JD |
356 | if (fclk_rate > 12000000) |
357 | psc = fclk_rate / 12000000; | |
010d442c KS |
358 | } |
359 | ||
3d522fb4 | 360 | if (cpu_is_omap2430() || cpu_is_omap34xx()) { |
4574eb68 | 361 | |
84bf2c86 AK |
362 | /* |
363 | * HSI2C controller internal clk rate should be 19.2 Mhz for | |
364 | * HS and for all modes on 2430. On 34xx we can use lower rate | |
365 | * to get longer filter period for better noise suppression. | |
366 | * The filter is iclk (fclk for HS) period. | |
367 | */ | |
ff0f2426 | 368 | if (dev->speed > 400 || cpu_is_omap2430()) |
84bf2c86 AK |
369 | internal_clk = 19200; |
370 | else if (dev->speed > 100) | |
371 | internal_clk = 9600; | |
372 | else | |
373 | internal_clk = 4000; | |
4574eb68 SMK |
374 | fclk_rate = clk_get_rate(dev->fclk) / 1000; |
375 | ||
376 | /* Compute prescaler divisor */ | |
377 | psc = fclk_rate / internal_clk; | |
378 | psc = psc - 1; | |
379 | ||
380 | /* If configured for High Speed */ | |
381 | if (dev->speed > 400) { | |
baf46b4e AK |
382 | unsigned long scl; |
383 | ||
4574eb68 | 384 | /* For first phase of HS mode */ |
baf46b4e AK |
385 | scl = internal_clk / 400; |
386 | fsscll = scl - (scl / 3) - 7; | |
387 | fssclh = (scl / 3) - 5; | |
4574eb68 SMK |
388 | |
389 | /* For second phase of HS mode */ | |
baf46b4e AK |
390 | scl = fclk_rate / dev->speed; |
391 | hsscll = scl - (scl / 3) - 7; | |
392 | hssclh = (scl / 3) - 5; | |
393 | } else if (dev->speed > 100) { | |
394 | unsigned long scl; | |
395 | ||
396 | /* Fast mode */ | |
397 | scl = internal_clk / dev->speed; | |
398 | fsscll = scl - (scl / 3) - 7; | |
399 | fssclh = (scl / 3) - 5; | |
4574eb68 | 400 | } else { |
baf46b4e AK |
401 | /* Standard mode */ |
402 | fsscll = internal_clk / (dev->speed * 2) - 7; | |
403 | fssclh = internal_clk / (dev->speed * 2) - 5; | |
4574eb68 SMK |
404 | } |
405 | scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll; | |
406 | sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh; | |
407 | } else { | |
408 | /* Program desired operating rate */ | |
409 | fclk_rate /= (psc + 1) * 1000; | |
410 | if (psc > 2) | |
411 | psc = 2; | |
412 | scll = fclk_rate / (dev->speed * 2) - 7 + psc; | |
413 | sclh = fclk_rate / (dev->speed * 2) - 7 + psc; | |
414 | } | |
415 | ||
010d442c KS |
416 | /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */ |
417 | omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc); | |
418 | ||
4574eb68 SMK |
419 | /* SCL low and high time values */ |
420 | omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, scll); | |
421 | omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, sclh); | |
010d442c | 422 | |
ef871432 RN |
423 | if (dev->fifo_size) { |
424 | /* Note: setup required fifo size - 1. RTRSH and XTRSH */ | |
425 | buf = (dev->fifo_size - 1) << 8 | OMAP_I2C_BUF_RXFIF_CLR | | |
426 | (dev->fifo_size - 1) | OMAP_I2C_BUF_TXFIF_CLR; | |
427 | omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, buf); | |
428 | } | |
b6ee52c3 | 429 | |
010d442c KS |
430 | /* Take the I2C module out of reset: */ |
431 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN); | |
432 | ||
433 | /* Enable interrupts */ | |
ef871432 | 434 | dev->iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY | |
c1a473bd TL |
435 | OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK | |
436 | OMAP_I2C_IE_AL) | ((dev->fifo_size) ? | |
ef871432 RN |
437 | (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0); |
438 | omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate); | |
439 | if (cpu_is_omap34xx()) { | |
440 | dev->pscstate = psc; | |
441 | dev->scllstate = scll; | |
442 | dev->sclhstate = sclh; | |
443 | dev->bufstate = buf; | |
444 | } | |
010d442c KS |
445 | return 0; |
446 | } | |
447 | ||
448 | /* | |
449 | * Waiting on Bus Busy | |
450 | */ | |
451 | static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev) | |
452 | { | |
453 | unsigned long timeout; | |
454 | ||
455 | timeout = jiffies + OMAP_I2C_TIMEOUT; | |
456 | while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) { | |
457 | if (time_after(jiffies, timeout)) { | |
458 | dev_warn(dev->dev, "timeout waiting for bus ready\n"); | |
459 | return -ETIMEDOUT; | |
460 | } | |
461 | msleep(1); | |
462 | } | |
463 | ||
464 | return 0; | |
465 | } | |
466 | ||
467 | /* | |
468 | * Low level master read/write transaction. | |
469 | */ | |
470 | static int omap_i2c_xfer_msg(struct i2c_adapter *adap, | |
471 | struct i2c_msg *msg, int stop) | |
472 | { | |
473 | struct omap_i2c_dev *dev = i2c_get_adapdata(adap); | |
474 | int r; | |
475 | u16 w; | |
476 | ||
477 | dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n", | |
478 | msg->addr, msg->len, msg->flags, stop); | |
479 | ||
480 | if (msg->len == 0) | |
481 | return -EINVAL; | |
482 | ||
483 | omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr); | |
484 | ||
485 | /* REVISIT: Could the STB bit of I2C_CON be used with probing? */ | |
486 | dev->buf = msg->buf; | |
487 | dev->buf_len = msg->len; | |
488 | ||
489 | omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len); | |
490 | ||
b6ee52c3 NM |
491 | /* Clear the FIFO Buffers */ |
492 | w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG); | |
493 | w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR; | |
494 | omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w); | |
495 | ||
010d442c KS |
496 | init_completion(&dev->cmd_complete); |
497 | dev->cmd_err = 0; | |
498 | ||
499 | w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT; | |
4574eb68 SMK |
500 | |
501 | /* High speed configuration */ | |
502 | if (dev->speed > 400) | |
b6ee52c3 | 503 | w |= OMAP_I2C_CON_OPMODE_HS; |
4574eb68 | 504 | |
010d442c KS |
505 | if (msg->flags & I2C_M_TEN) |
506 | w |= OMAP_I2C_CON_XA; | |
507 | if (!(msg->flags & I2C_M_RD)) | |
508 | w |= OMAP_I2C_CON_TRX; | |
c1a473bd | 509 | |
b6ee52c3 | 510 | if (!dev->b_hw && stop) |
010d442c | 511 | w |= OMAP_I2C_CON_STP; |
c1a473bd | 512 | |
010d442c KS |
513 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w); |
514 | ||
b6ee52c3 NM |
515 | /* |
516 | * Don't write stt and stp together on some hardware. | |
517 | */ | |
518 | if (dev->b_hw && stop) { | |
519 | unsigned long delay = jiffies + OMAP_I2C_TIMEOUT; | |
520 | u16 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG); | |
521 | while (con & OMAP_I2C_CON_STT) { | |
522 | con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG); | |
523 | ||
524 | /* Let the user know if i2c is in a bad state */ | |
525 | if (time_after(jiffies, delay)) { | |
526 | dev_err(dev->dev, "controller timed out " | |
527 | "waiting for start condition to finish\n"); | |
528 | return -ETIMEDOUT; | |
529 | } | |
530 | cpu_relax(); | |
531 | } | |
532 | ||
533 | w |= OMAP_I2C_CON_STP; | |
534 | w &= ~OMAP_I2C_CON_STT; | |
535 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w); | |
536 | } | |
537 | ||
b7af349b JN |
538 | /* |
539 | * REVISIT: We should abort the transfer on signals, but the bus goes | |
540 | * into arbitration and we're currently unable to recover from it. | |
541 | */ | |
542 | r = wait_for_completion_timeout(&dev->cmd_complete, | |
543 | OMAP_I2C_TIMEOUT); | |
010d442c KS |
544 | dev->buf_len = 0; |
545 | if (r < 0) | |
546 | return r; | |
547 | if (r == 0) { | |
548 | dev_err(dev->dev, "controller timed out\n"); | |
549 | omap_i2c_init(dev); | |
550 | return -ETIMEDOUT; | |
551 | } | |
552 | ||
553 | if (likely(!dev->cmd_err)) | |
554 | return 0; | |
555 | ||
556 | /* We have an error */ | |
557 | if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR | | |
558 | OMAP_I2C_STAT_XUDF)) { | |
559 | omap_i2c_init(dev); | |
560 | return -EIO; | |
561 | } | |
562 | ||
563 | if (dev->cmd_err & OMAP_I2C_STAT_NACK) { | |
564 | if (msg->flags & I2C_M_IGNORE_NAK) | |
565 | return 0; | |
566 | if (stop) { | |
567 | w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG); | |
568 | w |= OMAP_I2C_CON_STP; | |
569 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w); | |
570 | } | |
571 | return -EREMOTEIO; | |
572 | } | |
573 | return -EIO; | |
574 | } | |
575 | ||
576 | ||
577 | /* | |
578 | * Prepare controller for a transaction and call omap_i2c_xfer_msg | |
579 | * to do the work during IRQ processing. | |
580 | */ | |
581 | static int | |
582 | omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) | |
583 | { | |
584 | struct omap_i2c_dev *dev = i2c_get_adapdata(adap); | |
585 | int i; | |
586 | int r; | |
587 | ||
f08ac4e7 | 588 | omap_i2c_unidle(dev); |
010d442c | 589 | |
c1a473bd TL |
590 | r = omap_i2c_wait_for_bb(dev); |
591 | if (r < 0) | |
010d442c KS |
592 | goto out; |
593 | ||
594 | for (i = 0; i < num; i++) { | |
595 | r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1))); | |
596 | if (r != 0) | |
597 | break; | |
598 | } | |
599 | ||
600 | if (r == 0) | |
601 | r = num; | |
602 | out: | |
f08ac4e7 | 603 | omap_i2c_idle(dev); |
010d442c KS |
604 | return r; |
605 | } | |
606 | ||
607 | static u32 | |
608 | omap_i2c_func(struct i2c_adapter *adap) | |
609 | { | |
610 | return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); | |
611 | } | |
612 | ||
613 | static inline void | |
614 | omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err) | |
615 | { | |
616 | dev->cmd_err |= err; | |
617 | complete(&dev->cmd_complete); | |
618 | } | |
619 | ||
620 | static inline void | |
621 | omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat) | |
622 | { | |
623 | omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat); | |
624 | } | |
625 | ||
43469d8e PW |
626 | /* rev1 devices are apparently only on some 15xx */ |
627 | #ifdef CONFIG_ARCH_OMAP15XX | |
628 | ||
010d442c | 629 | static irqreturn_t |
7d12e780 | 630 | omap_i2c_rev1_isr(int this_irq, void *dev_id) |
010d442c KS |
631 | { |
632 | struct omap_i2c_dev *dev = dev_id; | |
633 | u16 iv, w; | |
634 | ||
f08ac4e7 TL |
635 | if (dev->idle) |
636 | return IRQ_NONE; | |
637 | ||
010d442c KS |
638 | iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG); |
639 | switch (iv) { | |
640 | case 0x00: /* None */ | |
641 | break; | |
642 | case 0x01: /* Arbitration lost */ | |
643 | dev_err(dev->dev, "Arbitration lost\n"); | |
644 | omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL); | |
645 | break; | |
646 | case 0x02: /* No acknowledgement */ | |
647 | omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK); | |
648 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP); | |
649 | break; | |
650 | case 0x03: /* Register access ready */ | |
651 | omap_i2c_complete_cmd(dev, 0); | |
652 | break; | |
653 | case 0x04: /* Receive data ready */ | |
654 | if (dev->buf_len) { | |
655 | w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG); | |
656 | *dev->buf++ = w; | |
657 | dev->buf_len--; | |
658 | if (dev->buf_len) { | |
659 | *dev->buf++ = w >> 8; | |
660 | dev->buf_len--; | |
661 | } | |
662 | } else | |
663 | dev_err(dev->dev, "RRDY IRQ while no data requested\n"); | |
664 | break; | |
665 | case 0x05: /* Transmit data ready */ | |
666 | if (dev->buf_len) { | |
667 | w = *dev->buf++; | |
668 | dev->buf_len--; | |
669 | if (dev->buf_len) { | |
670 | w |= *dev->buf++ << 8; | |
671 | dev->buf_len--; | |
672 | } | |
673 | omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w); | |
674 | } else | |
675 | dev_err(dev->dev, "XRDY IRQ while no data to send\n"); | |
676 | break; | |
677 | default: | |
678 | return IRQ_NONE; | |
679 | } | |
680 | ||
681 | return IRQ_HANDLED; | |
682 | } | |
43469d8e | 683 | #else |
c1a473bd | 684 | #define omap_i2c_rev1_isr NULL |
43469d8e | 685 | #endif |
010d442c KS |
686 | |
687 | static irqreturn_t | |
7d12e780 | 688 | omap_i2c_isr(int this_irq, void *dev_id) |
010d442c KS |
689 | { |
690 | struct omap_i2c_dev *dev = dev_id; | |
691 | u16 bits; | |
692 | u16 stat, w; | |
b6ee52c3 | 693 | int err, count = 0; |
010d442c | 694 | |
f08ac4e7 TL |
695 | if (dev->idle) |
696 | return IRQ_NONE; | |
697 | ||
010d442c KS |
698 | bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG); |
699 | while ((stat = (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG))) & bits) { | |
700 | dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat); | |
701 | if (count++ == 100) { | |
702 | dev_warn(dev->dev, "Too much work in one IRQ\n"); | |
703 | break; | |
704 | } | |
705 | ||
cd086d3a SM |
706 | err = 0; |
707 | complete: | |
dcc4ec26 NM |
708 | /* |
709 | * Ack the stat in one go, but [R/X]DR and [R/X]RDY should be | |
710 | * acked after the data operation is complete. | |
711 | * Ref: TRM SWPU114Q Figure 18-31 | |
712 | */ | |
713 | omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat & | |
714 | ~(OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR | | |
715 | OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR)); | |
010d442c | 716 | |
b6ee52c3 NM |
717 | if (stat & OMAP_I2C_STAT_NACK) { |
718 | err |= OMAP_I2C_STAT_NACK; | |
719 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, | |
720 | OMAP_I2C_CON_STP); | |
010d442c | 721 | } |
b6ee52c3 NM |
722 | if (stat & OMAP_I2C_STAT_AL) { |
723 | dev_err(dev->dev, "Arbitration lost\n"); | |
724 | err |= OMAP_I2C_STAT_AL; | |
725 | } | |
726 | if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK | | |
04c688dd | 727 | OMAP_I2C_STAT_AL)) { |
dd11976a MS |
728 | omap_i2c_ack_stat(dev, stat & |
729 | (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR | | |
730 | OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR)); | |
b6ee52c3 | 731 | omap_i2c_complete_cmd(dev, err); |
04c688dd SM |
732 | return IRQ_HANDLED; |
733 | } | |
b6ee52c3 NM |
734 | if (stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR)) { |
735 | u8 num_bytes = 1; | |
736 | if (dev->fifo_size) { | |
737 | if (stat & OMAP_I2C_STAT_RRDY) | |
738 | num_bytes = dev->fifo_size; | |
bfb6b658 SM |
739 | else /* read RXSTAT on RDR interrupt */ |
740 | num_bytes = (omap_i2c_read_reg(dev, | |
741 | OMAP_I2C_BUFSTAT_REG) | |
742 | >> 8) & 0x3F; | |
b6ee52c3 NM |
743 | } |
744 | while (num_bytes) { | |
745 | num_bytes--; | |
746 | w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG); | |
010d442c | 747 | if (dev->buf_len) { |
b6ee52c3 | 748 | *dev->buf++ = w; |
010d442c | 749 | dev->buf_len--; |
b6ee52c3 | 750 | /* Data reg from 2430 is 8 bit wide */ |
3d522fb4 C |
751 | if (!cpu_is_omap2430() && |
752 | !cpu_is_omap34xx()) { | |
b6ee52c3 NM |
753 | if (dev->buf_len) { |
754 | *dev->buf++ = w >> 8; | |
755 | dev->buf_len--; | |
756 | } | |
757 | } | |
758 | } else { | |
759 | if (stat & OMAP_I2C_STAT_RRDY) | |
760 | dev_err(dev->dev, | |
761 | "RRDY IRQ while no data" | |
762 | " requested\n"); | |
763 | if (stat & OMAP_I2C_STAT_RDR) | |
764 | dev_err(dev->dev, | |
765 | "RDR IRQ while no data" | |
766 | " requested\n"); | |
767 | break; | |
010d442c | 768 | } |
b6ee52c3 NM |
769 | } |
770 | omap_i2c_ack_stat(dev, | |
771 | stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR)); | |
010d442c KS |
772 | continue; |
773 | } | |
b6ee52c3 NM |
774 | if (stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR)) { |
775 | u8 num_bytes = 1; | |
776 | if (dev->fifo_size) { | |
777 | if (stat & OMAP_I2C_STAT_XRDY) | |
778 | num_bytes = dev->fifo_size; | |
bfb6b658 | 779 | else /* read TXSTAT on XDR interrupt */ |
b6ee52c3 | 780 | num_bytes = omap_i2c_read_reg(dev, |
bfb6b658 SM |
781 | OMAP_I2C_BUFSTAT_REG) |
782 | & 0x3F; | |
b6ee52c3 NM |
783 | } |
784 | while (num_bytes) { | |
785 | num_bytes--; | |
786 | w = 0; | |
010d442c | 787 | if (dev->buf_len) { |
b6ee52c3 | 788 | w = *dev->buf++; |
010d442c | 789 | dev->buf_len--; |
b6ee52c3 | 790 | /* Data reg from 2430 is 8 bit wide */ |
3d522fb4 C |
791 | if (!cpu_is_omap2430() && |
792 | !cpu_is_omap34xx()) { | |
b6ee52c3 NM |
793 | if (dev->buf_len) { |
794 | w |= *dev->buf++ << 8; | |
795 | dev->buf_len--; | |
796 | } | |
797 | } | |
798 | } else { | |
799 | if (stat & OMAP_I2C_STAT_XRDY) | |
800 | dev_err(dev->dev, | |
801 | "XRDY IRQ while no " | |
802 | "data to send\n"); | |
803 | if (stat & OMAP_I2C_STAT_XDR) | |
804 | dev_err(dev->dev, | |
805 | "XDR IRQ while no " | |
806 | "data to send\n"); | |
807 | break; | |
010d442c | 808 | } |
cd086d3a SM |
809 | |
810 | /* | |
811 | * OMAP3430 Errata 1.153: When an XRDY/XDR | |
812 | * is hit, wait for XUDF before writing data | |
813 | * to DATA_REG. Otherwise some data bytes can | |
814 | * be lost while transferring them from the | |
815 | * memory to the I2C interface. | |
816 | */ | |
817 | ||
61149787 | 818 | if (dev->rev <= OMAP_I2C_REV_ON_3430) { |
cd086d3a SM |
819 | while (!(stat & OMAP_I2C_STAT_XUDF)) { |
820 | if (stat & (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) { | |
821 | omap_i2c_ack_stat(dev, stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR)); | |
822 | err |= OMAP_I2C_STAT_XUDF; | |
823 | goto complete; | |
824 | } | |
825 | cpu_relax(); | |
826 | stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG); | |
827 | } | |
828 | } | |
829 | ||
b6ee52c3 NM |
830 | omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w); |
831 | } | |
832 | omap_i2c_ack_stat(dev, | |
833 | stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR)); | |
010d442c KS |
834 | continue; |
835 | } | |
836 | if (stat & OMAP_I2C_STAT_ROVR) { | |
837 | dev_err(dev->dev, "Receive overrun\n"); | |
838 | dev->cmd_err |= OMAP_I2C_STAT_ROVR; | |
839 | } | |
840 | if (stat & OMAP_I2C_STAT_XUDF) { | |
b6ee52c3 | 841 | dev_err(dev->dev, "Transmit underflow\n"); |
010d442c KS |
842 | dev->cmd_err |= OMAP_I2C_STAT_XUDF; |
843 | } | |
010d442c KS |
844 | } |
845 | ||
846 | return count ? IRQ_HANDLED : IRQ_NONE; | |
847 | } | |
848 | ||
8f9082c5 | 849 | static const struct i2c_algorithm omap_i2c_algo = { |
010d442c KS |
850 | .master_xfer = omap_i2c_xfer, |
851 | .functionality = omap_i2c_func, | |
852 | }; | |
853 | ||
1139aea9 | 854 | static int __devinit |
010d442c KS |
855 | omap_i2c_probe(struct platform_device *pdev) |
856 | { | |
857 | struct omap_i2c_dev *dev; | |
858 | struct i2c_adapter *adap; | |
859 | struct resource *mem, *irq, *ioarea; | |
e355204e | 860 | irq_handler_t isr; |
010d442c | 861 | int r; |
3d522fb4 | 862 | u32 speed = 0; |
010d442c KS |
863 | |
864 | /* NOTE: driver uses the static register mapping */ | |
865 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
866 | if (!mem) { | |
867 | dev_err(&pdev->dev, "no mem resource?\n"); | |
868 | return -ENODEV; | |
869 | } | |
870 | irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
871 | if (!irq) { | |
872 | dev_err(&pdev->dev, "no irq resource?\n"); | |
873 | return -ENODEV; | |
874 | } | |
875 | ||
59330825 | 876 | ioarea = request_mem_region(mem->start, resource_size(mem), |
010d442c KS |
877 | pdev->name); |
878 | if (!ioarea) { | |
879 | dev_err(&pdev->dev, "I2C region already claimed\n"); | |
880 | return -EBUSY; | |
881 | } | |
882 | ||
010d442c KS |
883 | dev = kzalloc(sizeof(struct omap_i2c_dev), GFP_KERNEL); |
884 | if (!dev) { | |
885 | r = -ENOMEM; | |
886 | goto err_release_region; | |
887 | } | |
888 | ||
4574eb68 | 889 | if (pdev->dev.platform_data != NULL) |
3d522fb4 | 890 | speed = *(u32 *)pdev->dev.platform_data; |
4574eb68 | 891 | else |
3d522fb4 | 892 | speed = 100; /* Defualt speed */ |
4574eb68 | 893 | |
3d522fb4 | 894 | dev->speed = speed; |
3831f154 | 895 | dev->idle = 1; |
010d442c KS |
896 | dev->dev = &pdev->dev; |
897 | dev->irq = irq->start; | |
c6ffddea | 898 | dev->base = ioremap(mem->start, resource_size(mem)); |
55c381e4 RK |
899 | if (!dev->base) { |
900 | r = -ENOMEM; | |
901 | goto err_free_mem; | |
902 | } | |
903 | ||
010d442c KS |
904 | platform_set_drvdata(pdev, dev); |
905 | ||
7c6bd201 MW |
906 | if (cpu_is_omap7xx()) |
907 | dev->reg_shift = 1; | |
908 | else | |
909 | dev->reg_shift = 2; | |
910 | ||
010d442c | 911 | if ((r = omap_i2c_get_clocks(dev)) != 0) |
55c381e4 | 912 | goto err_iounmap; |
010d442c | 913 | |
f08ac4e7 | 914 | omap_i2c_unidle(dev); |
010d442c | 915 | |
9c76b878 | 916 | dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff; |
010d442c | 917 | |
3d522fb4 | 918 | if (cpu_is_omap2430() || cpu_is_omap34xx()) { |
b6ee52c3 NM |
919 | u16 s; |
920 | ||
921 | /* Set up the fifo size - Get total size */ | |
922 | s = (omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3; | |
923 | dev->fifo_size = 0x8 << s; | |
924 | ||
925 | /* | |
926 | * Set up notification threshold as half the total available | |
927 | * size. This is to ensure that we can handle the status on int | |
928 | * call back latencies. | |
929 | */ | |
930 | dev->fifo_size = (dev->fifo_size / 2); | |
931 | dev->b_hw = 1; /* Enable hardware fixes */ | |
932 | } | |
933 | ||
010d442c KS |
934 | /* reset ASAP, clearing any IRQs */ |
935 | omap_i2c_init(dev); | |
936 | ||
9c76b878 PW |
937 | isr = (dev->rev < OMAP_I2C_REV_2) ? omap_i2c_rev1_isr : omap_i2c_isr; |
938 | r = request_irq(dev->irq, isr, 0, pdev->name, dev); | |
010d442c KS |
939 | |
940 | if (r) { | |
941 | dev_err(dev->dev, "failure requesting irq %i\n", dev->irq); | |
942 | goto err_unuse_clocks; | |
943 | } | |
9c76b878 | 944 | |
010d442c | 945 | dev_info(dev->dev, "bus %d rev%d.%d at %d kHz\n", |
9c76b878 | 946 | pdev->id, dev->rev >> 4, dev->rev & 0xf, dev->speed); |
010d442c | 947 | |
3831f154 PW |
948 | omap_i2c_idle(dev); |
949 | ||
010d442c KS |
950 | adap = &dev->adapter; |
951 | i2c_set_adapdata(adap, dev); | |
952 | adap->owner = THIS_MODULE; | |
953 | adap->class = I2C_CLASS_HWMON; | |
783fd6fa | 954 | strlcpy(adap->name, "OMAP I2C adapter", sizeof(adap->name)); |
010d442c KS |
955 | adap->algo = &omap_i2c_algo; |
956 | adap->dev.parent = &pdev->dev; | |
957 | ||
958 | /* i2c device drivers may be active on return from add_adapter() */ | |
7c175499 DB |
959 | adap->nr = pdev->id; |
960 | r = i2c_add_numbered_adapter(adap); | |
010d442c KS |
961 | if (r) { |
962 | dev_err(dev->dev, "failure adding adapter\n"); | |
963 | goto err_free_irq; | |
964 | } | |
965 | ||
010d442c KS |
966 | return 0; |
967 | ||
968 | err_free_irq: | |
969 | free_irq(dev->irq, dev); | |
970 | err_unuse_clocks: | |
3e39752d | 971 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0); |
f08ac4e7 | 972 | omap_i2c_idle(dev); |
010d442c | 973 | omap_i2c_put_clocks(dev); |
55c381e4 RK |
974 | err_iounmap: |
975 | iounmap(dev->base); | |
010d442c KS |
976 | err_free_mem: |
977 | platform_set_drvdata(pdev, NULL); | |
978 | kfree(dev); | |
979 | err_release_region: | |
59330825 | 980 | release_mem_region(mem->start, resource_size(mem)); |
010d442c KS |
981 | |
982 | return r; | |
983 | } | |
984 | ||
985 | static int | |
986 | omap_i2c_remove(struct platform_device *pdev) | |
987 | { | |
988 | struct omap_i2c_dev *dev = platform_get_drvdata(pdev); | |
989 | struct resource *mem; | |
990 | ||
991 | platform_set_drvdata(pdev, NULL); | |
992 | ||
993 | free_irq(dev->irq, dev); | |
994 | i2c_del_adapter(&dev->adapter); | |
995 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0); | |
996 | omap_i2c_put_clocks(dev); | |
55c381e4 | 997 | iounmap(dev->base); |
010d442c KS |
998 | kfree(dev); |
999 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
59330825 | 1000 | release_mem_region(mem->start, resource_size(mem)); |
010d442c KS |
1001 | return 0; |
1002 | } | |
1003 | ||
1004 | static struct platform_driver omap_i2c_driver = { | |
1005 | .probe = omap_i2c_probe, | |
1006 | .remove = omap_i2c_remove, | |
1007 | .driver = { | |
1008 | .name = "i2c_omap", | |
1009 | .owner = THIS_MODULE, | |
1010 | }, | |
1011 | }; | |
1012 | ||
1013 | /* I2C may be needed to bring up other drivers */ | |
1014 | static int __init | |
1015 | omap_i2c_init_driver(void) | |
1016 | { | |
1017 | return platform_driver_register(&omap_i2c_driver); | |
1018 | } | |
1019 | subsys_initcall(omap_i2c_init_driver); | |
1020 | ||
1021 | static void __exit omap_i2c_exit_driver(void) | |
1022 | { | |
1023 | platform_driver_unregister(&omap_i2c_driver); | |
1024 | } | |
1025 | module_exit(omap_i2c_exit_driver); | |
1026 | ||
1027 | MODULE_AUTHOR("MontaVista Software, Inc. (and others)"); | |
1028 | MODULE_DESCRIPTION("TI OMAP I2C bus adapter"); | |
1029 | MODULE_LICENSE("GPL"); | |
add8eda7 | 1030 | MODULE_ALIAS("platform:i2c_omap"); |