[deliverable/linux.git] / drivers / i2c / busses / i2c-piix4.c

/*
    piix4.c - Part of lm_sensors, Linux kernel modules for hardware
              monitoring
    Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl> and
    Philip Edelbrock <phil@netroedge.com>

    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 2 of the License, or
    (at your option) any later version.

    This program is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.

    You should have received a copy of the GNU General Public License
    along with this program; if not, write to the Free Software
    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/

/*
   Supports:
	Intel PIIX4, 440MX
	Serverworks OSB4, CSB5, CSB6, HT-1000
	ATI IXP200, IXP300, IXP400, SB600
	SMSC Victory66

   Note: we assume there can only be one device, with one SMBus interface.
*/

#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/stddef.h>
#include <linux/sched.h>
#include <linux/ioport.h>
#include <linux/i2c.h>
#include <linux/init.h>
#include <linux/apm_bios.h>
#include <linux/dmi.h>
#include <asm/io.h>


struct sd {
	const unsigned short mfr;
	const unsigned short dev;
	const unsigned char fn;
	const char *name;
};

/* PIIX4 SMBus address offsets */
#define SMBHSTSTS	(0 + piix4_smba)
#define SMBHSLVSTS	(1 + piix4_smba)
#define SMBHSTCNT	(2 + piix4_smba)
#define SMBHSTCMD	(3 + piix4_smba)
#define SMBHSTADD	(4 + piix4_smba)
#define SMBHSTDAT0	(5 + piix4_smba)
#define SMBHSTDAT1	(6 + piix4_smba)
#define SMBBLKDAT	(7 + piix4_smba)
#define SMBSLVCNT	(8 + piix4_smba)
#define SMBSHDWCMD	(9 + piix4_smba)
#define SMBSLVEVT	(0xA + piix4_smba)
#define SMBSLVDAT	(0xC + piix4_smba)

/* count for request_region */
#define SMBIOSIZE	8

/* PCI Address Constants */
#define SMBBA		0x090
#define SMBHSTCFG	0x0D2
#define SMBSLVC		0x0D3
#define SMBSHDW1	0x0D4
#define SMBSHDW2	0x0D5
#define SMBREV		0x0D6

/* Other settings */
#define MAX_TIMEOUT	500
#define  ENABLE_INT9	0

/* PIIX4 constants */
#define PIIX4_QUICK		0x00
#define PIIX4_BYTE		0x04
#define PIIX4_BYTE_DATA		0x08
#define PIIX4_WORD_DATA		0x0C
#define PIIX4_BLOCK_DATA	0x14

/* insmod parameters */

/* If force is set to anything different from 0, we forcibly enable the
   PIIX4. DANGEROUS! */
static int force;
module_param (force, int, 0);
MODULE_PARM_DESC(force, "Forcibly enable the PIIX4. DANGEROUS!");

/* If force_addr is set to anything different from 0, we forcibly enable
   the PIIX4 at the given address. VERY DANGEROUS! */
static int force_addr;
module_param (force_addr, int, 0);
MODULE_PARM_DESC(force_addr,
		 "Forcibly enable the PIIX4 at the given address. "
		 "EXTREMELY DANGEROUS!");

static int piix4_transaction(void);

static unsigned short piix4_smba;
static struct pci_driver piix4_driver;
static struct i2c_adapter piix4_adapter;

static struct dmi_system_id __devinitdata piix4_dmi_table[] = {
	{
		.ident = "IBM",
		.matches = { DMI_MATCH(DMI_SYS_VENDOR, "IBM"), },
	},
	{ },
};

static int __devinit piix4_setup(struct pci_dev *PIIX4_dev,
				const struct pci_device_id *id)
{
	unsigned char temp;

	/* match up the function */
	if (PCI_FUNC(PIIX4_dev->devfn) != id->driver_data)
		return -ENODEV;

	dev_info(&PIIX4_dev->dev, "Found %s device\n", pci_name(PIIX4_dev));

	/* Don't access SMBus on IBM systems which get corrupted eeproms */
	if (dmi_check_system(piix4_dmi_table) &&
			PIIX4_dev->vendor == PCI_VENDOR_ID_INTEL) {
		dev_err(&PIIX4_dev->dev, "IBM system detected; this module "
			"may corrupt your serial eeprom! Refusing to load "
			"module!\n");
		return -EPERM;
	}

	/* Determine the address of the SMBus areas */
	if (force_addr) {
		piix4_smba = force_addr & 0xfff0;
		force = 0;
	} else {
		pci_read_config_word(PIIX4_dev, SMBBA, &piix4_smba);
		piix4_smba &= 0xfff0;
		if(piix4_smba == 0) {
			dev_err(&PIIX4_dev->dev, "SMB base address "
				"uninitialized - upgrade BIOS or use "
				"force_addr=0xaddr\n");
			return -ENODEV;
		}
	}

	if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) {
		dev_err(&PIIX4_dev->dev, "SMB region 0x%x already in use!\n",
			piix4_smba);
		return -ENODEV;
	}

	pci_read_config_byte(PIIX4_dev, SMBHSTCFG, &temp);

	/* If force_addr is set, we program the new address here. Just to make
	   sure, we disable the PIIX4 first. */
	if (force_addr) {
		pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp & 0xfe);
		pci_write_config_word(PIIX4_dev, SMBBA, piix4_smba);
		pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp | 0x01);
		dev_info(&PIIX4_dev->dev, "WARNING: SMBus interface set to "
			"new address %04x!\n", piix4_smba);
	} else if ((temp & 1) == 0) {
		if (force) {
			/* This should never need to be done, but has been
			 * noted that many Dell machines have the SMBus
			 * interface on the PIIX4 disabled!? NOTE: This assumes
			 * I/O space and other allocations WERE done by the
			 * Bios!  Don't complain if your hardware does weird
			 * things after enabling this. :') Check for Bios
			 * updates before resorting to this.
			 */
			pci_write_config_byte(PIIX4_dev, SMBHSTCFG,
					      temp | 1);
			dev_printk(KERN_NOTICE, &PIIX4_dev->dev,
				"WARNING: SMBus interface has been "
				"FORCEFULLY ENABLED!\n");
		} else {
			dev_err(&PIIX4_dev->dev,
				"Host SMBus controller not enabled!\n");
			release_region(piix4_smba, SMBIOSIZE);
			piix4_smba = 0;
			return -ENODEV;
		}
	}

	if (((temp & 0x0E) == 8) || ((temp & 0x0E) == 2))
		dev_dbg(&PIIX4_dev->dev, "Using Interrupt 9 for SMBus.\n");
	else if ((temp & 0x0E) == 0)
		dev_dbg(&PIIX4_dev->dev, "Using Interrupt SMI# for SMBus.\n");
	else
		dev_err(&PIIX4_dev->dev, "Illegal Interrupt configuration "
			"(or code out of date)!\n");

	pci_read_config_byte(PIIX4_dev, SMBREV, &temp);
	dev_dbg(&PIIX4_dev->dev, "SMBREV = 0x%X\n", temp);
	dev_dbg(&PIIX4_dev->dev, "SMBA = 0x%X\n", piix4_smba);

	return 0;
}

/* Another internally used function */
static int piix4_transaction(void)
{
	int temp;
	int result = 0;
	int timeout = 0;

	dev_dbg(&piix4_adapter.dev, "Transaction (pre): CNT=%02x, CMD=%02x, "
		"ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
		inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
		inb_p(SMBHSTDAT1));

	/* Make sure the SMBus host is ready to start transmitting */
	if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
		dev_dbg(&piix4_adapter.dev, "SMBus busy (%02x). "
			"Resetting...\n", temp);
		outb_p(temp, SMBHSTSTS);
		if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
			dev_err(&piix4_adapter.dev, "Failed! (%02x)\n", temp);
			return -1;
		} else {
			dev_dbg(&piix4_adapter.dev, "Successfull!\n");
		}
	}

	/* start the transaction by setting bit 6 */
	outb_p(inb(SMBHSTCNT) | 0x040, SMBHSTCNT);

	/* We will always wait for a fraction of a second! (See PIIX4 docs errata) */
	do {
		msleep(1);
		temp = inb_p(SMBHSTSTS);
	} while ((temp & 0x01) && (timeout++ < MAX_TIMEOUT));

	/* If the SMBus is still busy, we give up */
	if (timeout >= MAX_TIMEOUT) {
		dev_err(&piix4_adapter.dev, "SMBus Timeout!\n");
		result = -1;
	}

	if (temp & 0x10) {
		result = -1;
		dev_err(&piix4_adapter.dev, "Error: Failed bus transaction\n");
	}

	if (temp & 0x08) {
		result = -1;
		dev_dbg(&piix4_adapter.dev, "Bus collision! SMBus may be "
			"locked until next hard reset. (sorry!)\n");
		/* Clock stops and slave is stuck in mid-transmission */
	}

	if (temp & 0x04) {
		result = -1;
		dev_dbg(&piix4_adapter.dev, "Error: no response!\n");
	}

	if (inb_p(SMBHSTSTS) != 0x00)
		outb_p(inb(SMBHSTSTS), SMBHSTSTS);

	if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
		dev_err(&piix4_adapter.dev, "Failed reset at end of "
			"transaction (%02x)\n", temp);
	}
	dev_dbg(&piix4_adapter.dev, "Transaction (post): CNT=%02x, CMD=%02x, "
		"ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
		inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
		inb_p(SMBHSTDAT1));
	return result;
}

/* Return -1 on error. */
static s32 piix4_access(struct i2c_adapter * adap, u16 addr,
		 unsigned short flags, char read_write,
		 u8 command, int size, union i2c_smbus_data * data)
{
	int i, len;

	switch (size) {
	case I2C_SMBUS_PROC_CALL:
		dev_err(&adap->dev, "I2C_SMBUS_PROC_CALL not supported!\n");
		return -1;
	case I2C_SMBUS_QUICK:
		outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
		       SMBHSTADD);
		size = PIIX4_QUICK;
		break;
	case I2C_SMBUS_BYTE:
		outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
		       SMBHSTADD);
		if (read_write == I2C_SMBUS_WRITE)
			outb_p(command, SMBHSTCMD);
		size = PIIX4_BYTE;
		break;
	case I2C_SMBUS_BYTE_DATA:
		outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
		       SMBHSTADD);
		outb_p(command, SMBHSTCMD);
		if (read_write == I2C_SMBUS_WRITE)
			outb_p(data->byte, SMBHSTDAT0);
		size = PIIX4_BYTE_DATA;
		break;
	case I2C_SMBUS_WORD_DATA:
		outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
		       SMBHSTADD);
		outb_p(command, SMBHSTCMD);
		if (read_write == I2C_SMBUS_WRITE) {
			outb_p(data->word & 0xff, SMBHSTDAT0);
			outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1);
		}
		size = PIIX4_WORD_DATA;
		break;
	case I2C_SMBUS_BLOCK_DATA:
		outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
		       SMBHSTADD);
		outb_p(command, SMBHSTCMD);
		if (read_write == I2C_SMBUS_WRITE) {
			len = data->block[0];
			if (len < 0)
				len = 0;
			if (len > 32)
				len = 32;
			outb_p(len, SMBHSTDAT0);
			i = inb_p(SMBHSTCNT);	/* Reset SMBBLKDAT */
			for (i = 1; i <= len; i++)
				outb_p(data->block[i], SMBBLKDAT);
		}
		size = PIIX4_BLOCK_DATA;
		break;
	}

	outb_p((size & 0x1C) + (ENABLE_INT9 & 1), SMBHSTCNT);

	if (piix4_transaction())	/* Error in transaction */
		return -1;

	if ((read_write == I2C_SMBUS_WRITE) || (size == PIIX4_QUICK))
		return 0;


	switch (size) {
	case PIIX4_BYTE:	/* Where is the result put? I assume here it is in
				   SMBHSTDAT0 but it might just as well be in the
				   SMBHSTCMD. No clue in the docs */

		data->byte = inb_p(SMBHSTDAT0);
		break;
	case PIIX4_BYTE_DATA:
		data->byte = inb_p(SMBHSTDAT0);
		break;
	case PIIX4_WORD_DATA:
		data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8);
		break;
	case PIIX4_BLOCK_DATA:
		data->block[0] = inb_p(SMBHSTDAT0);
		i = inb_p(SMBHSTCNT);	/* Reset SMBBLKDAT */
		for (i = 1; i <= data->block[0]; i++)
			data->block[i] = inb_p(SMBBLKDAT);
		break;
	}
	return 0;
}

static u32 piix4_func(struct i2c_adapter *adapter)
{
	return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
	    I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
	    I2C_FUNC_SMBUS_BLOCK_DATA;
}

static const struct i2c_algorithm smbus_algorithm = {
	.smbus_xfer	= piix4_access,
	.functionality	= piix4_func,
};

static struct i2c_adapter piix4_adapter = {
	.owner		= THIS_MODULE,
	.id		= I2C_HW_SMBUS_PIIX4,
	.class		= I2C_CLASS_HWMON,
	.algo		= &smbus_algorithm,
};

static struct pci_device_id piix4_ids[] = {
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3),
	  .driver_data = 3 },
	{ PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP200_SMBUS),
	  .driver_data = 0 },
	{ PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP300_SMBUS),
	  .driver_data = 0 },
	{ PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS),
	  .driver_data = 0 },
	{ PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SMBUS),
	  .driver_data = 0 },
	{ PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4),
	  .driver_data = 0 },
	{ PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5),
	  .driver_data = 0 },
	{ PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6),
	  .driver_data = 0 },
	{ PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB),
	  .driver_data = 0 },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3),
	  .driver_data = 3 },
	{ PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_3),
	  .driver_data = 0 },
	{ 0, }
};

MODULE_DEVICE_TABLE (pci, piix4_ids);

static int __devinit piix4_probe(struct pci_dev *dev,
				const struct pci_device_id *id)
{
	int retval;

	retval = piix4_setup(dev, id);
	if (retval)
		return retval;

	/* set up the driverfs linkage to our parent device */
	piix4_adapter.dev.parent = &dev->dev;

	snprintf(piix4_adapter.name, I2C_NAME_SIZE,
		"SMBus PIIX4 adapter at %04x", piix4_smba);

	if ((retval = i2c_add_adapter(&piix4_adapter))) {
		dev_err(&dev->dev, "Couldn't register adapter!\n");
		release_region(piix4_smba, SMBIOSIZE);
		piix4_smba = 0;
	}

	return retval;
}

static void __devexit piix4_remove(struct pci_dev *dev)
{
	if (piix4_smba) {
		i2c_del_adapter(&piix4_adapter);
		release_region(piix4_smba, SMBIOSIZE);
		piix4_smba = 0;
	}
}

static struct pci_driver piix4_driver = {
	.name		= "piix4_smbus",
	.id_table	= piix4_ids,
	.probe		= piix4_probe,
	.remove		= __devexit_p(piix4_remove),
};

static int __init i2c_piix4_init(void)
{
	return pci_register_driver(&piix4_driver);
}

static void __exit i2c_piix4_exit(void)
{
	pci_unregister_driver(&piix4_driver);
}

MODULE_AUTHOR("Frodo Looijaard <frodol@dds.nl> and "
		"Philip Edelbrock <phil@netroedge.com>");
MODULE_DESCRIPTION("PIIX4 SMBus driver");
MODULE_LICENSE("GPL");

module_init(i2c_piix4_init);
module_exit(i2c_piix4_exit);
Commit	Line	Data
1da177e4 LT	1	/*
	2	piix4.c - Part of lm_sensors, Linux kernel modules for hardware
	3	monitoring
	4	Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl> and
	5	Philip Edelbrock <phil@netroedge.com>
	6
	7	This program is free software; you can redistribute it and/or modify
	8	it under the terms of the GNU General Public License as published by
	9	the Free Software Foundation; either version 2 of the License, or
	10	(at your option) any later version.
	11
	12	This program is distributed in the hope that it will be useful,
	13	but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	GNU General Public License for more details.
	16
	17	You should have received a copy of the GNU General Public License
	18	along with this program; if not, write to the Free Software
	19	Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	20	*/
	21
	22	/*
	23	Supports:
	24	Intel PIIX4, 440MX
5f7ea3c5	25	Serverworks OSB4, CSB5, CSB6, HT-1000
4e6697fc	26	ATI IXP200, IXP300, IXP400, SB600
1da177e4 LT	27	SMSC Victory66
	28
	29	Note: we assume there can only be one device, with one SMBus interface.
	30	*/
	31
1da177e4 LT	32	#include <linux/module.h>
	33	#include <linux/moduleparam.h>
	34	#include <linux/pci.h>
	35	#include <linux/kernel.h>
	36	#include <linux/delay.h>
	37	#include <linux/stddef.h>
	38	#include <linux/sched.h>
	39	#include <linux/ioport.h>
	40	#include <linux/i2c.h>
	41	#include <linux/init.h>
	42	#include <linux/apm_bios.h>
	43	#include <linux/dmi.h>
	44	#include <asm/io.h>
	45
	46
	47	struct sd {
	48	const unsigned short mfr;
	49	const unsigned short dev;
	50	const unsigned char fn;
	51	const char *name;
	52	};
	53
	54	/* PIIX4 SMBus address offsets */
	55	#define SMBHSTSTS (0 + piix4_smba)
	56	#define SMBHSLVSTS (1 + piix4_smba)
	57	#define SMBHSTCNT (2 + piix4_smba)
	58	#define SMBHSTCMD (3 + piix4_smba)
	59	#define SMBHSTADD (4 + piix4_smba)
	60	#define SMBHSTDAT0 (5 + piix4_smba)
	61	#define SMBHSTDAT1 (6 + piix4_smba)
	62	#define SMBBLKDAT (7 + piix4_smba)
	63	#define SMBSLVCNT (8 + piix4_smba)
	64	#define SMBSHDWCMD (9 + piix4_smba)
	65	#define SMBSLVEVT (0xA + piix4_smba)
	66	#define SMBSLVDAT (0xC + piix4_smba)
	67
	68	/* count for request_region */
	69	#define SMBIOSIZE 8
	70
	71	/* PCI Address Constants */
	72	#define SMBBA 0x090
	73	#define SMBHSTCFG 0x0D2
	74	#define SMBSLVC 0x0D3
	75	#define SMBSHDW1 0x0D4
	76	#define SMBSHDW2 0x0D5
	77	#define SMBREV 0x0D6
	78
	79	/* Other settings */
	80	#define MAX_TIMEOUT 500
	81	#define ENABLE_INT9 0
	82
	83	/* PIIX4 constants */
	84	#define PIIX4_QUICK 0x00
	85	#define PIIX4_BYTE 0x04
	86	#define PIIX4_BYTE_DATA 0x08
	87	#define PIIX4_WORD_DATA 0x0C
	88	#define PIIX4_BLOCK_DATA 0x14
	89
	90	/* insmod parameters */
	91
	92	/* If force is set to anything different from 0, we forcibly enable the
	93	PIIX4. DANGEROUS! */
60507095	94	static int force;
1da177e4 LT	95	module_param (force, int, 0);
	96	MODULE_PARM_DESC(force, "Forcibly enable the PIIX4. DANGEROUS!");
	97
	98	/* If force_addr is set to anything different from 0, we forcibly enable
	99	the PIIX4 at the given address. VERY DANGEROUS! */
60507095	100	static int force_addr;
1da177e4 LT	101	module_param (force_addr, int, 0);
	102	MODULE_PARM_DESC(force_addr,
	103	"Forcibly enable the PIIX4 at the given address. "
	104	"EXTREMELY DANGEROUS!");
	105
1da177e4 LT	106	static int piix4_transaction(void);
1da177e4 LT	107
60507095	108	static unsigned short piix4_smba;
d6072f84	109	static struct pci_driver piix4_driver;
1da177e4 LT	110	static struct i2c_adapter piix4_adapter;
	111
	112	static struct dmi_system_id __devinitdata piix4_dmi_table[] = {
	113	{
	114	.ident = "IBM",
	115	.matches = { DMI_MATCH(DMI_SYS_VENDOR, "IBM"), },
	116	},
	117	{ },
	118	};
	119
	120	static int __devinit piix4_setup(struct pci_dev *PIIX4_dev,
	121	const struct pci_device_id *id)
	122	{
	123	unsigned char temp;
	124
	125	/* match up the function */
	126	if (PCI_FUNC(PIIX4_dev->devfn) != id->driver_data)
	127	return -ENODEV;
	128
	129	dev_info(&PIIX4_dev->dev, "Found %s device\n", pci_name(PIIX4_dev));
	130
	131	/* Don't access SMBus on IBM systems which get corrupted eeproms */
	132	if (dmi_check_system(piix4_dmi_table) &&
	133	PIIX4_dev->vendor == PCI_VENDOR_ID_INTEL) {
f9ba6c04	134	dev_err(&PIIX4_dev->dev, "IBM system detected; this module "
1da177e4 LT	135	"may corrupt your serial eeprom! Refusing to load "
	136	"module!\n");
	137	return -EPERM;
	138	}
	139
	140	/* Determine the address of the SMBus areas */
	141	if (force_addr) {
	142	piix4_smba = force_addr & 0xfff0;
	143	force = 0;
	144	} else {
	145	pci_read_config_word(PIIX4_dev, SMBBA, &piix4_smba);
	146	piix4_smba &= 0xfff0;
	147	if(piix4_smba == 0) {
	148	dev_err(&PIIX4_dev->dev, "SMB base address "
	149	"uninitialized - upgrade BIOS or use "
	150	"force_addr=0xaddr\n");
	151	return -ENODEV;
	152	}
	153	}
	154
d6072f84	155	if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) {
1da177e4 LT	156	dev_err(&PIIX4_dev->dev, "SMB region 0x%x already in use!\n",
	157	piix4_smba);
	158	return -ENODEV;
	159	}
	160
	161	pci_read_config_byte(PIIX4_dev, SMBHSTCFG, &temp);
	162
1da177e4 LT	163	/* If force_addr is set, we program the new address here. Just to make
	164	sure, we disable the PIIX4 first. */
	165	if (force_addr) {
	166	pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp & 0xfe);
	167	pci_write_config_word(PIIX4_dev, SMBBA, piix4_smba);
	168	pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp \| 0x01);
	169	dev_info(&PIIX4_dev->dev, "WARNING: SMBus interface set to "
	170	"new address %04x!\n", piix4_smba);
	171	} else if ((temp & 1) == 0) {
	172	if (force) {
	173	/* This should never need to be done, but has been
	174	* noted that many Dell machines have the SMBus
	175	* interface on the PIIX4 disabled!? NOTE: This assumes
	176	* I/O space and other allocations WERE done by the
	177	* Bios! Don't complain if your hardware does weird
	178	* things after enabling this. :') Check for Bios
	179	* updates before resorting to this.
	180	*/
	181	pci_write_config_byte(PIIX4_dev, SMBHSTCFG,
	182	temp \| 1);
	183	dev_printk(KERN_NOTICE, &PIIX4_dev->dev,
	184	"WARNING: SMBus interface has been "
	185	"FORCEFULLY ENABLED!\n");
	186	} else {
	187	dev_err(&PIIX4_dev->dev,
	188	"Host SMBus controller not enabled!\n");
	189	release_region(piix4_smba, SMBIOSIZE);
	190	piix4_smba = 0;
	191	return -ENODEV;
	192	}
	193	}
	194
54aaa1ca	195	if (((temp & 0x0E) == 8) \|\| ((temp & 0x0E) == 2))
1da177e4 LT	196	dev_dbg(&PIIX4_dev->dev, "Using Interrupt 9 for SMBus.\n");
	197	else if ((temp & 0x0E) == 0)
	198	dev_dbg(&PIIX4_dev->dev, "Using Interrupt SMI# for SMBus.\n");
	199	else
	200	dev_err(&PIIX4_dev->dev, "Illegal Interrupt configuration "
	201	"(or code out of date)!\n");
	202
	203	pci_read_config_byte(PIIX4_dev, SMBREV, &temp);
	204	dev_dbg(&PIIX4_dev->dev, "SMBREV = 0x%X\n", temp);
	205	dev_dbg(&PIIX4_dev->dev, "SMBA = 0x%X\n", piix4_smba);
	206
	207	return 0;
	208	}
	209
	210	/* Another internally used function */
	211	static int piix4_transaction(void)
	212	{
	213	int temp;
	214	int result = 0;
	215	int timeout = 0;
	216
	217	dev_dbg(&piix4_adapter.dev, "Transaction (pre): CNT=%02x, CMD=%02x, "
	218	"ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
	219	inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
	220	inb_p(SMBHSTDAT1));
	221
	222	/* Make sure the SMBus host is ready to start transmitting */
	223	if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
	224	dev_dbg(&piix4_adapter.dev, "SMBus busy (%02x). "
541e6a02	225	"Resetting...\n", temp);
1da177e4 LT	226	outb_p(temp, SMBHSTSTS);
	227	if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
	228	dev_err(&piix4_adapter.dev, "Failed! (%02x)\n", temp);
	229	return -1;
	230	} else {
	231	dev_dbg(&piix4_adapter.dev, "Successfull!\n");
	232	}
	233	}
	234
	235	/* start the transaction by setting bit 6 */
	236	outb_p(inb(SMBHSTCNT) \| 0x040, SMBHSTCNT);
	237
	238	/* We will always wait for a fraction of a second! (See PIIX4 docs errata) */
	239	do {
	240	msleep(1);
	241	temp = inb_p(SMBHSTSTS);
	242	} while ((temp & 0x01) && (timeout++ < MAX_TIMEOUT));
	243
	244	/* If the SMBus is still busy, we give up */
	245	if (timeout >= MAX_TIMEOUT) {
	246	dev_err(&piix4_adapter.dev, "SMBus Timeout!\n");
	247	result = -1;
	248	}
	249
	250	if (temp & 0x10) {
	251	result = -1;
	252	dev_err(&piix4_adapter.dev, "Error: Failed bus transaction\n");
	253	}
	254
	255	if (temp & 0x08) {
	256	result = -1;
	257	dev_dbg(&piix4_adapter.dev, "Bus collision! SMBus may be "
	258	"locked until next hard reset. (sorry!)\n");
	259	/* Clock stops and slave is stuck in mid-transmission */
	260	}
	261
	262	if (temp & 0x04) {
	263	result = -1;
	264	dev_dbg(&piix4_adapter.dev, "Error: no response!\n");
	265	}
	266
	267	if (inb_p(SMBHSTSTS) != 0x00)
	268	outb_p(inb(SMBHSTSTS), SMBHSTSTS);
	269
	270	if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
	271	dev_err(&piix4_adapter.dev, "Failed reset at end of "
	272	"transaction (%02x)\n", temp);
	273	}
	274	dev_dbg(&piix4_adapter.dev, "Transaction (post): CNT=%02x, CMD=%02x, "
	275	"ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
	276	inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
	277	inb_p(SMBHSTDAT1));
	278	return result;
	279	}
	280
	281	/* Return -1 on error. */
	282	static s32 piix4_access(struct i2c_adapter * adap, u16 addr,
	283	unsigned short flags, char read_write,
	284	u8 command, int size, union i2c_smbus_data * data)
	285	{
	286	int i, len;
	287
	288	switch (size) {
	289	case I2C_SMBUS_PROC_CALL:
290	dev_err(&adap->dev, "I2C_SMBUS_PROC_CALL not supported!\n");
291	return -1;
292	case I2C_SMBUS_QUICK:
293	outb_p(((addr & 0x7f) << 1) \| (read_write & 0x01),
294	SMBHSTADD);
295	size = PIIX4_QUICK;
296	break;
297	case I2C_SMBUS_BYTE:
298	outb_p(((addr & 0x7f) << 1) \| (read_write & 0x01),
299	SMBHSTADD);
300	if (read_write == I2C_SMBUS_WRITE)
301	outb_p(command, SMBHSTCMD);
302	size = PIIX4_BYTE;
303	break;
304	case I2C_SMBUS_BYTE_DATA:
305	outb_p(((addr & 0x7f) << 1) \| (read_write & 0x01),
306	SMBHSTADD);
307	outb_p(command, SMBHSTCMD);
308	if (read_write == I2C_SMBUS_WRITE)
309	outb_p(data->byte, SMBHSTDAT0);
310	size = PIIX4_BYTE_DATA;
311	break;
312	case I2C_SMBUS_WORD_DATA:
313	outb_p(((addr & 0x7f) << 1) \| (read_write & 0x01),
314	SMBHSTADD);
315	outb_p(command, SMBHSTCMD);
316	if (read_write == I2C_SMBUS_WRITE) {
317	outb_p(data->word & 0xff, SMBHSTDAT0);
318	outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1);
319	}
320	size = PIIX4_WORD_DATA;
321	break;
322	case I2C_SMBUS_BLOCK_DATA:
323	outb_p(((addr & 0x7f) << 1) \| (read_write & 0x01),
324	SMBHSTADD);
325	outb_p(command, SMBHSTCMD);
326	if (read_write == I2C_SMBUS_WRITE) {
327	len = data->block[0];
328	if (len < 0)
329	len = 0;
330	if (len > 32)
331	len = 32;
332	outb_p(len, SMBHSTDAT0);
333	i = inb_p(SMBHSTCNT); /* Reset SMBBLKDAT */
334	for (i = 1; i <= len; i++)
335	outb_p(data->block[i], SMBBLKDAT);
336	}
337	size = PIIX4_BLOCK_DATA;
338	break;
339	}
340
341	outb_p((size & 0x1C) + (ENABLE_INT9 & 1), SMBHSTCNT);
342
343	if (piix4_transaction()) /* Error in transaction */
344	return -1;
345
346	if ((read_write == I2C_SMBUS_WRITE) \|\| (size == PIIX4_QUICK))
347	return 0;
348
349
350	switch (size) {
351	case PIIX4_BYTE: /* Where is the result put? I assume here it is in
352	SMBHSTDAT0 but it might just as well be in the
353	SMBHSTCMD. No clue in the docs */
354
355	data->byte = inb_p(SMBHSTDAT0);
356	break;
357	case PIIX4_BYTE_DATA:
358	data->byte = inb_p(SMBHSTDAT0);
359	break;
360	case PIIX4_WORD_DATA:
361	data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8);
362	break;
363	case PIIX4_BLOCK_DATA:
364	data->block[0] = inb_p(SMBHSTDAT0);
365	i = inb_p(SMBHSTCNT); /* Reset SMBBLKDAT */
366	for (i = 1; i <= data->block[0]; i++)
367	data->block[i] = inb_p(SMBBLKDAT);
368	break;
369	}
370	return 0;
371	}
372
373	static u32 piix4_func(struct i2c_adapter *adapter)
374	{
375	return I2C_FUNC_SMBUS_QUICK \| I2C_FUNC_SMBUS_BYTE \|
376	I2C_FUNC_SMBUS_BYTE_DATA \| I2C_FUNC_SMBUS_WORD_DATA \|
377	I2C_FUNC_SMBUS_BLOCK_DATA;
378	}
379
8f9082c5	380	static const struct i2c_algorithm smbus_algorithm = {
1da177e4 LT	381	.smbus_xfer = piix4_access,
	382	.functionality = piix4_func,
	383	};
	384
	385	static struct i2c_adapter piix4_adapter = {
	386	.owner = THIS_MODULE,
9ace555d	387	.id = I2C_HW_SMBUS_PIIX4,
1da177e4 LT	388	.class = I2C_CLASS_HWMON,
1da177e4 LT	389	.algo = &smbus_algorithm,
1da177e4 LT	390	};
	391
	392	static struct pci_device_id piix4_ids[] = {
	393	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3),
	394	.driver_data = 3 },
02e0c5d5 RM	395	{ PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP200_SMBUS),
	396	.driver_data = 0 },
	397	{ PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP300_SMBUS),
	398	.driver_data = 0 },
	399	{ PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS),
	400	.driver_data = 0 },
4e6697fc JD	401	{ PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SMBUS),
4e6697fc JD	402	.driver_data = 0 },
1da177e4 LT	403	{ PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4),
	404	.driver_data = 0 },
	405	{ PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5),
	406	.driver_data = 0 },
	407	{ PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6),
	408	.driver_data = 0 },
5f7ea3c5 MD	409	{ PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB),
5f7ea3c5 MD	410	.driver_data = 0 },
1da177e4 LT	411	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3),
	412	.driver_data = 3 },
	413	{ PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_3),
	414	.driver_data = 0 },
	415	{ 0, }
	416	};
	417
	418	MODULE_DEVICE_TABLE (pci, piix4_ids);
	419
	420	static int __devinit piix4_probe(struct pci_dev *dev,
	421	const struct pci_device_id *id)
	422	{
	423	int retval;
	424
	425	retval = piix4_setup(dev, id);
	426	if (retval)
	427	return retval;
	428
	429	/* set up the driverfs linkage to our parent device */
	430	piix4_adapter.dev.parent = &dev->dev;
	431
	432	snprintf(piix4_adapter.name, I2C_NAME_SIZE,
	433	"SMBus PIIX4 adapter at %04x", piix4_smba);
	434
	435	if ((retval = i2c_add_adapter(&piix4_adapter))) {
	436	dev_err(&dev->dev, "Couldn't register adapter!\n");
	437	release_region(piix4_smba, SMBIOSIZE);
	438	piix4_smba = 0;
	439	}
	440
	441	return retval;
	442	}
	443
	444	static void __devexit piix4_remove(struct pci_dev *dev)
	445	{
	446	if (piix4_smba) {
	447	i2c_del_adapter(&piix4_adapter);
	448	release_region(piix4_smba, SMBIOSIZE);
	449	piix4_smba = 0;
	450	}
	451	}
	452
	453	static struct pci_driver piix4_driver = {
	454	.name = "piix4_smbus",
	455	.id_table = piix4_ids,
	456	.probe = piix4_probe,
	457	.remove = __devexit_p(piix4_remove),
	458	};
	459
	460	static int __init i2c_piix4_init(void)
	461	{
	462	return pci_register_driver(&piix4_driver);
	463	}
	464
	465	static void __exit i2c_piix4_exit(void)
	466	{
	467	pci_unregister_driver(&piix4_driver);
	468	}
	469
	470	MODULE_AUTHOR("Frodo Looijaard <frodol@dds.nl> and "
	471	"Philip Edelbrock <phil@netroedge.com>");
	472	MODULE_DESCRIPTION("PIIX4 SMBus driver");
	473	MODULE_LICENSE("GPL");
	474
475	module_init(i2c_piix4_init);
476	module_exit(i2c_piix4_exit);