[deliverable/linux.git] / drivers / i2c / busses / i2c-piix4.c

/*
    Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl> and
    Philip Edelbrock <phil@netroedge.com>

    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 2 of the License, or
    (at your option) any later version.

    This program is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.

    You should have received a copy of the GNU General Public License
    along with this program; if not, write to the Free Software
    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/

/*
   Supports:
	Intel PIIX4, 440MX
	Serverworks OSB4, CSB5, CSB6, HT-1000, HT-1100
	ATI IXP200, IXP300, IXP400, SB600, SB700, SB800
	AMD Hudson-2
	SMSC Victory66

   Note: we assume there can only be one device, with one SMBus interface.
*/

#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/stddef.h>
#include <linux/ioport.h>
#include <linux/i2c.h>
#include <linux/init.h>
#include <linux/dmi.h>
#include <linux/acpi.h>
#include <linux/io.h>


/* PIIX4 SMBus address offsets */
#define SMBHSTSTS	(0 + piix4_smba)
#define SMBHSLVSTS	(1 + piix4_smba)
#define SMBHSTCNT	(2 + piix4_smba)
#define SMBHSTCMD	(3 + piix4_smba)
#define SMBHSTADD	(4 + piix4_smba)
#define SMBHSTDAT0	(5 + piix4_smba)
#define SMBHSTDAT1	(6 + piix4_smba)
#define SMBBLKDAT	(7 + piix4_smba)
#define SMBSLVCNT	(8 + piix4_smba)
#define SMBSHDWCMD	(9 + piix4_smba)
#define SMBSLVEVT	(0xA + piix4_smba)
#define SMBSLVDAT	(0xC + piix4_smba)

/* count for request_region */
#define SMBIOSIZE	8

/* PCI Address Constants */
#define SMBBA		0x090
#define SMBHSTCFG	0x0D2
#define SMBSLVC		0x0D3
#define SMBSHDW1	0x0D4
#define SMBSHDW2	0x0D5
#define SMBREV		0x0D6

/* Other settings */
#define MAX_TIMEOUT	500
#define  ENABLE_INT9	0

/* PIIX4 constants */
#define PIIX4_QUICK		0x00
#define PIIX4_BYTE		0x04
#define PIIX4_BYTE_DATA		0x08
#define PIIX4_WORD_DATA		0x0C
#define PIIX4_BLOCK_DATA	0x14

/* insmod parameters */

/* If force is set to anything different from 0, we forcibly enable the
   PIIX4. DANGEROUS! */
static int force;
module_param (force, int, 0);
MODULE_PARM_DESC(force, "Forcibly enable the PIIX4. DANGEROUS!");

/* If force_addr is set to anything different from 0, we forcibly enable
   the PIIX4 at the given address. VERY DANGEROUS! */
static int force_addr;
module_param (force_addr, int, 0);
MODULE_PARM_DESC(force_addr,
		 "Forcibly enable the PIIX4 at the given address. "
		 "EXTREMELY DANGEROUS!");

static int srvrworks_csb5_delay;
static struct pci_driver piix4_driver;

static struct dmi_system_id __devinitdata piix4_dmi_blacklist[] = {
	{
		.ident = "Sapphire AM2RD790",
		.matches = {
			DMI_MATCH(DMI_BOARD_VENDOR, "SAPPHIRE Inc."),
			DMI_MATCH(DMI_BOARD_NAME, "PC-AM2RD790"),
		},
	},
	{
		.ident = "DFI Lanparty UT 790FX",
		.matches = {
			DMI_MATCH(DMI_BOARD_VENDOR, "DFI Inc."),
			DMI_MATCH(DMI_BOARD_NAME, "LP UT 790FX"),
		},
	},
	{ }
};

/* The IBM entry is in a separate table because we only check it
   on Intel-based systems */
static struct dmi_system_id __devinitdata piix4_dmi_ibm[] = {
	{
		.ident = "IBM",
		.matches = { DMI_MATCH(DMI_SYS_VENDOR, "IBM"), },
	},
	{ },
};

struct i2c_piix4_adapdata {
	unsigned short smba;
};

static int __devinit piix4_setup(struct pci_dev *PIIX4_dev,
				const struct pci_device_id *id)
{
	unsigned char temp;
	unsigned short piix4_smba;

	if ((PIIX4_dev->vendor == PCI_VENDOR_ID_SERVERWORKS) &&
	    (PIIX4_dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5))
		srvrworks_csb5_delay = 1;

	/* On some motherboards, it was reported that accessing the SMBus
	   caused severe hardware problems */
	if (dmi_check_system(piix4_dmi_blacklist)) {
		dev_err(&PIIX4_dev->dev,
			"Accessing the SMBus on this system is unsafe!\n");
		return -EPERM;
	}

	/* Don't access SMBus on IBM systems which get corrupted eeproms */
	if (dmi_check_system(piix4_dmi_ibm) &&
			PIIX4_dev->vendor == PCI_VENDOR_ID_INTEL) {
		dev_err(&PIIX4_dev->dev, "IBM system detected; this module "
			"may corrupt your serial eeprom! Refusing to load "
			"module!\n");
		return -EPERM;
	}

	/* Determine the address of the SMBus areas */
	if (force_addr) {
		piix4_smba = force_addr & 0xfff0;
		force = 0;
	} else {
		pci_read_config_word(PIIX4_dev, SMBBA, &piix4_smba);
		piix4_smba &= 0xfff0;
		if(piix4_smba == 0) {
			dev_err(&PIIX4_dev->dev, "SMBus base address "
				"uninitialized - upgrade BIOS or use "
				"force_addr=0xaddr\n");
			return -ENODEV;
		}
	}

	if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name))
		return -ENODEV;

	if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) {
		dev_err(&PIIX4_dev->dev, "SMBus region 0x%x already in use!\n",
			piix4_smba);
		return -EBUSY;
	}

	pci_read_config_byte(PIIX4_dev, SMBHSTCFG, &temp);

	/* If force_addr is set, we program the new address here. Just to make
	   sure, we disable the PIIX4 first. */
	if (force_addr) {
		pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp & 0xfe);
		pci_write_config_word(PIIX4_dev, SMBBA, piix4_smba);
		pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp | 0x01);
		dev_info(&PIIX4_dev->dev, "WARNING: SMBus interface set to "
			"new address %04x!\n", piix4_smba);
	} else if ((temp & 1) == 0) {
		if (force) {
			/* This should never need to be done, but has been
			 * noted that many Dell machines have the SMBus
			 * interface on the PIIX4 disabled!? NOTE: This assumes
			 * I/O space and other allocations WERE done by the
			 * Bios!  Don't complain if your hardware does weird
			 * things after enabling this. :') Check for Bios
			 * updates before resorting to this.
			 */
			pci_write_config_byte(PIIX4_dev, SMBHSTCFG,
					      temp | 1);
			dev_printk(KERN_NOTICE, &PIIX4_dev->dev,
				"WARNING: SMBus interface has been "
				"FORCEFULLY ENABLED!\n");
		} else {
			dev_err(&PIIX4_dev->dev,
				"Host SMBus controller not enabled!\n");
			release_region(piix4_smba, SMBIOSIZE);
			return -ENODEV;
		}
	}

	if (((temp & 0x0E) == 8) || ((temp & 0x0E) == 2))
		dev_dbg(&PIIX4_dev->dev, "Using Interrupt 9 for SMBus.\n");
	else if ((temp & 0x0E) == 0)
		dev_dbg(&PIIX4_dev->dev, "Using Interrupt SMI# for SMBus.\n");
	else
		dev_err(&PIIX4_dev->dev, "Illegal Interrupt configuration "
			"(or code out of date)!\n");

	pci_read_config_byte(PIIX4_dev, SMBREV, &temp);
	dev_info(&PIIX4_dev->dev,
		 "SMBus Host Controller at 0x%x, revision %d\n",
		 piix4_smba, temp);

	return piix4_smba;
}

static int __devinit piix4_setup_sb800(struct pci_dev *PIIX4_dev,
				const struct pci_device_id *id)
{
	unsigned short piix4_smba;
	unsigned short smba_idx = 0xcd6;
	u8 smba_en_lo, smba_en_hi, i2ccfg, i2ccfg_offset = 0x10, smb_en = 0x2c;

	/* SB800 and later SMBus does not support forcing address */
	if (force || force_addr) {
		dev_err(&PIIX4_dev->dev, "SMBus does not support "
			"forcing address!\n");
		return -EINVAL;
	}

	/* Determine the address of the SMBus areas */
	if (!request_region(smba_idx, 2, "smba_idx")) {
		dev_err(&PIIX4_dev->dev, "SMBus base address index region "
			"0x%x already in use!\n", smba_idx);
		return -EBUSY;
	}
	outb_p(smb_en, smba_idx);
	smba_en_lo = inb_p(smba_idx + 1);
	outb_p(smb_en + 1, smba_idx);
	smba_en_hi = inb_p(smba_idx + 1);
	release_region(smba_idx, 2);

	if ((smba_en_lo & 1) == 0) {
		dev_err(&PIIX4_dev->dev,
			"Host SMBus controller not enabled!\n");
		return -ENODEV;
	}

	piix4_smba = ((smba_en_hi << 8) | smba_en_lo) & 0xffe0;
	if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name))
		return -ENODEV;

	if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) {
		dev_err(&PIIX4_dev->dev, "SMBus region 0x%x already in use!\n",
			piix4_smba);
		return -EBUSY;
	}

	/* Request the SMBus I2C bus config region */
	if (!request_region(piix4_smba + i2ccfg_offset, 1, "i2ccfg")) {
		dev_err(&PIIX4_dev->dev, "SMBus I2C bus config region "
			"0x%x already in use!\n", piix4_smba + i2ccfg_offset);
		release_region(piix4_smba, SMBIOSIZE);
		return -EBUSY;
	}
	i2ccfg = inb_p(piix4_smba + i2ccfg_offset);
	release_region(piix4_smba + i2ccfg_offset, 1);

	if (i2ccfg & 1)
		dev_dbg(&PIIX4_dev->dev, "Using IRQ for SMBus.\n");
	else
		dev_dbg(&PIIX4_dev->dev, "Using SMI# for SMBus.\n");

	dev_info(&PIIX4_dev->dev,
		 "SMBus Host Controller at 0x%x, revision %d\n",
		 piix4_smba, i2ccfg >> 4);

	return piix4_smba;
}

static int piix4_transaction(struct i2c_adapter *piix4_adapter)
{
	struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(piix4_adapter);
	unsigned short piix4_smba = adapdata->smba;
	int temp;
	int result = 0;
	int timeout = 0;

	dev_dbg(&piix4_adapter->dev, "Transaction (pre): CNT=%02x, CMD=%02x, "
		"ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
		inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
		inb_p(SMBHSTDAT1));

	/* Make sure the SMBus host is ready to start transmitting */
	if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
		dev_dbg(&piix4_adapter->dev, "SMBus busy (%02x). "
			"Resetting...\n", temp);
		outb_p(temp, SMBHSTSTS);
		if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
			dev_err(&piix4_adapter->dev, "Failed! (%02x)\n", temp);
			return -EBUSY;
		} else {
			dev_dbg(&piix4_adapter->dev, "Successful!\n");
		}
	}

	/* start the transaction by setting bit 6 */
	outb_p(inb(SMBHSTCNT) | 0x040, SMBHSTCNT);

	/* We will always wait for a fraction of a second! (See PIIX4 docs errata) */
	if (srvrworks_csb5_delay) /* Extra delay for SERVERWORKS_CSB5 */
		msleep(2);
	else
		msleep(1);

	while ((++timeout < MAX_TIMEOUT) &&
	       ((temp = inb_p(SMBHSTSTS)) & 0x01))
		msleep(1);

	/* If the SMBus is still busy, we give up */
	if (timeout == MAX_TIMEOUT) {
		dev_err(&piix4_adapter->dev, "SMBus Timeout!\n");
		result = -ETIMEDOUT;
	}

	if (temp & 0x10) {
		result = -EIO;
		dev_err(&piix4_adapter->dev, "Error: Failed bus transaction\n");
	}

	if (temp & 0x08) {
		result = -EIO;
		dev_dbg(&piix4_adapter->dev, "Bus collision! SMBus may be "
			"locked until next hard reset. (sorry!)\n");
		/* Clock stops and slave is stuck in mid-transmission */
	}

	if (temp & 0x04) {
		result = -ENXIO;
		dev_dbg(&piix4_adapter->dev, "Error: no response!\n");
	}

	if (inb_p(SMBHSTSTS) != 0x00)
		outb_p(inb(SMBHSTSTS), SMBHSTSTS);

	if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
		dev_err(&piix4_adapter->dev, "Failed reset at end of "
			"transaction (%02x)\n", temp);
	}
	dev_dbg(&piix4_adapter->dev, "Transaction (post): CNT=%02x, CMD=%02x, "
		"ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
		inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
		inb_p(SMBHSTDAT1));
	return result;
}

/* Return negative errno on error. */
static s32 piix4_access(struct i2c_adapter * adap, u16 addr,
		 unsigned short flags, char read_write,
		 u8 command, int size, union i2c_smbus_data * data)
{
	struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap);
	unsigned short piix4_smba = adapdata->smba;
	int i, len;
	int status;

	switch (size) {
	case I2C_SMBUS_QUICK:
		outb_p((addr << 1) | read_write,
		       SMBHSTADD);
		size = PIIX4_QUICK;
		break;
	case I2C_SMBUS_BYTE:
		outb_p((addr << 1) | read_write,
		       SMBHSTADD);
		if (read_write == I2C_SMBUS_WRITE)
			outb_p(command, SMBHSTCMD);
		size = PIIX4_BYTE;
		break;
	case I2C_SMBUS_BYTE_DATA:
		outb_p((addr << 1) | read_write,
		       SMBHSTADD);
		outb_p(command, SMBHSTCMD);
		if (read_write == I2C_SMBUS_WRITE)
			outb_p(data->byte, SMBHSTDAT0);
		size = PIIX4_BYTE_DATA;
		break;
	case I2C_SMBUS_WORD_DATA:
		outb_p((addr << 1) | read_write,
		       SMBHSTADD);
		outb_p(command, SMBHSTCMD);
		if (read_write == I2C_SMBUS_WRITE) {
			outb_p(data->word & 0xff, SMBHSTDAT0);
			outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1);
		}
		size = PIIX4_WORD_DATA;
		break;
	case I2C_SMBUS_BLOCK_DATA:
		outb_p((addr << 1) | read_write,
		       SMBHSTADD);
		outb_p(command, SMBHSTCMD);
		if (read_write == I2C_SMBUS_WRITE) {
			len = data->block[0];
			if (len == 0 || len > I2C_SMBUS_BLOCK_MAX)
				return -EINVAL;
			outb_p(len, SMBHSTDAT0);
			i = inb_p(SMBHSTCNT);	/* Reset SMBBLKDAT */
			for (i = 1; i <= len; i++)
				outb_p(data->block[i], SMBBLKDAT);
		}
		size = PIIX4_BLOCK_DATA;
		break;
	default:
		dev_warn(&adap->dev, "Unsupported transaction %d\n", size);
		return -EOPNOTSUPP;
	}

	outb_p((size & 0x1C) + (ENABLE_INT9 & 1), SMBHSTCNT);

	status = piix4_transaction(adap);
	if (status)
		return status;

	if ((read_write == I2C_SMBUS_WRITE) || (size == PIIX4_QUICK))
		return 0;


	switch (size) {
	case PIIX4_BYTE:
	case PIIX4_BYTE_DATA:
		data->byte = inb_p(SMBHSTDAT0);
		break;
	case PIIX4_WORD_DATA:
		data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8);
		break;
	case PIIX4_BLOCK_DATA:
		data->block[0] = inb_p(SMBHSTDAT0);
		if (data->block[0] == 0 || data->block[0] > I2C_SMBUS_BLOCK_MAX)
			return -EPROTO;
		i = inb_p(SMBHSTCNT);	/* Reset SMBBLKDAT */
		for (i = 1; i <= data->block[0]; i++)
			data->block[i] = inb_p(SMBBLKDAT);
		break;
	}
	return 0;
}

static u32 piix4_func(struct i2c_adapter *adapter)
{
	return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
	    I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
	    I2C_FUNC_SMBUS_BLOCK_DATA;
}

static const struct i2c_algorithm smbus_algorithm = {
	.smbus_xfer	= piix4_access,
	.functionality	= piix4_func,
};

static DEFINE_PCI_DEVICE_TABLE(piix4_ids) = {
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3) },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3) },
	{ PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_3) },
	{ PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP200_SMBUS) },
	{ PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP300_SMBUS) },
	{ PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS) },
	{ PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS) },
	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SMBUS) },
	{ PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
		     PCI_DEVICE_ID_SERVERWORKS_OSB4) },
	{ PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
		     PCI_DEVICE_ID_SERVERWORKS_CSB5) },
	{ PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
		     PCI_DEVICE_ID_SERVERWORKS_CSB6) },
	{ PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
		     PCI_DEVICE_ID_SERVERWORKS_HT1000SB) },
	{ PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
		     PCI_DEVICE_ID_SERVERWORKS_HT1100LD) },
	{ 0, }
};

MODULE_DEVICE_TABLE (pci, piix4_ids);

static struct i2c_adapter *piix4_main_adapter;

static int __devinit piix4_add_adapter(struct pci_dev *dev,
					unsigned short smba,
					struct i2c_adapter **padap)
{
	struct i2c_adapter *adap;
	struct i2c_piix4_adapdata *adapdata;
	int retval;

	adap = kzalloc(sizeof(*adap), GFP_KERNEL);
	if (adap == NULL) {
		release_region(smba, SMBIOSIZE);
		return -ENOMEM;
	}

	adap->owner = THIS_MODULE;
	adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
	adap->algo = &smbus_algorithm;

	adapdata = kzalloc(sizeof(*adapdata), GFP_KERNEL);
	if (adapdata == NULL) {
		kfree(adap);
		release_region(smba, SMBIOSIZE);
		return -ENOMEM;
	}

	adapdata->smba = smba;

	/* set up the sysfs linkage to our parent device */
	adap->dev.parent = &dev->dev;

	snprintf(adap->name, sizeof(adap->name),
		"SMBus PIIX4 adapter at %04x", smba);

	i2c_set_adapdata(adap, adapdata);

	retval = i2c_add_adapter(adap);
	if (retval) {
		dev_err(&dev->dev, "Couldn't register adapter!\n");
		kfree(adapdata);
		kfree(adap);
		release_region(smba, SMBIOSIZE);
		return retval;
	}

	*padap = adap;
	return 0;
}

static int __devinit piix4_probe(struct pci_dev *dev,
				const struct pci_device_id *id)
{
	int retval;

	if ((dev->vendor == PCI_VENDOR_ID_ATI &&
	     dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS &&
	     dev->revision >= 0x40) ||
	    dev->vendor == PCI_VENDOR_ID_AMD)
		/* base address location etc changed in SB800 */
		retval = piix4_setup_sb800(dev, id);
	else
		retval = piix4_setup(dev, id);

	if (retval < 0)
		return retval;

	return piix4_add_adapter(dev, retval, &piix4_main_adapter);
}

static void __devexit piix4_adap_remove(struct i2c_adapter *adap)
{
	struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap);

	if (adapdata->smba) {
		i2c_del_adapter(adap);
		release_region(adapdata->smba, SMBIOSIZE);
		kfree(adapdata);
		kfree(adap);
	}
}

static void __devexit piix4_remove(struct pci_dev *dev)
{
	if (piix4_main_adapter) {
		piix4_adap_remove(piix4_main_adapter);
		piix4_main_adapter = NULL;
	}
}

static struct pci_driver piix4_driver = {
	.name		= "piix4_smbus",
	.id_table	= piix4_ids,
	.probe		= piix4_probe,
	.remove		= __devexit_p(piix4_remove),
};

module_pci_driver(piix4_driver);

MODULE_AUTHOR("Frodo Looijaard <frodol@dds.nl> and "
		"Philip Edelbrock <phil@netroedge.com>");
MODULE_DESCRIPTION("PIIX4 SMBus driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4	1	/*
1da177e4 LT	2	Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl> and
	3	Philip Edelbrock <phil@netroedge.com>
	4
	5	This program is free software; you can redistribute it and/or modify
	6	it under the terms of the GNU General Public License as published by
	7	the Free Software Foundation; either version 2 of the License, or
	8	(at your option) any later version.
	9
	10	This program is distributed in the hope that it will be useful,
	11	but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	GNU General Public License for more details.
	14
	15	You should have received a copy of the GNU General Public License
	16	along with this program; if not, write to the Free Software
	17	Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	18	*/
	19
	20	/*
	21	Supports:
	22	Intel PIIX4, 440MX
506a8b6c	23	Serverworks OSB4, CSB5, CSB6, HT-1000, HT-1100
60693e5a	24	ATI IXP200, IXP300, IXP400, SB600, SB700, SB800
3806e94b	25	AMD Hudson-2
1da177e4 LT	26	SMSC Victory66
	27
	28	Note: we assume there can only be one device, with one SMBus interface.
	29	*/
	30
1da177e4 LT	31	#include <linux/module.h>
	32	#include <linux/moduleparam.h>
	33	#include <linux/pci.h>
	34	#include <linux/kernel.h>
	35	#include <linux/delay.h>
	36	#include <linux/stddef.h>
1da177e4 LT	37	#include <linux/ioport.h>
	38	#include <linux/i2c.h>
	39	#include <linux/init.h>
1da177e4	40	#include <linux/dmi.h>
54fb4a05	41	#include <linux/acpi.h>
21782180	42	#include <linux/io.h>
1da177e4 LT	43
1da177e4 LT	44
1da177e4 LT	45	/* PIIX4 SMBus address offsets */
	46	#define SMBHSTSTS (0 + piix4_smba)
	47	#define SMBHSLVSTS (1 + piix4_smba)
	48	#define SMBHSTCNT (2 + piix4_smba)
	49	#define SMBHSTCMD (3 + piix4_smba)
	50	#define SMBHSTADD (4 + piix4_smba)
	51	#define SMBHSTDAT0 (5 + piix4_smba)
	52	#define SMBHSTDAT1 (6 + piix4_smba)
	53	#define SMBBLKDAT (7 + piix4_smba)
	54	#define SMBSLVCNT (8 + piix4_smba)
	55	#define SMBSHDWCMD (9 + piix4_smba)
	56	#define SMBSLVEVT (0xA + piix4_smba)
	57	#define SMBSLVDAT (0xC + piix4_smba)
	58
	59	/* count for request_region */
	60	#define SMBIOSIZE 8
	61
	62	/* PCI Address Constants */
	63	#define SMBBA 0x090
	64	#define SMBHSTCFG 0x0D2
	65	#define SMBSLVC 0x0D3
	66	#define SMBSHDW1 0x0D4
	67	#define SMBSHDW2 0x0D5
	68	#define SMBREV 0x0D6
	69
	70	/* Other settings */
	71	#define MAX_TIMEOUT 500
	72	#define ENABLE_INT9 0
	73
	74	/* PIIX4 constants */
	75	#define PIIX4_QUICK 0x00
	76	#define PIIX4_BYTE 0x04
	77	#define PIIX4_BYTE_DATA 0x08
	78	#define PIIX4_WORD_DATA 0x0C
	79	#define PIIX4_BLOCK_DATA 0x14
	80
	81	/* insmod parameters */
	82
	83	/* If force is set to anything different from 0, we forcibly enable the
	84	PIIX4. DANGEROUS! */
60507095	85	static int force;
1da177e4 LT	86	module_param (force, int, 0);
	87	MODULE_PARM_DESC(force, "Forcibly enable the PIIX4. DANGEROUS!");
	88
	89	/* If force_addr is set to anything different from 0, we forcibly enable
	90	the PIIX4 at the given address. VERY DANGEROUS! */
60507095	91	static int force_addr;
1da177e4 LT	92	module_param (force_addr, int, 0);
	93	MODULE_PARM_DESC(force_addr,
	94	"Forcibly enable the PIIX4 at the given address. "
	95	"EXTREMELY DANGEROUS!");
	96
b1c1759c	97	static int srvrworks_csb5_delay;
d6072f84	98	static struct pci_driver piix4_driver;
1da177e4	99
c2fc54fc JD	100	static struct dmi_system_id __devinitdata piix4_dmi_blacklist[] = {
	101	{
	102	.ident = "Sapphire AM2RD790",
	103	.matches = {
	104	DMI_MATCH(DMI_BOARD_VENDOR, "SAPPHIRE Inc."),
	105	DMI_MATCH(DMI_BOARD_NAME, "PC-AM2RD790"),
	106	},
	107	},
	108	{
	109	.ident = "DFI Lanparty UT 790FX",
	110	.matches = {
	111	DMI_MATCH(DMI_BOARD_VENDOR, "DFI Inc."),
	112	DMI_MATCH(DMI_BOARD_NAME, "LP UT 790FX"),
	113	},
	114	},
	115	{ }
	116	};
	117
	118	/* The IBM entry is in a separate table because we only check it
	119	on Intel-based systems */
	120	static struct dmi_system_id __devinitdata piix4_dmi_ibm[] = {
1da177e4 LT	121	{
	122	.ident = "IBM",
	123	.matches = { DMI_MATCH(DMI_SYS_VENDOR, "IBM"), },
	124	},
	125	{ },
	126	};
	127
14a8086d AA	128	struct i2c_piix4_adapdata {
	129	unsigned short smba;
	130	};
	131
1da177e4 LT	132	static int __devinit piix4_setup(struct pci_dev *PIIX4_dev,
	133	const struct pci_device_id *id)
	134	{
	135	unsigned char temp;
14a8086d	136	unsigned short piix4_smba;
1da177e4	137
b1c1759c DM	138	if ((PIIX4_dev->vendor == PCI_VENDOR_ID_SERVERWORKS) &&
	139	(PIIX4_dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5))
	140	srvrworks_csb5_delay = 1;
	141
c2fc54fc JD	142	/* On some motherboards, it was reported that accessing the SMBus
	143	caused severe hardware problems */
	144	if (dmi_check_system(piix4_dmi_blacklist)) {
	145	dev_err(&PIIX4_dev->dev,
	146	"Accessing the SMBus on this system is unsafe!\n");
	147	return -EPERM;
	148	}
	149
1da177e4	150	/* Don't access SMBus on IBM systems which get corrupted eeproms */
c2fc54fc	151	if (dmi_check_system(piix4_dmi_ibm) &&
1da177e4	152	PIIX4_dev->vendor == PCI_VENDOR_ID_INTEL) {
f9ba6c04	153	dev_err(&PIIX4_dev->dev, "IBM system detected; this module "
1da177e4 LT	154	"may corrupt your serial eeprom! Refusing to load "
	155	"module!\n");
	156	return -EPERM;
	157	}
	158
	159	/* Determine the address of the SMBus areas */
	160	if (force_addr) {
	161	piix4_smba = force_addr & 0xfff0;
	162	force = 0;
	163	} else {
	164	pci_read_config_word(PIIX4_dev, SMBBA, &piix4_smba);
	165	piix4_smba &= 0xfff0;
	166	if(piix4_smba == 0) {
fa63cd56	167	dev_err(&PIIX4_dev->dev, "SMBus base address "
1da177e4 LT	168	"uninitialized - upgrade BIOS or use "
	169	"force_addr=0xaddr\n");
	170	return -ENODEV;
	171	}
	172	}
	173
54fb4a05	174	if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name))
18669eab	175	return -ENODEV;
54fb4a05	176
d6072f84	177	if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) {
fa63cd56	178	dev_err(&PIIX4_dev->dev, "SMBus region 0x%x already in use!\n",
1da177e4	179	piix4_smba);
fa63cd56	180	return -EBUSY;
1da177e4 LT	181	}
	182
	183	pci_read_config_byte(PIIX4_dev, SMBHSTCFG, &temp);
	184
1da177e4 LT	185	/* If force_addr is set, we program the new address here. Just to make
	186	sure, we disable the PIIX4 first. */
	187	if (force_addr) {
	188	pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp & 0xfe);
	189	pci_write_config_word(PIIX4_dev, SMBBA, piix4_smba);
	190	pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp \| 0x01);
	191	dev_info(&PIIX4_dev->dev, "WARNING: SMBus interface set to "
	192	"new address %04x!\n", piix4_smba);
	193	} else if ((temp & 1) == 0) {
	194	if (force) {
	195	/* This should never need to be done, but has been
	196	* noted that many Dell machines have the SMBus
	197	* interface on the PIIX4 disabled!? NOTE: This assumes
	198	* I/O space and other allocations WERE done by the
	199	* Bios! Don't complain if your hardware does weird
	200	* things after enabling this. :') Check for Bios
	201	* updates before resorting to this.
	202	*/
	203	pci_write_config_byte(PIIX4_dev, SMBHSTCFG,
	204	temp \| 1);
	205	dev_printk(KERN_NOTICE, &PIIX4_dev->dev,
	206	"WARNING: SMBus interface has been "
	207	"FORCEFULLY ENABLED!\n");
	208	} else {
	209	dev_err(&PIIX4_dev->dev,
	210	"Host SMBus controller not enabled!\n");
	211	release_region(piix4_smba, SMBIOSIZE);
1da177e4 LT	212	return -ENODEV;
	213	}
	214	}
	215
54aaa1ca	216	if (((temp & 0x0E) == 8) \|\| ((temp & 0x0E) == 2))
1da177e4 LT	217	dev_dbg(&PIIX4_dev->dev, "Using Interrupt 9 for SMBus.\n");
	218	else if ((temp & 0x0E) == 0)
	219	dev_dbg(&PIIX4_dev->dev, "Using Interrupt SMI# for SMBus.\n");
	220	else
	221	dev_err(&PIIX4_dev->dev, "Illegal Interrupt configuration "
	222	"(or code out of date)!\n");
	223
	224	pci_read_config_byte(PIIX4_dev, SMBREV, &temp);
fa63cd56 JD	225	dev_info(&PIIX4_dev->dev,
	226	"SMBus Host Controller at 0x%x, revision %d\n",
	227	piix4_smba, temp);
1da177e4	228
14a8086d	229	return piix4_smba;
1da177e4 LT	230	}
1da177e4 LT	231
87e1960e SH	232	static int __devinit piix4_setup_sb800(struct pci_dev *PIIX4_dev,
	233	const struct pci_device_id *id)
	234	{
14a8086d	235	unsigned short piix4_smba;
87e1960e SH	236	unsigned short smba_idx = 0xcd6;
	237	u8 smba_en_lo, smba_en_hi, i2ccfg, i2ccfg_offset = 0x10, smb_en = 0x2c;
	238
3806e94b	239	/* SB800 and later SMBus does not support forcing address */
87e1960e	240	if (force \|\| force_addr) {
3806e94b	241	dev_err(&PIIX4_dev->dev, "SMBus does not support "
87e1960e SH	242	"forcing address!\n");
	243	return -EINVAL;
	244	}
	245
	246	/* Determine the address of the SMBus areas */
	247	if (!request_region(smba_idx, 2, "smba_idx")) {
	248	dev_err(&PIIX4_dev->dev, "SMBus base address index region "
	249	"0x%x already in use!\n", smba_idx);
	250	return -EBUSY;
	251	}
	252	outb_p(smb_en, smba_idx);
	253	smba_en_lo = inb_p(smba_idx + 1);
	254	outb_p(smb_en + 1, smba_idx);
	255	smba_en_hi = inb_p(smba_idx + 1);
	256	release_region(smba_idx, 2);
	257
	258	if ((smba_en_lo & 1) == 0) {
	259	dev_err(&PIIX4_dev->dev,
	260	"Host SMBus controller not enabled!\n");
	261	return -ENODEV;
	262	}
	263
	264	piix4_smba = ((smba_en_hi << 8) \| smba_en_lo) & 0xffe0;
	265	if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name))
18669eab	266	return -ENODEV;
87e1960e SH	267
	268	if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) {
	269	dev_err(&PIIX4_dev->dev, "SMBus region 0x%x already in use!\n",
	270	piix4_smba);
	271	return -EBUSY;
	272	}
	273
	274	/* Request the SMBus I2C bus config region */
	275	if (!request_region(piix4_smba + i2ccfg_offset, 1, "i2ccfg")) {
	276	dev_err(&PIIX4_dev->dev, "SMBus I2C bus config region "
	277	"0x%x already in use!\n", piix4_smba + i2ccfg_offset);
	278	release_region(piix4_smba, SMBIOSIZE);
87e1960e SH	279	return -EBUSY;
	280	}
	281	i2ccfg = inb_p(piix4_smba + i2ccfg_offset);
	282	release_region(piix4_smba + i2ccfg_offset, 1);
	283
	284	if (i2ccfg & 1)
	285	dev_dbg(&PIIX4_dev->dev, "Using IRQ for SMBus.\n");
	286	else
	287	dev_dbg(&PIIX4_dev->dev, "Using SMI# for SMBus.\n");
	288
	289	dev_info(&PIIX4_dev->dev,
	290	"SMBus Host Controller at 0x%x, revision %d\n",
	291	piix4_smba, i2ccfg >> 4);
	292
14a8086d	293	return piix4_smba;
87e1960e SH	294	}
87e1960e SH	295
e154bf6f	296	static int piix4_transaction(struct i2c_adapter *piix4_adapter)
1da177e4	297	{
e154bf6f AA	298	struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(piix4_adapter);
e154bf6f AA	299	unsigned short piix4_smba = adapdata->smba;
1da177e4 LT	300	int temp;
	301	int result = 0;
	302	int timeout = 0;
	303
e154bf6f	304	dev_dbg(&piix4_adapter->dev, "Transaction (pre): CNT=%02x, CMD=%02x, "
1da177e4 LT	305	"ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
	306	inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
	307	inb_p(SMBHSTDAT1));
	308
	309	/* Make sure the SMBus host is ready to start transmitting */
	310	if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
e154bf6f	311	dev_dbg(&piix4_adapter->dev, "SMBus busy (%02x). "
541e6a02	312	"Resetting...\n", temp);
1da177e4 LT	313	outb_p(temp, SMBHSTSTS);
1da177e4 LT	314	if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
e154bf6f	315	dev_err(&piix4_adapter->dev, "Failed! (%02x)\n", temp);
97140342	316	return -EBUSY;
1da177e4	317	} else {
e154bf6f	318	dev_dbg(&piix4_adapter->dev, "Successful!\n");
1da177e4 LT	319	}
	320	}
	321
	322	/* start the transaction by setting bit 6 */
	323	outb_p(inb(SMBHSTCNT) \| 0x040, SMBHSTCNT);
	324
	325	/* We will always wait for a fraction of a second! (See PIIX4 docs errata) */
b1c1759c DM	326	if (srvrworks_csb5_delay) /* Extra delay for SERVERWORKS_CSB5 */
	327	msleep(2);
	328	else
	329	msleep(1);
	330
b6a31950	331	while ((++timeout < MAX_TIMEOUT) &&
b1c1759c	332	((temp = inb_p(SMBHSTSTS)) & 0x01))
1da177e4	333	msleep(1);
1da177e4 LT	334
1da177e4 LT	335	/* If the SMBus is still busy, we give up */
b6a31950	336	if (timeout == MAX_TIMEOUT) {
e154bf6f	337	dev_err(&piix4_adapter->dev, "SMBus Timeout!\n");
97140342	338	result = -ETIMEDOUT;
1da177e4 LT	339	}
	340
	341	if (temp & 0x10) {
97140342	342	result = -EIO;
e154bf6f	343	dev_err(&piix4_adapter->dev, "Error: Failed bus transaction\n");
1da177e4 LT	344	}
	345
	346	if (temp & 0x08) {
97140342	347	result = -EIO;
e154bf6f	348	dev_dbg(&piix4_adapter->dev, "Bus collision! SMBus may be "
1da177e4 LT	349	"locked until next hard reset. (sorry!)\n");
	350	/* Clock stops and slave is stuck in mid-transmission */
	351	}
	352
	353	if (temp & 0x04) {
97140342	354	result = -ENXIO;
e154bf6f	355	dev_dbg(&piix4_adapter->dev, "Error: no response!\n");
1da177e4 LT	356	}
	357
	358	if (inb_p(SMBHSTSTS) != 0x00)
	359	outb_p(inb(SMBHSTSTS), SMBHSTSTS);
	360
	361	if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
e154bf6f	362	dev_err(&piix4_adapter->dev, "Failed reset at end of "
1da177e4 LT	363	"transaction (%02x)\n", temp);
1da177e4 LT	364	}
e154bf6f	365	dev_dbg(&piix4_adapter->dev, "Transaction (post): CNT=%02x, CMD=%02x, "
1da177e4 LT	366	"ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
	367	inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
	368	inb_p(SMBHSTDAT1));
	369	return result;
	370	}
	371
97140342	372	/* Return negative errno on error. */
1da177e4 LT	373	static s32 piix4_access(struct i2c_adapter * adap, u16 addr,
	374	unsigned short flags, char read_write,
	375	u8 command, int size, union i2c_smbus_data * data)
	376	{
14a8086d AA	377	struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap);
14a8086d AA	378	unsigned short piix4_smba = adapdata->smba;
1da177e4	379	int i, len;
97140342	380	int status;
1da177e4 LT	381
1da177e4 LT	382	switch (size) {
1da177e4	383	case I2C_SMBUS_QUICK:
fa63cd56	384	outb_p((addr << 1) \| read_write,
1da177e4 LT	385	SMBHSTADD);
	386	size = PIIX4_QUICK;
	387	break;
	388	case I2C_SMBUS_BYTE:
fa63cd56	389	outb_p((addr << 1) \| read_write,
1da177e4 LT	390	SMBHSTADD);
	391	if (read_write == I2C_SMBUS_WRITE)
	392	outb_p(command, SMBHSTCMD);
	393	size = PIIX4_BYTE;
	394	break;
	395	case I2C_SMBUS_BYTE_DATA:
fa63cd56	396	outb_p((addr << 1) \| read_write,
1da177e4 LT	397	SMBHSTADD);
	398	outb_p(command, SMBHSTCMD);
	399	if (read_write == I2C_SMBUS_WRITE)
	400	outb_p(data->byte, SMBHSTDAT0);
	401	size = PIIX4_BYTE_DATA;
	402	break;
	403	case I2C_SMBUS_WORD_DATA:
fa63cd56	404	outb_p((addr << 1) \| read_write,
1da177e4 LT	405	SMBHSTADD);
	406	outb_p(command, SMBHSTCMD);
	407	if (read_write == I2C_SMBUS_WRITE) {
	408	outb_p(data->word & 0xff, SMBHSTDAT0);
	409	outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1);
	410	}
	411	size = PIIX4_WORD_DATA;
	412	break;
	413	case I2C_SMBUS_BLOCK_DATA:
fa63cd56	414	outb_p((addr << 1) \| read_write,
1da177e4 LT	415	SMBHSTADD);
	416	outb_p(command, SMBHSTCMD);
	417	if (read_write == I2C_SMBUS_WRITE) {
	418	len = data->block[0];
fa63cd56 JD	419	if (len == 0 \|\| len > I2C_SMBUS_BLOCK_MAX)
fa63cd56 JD	420	return -EINVAL;
1da177e4 LT	421	outb_p(len, SMBHSTDAT0);
	422	i = inb_p(SMBHSTCNT); /* Reset SMBBLKDAT */
	423	for (i = 1; i <= len; i++)
	424	outb_p(data->block[i], SMBBLKDAT);
	425	}
	426	size = PIIX4_BLOCK_DATA;
	427	break;
ac7fc4fb JD	428	default:
	429	dev_warn(&adap->dev, "Unsupported transaction %d\n", size);
	430	return -EOPNOTSUPP;
1da177e4 LT	431	}
	432
	433	outb_p((size & 0x1C) + (ENABLE_INT9 & 1), SMBHSTCNT);
	434
e154bf6f	435	status = piix4_transaction(adap);
97140342 DB	436	if (status)
97140342 DB	437	return status;
1da177e4 LT	438
	439	if ((read_write == I2C_SMBUS_WRITE) \|\| (size == PIIX4_QUICK))
	440	return 0;
	441
	442
	443	switch (size) {
3578a075	444	case PIIX4_BYTE:
1da177e4 LT	445	case PIIX4_BYTE_DATA:
	446	data->byte = inb_p(SMBHSTDAT0);
	447	break;
	448	case PIIX4_WORD_DATA:
	449	data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8);
	450	break;
	451	case PIIX4_BLOCK_DATA:
	452	data->block[0] = inb_p(SMBHSTDAT0);
fa63cd56 JD	453	if (data->block[0] == 0 \|\| data->block[0] > I2C_SMBUS_BLOCK_MAX)
fa63cd56 JD	454	return -EPROTO;
1da177e4 LT	455	i = inb_p(SMBHSTCNT); /* Reset SMBBLKDAT */
	456	for (i = 1; i <= data->block[0]; i++)
	457	data->block[i] = inb_p(SMBBLKDAT);
	458	break;
	459	}
	460	return 0;
	461	}
	462
	463	static u32 piix4_func(struct i2c_adapter *adapter)
	464	{
	465	return I2C_FUNC_SMBUS_QUICK \| I2C_FUNC_SMBUS_BYTE \|
	466	I2C_FUNC_SMBUS_BYTE_DATA \| I2C_FUNC_SMBUS_WORD_DATA \|
	467	I2C_FUNC_SMBUS_BLOCK_DATA;
	468	}
	469
8f9082c5	470	static const struct i2c_algorithm smbus_algorithm = {
1da177e4 LT	471	.smbus_xfer = piix4_access,
	472	.functionality = piix4_func,
	473	};
	474
3527bd50	475	static DEFINE_PCI_DEVICE_TABLE(piix4_ids) = {
9b7389c0 JD	476	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3) },
	477	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3) },
	478	{ PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_3) },
	479	{ PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP200_SMBUS) },
	480	{ PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP300_SMBUS) },
	481	{ PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS) },
	482	{ PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS) },
3806e94b	483	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SMBUS) },
9b7389c0 JD	484	{ PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
	485	PCI_DEVICE_ID_SERVERWORKS_OSB4) },
	486	{ PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
	487	PCI_DEVICE_ID_SERVERWORKS_CSB5) },
	488	{ PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
	489	PCI_DEVICE_ID_SERVERWORKS_CSB6) },
	490	{ PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
	491	PCI_DEVICE_ID_SERVERWORKS_HT1000SB) },
506a8b6c FL	492	{ PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
506a8b6c FL	493	PCI_DEVICE_ID_SERVERWORKS_HT1100LD) },
1da177e4 LT	494	{ 0, }
	495	};
	496
	497	MODULE_DEVICE_TABLE (pci, piix4_ids);
	498
e154bf6f AA	499	static struct i2c_adapter *piix4_main_adapter;
	500
	501	static int __devinit piix4_add_adapter(struct pci_dev *dev,
	502	unsigned short smba,
	503	struct i2c_adapter **padap)
	504	{
	505	struct i2c_adapter *adap;
	506	struct i2c_piix4_adapdata *adapdata;
	507	int retval;
	508
	509	adap = kzalloc(sizeof(*adap), GFP_KERNEL);
	510	if (adap == NULL) {
	511	release_region(smba, SMBIOSIZE);
	512	return -ENOMEM;
	513	}
	514
	515	adap->owner = THIS_MODULE;
	516	adap->class = I2C_CLASS_HWMON \| I2C_CLASS_SPD;
	517	adap->algo = &smbus_algorithm;
	518
	519	adapdata = kzalloc(sizeof(*adapdata), GFP_KERNEL);
	520	if (adapdata == NULL) {
	521	kfree(adap);
	522	release_region(smba, SMBIOSIZE);
	523	return -ENOMEM;
	524	}
	525
	526	adapdata->smba = smba;
	527
	528	/* set up the sysfs linkage to our parent device */
	529	adap->dev.parent = &dev->dev;
	530
	531	snprintf(adap->name, sizeof(adap->name),
	532	"SMBus PIIX4 adapter at %04x", smba);
	533
	534	i2c_set_adapdata(adap, adapdata);
	535
	536	retval = i2c_add_adapter(adap);
	537	if (retval) {
	538	dev_err(&dev->dev, "Couldn't register adapter!\n");
	539	kfree(adapdata);
	540	kfree(adap);
	541	release_region(smba, SMBIOSIZE);
	542	return retval;
	543	}
	544
	545	*padap = adap;
	546	return 0;
	547	}
	548
1da177e4 LT	549	static int __devinit piix4_probe(struct pci_dev *dev,
	550	const struct pci_device_id *id)
	551	{
	552	int retval;
	553
76b3e28f CC	554	if ((dev->vendor == PCI_VENDOR_ID_ATI &&
	555	dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS &&
	556	dev->revision >= 0x40) \|\|
	557	dev->vendor == PCI_VENDOR_ID_AMD)
87e1960e SH	558	/* base address location etc changed in SB800 */
	559	retval = piix4_setup_sb800(dev, id);
	560	else
	561	retval = piix4_setup(dev, id);
	562
14a8086d	563	if (retval < 0)
1da177e4 LT	564	return retval;
1da177e4 LT	565
e154bf6f	566	return piix4_add_adapter(dev, retval, &piix4_main_adapter);
1da177e4 LT	567	}
1da177e4 LT	568
14a8086d	569	static void __devexit piix4_adap_remove(struct i2c_adapter *adap)
1da177e4	570	{
14a8086d AA	571	struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap);
	572
	573	if (adapdata->smba) {
	574	i2c_del_adapter(adap);
	575	release_region(adapdata->smba, SMBIOSIZE);
e154bf6f AA	576	kfree(adapdata);
e154bf6f AA	577	kfree(adap);
1da177e4 LT	578	}
	579	}
	580
14a8086d AA	581	static void __devexit piix4_remove(struct pci_dev *dev)
14a8086d AA	582	{
e154bf6f AA	583	if (piix4_main_adapter) {
	584	piix4_adap_remove(piix4_main_adapter);
	585	piix4_main_adapter = NULL;
	586	}
14a8086d AA	587	}
14a8086d AA	588
1da177e4 LT	589	static struct pci_driver piix4_driver = {
	590	.name = "piix4_smbus",
	591	.id_table = piix4_ids,
	592	.probe = piix4_probe,
	593	.remove = __devexit_p(piix4_remove),
	594	};
	595
56f21788	596	module_pci_driver(piix4_driver);
1da177e4 LT	597
	598	MODULE_AUTHOR("Frodo Looijaard <frodol@dds.nl> and "
	599	"Philip Edelbrock <phil@netroedge.com>");
	600	MODULE_DESCRIPTION("PIIX4 SMBus driver");
	601	MODULE_LICENSE("GPL");