Commit | Line | Data |
---|---|---|
b652b438 RK |
1 | /* |
2 | * i2c_adap_pxa.c | |
3 | * | |
4 | * I2C adapter for the PXA I2C bus access. | |
5 | * | |
6 | * Copyright (C) 2002 Intrinsyc Software Inc. | |
7 | * Copyright (C) 2004-2005 Deep Blue Solutions Ltd. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * History: | |
14 | * Apr 2002: Initial version [CS] | |
15 | * Jun 2002: Properly seperated algo/adap [FB] | |
16 | * Jan 2003: Fixed several bugs concerning interrupt handling [Kai-Uwe Bloem] | |
17 | * Jan 2003: added limited signal handling [Kai-Uwe Bloem] | |
18 | * Sep 2004: Major rework to ensure efficient bus handling [RMK] | |
19 | * Dec 2004: Added support for PXA27x and slave device probing [Liam Girdwood] | |
20 | * Feb 2005: Rework slave mode handling [RMK] | |
21 | */ | |
22 | #include <linux/kernel.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/i2c.h> | |
25 | #include <linux/i2c-id.h> | |
26 | #include <linux/init.h> | |
27 | #include <linux/time.h> | |
28 | #include <linux/sched.h> | |
29 | #include <linux/delay.h> | |
30 | #include <linux/errno.h> | |
31 | #include <linux/interrupt.h> | |
32 | #include <linux/i2c-pxa.h> | |
d052d1be | 33 | #include <linux/platform_device.h> |
c3cef3f3 RK |
34 | #include <linux/err.h> |
35 | #include <linux/clk.h> | |
b652b438 | 36 | |
b652b438 | 37 | #include <asm/irq.h> |
a7b4e550 | 38 | #include <asm/io.h> |
f0a83701 | 39 | #include <plat/i2c.h> |
283afa06 | 40 | |
f23d4911 EM |
41 | /* |
42 | * I2C register offsets will be shifted 0 or 1 bit left, depending on | |
43 | * different SoCs | |
44 | */ | |
45 | #define REG_SHIFT_0 (0 << 0) | |
46 | #define REG_SHIFT_1 (1 << 0) | |
47 | #define REG_SHIFT(d) ((d) & 0x1) | |
48 | ||
49 | static const struct platform_device_id i2c_pxa_id_table[] = { | |
50 | { "pxa2xx-i2c", REG_SHIFT_1 }, | |
51 | { "pxa3xx-pwri2c", REG_SHIFT_0 }, | |
52 | { }, | |
53 | }; | |
54 | MODULE_DEVICE_TABLE(platform, i2c_pxa_id_table); | |
55 | ||
283afa06 EM |
56 | /* |
57 | * I2C registers and bit definitions | |
58 | */ | |
59 | #define IBMR (0x00) | |
60 | #define IDBR (0x08) | |
61 | #define ICR (0x10) | |
62 | #define ISR (0x18) | |
63 | #define ISAR (0x20) | |
64 | ||
65 | #define ICR_START (1 << 0) /* start bit */ | |
66 | #define ICR_STOP (1 << 1) /* stop bit */ | |
67 | #define ICR_ACKNAK (1 << 2) /* send ACK(0) or NAK(1) */ | |
68 | #define ICR_TB (1 << 3) /* transfer byte bit */ | |
69 | #define ICR_MA (1 << 4) /* master abort */ | |
70 | #define ICR_SCLE (1 << 5) /* master clock enable */ | |
71 | #define ICR_IUE (1 << 6) /* unit enable */ | |
72 | #define ICR_GCD (1 << 7) /* general call disable */ | |
73 | #define ICR_ITEIE (1 << 8) /* enable tx interrupts */ | |
74 | #define ICR_IRFIE (1 << 9) /* enable rx interrupts */ | |
75 | #define ICR_BEIE (1 << 10) /* enable bus error ints */ | |
76 | #define ICR_SSDIE (1 << 11) /* slave STOP detected int enable */ | |
77 | #define ICR_ALDIE (1 << 12) /* enable arbitration interrupt */ | |
78 | #define ICR_SADIE (1 << 13) /* slave address detected int enable */ | |
79 | #define ICR_UR (1 << 14) /* unit reset */ | |
80 | #define ICR_FM (1 << 15) /* fast mode */ | |
81 | ||
82 | #define ISR_RWM (1 << 0) /* read/write mode */ | |
83 | #define ISR_ACKNAK (1 << 1) /* ack/nak status */ | |
84 | #define ISR_UB (1 << 2) /* unit busy */ | |
85 | #define ISR_IBB (1 << 3) /* bus busy */ | |
86 | #define ISR_SSD (1 << 4) /* slave stop detected */ | |
87 | #define ISR_ALD (1 << 5) /* arbitration loss detected */ | |
88 | #define ISR_ITE (1 << 6) /* tx buffer empty */ | |
89 | #define ISR_IRF (1 << 7) /* rx buffer full */ | |
90 | #define ISR_GCAD (1 << 8) /* general call address detected */ | |
91 | #define ISR_SAD (1 << 9) /* slave address detected */ | |
92 | #define ISR_BED (1 << 10) /* bus error no ACK/NAK */ | |
b652b438 RK |
93 | |
94 | struct pxa_i2c { | |
95 | spinlock_t lock; | |
96 | wait_queue_head_t wait; | |
97 | struct i2c_msg *msg; | |
98 | unsigned int msg_num; | |
99 | unsigned int msg_idx; | |
100 | unsigned int msg_ptr; | |
101 | unsigned int slave_addr; | |
102 | ||
103 | struct i2c_adapter adap; | |
c3cef3f3 | 104 | struct clk *clk; |
b652b438 RK |
105 | #ifdef CONFIG_I2C_PXA_SLAVE |
106 | struct i2c_slave_client *slave; | |
107 | #endif | |
108 | ||
109 | unsigned int irqlogidx; | |
110 | u32 isrlog[32]; | |
111 | u32 icrlog[32]; | |
a7b4e550 GL |
112 | |
113 | void __iomem *reg_base; | |
9ba63c4f | 114 | unsigned int reg_shift; |
a7b4e550 GL |
115 | |
116 | unsigned long iobase; | |
117 | unsigned long iosize; | |
118 | ||
119 | int irq; | |
c46c9482 JC |
120 | unsigned int use_pio :1; |
121 | unsigned int fast_mode :1; | |
b652b438 RK |
122 | }; |
123 | ||
9ba63c4f MR |
124 | #define _IBMR(i2c) ((i2c)->reg_base + (0x0 << (i2c)->reg_shift)) |
125 | #define _IDBR(i2c) ((i2c)->reg_base + (0x4 << (i2c)->reg_shift)) | |
126 | #define _ICR(i2c) ((i2c)->reg_base + (0x8 << (i2c)->reg_shift)) | |
127 | #define _ISR(i2c) ((i2c)->reg_base + (0xc << (i2c)->reg_shift)) | |
128 | #define _ISAR(i2c) ((i2c)->reg_base + (0x10 << (i2c)->reg_shift)) | |
a7b4e550 | 129 | |
b652b438 RK |
130 | /* |
131 | * I2C Slave mode address | |
132 | */ | |
133 | #define I2C_PXA_SLAVE_ADDR 0x1 | |
134 | ||
b652b438 RK |
135 | #ifdef DEBUG |
136 | ||
137 | struct bits { | |
138 | u32 mask; | |
139 | const char *set; | |
140 | const char *unset; | |
141 | }; | |
ed11399d | 142 | #define PXA_BIT(m, s, u) { .mask = m, .set = s, .unset = u } |
b652b438 RK |
143 | |
144 | static inline void | |
145 | decode_bits(const char *prefix, const struct bits *bits, int num, u32 val) | |
146 | { | |
147 | printk("%s %08x: ", prefix, val); | |
148 | while (num--) { | |
149 | const char *str = val & bits->mask ? bits->set : bits->unset; | |
150 | if (str) | |
151 | printk("%s ", str); | |
152 | bits++; | |
153 | } | |
154 | } | |
155 | ||
156 | static const struct bits isr_bits[] = { | |
ed11399d JS |
157 | PXA_BIT(ISR_RWM, "RX", "TX"), |
158 | PXA_BIT(ISR_ACKNAK, "NAK", "ACK"), | |
159 | PXA_BIT(ISR_UB, "Bsy", "Rdy"), | |
160 | PXA_BIT(ISR_IBB, "BusBsy", "BusRdy"), | |
161 | PXA_BIT(ISR_SSD, "SlaveStop", NULL), | |
162 | PXA_BIT(ISR_ALD, "ALD", NULL), | |
163 | PXA_BIT(ISR_ITE, "TxEmpty", NULL), | |
164 | PXA_BIT(ISR_IRF, "RxFull", NULL), | |
165 | PXA_BIT(ISR_GCAD, "GenCall", NULL), | |
166 | PXA_BIT(ISR_SAD, "SlaveAddr", NULL), | |
167 | PXA_BIT(ISR_BED, "BusErr", NULL), | |
b652b438 RK |
168 | }; |
169 | ||
170 | static void decode_ISR(unsigned int val) | |
171 | { | |
6fd60fa9 | 172 | decode_bits(KERN_DEBUG "ISR", isr_bits, ARRAY_SIZE(isr_bits), val); |
b652b438 RK |
173 | printk("\n"); |
174 | } | |
175 | ||
176 | static const struct bits icr_bits[] = { | |
ed11399d JS |
177 | PXA_BIT(ICR_START, "START", NULL), |
178 | PXA_BIT(ICR_STOP, "STOP", NULL), | |
179 | PXA_BIT(ICR_ACKNAK, "ACKNAK", NULL), | |
180 | PXA_BIT(ICR_TB, "TB", NULL), | |
181 | PXA_BIT(ICR_MA, "MA", NULL), | |
182 | PXA_BIT(ICR_SCLE, "SCLE", "scle"), | |
183 | PXA_BIT(ICR_IUE, "IUE", "iue"), | |
184 | PXA_BIT(ICR_GCD, "GCD", NULL), | |
185 | PXA_BIT(ICR_ITEIE, "ITEIE", NULL), | |
186 | PXA_BIT(ICR_IRFIE, "IRFIE", NULL), | |
187 | PXA_BIT(ICR_BEIE, "BEIE", NULL), | |
188 | PXA_BIT(ICR_SSDIE, "SSDIE", NULL), | |
189 | PXA_BIT(ICR_ALDIE, "ALDIE", NULL), | |
190 | PXA_BIT(ICR_SADIE, "SADIE", NULL), | |
191 | PXA_BIT(ICR_UR, "UR", "ur"), | |
b652b438 RK |
192 | }; |
193 | ||
d6a7b5f8 | 194 | #ifdef CONFIG_I2C_PXA_SLAVE |
b652b438 RK |
195 | static void decode_ICR(unsigned int val) |
196 | { | |
6fd60fa9 | 197 | decode_bits(KERN_DEBUG "ICR", icr_bits, ARRAY_SIZE(icr_bits), val); |
b652b438 RK |
198 | printk("\n"); |
199 | } | |
d6a7b5f8 | 200 | #endif |
b652b438 RK |
201 | |
202 | static unsigned int i2c_debug = DEBUG; | |
203 | ||
204 | static void i2c_pxa_show_state(struct pxa_i2c *i2c, int lno, const char *fname) | |
205 | { | |
a7b4e550 GL |
206 | dev_dbg(&i2c->adap.dev, "state:%s:%d: ISR=%08x, ICR=%08x, IBMR=%02x\n", fname, lno, |
207 | readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c))); | |
b652b438 RK |
208 | } |
209 | ||
08882d20 | 210 | #define show_state(i2c) i2c_pxa_show_state(i2c, __LINE__, __func__) |
b652b438 RK |
211 | #else |
212 | #define i2c_debug 0 | |
213 | ||
214 | #define show_state(i2c) do { } while (0) | |
215 | #define decode_ISR(val) do { } while (0) | |
216 | #define decode_ICR(val) do { } while (0) | |
217 | #endif | |
218 | ||
6fd60fa9 | 219 | #define eedbg(lvl, x...) do { if ((lvl) < 1) { printk(KERN_DEBUG "" x); } } while(0) |
b652b438 RK |
220 | |
221 | static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret); | |
b7a36701 | 222 | static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id); |
b652b438 RK |
223 | |
224 | static void i2c_pxa_scream_blue_murder(struct pxa_i2c *i2c, const char *why) | |
225 | { | |
226 | unsigned int i; | |
154d22b0 FS |
227 | printk(KERN_ERR "i2c: error: %s\n", why); |
228 | printk(KERN_ERR "i2c: msg_num: %d msg_idx: %d msg_ptr: %d\n", | |
b652b438 | 229 | i2c->msg_num, i2c->msg_idx, i2c->msg_ptr); |
154d22b0 FS |
230 | printk(KERN_ERR "i2c: ICR: %08x ISR: %08x\n", |
231 | readl(_ICR(i2c)), readl(_ISR(i2c))); | |
232 | printk(KERN_DEBUG "i2c: log: "); | |
b652b438 RK |
233 | for (i = 0; i < i2c->irqlogidx; i++) |
234 | printk("[%08x:%08x] ", i2c->isrlog[i], i2c->icrlog[i]); | |
235 | printk("\n"); | |
236 | } | |
237 | ||
238 | static inline int i2c_pxa_is_slavemode(struct pxa_i2c *i2c) | |
239 | { | |
a7b4e550 | 240 | return !(readl(_ICR(i2c)) & ICR_SCLE); |
b652b438 RK |
241 | } |
242 | ||
243 | static void i2c_pxa_abort(struct pxa_i2c *i2c) | |
244 | { | |
387fa6a5 | 245 | int i = 250; |
b652b438 RK |
246 | |
247 | if (i2c_pxa_is_slavemode(i2c)) { | |
6fd60fa9 | 248 | dev_dbg(&i2c->adap.dev, "%s: called in slave mode\n", __func__); |
b652b438 RK |
249 | return; |
250 | } | |
251 | ||
387fa6a5 | 252 | while ((i > 0) && (readl(_IBMR(i2c)) & 0x1) == 0) { |
a7b4e550 | 253 | unsigned long icr = readl(_ICR(i2c)); |
b652b438 RK |
254 | |
255 | icr &= ~ICR_START; | |
256 | icr |= ICR_ACKNAK | ICR_STOP | ICR_TB; | |
257 | ||
a7b4e550 | 258 | writel(icr, _ICR(i2c)); |
b652b438 RK |
259 | |
260 | show_state(i2c); | |
261 | ||
387fa6a5 DB |
262 | mdelay(1); |
263 | i --; | |
b652b438 RK |
264 | } |
265 | ||
a7b4e550 GL |
266 | writel(readl(_ICR(i2c)) & ~(ICR_MA | ICR_START | ICR_STOP), |
267 | _ICR(i2c)); | |
b652b438 RK |
268 | } |
269 | ||
270 | static int i2c_pxa_wait_bus_not_busy(struct pxa_i2c *i2c) | |
271 | { | |
272 | int timeout = DEF_TIMEOUT; | |
273 | ||
a7b4e550 GL |
274 | while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB)) { |
275 | if ((readl(_ISR(i2c)) & ISR_SAD) != 0) | |
b652b438 RK |
276 | timeout += 4; |
277 | ||
278 | msleep(2); | |
279 | show_state(i2c); | |
280 | } | |
281 | ||
d10db3a0 | 282 | if (timeout < 0) |
b652b438 RK |
283 | show_state(i2c); |
284 | ||
d10db3a0 | 285 | return timeout < 0 ? I2C_RETRY : 0; |
b652b438 RK |
286 | } |
287 | ||
288 | static int i2c_pxa_wait_master(struct pxa_i2c *i2c) | |
289 | { | |
290 | unsigned long timeout = jiffies + HZ*4; | |
291 | ||
292 | while (time_before(jiffies, timeout)) { | |
293 | if (i2c_debug > 1) | |
6fd60fa9 | 294 | dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n", |
a7b4e550 | 295 | __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c))); |
b652b438 | 296 | |
a7b4e550 | 297 | if (readl(_ISR(i2c)) & ISR_SAD) { |
b652b438 | 298 | if (i2c_debug > 0) |
6fd60fa9 | 299 | dev_dbg(&i2c->adap.dev, "%s: Slave detected\n", __func__); |
b652b438 RK |
300 | goto out; |
301 | } | |
302 | ||
303 | /* wait for unit and bus being not busy, and we also do a | |
304 | * quick check of the i2c lines themselves to ensure they've | |
305 | * gone high... | |
306 | */ | |
a7b4e550 | 307 | if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) == 0 && readl(_IBMR(i2c)) == 3) { |
b652b438 | 308 | if (i2c_debug > 0) |
6fd60fa9 | 309 | dev_dbg(&i2c->adap.dev, "%s: done\n", __func__); |
b652b438 RK |
310 | return 1; |
311 | } | |
312 | ||
313 | msleep(1); | |
314 | } | |
315 | ||
316 | if (i2c_debug > 0) | |
6fd60fa9 | 317 | dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__); |
b652b438 RK |
318 | out: |
319 | return 0; | |
320 | } | |
321 | ||
322 | static int i2c_pxa_set_master(struct pxa_i2c *i2c) | |
323 | { | |
324 | if (i2c_debug) | |
6fd60fa9 | 325 | dev_dbg(&i2c->adap.dev, "setting to bus master\n"); |
b652b438 | 326 | |
a7b4e550 | 327 | if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) != 0) { |
6fd60fa9 | 328 | dev_dbg(&i2c->adap.dev, "%s: unit is busy\n", __func__); |
b652b438 | 329 | if (!i2c_pxa_wait_master(i2c)) { |
6fd60fa9 | 330 | dev_dbg(&i2c->adap.dev, "%s: error: unit busy\n", __func__); |
b652b438 RK |
331 | return I2C_RETRY; |
332 | } | |
333 | } | |
334 | ||
a7b4e550 | 335 | writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c)); |
b652b438 RK |
336 | return 0; |
337 | } | |
338 | ||
339 | #ifdef CONFIG_I2C_PXA_SLAVE | |
340 | static int i2c_pxa_wait_slave(struct pxa_i2c *i2c) | |
341 | { | |
342 | unsigned long timeout = jiffies + HZ*1; | |
343 | ||
344 | /* wait for stop */ | |
345 | ||
346 | show_state(i2c); | |
347 | ||
348 | while (time_before(jiffies, timeout)) { | |
349 | if (i2c_debug > 1) | |
6fd60fa9 | 350 | dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n", |
a7b4e550 | 351 | __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c))); |
b652b438 | 352 | |
a7b4e550 GL |
353 | if ((readl(_ISR(i2c)) & (ISR_UB|ISR_IBB)) == 0 || |
354 | (readl(_ISR(i2c)) & ISR_SAD) != 0 || | |
355 | (readl(_ICR(i2c)) & ICR_SCLE) == 0) { | |
b652b438 | 356 | if (i2c_debug > 1) |
6fd60fa9 | 357 | dev_dbg(&i2c->adap.dev, "%s: done\n", __func__); |
b652b438 RK |
358 | return 1; |
359 | } | |
360 | ||
361 | msleep(1); | |
362 | } | |
363 | ||
364 | if (i2c_debug > 0) | |
6fd60fa9 | 365 | dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__); |
b652b438 RK |
366 | return 0; |
367 | } | |
368 | ||
369 | /* | |
370 | * clear the hold on the bus, and take of anything else | |
371 | * that has been configured | |
372 | */ | |
373 | static void i2c_pxa_set_slave(struct pxa_i2c *i2c, int errcode) | |
374 | { | |
375 | show_state(i2c); | |
376 | ||
377 | if (errcode < 0) { | |
378 | udelay(100); /* simple delay */ | |
379 | } else { | |
380 | /* we need to wait for the stop condition to end */ | |
381 | ||
382 | /* if we where in stop, then clear... */ | |
a7b4e550 | 383 | if (readl(_ICR(i2c)) & ICR_STOP) { |
b652b438 | 384 | udelay(100); |
a7b4e550 | 385 | writel(readl(_ICR(i2c)) & ~ICR_STOP, _ICR(i2c)); |
b652b438 RK |
386 | } |
387 | ||
388 | if (!i2c_pxa_wait_slave(i2c)) { | |
6fd60fa9 RK |
389 | dev_err(&i2c->adap.dev, "%s: wait timedout\n", |
390 | __func__); | |
b652b438 RK |
391 | return; |
392 | } | |
393 | } | |
394 | ||
a7b4e550 GL |
395 | writel(readl(_ICR(i2c)) & ~(ICR_STOP|ICR_ACKNAK|ICR_MA), _ICR(i2c)); |
396 | writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c)); | |
b652b438 RK |
397 | |
398 | if (i2c_debug) { | |
a7b4e550 GL |
399 | dev_dbg(&i2c->adap.dev, "ICR now %08x, ISR %08x\n", readl(_ICR(i2c)), readl(_ISR(i2c))); |
400 | decode_ICR(readl(_ICR(i2c))); | |
b652b438 RK |
401 | } |
402 | } | |
403 | #else | |
404 | #define i2c_pxa_set_slave(i2c, err) do { } while (0) | |
405 | #endif | |
406 | ||
407 | static void i2c_pxa_reset(struct pxa_i2c *i2c) | |
408 | { | |
409 | pr_debug("Resetting I2C Controller Unit\n"); | |
410 | ||
411 | /* abort any transfer currently under way */ | |
412 | i2c_pxa_abort(i2c); | |
413 | ||
414 | /* reset according to 9.8 */ | |
a7b4e550 GL |
415 | writel(ICR_UR, _ICR(i2c)); |
416 | writel(I2C_ISR_INIT, _ISR(i2c)); | |
417 | writel(readl(_ICR(i2c)) & ~ICR_UR, _ICR(i2c)); | |
b652b438 | 418 | |
a7b4e550 | 419 | writel(i2c->slave_addr, _ISAR(i2c)); |
b652b438 RK |
420 | |
421 | /* set control register values */ | |
c46c9482 | 422 | writel(I2C_ICR_INIT | (i2c->fast_mode ? ICR_FM : 0), _ICR(i2c)); |
b652b438 RK |
423 | |
424 | #ifdef CONFIG_I2C_PXA_SLAVE | |
6fd60fa9 | 425 | dev_info(&i2c->adap.dev, "Enabling slave mode\n"); |
a7b4e550 | 426 | writel(readl(_ICR(i2c)) | ICR_SADIE | ICR_ALDIE | ICR_SSDIE, _ICR(i2c)); |
b652b438 RK |
427 | #endif |
428 | ||
429 | i2c_pxa_set_slave(i2c, 0); | |
430 | ||
431 | /* enable unit */ | |
a7b4e550 | 432 | writel(readl(_ICR(i2c)) | ICR_IUE, _ICR(i2c)); |
b652b438 RK |
433 | udelay(100); |
434 | } | |
435 | ||
436 | ||
437 | #ifdef CONFIG_I2C_PXA_SLAVE | |
b652b438 RK |
438 | /* |
439 | * PXA I2C Slave mode | |
440 | */ | |
441 | ||
442 | static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr) | |
443 | { | |
444 | if (isr & ISR_BED) { | |
445 | /* what should we do here? */ | |
446 | } else { | |
84b5abe6 RK |
447 | int ret = 0; |
448 | ||
449 | if (i2c->slave != NULL) | |
450 | ret = i2c->slave->read(i2c->slave->data); | |
b652b438 | 451 | |
a7b4e550 GL |
452 | writel(ret, _IDBR(i2c)); |
453 | writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c)); /* allow next byte */ | |
b652b438 RK |
454 | } |
455 | } | |
456 | ||
457 | static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr) | |
458 | { | |
a7b4e550 | 459 | unsigned int byte = readl(_IDBR(i2c)); |
b652b438 RK |
460 | |
461 | if (i2c->slave != NULL) | |
462 | i2c->slave->write(i2c->slave->data, byte); | |
463 | ||
a7b4e550 | 464 | writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c)); |
b652b438 RK |
465 | } |
466 | ||
467 | static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr) | |
468 | { | |
469 | int timeout; | |
470 | ||
471 | if (i2c_debug > 0) | |
6fd60fa9 | 472 | dev_dbg(&i2c->adap.dev, "SAD, mode is slave-%cx\n", |
b652b438 RK |
473 | (isr & ISR_RWM) ? 'r' : 't'); |
474 | ||
475 | if (i2c->slave != NULL) | |
476 | i2c->slave->event(i2c->slave->data, | |
477 | (isr & ISR_RWM) ? I2C_SLAVE_EVENT_START_READ : I2C_SLAVE_EVENT_START_WRITE); | |
478 | ||
479 | /* | |
480 | * slave could interrupt in the middle of us generating a | |
481 | * start condition... if this happens, we'd better back off | |
482 | * and stop holding the poor thing up | |
483 | */ | |
a7b4e550 GL |
484 | writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c)); |
485 | writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c)); | |
b652b438 RK |
486 | |
487 | timeout = 0x10000; | |
488 | ||
489 | while (1) { | |
a7b4e550 | 490 | if ((readl(_IBMR(i2c)) & 2) == 2) |
b652b438 RK |
491 | break; |
492 | ||
493 | timeout--; | |
494 | ||
495 | if (timeout <= 0) { | |
6fd60fa9 | 496 | dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n"); |
b652b438 RK |
497 | break; |
498 | } | |
499 | } | |
500 | ||
a7b4e550 | 501 | writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c)); |
b652b438 RK |
502 | } |
503 | ||
504 | static void i2c_pxa_slave_stop(struct pxa_i2c *i2c) | |
505 | { | |
506 | if (i2c_debug > 2) | |
6fd60fa9 | 507 | dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop)\n"); |
b652b438 RK |
508 | |
509 | if (i2c->slave != NULL) | |
510 | i2c->slave->event(i2c->slave->data, I2C_SLAVE_EVENT_STOP); | |
511 | ||
512 | if (i2c_debug > 2) | |
6fd60fa9 | 513 | dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop) acked\n"); |
b652b438 RK |
514 | |
515 | /* | |
516 | * If we have a master-mode message waiting, | |
517 | * kick it off now that the slave has completed. | |
518 | */ | |
519 | if (i2c->msg) | |
520 | i2c_pxa_master_complete(i2c, I2C_RETRY); | |
521 | } | |
522 | #else | |
523 | static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr) | |
524 | { | |
525 | if (isr & ISR_BED) { | |
526 | /* what should we do here? */ | |
527 | } else { | |
a7b4e550 GL |
528 | writel(0, _IDBR(i2c)); |
529 | writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c)); | |
b652b438 RK |
530 | } |
531 | } | |
532 | ||
533 | static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr) | |
534 | { | |
a7b4e550 | 535 | writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c)); |
b652b438 RK |
536 | } |
537 | ||
538 | static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr) | |
539 | { | |
540 | int timeout; | |
541 | ||
542 | /* | |
543 | * slave could interrupt in the middle of us generating a | |
544 | * start condition... if this happens, we'd better back off | |
545 | * and stop holding the poor thing up | |
546 | */ | |
a7b4e550 GL |
547 | writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c)); |
548 | writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c)); | |
b652b438 RK |
549 | |
550 | timeout = 0x10000; | |
551 | ||
552 | while (1) { | |
a7b4e550 | 553 | if ((readl(_IBMR(i2c)) & 2) == 2) |
b652b438 RK |
554 | break; |
555 | ||
556 | timeout--; | |
557 | ||
558 | if (timeout <= 0) { | |
6fd60fa9 | 559 | dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n"); |
b652b438 RK |
560 | break; |
561 | } | |
562 | } | |
563 | ||
a7b4e550 | 564 | writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c)); |
b652b438 RK |
565 | } |
566 | ||
567 | static void i2c_pxa_slave_stop(struct pxa_i2c *i2c) | |
568 | { | |
569 | if (i2c->msg) | |
570 | i2c_pxa_master_complete(i2c, I2C_RETRY); | |
571 | } | |
572 | #endif | |
573 | ||
574 | /* | |
575 | * PXA I2C Master mode | |
576 | */ | |
577 | ||
578 | static inline unsigned int i2c_pxa_addr_byte(struct i2c_msg *msg) | |
579 | { | |
580 | unsigned int addr = (msg->addr & 0x7f) << 1; | |
581 | ||
582 | if (msg->flags & I2C_M_RD) | |
583 | addr |= 1; | |
584 | ||
585 | return addr; | |
586 | } | |
587 | ||
588 | static inline void i2c_pxa_start_message(struct pxa_i2c *i2c) | |
589 | { | |
590 | u32 icr; | |
591 | ||
592 | /* | |
593 | * Step 1: target slave address into IDBR | |
594 | */ | |
a7b4e550 | 595 | writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c)); |
b652b438 RK |
596 | |
597 | /* | |
598 | * Step 2: initiate the write. | |
599 | */ | |
a7b4e550 GL |
600 | icr = readl(_ICR(i2c)) & ~(ICR_STOP | ICR_ALDIE); |
601 | writel(icr | ICR_START | ICR_TB, _ICR(i2c)); | |
b652b438 RK |
602 | } |
603 | ||
7d054817 JD |
604 | static inline void i2c_pxa_stop_message(struct pxa_i2c *i2c) |
605 | { | |
606 | u32 icr; | |
607 | ||
608 | /* | |
609 | * Clear the STOP and ACK flags | |
610 | */ | |
611 | icr = readl(_ICR(i2c)); | |
612 | icr &= ~(ICR_STOP | ICR_ACKNAK); | |
0cfe61e1 | 613 | writel(icr, _ICR(i2c)); |
7d054817 JD |
614 | } |
615 | ||
b7a36701 MR |
616 | static int i2c_pxa_pio_set_master(struct pxa_i2c *i2c) |
617 | { | |
618 | /* make timeout the same as for interrupt based functions */ | |
619 | long timeout = 2 * DEF_TIMEOUT; | |
620 | ||
621 | /* | |
622 | * Wait for the bus to become free. | |
623 | */ | |
624 | while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB)) { | |
625 | udelay(1000); | |
626 | show_state(i2c); | |
627 | } | |
628 | ||
d10db3a0 | 629 | if (timeout < 0) { |
b7a36701 MR |
630 | show_state(i2c); |
631 | dev_err(&i2c->adap.dev, | |
632 | "i2c_pxa: timeout waiting for bus free\n"); | |
633 | return I2C_RETRY; | |
634 | } | |
635 | ||
636 | /* | |
637 | * Set master mode. | |
638 | */ | |
639 | writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c)); | |
640 | ||
641 | return 0; | |
642 | } | |
643 | ||
644 | static int i2c_pxa_do_pio_xfer(struct pxa_i2c *i2c, | |
645 | struct i2c_msg *msg, int num) | |
646 | { | |
647 | unsigned long timeout = 500000; /* 5 seconds */ | |
648 | int ret = 0; | |
649 | ||
650 | ret = i2c_pxa_pio_set_master(i2c); | |
651 | if (ret) | |
652 | goto out; | |
653 | ||
654 | i2c->msg = msg; | |
655 | i2c->msg_num = num; | |
656 | i2c->msg_idx = 0; | |
657 | i2c->msg_ptr = 0; | |
658 | i2c->irqlogidx = 0; | |
659 | ||
660 | i2c_pxa_start_message(i2c); | |
661 | ||
a746b578 | 662 | while (i2c->msg_num > 0 && --timeout) { |
b7a36701 MR |
663 | i2c_pxa_handler(0, i2c); |
664 | udelay(10); | |
665 | } | |
666 | ||
667 | i2c_pxa_stop_message(i2c); | |
668 | ||
669 | /* | |
670 | * We place the return code in i2c->msg_idx. | |
671 | */ | |
672 | ret = i2c->msg_idx; | |
673 | ||
674 | out: | |
675 | if (timeout == 0) | |
676 | i2c_pxa_scream_blue_murder(i2c, "timeout"); | |
677 | ||
678 | return ret; | |
679 | } | |
680 | ||
b652b438 | 681 | /* |
3fb9a655 | 682 | * We are protected by the adapter bus mutex. |
b652b438 RK |
683 | */ |
684 | static int i2c_pxa_do_xfer(struct pxa_i2c *i2c, struct i2c_msg *msg, int num) | |
685 | { | |
686 | long timeout; | |
687 | int ret; | |
688 | ||
689 | /* | |
690 | * Wait for the bus to become free. | |
691 | */ | |
692 | ret = i2c_pxa_wait_bus_not_busy(i2c); | |
693 | if (ret) { | |
6fd60fa9 | 694 | dev_err(&i2c->adap.dev, "i2c_pxa: timeout waiting for bus free\n"); |
b652b438 RK |
695 | goto out; |
696 | } | |
697 | ||
698 | /* | |
699 | * Set master mode. | |
700 | */ | |
701 | ret = i2c_pxa_set_master(i2c); | |
702 | if (ret) { | |
6fd60fa9 | 703 | dev_err(&i2c->adap.dev, "i2c_pxa_set_master: error %d\n", ret); |
b652b438 RK |
704 | goto out; |
705 | } | |
706 | ||
707 | spin_lock_irq(&i2c->lock); | |
708 | ||
709 | i2c->msg = msg; | |
710 | i2c->msg_num = num; | |
711 | i2c->msg_idx = 0; | |
712 | i2c->msg_ptr = 0; | |
713 | i2c->irqlogidx = 0; | |
714 | ||
715 | i2c_pxa_start_message(i2c); | |
716 | ||
717 | spin_unlock_irq(&i2c->lock); | |
718 | ||
719 | /* | |
720 | * The rest of the processing occurs in the interrupt handler. | |
721 | */ | |
722 | timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5); | |
7d054817 | 723 | i2c_pxa_stop_message(i2c); |
b652b438 RK |
724 | |
725 | /* | |
726 | * We place the return code in i2c->msg_idx. | |
727 | */ | |
728 | ret = i2c->msg_idx; | |
729 | ||
730 | if (timeout == 0) | |
731 | i2c_pxa_scream_blue_murder(i2c, "timeout"); | |
732 | ||
733 | out: | |
734 | return ret; | |
735 | } | |
736 | ||
b7a36701 MR |
737 | static int i2c_pxa_pio_xfer(struct i2c_adapter *adap, |
738 | struct i2c_msg msgs[], int num) | |
739 | { | |
740 | struct pxa_i2c *i2c = adap->algo_data; | |
741 | int ret, i; | |
742 | ||
743 | /* If the I2C controller is disabled we need to reset it | |
744 | (probably due to a suspend/resume destroying state). We do | |
745 | this here as we can then avoid worrying about resuming the | |
746 | controller before its users. */ | |
747 | if (!(readl(_ICR(i2c)) & ICR_IUE)) | |
748 | i2c_pxa_reset(i2c); | |
749 | ||
750 | for (i = adap->retries; i >= 0; i--) { | |
751 | ret = i2c_pxa_do_pio_xfer(i2c, msgs, num); | |
752 | if (ret != I2C_RETRY) | |
753 | goto out; | |
754 | ||
755 | if (i2c_debug) | |
756 | dev_dbg(&adap->dev, "Retrying transmission\n"); | |
757 | udelay(100); | |
758 | } | |
759 | i2c_pxa_scream_blue_murder(i2c, "exhausted retries"); | |
760 | ret = -EREMOTEIO; | |
761 | out: | |
762 | i2c_pxa_set_slave(i2c, ret); | |
763 | return ret; | |
764 | } | |
765 | ||
b652b438 RK |
766 | /* |
767 | * i2c_pxa_master_complete - complete the message and wake up. | |
768 | */ | |
769 | static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret) | |
770 | { | |
771 | i2c->msg_ptr = 0; | |
772 | i2c->msg = NULL; | |
773 | i2c->msg_idx ++; | |
774 | i2c->msg_num = 0; | |
775 | if (ret) | |
776 | i2c->msg_idx = ret; | |
b7a36701 MR |
777 | if (!i2c->use_pio) |
778 | wake_up(&i2c->wait); | |
b652b438 RK |
779 | } |
780 | ||
781 | static void i2c_pxa_irq_txempty(struct pxa_i2c *i2c, u32 isr) | |
782 | { | |
a7b4e550 | 783 | u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB); |
b652b438 RK |
784 | |
785 | again: | |
786 | /* | |
787 | * If ISR_ALD is set, we lost arbitration. | |
788 | */ | |
789 | if (isr & ISR_ALD) { | |
790 | /* | |
791 | * Do we need to do anything here? The PXA docs | |
792 | * are vague about what happens. | |
793 | */ | |
794 | i2c_pxa_scream_blue_murder(i2c, "ALD set"); | |
795 | ||
796 | /* | |
797 | * We ignore this error. We seem to see spurious ALDs | |
798 | * for seemingly no reason. If we handle them as I think | |
799 | * they should, we end up causing an I2C error, which | |
800 | * is painful for some systems. | |
801 | */ | |
802 | return; /* ignore */ | |
803 | } | |
804 | ||
805 | if (isr & ISR_BED) { | |
806 | int ret = BUS_ERROR; | |
807 | ||
808 | /* | |
809 | * I2C bus error - either the device NAK'd us, or | |
810 | * something more serious happened. If we were NAK'd | |
811 | * on the initial address phase, we can retry. | |
812 | */ | |
813 | if (isr & ISR_ACKNAK) { | |
814 | if (i2c->msg_ptr == 0 && i2c->msg_idx == 0) | |
815 | ret = I2C_RETRY; | |
816 | else | |
817 | ret = XFER_NAKED; | |
818 | } | |
819 | i2c_pxa_master_complete(i2c, ret); | |
820 | } else if (isr & ISR_RWM) { | |
821 | /* | |
822 | * Read mode. We have just sent the address byte, and | |
823 | * now we must initiate the transfer. | |
824 | */ | |
825 | if (i2c->msg_ptr == i2c->msg->len - 1 && | |
826 | i2c->msg_idx == i2c->msg_num - 1) | |
827 | icr |= ICR_STOP | ICR_ACKNAK; | |
828 | ||
829 | icr |= ICR_ALDIE | ICR_TB; | |
830 | } else if (i2c->msg_ptr < i2c->msg->len) { | |
831 | /* | |
832 | * Write mode. Write the next data byte. | |
833 | */ | |
a7b4e550 | 834 | writel(i2c->msg->buf[i2c->msg_ptr++], _IDBR(i2c)); |
b652b438 RK |
835 | |
836 | icr |= ICR_ALDIE | ICR_TB; | |
837 | ||
838 | /* | |
839 | * If this is the last byte of the last message, send | |
840 | * a STOP. | |
841 | */ | |
842 | if (i2c->msg_ptr == i2c->msg->len && | |
843 | i2c->msg_idx == i2c->msg_num - 1) | |
844 | icr |= ICR_STOP; | |
845 | } else if (i2c->msg_idx < i2c->msg_num - 1) { | |
846 | /* | |
847 | * Next segment of the message. | |
848 | */ | |
849 | i2c->msg_ptr = 0; | |
850 | i2c->msg_idx ++; | |
851 | i2c->msg++; | |
852 | ||
853 | /* | |
854 | * If we aren't doing a repeated start and address, | |
855 | * go back and try to send the next byte. Note that | |
856 | * we do not support switching the R/W direction here. | |
857 | */ | |
858 | if (i2c->msg->flags & I2C_M_NOSTART) | |
859 | goto again; | |
860 | ||
861 | /* | |
862 | * Write the next address. | |
863 | */ | |
a7b4e550 | 864 | writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c)); |
b652b438 RK |
865 | |
866 | /* | |
867 | * And trigger a repeated start, and send the byte. | |
868 | */ | |
869 | icr &= ~ICR_ALDIE; | |
870 | icr |= ICR_START | ICR_TB; | |
871 | } else { | |
872 | if (i2c->msg->len == 0) { | |
873 | /* | |
874 | * Device probes have a message length of zero | |
875 | * and need the bus to be reset before it can | |
876 | * be used again. | |
877 | */ | |
878 | i2c_pxa_reset(i2c); | |
879 | } | |
880 | i2c_pxa_master_complete(i2c, 0); | |
881 | } | |
882 | ||
883 | i2c->icrlog[i2c->irqlogidx-1] = icr; | |
884 | ||
a7b4e550 | 885 | writel(icr, _ICR(i2c)); |
b652b438 RK |
886 | show_state(i2c); |
887 | } | |
888 | ||
889 | static void i2c_pxa_irq_rxfull(struct pxa_i2c *i2c, u32 isr) | |
890 | { | |
a7b4e550 | 891 | u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB); |
b652b438 RK |
892 | |
893 | /* | |
894 | * Read the byte. | |
895 | */ | |
a7b4e550 | 896 | i2c->msg->buf[i2c->msg_ptr++] = readl(_IDBR(i2c)); |
b652b438 RK |
897 | |
898 | if (i2c->msg_ptr < i2c->msg->len) { | |
899 | /* | |
900 | * If this is the last byte of the last | |
901 | * message, send a STOP. | |
902 | */ | |
903 | if (i2c->msg_ptr == i2c->msg->len - 1) | |
904 | icr |= ICR_STOP | ICR_ACKNAK; | |
905 | ||
906 | icr |= ICR_ALDIE | ICR_TB; | |
907 | } else { | |
908 | i2c_pxa_master_complete(i2c, 0); | |
909 | } | |
910 | ||
911 | i2c->icrlog[i2c->irqlogidx-1] = icr; | |
912 | ||
a7b4e550 | 913 | writel(icr, _ICR(i2c)); |
b652b438 RK |
914 | } |
915 | ||
7d12e780 | 916 | static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id) |
b652b438 RK |
917 | { |
918 | struct pxa_i2c *i2c = dev_id; | |
a7b4e550 | 919 | u32 isr = readl(_ISR(i2c)); |
b652b438 RK |
920 | |
921 | if (i2c_debug > 2 && 0) { | |
6fd60fa9 | 922 | dev_dbg(&i2c->adap.dev, "%s: ISR=%08x, ICR=%08x, IBMR=%02x\n", |
a7b4e550 | 923 | __func__, isr, readl(_ICR(i2c)), readl(_IBMR(i2c))); |
b652b438 RK |
924 | decode_ISR(isr); |
925 | } | |
926 | ||
7e3d7db5 | 927 | if (i2c->irqlogidx < ARRAY_SIZE(i2c->isrlog)) |
b652b438 RK |
928 | i2c->isrlog[i2c->irqlogidx++] = isr; |
929 | ||
930 | show_state(i2c); | |
931 | ||
932 | /* | |
933 | * Always clear all pending IRQs. | |
934 | */ | |
a7b4e550 | 935 | writel(isr & (ISR_SSD|ISR_ALD|ISR_ITE|ISR_IRF|ISR_SAD|ISR_BED), _ISR(i2c)); |
b652b438 RK |
936 | |
937 | if (isr & ISR_SAD) | |
938 | i2c_pxa_slave_start(i2c, isr); | |
939 | if (isr & ISR_SSD) | |
940 | i2c_pxa_slave_stop(i2c); | |
941 | ||
942 | if (i2c_pxa_is_slavemode(i2c)) { | |
943 | if (isr & ISR_ITE) | |
944 | i2c_pxa_slave_txempty(i2c, isr); | |
945 | if (isr & ISR_IRF) | |
946 | i2c_pxa_slave_rxfull(i2c, isr); | |
947 | } else if (i2c->msg) { | |
948 | if (isr & ISR_ITE) | |
949 | i2c_pxa_irq_txempty(i2c, isr); | |
950 | if (isr & ISR_IRF) | |
951 | i2c_pxa_irq_rxfull(i2c, isr); | |
952 | } else { | |
953 | i2c_pxa_scream_blue_murder(i2c, "spurious irq"); | |
954 | } | |
955 | ||
956 | return IRQ_HANDLED; | |
957 | } | |
958 | ||
959 | ||
960 | static int i2c_pxa_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) | |
961 | { | |
962 | struct pxa_i2c *i2c = adap->algo_data; | |
963 | int ret, i; | |
964 | ||
965 | for (i = adap->retries; i >= 0; i--) { | |
966 | ret = i2c_pxa_do_xfer(i2c, msgs, num); | |
967 | if (ret != I2C_RETRY) | |
968 | goto out; | |
969 | ||
970 | if (i2c_debug) | |
6fd60fa9 | 971 | dev_dbg(&adap->dev, "Retrying transmission\n"); |
b652b438 RK |
972 | udelay(100); |
973 | } | |
974 | i2c_pxa_scream_blue_murder(i2c, "exhausted retries"); | |
975 | ret = -EREMOTEIO; | |
976 | out: | |
977 | i2c_pxa_set_slave(i2c, ret); | |
978 | return ret; | |
979 | } | |
980 | ||
da16e324 RK |
981 | static u32 i2c_pxa_functionality(struct i2c_adapter *adap) |
982 | { | |
983 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; | |
984 | } | |
985 | ||
8f9082c5 | 986 | static const struct i2c_algorithm i2c_pxa_algorithm = { |
b652b438 | 987 | .master_xfer = i2c_pxa_xfer, |
da16e324 | 988 | .functionality = i2c_pxa_functionality, |
b652b438 RK |
989 | }; |
990 | ||
b7a36701 MR |
991 | static const struct i2c_algorithm i2c_pxa_pio_algorithm = { |
992 | .master_xfer = i2c_pxa_pio_xfer, | |
993 | .functionality = i2c_pxa_functionality, | |
994 | }; | |
995 | ||
3ae5eaec | 996 | static int i2c_pxa_probe(struct platform_device *dev) |
b652b438 | 997 | { |
6776f3d2 | 998 | struct pxa_i2c *i2c; |
a7b4e550 | 999 | struct resource *res; |
3ae5eaec | 1000 | struct i2c_pxa_platform_data *plat = dev->dev.platform_data; |
f23d4911 | 1001 | struct platform_device_id *id = platform_get_device_id(dev); |
b652b438 | 1002 | int ret; |
a7b4e550 | 1003 | int irq; |
b652b438 | 1004 | |
a7b4e550 GL |
1005 | res = platform_get_resource(dev, IORESOURCE_MEM, 0); |
1006 | irq = platform_get_irq(dev, 0); | |
1007 | if (res == NULL || irq < 0) | |
1008 | return -ENODEV; | |
1009 | ||
c6ffddea | 1010 | if (!request_mem_region(res->start, resource_size(res), res->name)) |
a7b4e550 GL |
1011 | return -ENOMEM; |
1012 | ||
6776f3d2 | 1013 | i2c = kzalloc(sizeof(struct pxa_i2c), GFP_KERNEL); |
a7b4e550 GL |
1014 | if (!i2c) { |
1015 | ret = -ENOMEM; | |
1016 | goto emalloc; | |
1017 | } | |
1018 | ||
6776f3d2 | 1019 | i2c->adap.owner = THIS_MODULE; |
6776f3d2 ES |
1020 | i2c->adap.retries = 5; |
1021 | ||
1022 | spin_lock_init(&i2c->lock); | |
a7b4e550 | 1023 | init_waitqueue_head(&i2c->wait); |
6776f3d2 | 1024 | |
a92b36ed WS |
1025 | /* |
1026 | * If "dev->id" is negative we consider it as zero. | |
1027 | * The reason to do so is to avoid sysfs names that only make | |
1028 | * sense when there are multiple adapters. | |
1029 | */ | |
1030 | i2c->adap.nr = dev->id != -1 ? dev->id : 0; | |
1031 | snprintf(i2c->adap.name, sizeof(i2c->adap.name), "pxa_i2c-i2c.%u", | |
1032 | i2c->adap.nr); | |
a7b4e550 | 1033 | |
e0d8b13a | 1034 | i2c->clk = clk_get(&dev->dev, NULL); |
c3cef3f3 RK |
1035 | if (IS_ERR(i2c->clk)) { |
1036 | ret = PTR_ERR(i2c->clk); | |
1037 | goto eclk; | |
1038 | } | |
1039 | ||
c6ffddea | 1040 | i2c->reg_base = ioremap(res->start, resource_size(res)); |
a7b4e550 GL |
1041 | if (!i2c->reg_base) { |
1042 | ret = -EIO; | |
1043 | goto eremap; | |
1044 | } | |
f23d4911 | 1045 | i2c->reg_shift = REG_SHIFT(id->driver_data); |
a7b4e550 GL |
1046 | |
1047 | i2c->iobase = res->start; | |
c6ffddea | 1048 | i2c->iosize = resource_size(res); |
a7b4e550 GL |
1049 | |
1050 | i2c->irq = irq; | |
b652b438 RK |
1051 | |
1052 | i2c->slave_addr = I2C_PXA_SLAVE_ADDR; | |
1053 | ||
1054 | #ifdef CONFIG_I2C_PXA_SLAVE | |
b652b438 RK |
1055 | if (plat) { |
1056 | i2c->slave_addr = plat->slave_addr; | |
beea494d | 1057 | i2c->slave = plat->slave; |
b652b438 RK |
1058 | } |
1059 | #endif | |
1060 | ||
c3cef3f3 | 1061 | clk_enable(i2c->clk); |
a7b4e550 | 1062 | |
b7a36701 MR |
1063 | if (plat) { |
1064 | i2c->adap.class = plat->class; | |
1065 | i2c->use_pio = plat->use_pio; | |
c46c9482 | 1066 | i2c->fast_mode = plat->fast_mode; |
b7a36701 MR |
1067 | } |
1068 | ||
1069 | if (i2c->use_pio) { | |
1070 | i2c->adap.algo = &i2c_pxa_pio_algorithm; | |
1071 | } else { | |
1072 | i2c->adap.algo = &i2c_pxa_algorithm; | |
1073 | ret = request_irq(irq, i2c_pxa_handler, IRQF_DISABLED, | |
1074 | i2c->adap.name, i2c); | |
1075 | if (ret) | |
1076 | goto ereqirq; | |
1077 | } | |
a7b4e550 | 1078 | |
b652b438 RK |
1079 | i2c_pxa_reset(i2c); |
1080 | ||
1081 | i2c->adap.algo_data = i2c; | |
3ae5eaec | 1082 | i2c->adap.dev.parent = &dev->dev; |
b652b438 | 1083 | |
066af983 | 1084 | ret = i2c_add_numbered_adapter(&i2c->adap); |
b652b438 RK |
1085 | if (ret < 0) { |
1086 | printk(KERN_INFO "I2C: Failed to add bus\n"); | |
a7b4e550 | 1087 | goto eadapt; |
b652b438 RK |
1088 | } |
1089 | ||
3ae5eaec | 1090 | platform_set_drvdata(dev, i2c); |
b652b438 RK |
1091 | |
1092 | #ifdef CONFIG_I2C_PXA_SLAVE | |
1093 | printk(KERN_INFO "I2C: %s: PXA I2C adapter, slave address %d\n", | |
22e965c2 | 1094 | dev_name(&i2c->adap.dev), i2c->slave_addr); |
b652b438 RK |
1095 | #else |
1096 | printk(KERN_INFO "I2C: %s: PXA I2C adapter\n", | |
22e965c2 | 1097 | dev_name(&i2c->adap.dev)); |
b652b438 RK |
1098 | #endif |
1099 | return 0; | |
1100 | ||
a7b4e550 | 1101 | eadapt: |
b7a36701 MR |
1102 | if (!i2c->use_pio) |
1103 | free_irq(irq, i2c); | |
a7b4e550 | 1104 | ereqirq: |
c3cef3f3 | 1105 | clk_disable(i2c->clk); |
a92b36ed | 1106 | iounmap(i2c->reg_base); |
a7b4e550 | 1107 | eremap: |
c3cef3f3 RK |
1108 | clk_put(i2c->clk); |
1109 | eclk: | |
a7b4e550 GL |
1110 | kfree(i2c); |
1111 | emalloc: | |
c6ffddea | 1112 | release_mem_region(res->start, resource_size(res)); |
b652b438 RK |
1113 | return ret; |
1114 | } | |
1115 | ||
a92b36ed | 1116 | static int __exit i2c_pxa_remove(struct platform_device *dev) |
b652b438 | 1117 | { |
3ae5eaec | 1118 | struct pxa_i2c *i2c = platform_get_drvdata(dev); |
b652b438 | 1119 | |
3ae5eaec | 1120 | platform_set_drvdata(dev, NULL); |
b652b438 RK |
1121 | |
1122 | i2c_del_adapter(&i2c->adap); | |
b7a36701 MR |
1123 | if (!i2c->use_pio) |
1124 | free_irq(i2c->irq, i2c); | |
c3cef3f3 RK |
1125 | |
1126 | clk_disable(i2c->clk); | |
1127 | clk_put(i2c->clk); | |
c3cef3f3 | 1128 | |
a92b36ed | 1129 | iounmap(i2c->reg_base); |
a7b4e550 GL |
1130 | release_mem_region(i2c->iobase, i2c->iosize); |
1131 | kfree(i2c); | |
b652b438 RK |
1132 | |
1133 | return 0; | |
1134 | } | |
1135 | ||
e7d48fa2 | 1136 | #ifdef CONFIG_PM |
57f4d4f1 | 1137 | static int i2c_pxa_suspend_noirq(struct device *dev) |
e7d48fa2 | 1138 | { |
57f4d4f1 MD |
1139 | struct platform_device *pdev = to_platform_device(dev); |
1140 | struct pxa_i2c *i2c = platform_get_drvdata(pdev); | |
1141 | ||
e7d48fa2 | 1142 | clk_disable(i2c->clk); |
57f4d4f1 | 1143 | |
e7d48fa2 RK |
1144 | return 0; |
1145 | } | |
1146 | ||
57f4d4f1 | 1147 | static int i2c_pxa_resume_noirq(struct device *dev) |
e7d48fa2 | 1148 | { |
57f4d4f1 MD |
1149 | struct platform_device *pdev = to_platform_device(dev); |
1150 | struct pxa_i2c *i2c = platform_get_drvdata(pdev); | |
e7d48fa2 RK |
1151 | |
1152 | clk_enable(i2c->clk); | |
1153 | i2c_pxa_reset(i2c); | |
1154 | ||
1155 | return 0; | |
1156 | } | |
57f4d4f1 | 1157 | |
47145210 | 1158 | static const struct dev_pm_ops i2c_pxa_dev_pm_ops = { |
57f4d4f1 MD |
1159 | .suspend_noirq = i2c_pxa_suspend_noirq, |
1160 | .resume_noirq = i2c_pxa_resume_noirq, | |
1161 | }; | |
1162 | ||
1163 | #define I2C_PXA_DEV_PM_OPS (&i2c_pxa_dev_pm_ops) | |
e7d48fa2 | 1164 | #else |
57f4d4f1 | 1165 | #define I2C_PXA_DEV_PM_OPS NULL |
e7d48fa2 RK |
1166 | #endif |
1167 | ||
3ae5eaec | 1168 | static struct platform_driver i2c_pxa_driver = { |
b652b438 | 1169 | .probe = i2c_pxa_probe, |
a92b36ed | 1170 | .remove = __exit_p(i2c_pxa_remove), |
3ae5eaec RK |
1171 | .driver = { |
1172 | .name = "pxa2xx-i2c", | |
a92b36ed | 1173 | .owner = THIS_MODULE, |
57f4d4f1 | 1174 | .pm = I2C_PXA_DEV_PM_OPS, |
3ae5eaec | 1175 | }, |
f23d4911 | 1176 | .id_table = i2c_pxa_id_table, |
b652b438 RK |
1177 | }; |
1178 | ||
1179 | static int __init i2c_adap_pxa_init(void) | |
1180 | { | |
3ae5eaec | 1181 | return platform_driver_register(&i2c_pxa_driver); |
b652b438 RK |
1182 | } |
1183 | ||
a92b36ed | 1184 | static void __exit i2c_adap_pxa_exit(void) |
b652b438 | 1185 | { |
d6a7b5f8 | 1186 | platform_driver_unregister(&i2c_pxa_driver); |
b652b438 RK |
1187 | } |
1188 | ||
ece5f7b3 | 1189 | MODULE_LICENSE("GPL"); |
add8eda7 | 1190 | MODULE_ALIAS("platform:pxa2xx-i2c"); |
ece5f7b3 | 1191 | |
47a9b137 | 1192 | subsys_initcall(i2c_adap_pxa_init); |
b652b438 | 1193 | module_exit(i2c_adap_pxa_exit); |