Commit | Line | Data |
---|---|---|
b652b438 RK |
1 | /* |
2 | * i2c_adap_pxa.c | |
3 | * | |
4 | * I2C adapter for the PXA I2C bus access. | |
5 | * | |
6 | * Copyright (C) 2002 Intrinsyc Software Inc. | |
7 | * Copyright (C) 2004-2005 Deep Blue Solutions Ltd. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * History: | |
14 | * Apr 2002: Initial version [CS] | |
15 | * Jun 2002: Properly seperated algo/adap [FB] | |
16 | * Jan 2003: Fixed several bugs concerning interrupt handling [Kai-Uwe Bloem] | |
17 | * Jan 2003: added limited signal handling [Kai-Uwe Bloem] | |
18 | * Sep 2004: Major rework to ensure efficient bus handling [RMK] | |
19 | * Dec 2004: Added support for PXA27x and slave device probing [Liam Girdwood] | |
20 | * Feb 2005: Rework slave mode handling [RMK] | |
21 | */ | |
22 | #include <linux/kernel.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/i2c.h> | |
25 | #include <linux/i2c-id.h> | |
26 | #include <linux/init.h> | |
27 | #include <linux/time.h> | |
28 | #include <linux/sched.h> | |
29 | #include <linux/delay.h> | |
30 | #include <linux/errno.h> | |
31 | #include <linux/interrupt.h> | |
32 | #include <linux/i2c-pxa.h> | |
d052d1be | 33 | #include <linux/platform_device.h> |
c3cef3f3 RK |
34 | #include <linux/err.h> |
35 | #include <linux/clk.h> | |
b652b438 RK |
36 | |
37 | #include <asm/hardware.h> | |
38 | #include <asm/irq.h> | |
a7b4e550 | 39 | #include <asm/io.h> |
b652b438 RK |
40 | #include <asm/arch/i2c.h> |
41 | #include <asm/arch/pxa-regs.h> | |
42 | ||
43 | struct pxa_i2c { | |
44 | spinlock_t lock; | |
45 | wait_queue_head_t wait; | |
46 | struct i2c_msg *msg; | |
47 | unsigned int msg_num; | |
48 | unsigned int msg_idx; | |
49 | unsigned int msg_ptr; | |
50 | unsigned int slave_addr; | |
51 | ||
52 | struct i2c_adapter adap; | |
c3cef3f3 | 53 | struct clk *clk; |
b652b438 RK |
54 | #ifdef CONFIG_I2C_PXA_SLAVE |
55 | struct i2c_slave_client *slave; | |
56 | #endif | |
57 | ||
58 | unsigned int irqlogidx; | |
59 | u32 isrlog[32]; | |
60 | u32 icrlog[32]; | |
a7b4e550 GL |
61 | |
62 | void __iomem *reg_base; | |
63 | ||
64 | unsigned long iobase; | |
65 | unsigned long iosize; | |
66 | ||
67 | int irq; | |
b652b438 RK |
68 | }; |
69 | ||
a7b4e550 GL |
70 | #define _IBMR(i2c) ((i2c)->reg_base + 0) |
71 | #define _IDBR(i2c) ((i2c)->reg_base + 8) | |
72 | #define _ICR(i2c) ((i2c)->reg_base + 0x10) | |
73 | #define _ISR(i2c) ((i2c)->reg_base + 0x18) | |
74 | #define _ISAR(i2c) ((i2c)->reg_base + 0x20) | |
75 | ||
b652b438 RK |
76 | /* |
77 | * I2C Slave mode address | |
78 | */ | |
79 | #define I2C_PXA_SLAVE_ADDR 0x1 | |
80 | ||
b652b438 RK |
81 | #ifdef DEBUG |
82 | ||
83 | struct bits { | |
84 | u32 mask; | |
85 | const char *set; | |
86 | const char *unset; | |
87 | }; | |
ed11399d | 88 | #define PXA_BIT(m, s, u) { .mask = m, .set = s, .unset = u } |
b652b438 RK |
89 | |
90 | static inline void | |
91 | decode_bits(const char *prefix, const struct bits *bits, int num, u32 val) | |
92 | { | |
93 | printk("%s %08x: ", prefix, val); | |
94 | while (num--) { | |
95 | const char *str = val & bits->mask ? bits->set : bits->unset; | |
96 | if (str) | |
97 | printk("%s ", str); | |
98 | bits++; | |
99 | } | |
100 | } | |
101 | ||
102 | static const struct bits isr_bits[] = { | |
ed11399d JS |
103 | PXA_BIT(ISR_RWM, "RX", "TX"), |
104 | PXA_BIT(ISR_ACKNAK, "NAK", "ACK"), | |
105 | PXA_BIT(ISR_UB, "Bsy", "Rdy"), | |
106 | PXA_BIT(ISR_IBB, "BusBsy", "BusRdy"), | |
107 | PXA_BIT(ISR_SSD, "SlaveStop", NULL), | |
108 | PXA_BIT(ISR_ALD, "ALD", NULL), | |
109 | PXA_BIT(ISR_ITE, "TxEmpty", NULL), | |
110 | PXA_BIT(ISR_IRF, "RxFull", NULL), | |
111 | PXA_BIT(ISR_GCAD, "GenCall", NULL), | |
112 | PXA_BIT(ISR_SAD, "SlaveAddr", NULL), | |
113 | PXA_BIT(ISR_BED, "BusErr", NULL), | |
b652b438 RK |
114 | }; |
115 | ||
116 | static void decode_ISR(unsigned int val) | |
117 | { | |
6fd60fa9 | 118 | decode_bits(KERN_DEBUG "ISR", isr_bits, ARRAY_SIZE(isr_bits), val); |
b652b438 RK |
119 | printk("\n"); |
120 | } | |
121 | ||
122 | static const struct bits icr_bits[] = { | |
ed11399d JS |
123 | PXA_BIT(ICR_START, "START", NULL), |
124 | PXA_BIT(ICR_STOP, "STOP", NULL), | |
125 | PXA_BIT(ICR_ACKNAK, "ACKNAK", NULL), | |
126 | PXA_BIT(ICR_TB, "TB", NULL), | |
127 | PXA_BIT(ICR_MA, "MA", NULL), | |
128 | PXA_BIT(ICR_SCLE, "SCLE", "scle"), | |
129 | PXA_BIT(ICR_IUE, "IUE", "iue"), | |
130 | PXA_BIT(ICR_GCD, "GCD", NULL), | |
131 | PXA_BIT(ICR_ITEIE, "ITEIE", NULL), | |
132 | PXA_BIT(ICR_IRFIE, "IRFIE", NULL), | |
133 | PXA_BIT(ICR_BEIE, "BEIE", NULL), | |
134 | PXA_BIT(ICR_SSDIE, "SSDIE", NULL), | |
135 | PXA_BIT(ICR_ALDIE, "ALDIE", NULL), | |
136 | PXA_BIT(ICR_SADIE, "SADIE", NULL), | |
137 | PXA_BIT(ICR_UR, "UR", "ur"), | |
b652b438 RK |
138 | }; |
139 | ||
140 | static void decode_ICR(unsigned int val) | |
141 | { | |
6fd60fa9 | 142 | decode_bits(KERN_DEBUG "ICR", icr_bits, ARRAY_SIZE(icr_bits), val); |
b652b438 RK |
143 | printk("\n"); |
144 | } | |
145 | ||
146 | static unsigned int i2c_debug = DEBUG; | |
147 | ||
148 | static void i2c_pxa_show_state(struct pxa_i2c *i2c, int lno, const char *fname) | |
149 | { | |
a7b4e550 GL |
150 | dev_dbg(&i2c->adap.dev, "state:%s:%d: ISR=%08x, ICR=%08x, IBMR=%02x\n", fname, lno, |
151 | readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c))); | |
b652b438 RK |
152 | } |
153 | ||
154 | #define show_state(i2c) i2c_pxa_show_state(i2c, __LINE__, __FUNCTION__) | |
155 | #else | |
156 | #define i2c_debug 0 | |
157 | ||
158 | #define show_state(i2c) do { } while (0) | |
159 | #define decode_ISR(val) do { } while (0) | |
160 | #define decode_ICR(val) do { } while (0) | |
161 | #endif | |
162 | ||
6fd60fa9 | 163 | #define eedbg(lvl, x...) do { if ((lvl) < 1) { printk(KERN_DEBUG "" x); } } while(0) |
b652b438 RK |
164 | |
165 | static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret); | |
166 | ||
167 | static void i2c_pxa_scream_blue_murder(struct pxa_i2c *i2c, const char *why) | |
168 | { | |
169 | unsigned int i; | |
170 | printk("i2c: error: %s\n", why); | |
171 | printk("i2c: msg_num: %d msg_idx: %d msg_ptr: %d\n", | |
172 | i2c->msg_num, i2c->msg_idx, i2c->msg_ptr); | |
6fd60fa9 | 173 | printk("i2c: ICR: %08x ISR: %08x\n" |
a7b4e550 | 174 | "i2c: log: ", readl(_ICR(i2c)), readl(_ISR(i2c))); |
b652b438 RK |
175 | for (i = 0; i < i2c->irqlogidx; i++) |
176 | printk("[%08x:%08x] ", i2c->isrlog[i], i2c->icrlog[i]); | |
177 | printk("\n"); | |
178 | } | |
179 | ||
180 | static inline int i2c_pxa_is_slavemode(struct pxa_i2c *i2c) | |
181 | { | |
a7b4e550 | 182 | return !(readl(_ICR(i2c)) & ICR_SCLE); |
b652b438 RK |
183 | } |
184 | ||
185 | static void i2c_pxa_abort(struct pxa_i2c *i2c) | |
186 | { | |
187 | unsigned long timeout = jiffies + HZ/4; | |
188 | ||
189 | if (i2c_pxa_is_slavemode(i2c)) { | |
6fd60fa9 | 190 | dev_dbg(&i2c->adap.dev, "%s: called in slave mode\n", __func__); |
b652b438 RK |
191 | return; |
192 | } | |
193 | ||
a7b4e550 GL |
194 | while (time_before(jiffies, timeout) && (readl(_IBMR(i2c)) & 0x1) == 0) { |
195 | unsigned long icr = readl(_ICR(i2c)); | |
b652b438 RK |
196 | |
197 | icr &= ~ICR_START; | |
198 | icr |= ICR_ACKNAK | ICR_STOP | ICR_TB; | |
199 | ||
a7b4e550 | 200 | writel(icr, _ICR(i2c)); |
b652b438 RK |
201 | |
202 | show_state(i2c); | |
203 | ||
204 | msleep(1); | |
205 | } | |
206 | ||
a7b4e550 GL |
207 | writel(readl(_ICR(i2c)) & ~(ICR_MA | ICR_START | ICR_STOP), |
208 | _ICR(i2c)); | |
b652b438 RK |
209 | } |
210 | ||
211 | static int i2c_pxa_wait_bus_not_busy(struct pxa_i2c *i2c) | |
212 | { | |
213 | int timeout = DEF_TIMEOUT; | |
214 | ||
a7b4e550 GL |
215 | while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB)) { |
216 | if ((readl(_ISR(i2c)) & ISR_SAD) != 0) | |
b652b438 RK |
217 | timeout += 4; |
218 | ||
219 | msleep(2); | |
220 | show_state(i2c); | |
221 | } | |
222 | ||
223 | if (timeout <= 0) | |
224 | show_state(i2c); | |
225 | ||
226 | return timeout <= 0 ? I2C_RETRY : 0; | |
227 | } | |
228 | ||
229 | static int i2c_pxa_wait_master(struct pxa_i2c *i2c) | |
230 | { | |
231 | unsigned long timeout = jiffies + HZ*4; | |
232 | ||
233 | while (time_before(jiffies, timeout)) { | |
234 | if (i2c_debug > 1) | |
6fd60fa9 | 235 | dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n", |
a7b4e550 | 236 | __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c))); |
b652b438 | 237 | |
a7b4e550 | 238 | if (readl(_ISR(i2c)) & ISR_SAD) { |
b652b438 | 239 | if (i2c_debug > 0) |
6fd60fa9 | 240 | dev_dbg(&i2c->adap.dev, "%s: Slave detected\n", __func__); |
b652b438 RK |
241 | goto out; |
242 | } | |
243 | ||
244 | /* wait for unit and bus being not busy, and we also do a | |
245 | * quick check of the i2c lines themselves to ensure they've | |
246 | * gone high... | |
247 | */ | |
a7b4e550 | 248 | if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) == 0 && readl(_IBMR(i2c)) == 3) { |
b652b438 | 249 | if (i2c_debug > 0) |
6fd60fa9 | 250 | dev_dbg(&i2c->adap.dev, "%s: done\n", __func__); |
b652b438 RK |
251 | return 1; |
252 | } | |
253 | ||
254 | msleep(1); | |
255 | } | |
256 | ||
257 | if (i2c_debug > 0) | |
6fd60fa9 | 258 | dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__); |
b652b438 RK |
259 | out: |
260 | return 0; | |
261 | } | |
262 | ||
263 | static int i2c_pxa_set_master(struct pxa_i2c *i2c) | |
264 | { | |
265 | if (i2c_debug) | |
6fd60fa9 | 266 | dev_dbg(&i2c->adap.dev, "setting to bus master\n"); |
b652b438 | 267 | |
a7b4e550 | 268 | if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) != 0) { |
6fd60fa9 | 269 | dev_dbg(&i2c->adap.dev, "%s: unit is busy\n", __func__); |
b652b438 | 270 | if (!i2c_pxa_wait_master(i2c)) { |
6fd60fa9 | 271 | dev_dbg(&i2c->adap.dev, "%s: error: unit busy\n", __func__); |
b652b438 RK |
272 | return I2C_RETRY; |
273 | } | |
274 | } | |
275 | ||
a7b4e550 | 276 | writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c)); |
b652b438 RK |
277 | return 0; |
278 | } | |
279 | ||
280 | #ifdef CONFIG_I2C_PXA_SLAVE | |
281 | static int i2c_pxa_wait_slave(struct pxa_i2c *i2c) | |
282 | { | |
283 | unsigned long timeout = jiffies + HZ*1; | |
284 | ||
285 | /* wait for stop */ | |
286 | ||
287 | show_state(i2c); | |
288 | ||
289 | while (time_before(jiffies, timeout)) { | |
290 | if (i2c_debug > 1) | |
6fd60fa9 | 291 | dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n", |
a7b4e550 | 292 | __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c))); |
b652b438 | 293 | |
a7b4e550 GL |
294 | if ((readl(_ISR(i2c)) & (ISR_UB|ISR_IBB)) == 0 || |
295 | (readl(_ISR(i2c)) & ISR_SAD) != 0 || | |
296 | (readl(_ICR(i2c)) & ICR_SCLE) == 0) { | |
b652b438 | 297 | if (i2c_debug > 1) |
6fd60fa9 | 298 | dev_dbg(&i2c->adap.dev, "%s: done\n", __func__); |
b652b438 RK |
299 | return 1; |
300 | } | |
301 | ||
302 | msleep(1); | |
303 | } | |
304 | ||
305 | if (i2c_debug > 0) | |
6fd60fa9 | 306 | dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__); |
b652b438 RK |
307 | return 0; |
308 | } | |
309 | ||
310 | /* | |
311 | * clear the hold on the bus, and take of anything else | |
312 | * that has been configured | |
313 | */ | |
314 | static void i2c_pxa_set_slave(struct pxa_i2c *i2c, int errcode) | |
315 | { | |
316 | show_state(i2c); | |
317 | ||
318 | if (errcode < 0) { | |
319 | udelay(100); /* simple delay */ | |
320 | } else { | |
321 | /* we need to wait for the stop condition to end */ | |
322 | ||
323 | /* if we where in stop, then clear... */ | |
a7b4e550 | 324 | if (readl(_ICR(i2c)) & ICR_STOP) { |
b652b438 | 325 | udelay(100); |
a7b4e550 | 326 | writel(readl(_ICR(i2c)) & ~ICR_STOP, _ICR(i2c)); |
b652b438 RK |
327 | } |
328 | ||
329 | if (!i2c_pxa_wait_slave(i2c)) { | |
6fd60fa9 RK |
330 | dev_err(&i2c->adap.dev, "%s: wait timedout\n", |
331 | __func__); | |
b652b438 RK |
332 | return; |
333 | } | |
334 | } | |
335 | ||
a7b4e550 GL |
336 | writel(readl(_ICR(i2c)) & ~(ICR_STOP|ICR_ACKNAK|ICR_MA), _ICR(i2c)); |
337 | writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c)); | |
b652b438 RK |
338 | |
339 | if (i2c_debug) { | |
a7b4e550 GL |
340 | dev_dbg(&i2c->adap.dev, "ICR now %08x, ISR %08x\n", readl(_ICR(i2c)), readl(_ISR(i2c))); |
341 | decode_ICR(readl(_ICR(i2c))); | |
b652b438 RK |
342 | } |
343 | } | |
344 | #else | |
345 | #define i2c_pxa_set_slave(i2c, err) do { } while (0) | |
346 | #endif | |
347 | ||
348 | static void i2c_pxa_reset(struct pxa_i2c *i2c) | |
349 | { | |
350 | pr_debug("Resetting I2C Controller Unit\n"); | |
351 | ||
352 | /* abort any transfer currently under way */ | |
353 | i2c_pxa_abort(i2c); | |
354 | ||
355 | /* reset according to 9.8 */ | |
a7b4e550 GL |
356 | writel(ICR_UR, _ICR(i2c)); |
357 | writel(I2C_ISR_INIT, _ISR(i2c)); | |
358 | writel(readl(_ICR(i2c)) & ~ICR_UR, _ICR(i2c)); | |
b652b438 | 359 | |
a7b4e550 | 360 | writel(i2c->slave_addr, _ISAR(i2c)); |
b652b438 RK |
361 | |
362 | /* set control register values */ | |
a7b4e550 | 363 | writel(I2C_ICR_INIT, _ICR(i2c)); |
b652b438 RK |
364 | |
365 | #ifdef CONFIG_I2C_PXA_SLAVE | |
6fd60fa9 | 366 | dev_info(&i2c->adap.dev, "Enabling slave mode\n"); |
a7b4e550 | 367 | writel(readl(_ICR(i2c)) | ICR_SADIE | ICR_ALDIE | ICR_SSDIE, _ICR(i2c)); |
b652b438 RK |
368 | #endif |
369 | ||
370 | i2c_pxa_set_slave(i2c, 0); | |
371 | ||
372 | /* enable unit */ | |
a7b4e550 | 373 | writel(readl(_ICR(i2c)) | ICR_IUE, _ICR(i2c)); |
b652b438 RK |
374 | udelay(100); |
375 | } | |
376 | ||
377 | ||
378 | #ifdef CONFIG_I2C_PXA_SLAVE | |
b652b438 RK |
379 | /* |
380 | * PXA I2C Slave mode | |
381 | */ | |
382 | ||
383 | static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr) | |
384 | { | |
385 | if (isr & ISR_BED) { | |
386 | /* what should we do here? */ | |
387 | } else { | |
84b5abe6 RK |
388 | int ret = 0; |
389 | ||
390 | if (i2c->slave != NULL) | |
391 | ret = i2c->slave->read(i2c->slave->data); | |
b652b438 | 392 | |
a7b4e550 GL |
393 | writel(ret, _IDBR(i2c)); |
394 | writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c)); /* allow next byte */ | |
b652b438 RK |
395 | } |
396 | } | |
397 | ||
398 | static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr) | |
399 | { | |
a7b4e550 | 400 | unsigned int byte = readl(_IDBR(i2c)); |
b652b438 RK |
401 | |
402 | if (i2c->slave != NULL) | |
403 | i2c->slave->write(i2c->slave->data, byte); | |
404 | ||
a7b4e550 | 405 | writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c)); |
b652b438 RK |
406 | } |
407 | ||
408 | static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr) | |
409 | { | |
410 | int timeout; | |
411 | ||
412 | if (i2c_debug > 0) | |
6fd60fa9 | 413 | dev_dbg(&i2c->adap.dev, "SAD, mode is slave-%cx\n", |
b652b438 RK |
414 | (isr & ISR_RWM) ? 'r' : 't'); |
415 | ||
416 | if (i2c->slave != NULL) | |
417 | i2c->slave->event(i2c->slave->data, | |
418 | (isr & ISR_RWM) ? I2C_SLAVE_EVENT_START_READ : I2C_SLAVE_EVENT_START_WRITE); | |
419 | ||
420 | /* | |
421 | * slave could interrupt in the middle of us generating a | |
422 | * start condition... if this happens, we'd better back off | |
423 | * and stop holding the poor thing up | |
424 | */ | |
a7b4e550 GL |
425 | writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c)); |
426 | writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c)); | |
b652b438 RK |
427 | |
428 | timeout = 0x10000; | |
429 | ||
430 | while (1) { | |
a7b4e550 | 431 | if ((readl(_IBMR(i2c)) & 2) == 2) |
b652b438 RK |
432 | break; |
433 | ||
434 | timeout--; | |
435 | ||
436 | if (timeout <= 0) { | |
6fd60fa9 | 437 | dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n"); |
b652b438 RK |
438 | break; |
439 | } | |
440 | } | |
441 | ||
a7b4e550 | 442 | writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c)); |
b652b438 RK |
443 | } |
444 | ||
445 | static void i2c_pxa_slave_stop(struct pxa_i2c *i2c) | |
446 | { | |
447 | if (i2c_debug > 2) | |
6fd60fa9 | 448 | dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop)\n"); |
b652b438 RK |
449 | |
450 | if (i2c->slave != NULL) | |
451 | i2c->slave->event(i2c->slave->data, I2C_SLAVE_EVENT_STOP); | |
452 | ||
453 | if (i2c_debug > 2) | |
6fd60fa9 | 454 | dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop) acked\n"); |
b652b438 RK |
455 | |
456 | /* | |
457 | * If we have a master-mode message waiting, | |
458 | * kick it off now that the slave has completed. | |
459 | */ | |
460 | if (i2c->msg) | |
461 | i2c_pxa_master_complete(i2c, I2C_RETRY); | |
462 | } | |
463 | #else | |
464 | static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr) | |
465 | { | |
466 | if (isr & ISR_BED) { | |
467 | /* what should we do here? */ | |
468 | } else { | |
a7b4e550 GL |
469 | writel(0, _IDBR(i2c)); |
470 | writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c)); | |
b652b438 RK |
471 | } |
472 | } | |
473 | ||
474 | static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr) | |
475 | { | |
a7b4e550 | 476 | writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c)); |
b652b438 RK |
477 | } |
478 | ||
479 | static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr) | |
480 | { | |
481 | int timeout; | |
482 | ||
483 | /* | |
484 | * slave could interrupt in the middle of us generating a | |
485 | * start condition... if this happens, we'd better back off | |
486 | * and stop holding the poor thing up | |
487 | */ | |
a7b4e550 GL |
488 | writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c)); |
489 | writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c)); | |
b652b438 RK |
490 | |
491 | timeout = 0x10000; | |
492 | ||
493 | while (1) { | |
a7b4e550 | 494 | if ((readl(_IBMR(i2c)) & 2) == 2) |
b652b438 RK |
495 | break; |
496 | ||
497 | timeout--; | |
498 | ||
499 | if (timeout <= 0) { | |
6fd60fa9 | 500 | dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n"); |
b652b438 RK |
501 | break; |
502 | } | |
503 | } | |
504 | ||
a7b4e550 | 505 | writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c)); |
b652b438 RK |
506 | } |
507 | ||
508 | static void i2c_pxa_slave_stop(struct pxa_i2c *i2c) | |
509 | { | |
510 | if (i2c->msg) | |
511 | i2c_pxa_master_complete(i2c, I2C_RETRY); | |
512 | } | |
513 | #endif | |
514 | ||
515 | /* | |
516 | * PXA I2C Master mode | |
517 | */ | |
518 | ||
519 | static inline unsigned int i2c_pxa_addr_byte(struct i2c_msg *msg) | |
520 | { | |
521 | unsigned int addr = (msg->addr & 0x7f) << 1; | |
522 | ||
523 | if (msg->flags & I2C_M_RD) | |
524 | addr |= 1; | |
525 | ||
526 | return addr; | |
527 | } | |
528 | ||
529 | static inline void i2c_pxa_start_message(struct pxa_i2c *i2c) | |
530 | { | |
531 | u32 icr; | |
532 | ||
533 | /* | |
534 | * Step 1: target slave address into IDBR | |
535 | */ | |
a7b4e550 | 536 | writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c)); |
b652b438 RK |
537 | |
538 | /* | |
539 | * Step 2: initiate the write. | |
540 | */ | |
a7b4e550 GL |
541 | icr = readl(_ICR(i2c)) & ~(ICR_STOP | ICR_ALDIE); |
542 | writel(icr | ICR_START | ICR_TB, _ICR(i2c)); | |
b652b438 RK |
543 | } |
544 | ||
7d054817 JD |
545 | static inline void i2c_pxa_stop_message(struct pxa_i2c *i2c) |
546 | { | |
547 | u32 icr; | |
548 | ||
549 | /* | |
550 | * Clear the STOP and ACK flags | |
551 | */ | |
552 | icr = readl(_ICR(i2c)); | |
553 | icr &= ~(ICR_STOP | ICR_ACKNAK); | |
0cfe61e1 | 554 | writel(icr, _ICR(i2c)); |
7d054817 JD |
555 | } |
556 | ||
b652b438 | 557 | /* |
3fb9a655 | 558 | * We are protected by the adapter bus mutex. |
b652b438 RK |
559 | */ |
560 | static int i2c_pxa_do_xfer(struct pxa_i2c *i2c, struct i2c_msg *msg, int num) | |
561 | { | |
562 | long timeout; | |
563 | int ret; | |
564 | ||
565 | /* | |
566 | * Wait for the bus to become free. | |
567 | */ | |
568 | ret = i2c_pxa_wait_bus_not_busy(i2c); | |
569 | if (ret) { | |
6fd60fa9 | 570 | dev_err(&i2c->adap.dev, "i2c_pxa: timeout waiting for bus free\n"); |
b652b438 RK |
571 | goto out; |
572 | } | |
573 | ||
574 | /* | |
575 | * Set master mode. | |
576 | */ | |
577 | ret = i2c_pxa_set_master(i2c); | |
578 | if (ret) { | |
6fd60fa9 | 579 | dev_err(&i2c->adap.dev, "i2c_pxa_set_master: error %d\n", ret); |
b652b438 RK |
580 | goto out; |
581 | } | |
582 | ||
583 | spin_lock_irq(&i2c->lock); | |
584 | ||
585 | i2c->msg = msg; | |
586 | i2c->msg_num = num; | |
587 | i2c->msg_idx = 0; | |
588 | i2c->msg_ptr = 0; | |
589 | i2c->irqlogidx = 0; | |
590 | ||
591 | i2c_pxa_start_message(i2c); | |
592 | ||
593 | spin_unlock_irq(&i2c->lock); | |
594 | ||
595 | /* | |
596 | * The rest of the processing occurs in the interrupt handler. | |
597 | */ | |
598 | timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5); | |
7d054817 | 599 | i2c_pxa_stop_message(i2c); |
b652b438 RK |
600 | |
601 | /* | |
602 | * We place the return code in i2c->msg_idx. | |
603 | */ | |
604 | ret = i2c->msg_idx; | |
605 | ||
606 | if (timeout == 0) | |
607 | i2c_pxa_scream_blue_murder(i2c, "timeout"); | |
608 | ||
609 | out: | |
610 | return ret; | |
611 | } | |
612 | ||
613 | /* | |
614 | * i2c_pxa_master_complete - complete the message and wake up. | |
615 | */ | |
616 | static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret) | |
617 | { | |
618 | i2c->msg_ptr = 0; | |
619 | i2c->msg = NULL; | |
620 | i2c->msg_idx ++; | |
621 | i2c->msg_num = 0; | |
622 | if (ret) | |
623 | i2c->msg_idx = ret; | |
624 | wake_up(&i2c->wait); | |
625 | } | |
626 | ||
627 | static void i2c_pxa_irq_txempty(struct pxa_i2c *i2c, u32 isr) | |
628 | { | |
a7b4e550 | 629 | u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB); |
b652b438 RK |
630 | |
631 | again: | |
632 | /* | |
633 | * If ISR_ALD is set, we lost arbitration. | |
634 | */ | |
635 | if (isr & ISR_ALD) { | |
636 | /* | |
637 | * Do we need to do anything here? The PXA docs | |
638 | * are vague about what happens. | |
639 | */ | |
640 | i2c_pxa_scream_blue_murder(i2c, "ALD set"); | |
641 | ||
642 | /* | |
643 | * We ignore this error. We seem to see spurious ALDs | |
644 | * for seemingly no reason. If we handle them as I think | |
645 | * they should, we end up causing an I2C error, which | |
646 | * is painful for some systems. | |
647 | */ | |
648 | return; /* ignore */ | |
649 | } | |
650 | ||
651 | if (isr & ISR_BED) { | |
652 | int ret = BUS_ERROR; | |
653 | ||
654 | /* | |
655 | * I2C bus error - either the device NAK'd us, or | |
656 | * something more serious happened. If we were NAK'd | |
657 | * on the initial address phase, we can retry. | |
658 | */ | |
659 | if (isr & ISR_ACKNAK) { | |
660 | if (i2c->msg_ptr == 0 && i2c->msg_idx == 0) | |
661 | ret = I2C_RETRY; | |
662 | else | |
663 | ret = XFER_NAKED; | |
664 | } | |
665 | i2c_pxa_master_complete(i2c, ret); | |
666 | } else if (isr & ISR_RWM) { | |
667 | /* | |
668 | * Read mode. We have just sent the address byte, and | |
669 | * now we must initiate the transfer. | |
670 | */ | |
671 | if (i2c->msg_ptr == i2c->msg->len - 1 && | |
672 | i2c->msg_idx == i2c->msg_num - 1) | |
673 | icr |= ICR_STOP | ICR_ACKNAK; | |
674 | ||
675 | icr |= ICR_ALDIE | ICR_TB; | |
676 | } else if (i2c->msg_ptr < i2c->msg->len) { | |
677 | /* | |
678 | * Write mode. Write the next data byte. | |
679 | */ | |
a7b4e550 | 680 | writel(i2c->msg->buf[i2c->msg_ptr++], _IDBR(i2c)); |
b652b438 RK |
681 | |
682 | icr |= ICR_ALDIE | ICR_TB; | |
683 | ||
684 | /* | |
685 | * If this is the last byte of the last message, send | |
686 | * a STOP. | |
687 | */ | |
688 | if (i2c->msg_ptr == i2c->msg->len && | |
689 | i2c->msg_idx == i2c->msg_num - 1) | |
690 | icr |= ICR_STOP; | |
691 | } else if (i2c->msg_idx < i2c->msg_num - 1) { | |
692 | /* | |
693 | * Next segment of the message. | |
694 | */ | |
695 | i2c->msg_ptr = 0; | |
696 | i2c->msg_idx ++; | |
697 | i2c->msg++; | |
698 | ||
699 | /* | |
700 | * If we aren't doing a repeated start and address, | |
701 | * go back and try to send the next byte. Note that | |
702 | * we do not support switching the R/W direction here. | |
703 | */ | |
704 | if (i2c->msg->flags & I2C_M_NOSTART) | |
705 | goto again; | |
706 | ||
707 | /* | |
708 | * Write the next address. | |
709 | */ | |
a7b4e550 | 710 | writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c)); |
b652b438 RK |
711 | |
712 | /* | |
713 | * And trigger a repeated start, and send the byte. | |
714 | */ | |
715 | icr &= ~ICR_ALDIE; | |
716 | icr |= ICR_START | ICR_TB; | |
717 | } else { | |
718 | if (i2c->msg->len == 0) { | |
719 | /* | |
720 | * Device probes have a message length of zero | |
721 | * and need the bus to be reset before it can | |
722 | * be used again. | |
723 | */ | |
724 | i2c_pxa_reset(i2c); | |
725 | } | |
726 | i2c_pxa_master_complete(i2c, 0); | |
727 | } | |
728 | ||
729 | i2c->icrlog[i2c->irqlogidx-1] = icr; | |
730 | ||
a7b4e550 | 731 | writel(icr, _ICR(i2c)); |
b652b438 RK |
732 | show_state(i2c); |
733 | } | |
734 | ||
735 | static void i2c_pxa_irq_rxfull(struct pxa_i2c *i2c, u32 isr) | |
736 | { | |
a7b4e550 | 737 | u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB); |
b652b438 RK |
738 | |
739 | /* | |
740 | * Read the byte. | |
741 | */ | |
a7b4e550 | 742 | i2c->msg->buf[i2c->msg_ptr++] = readl(_IDBR(i2c)); |
b652b438 RK |
743 | |
744 | if (i2c->msg_ptr < i2c->msg->len) { | |
745 | /* | |
746 | * If this is the last byte of the last | |
747 | * message, send a STOP. | |
748 | */ | |
749 | if (i2c->msg_ptr == i2c->msg->len - 1) | |
750 | icr |= ICR_STOP | ICR_ACKNAK; | |
751 | ||
752 | icr |= ICR_ALDIE | ICR_TB; | |
753 | } else { | |
754 | i2c_pxa_master_complete(i2c, 0); | |
755 | } | |
756 | ||
757 | i2c->icrlog[i2c->irqlogidx-1] = icr; | |
758 | ||
a7b4e550 | 759 | writel(icr, _ICR(i2c)); |
b652b438 RK |
760 | } |
761 | ||
7d12e780 | 762 | static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id) |
b652b438 RK |
763 | { |
764 | struct pxa_i2c *i2c = dev_id; | |
a7b4e550 | 765 | u32 isr = readl(_ISR(i2c)); |
b652b438 RK |
766 | |
767 | if (i2c_debug > 2 && 0) { | |
6fd60fa9 | 768 | dev_dbg(&i2c->adap.dev, "%s: ISR=%08x, ICR=%08x, IBMR=%02x\n", |
a7b4e550 | 769 | __func__, isr, readl(_ICR(i2c)), readl(_IBMR(i2c))); |
b652b438 RK |
770 | decode_ISR(isr); |
771 | } | |
772 | ||
7e3d7db5 | 773 | if (i2c->irqlogidx < ARRAY_SIZE(i2c->isrlog)) |
b652b438 RK |
774 | i2c->isrlog[i2c->irqlogidx++] = isr; |
775 | ||
776 | show_state(i2c); | |
777 | ||
778 | /* | |
779 | * Always clear all pending IRQs. | |
780 | */ | |
a7b4e550 | 781 | writel(isr & (ISR_SSD|ISR_ALD|ISR_ITE|ISR_IRF|ISR_SAD|ISR_BED), _ISR(i2c)); |
b652b438 RK |
782 | |
783 | if (isr & ISR_SAD) | |
784 | i2c_pxa_slave_start(i2c, isr); | |
785 | if (isr & ISR_SSD) | |
786 | i2c_pxa_slave_stop(i2c); | |
787 | ||
788 | if (i2c_pxa_is_slavemode(i2c)) { | |
789 | if (isr & ISR_ITE) | |
790 | i2c_pxa_slave_txempty(i2c, isr); | |
791 | if (isr & ISR_IRF) | |
792 | i2c_pxa_slave_rxfull(i2c, isr); | |
793 | } else if (i2c->msg) { | |
794 | if (isr & ISR_ITE) | |
795 | i2c_pxa_irq_txempty(i2c, isr); | |
796 | if (isr & ISR_IRF) | |
797 | i2c_pxa_irq_rxfull(i2c, isr); | |
798 | } else { | |
799 | i2c_pxa_scream_blue_murder(i2c, "spurious irq"); | |
800 | } | |
801 | ||
802 | return IRQ_HANDLED; | |
803 | } | |
804 | ||
805 | ||
806 | static int i2c_pxa_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) | |
807 | { | |
808 | struct pxa_i2c *i2c = adap->algo_data; | |
809 | int ret, i; | |
810 | ||
ece5f7b3 RP |
811 | /* If the I2C controller is disabled we need to reset it (probably due |
812 | to a suspend/resume destroying state). We do this here as we can then | |
813 | avoid worrying about resuming the controller before its users. */ | |
a7b4e550 | 814 | if (!(readl(_ICR(i2c)) & ICR_IUE)) |
ece5f7b3 RP |
815 | i2c_pxa_reset(i2c); |
816 | ||
b652b438 RK |
817 | for (i = adap->retries; i >= 0; i--) { |
818 | ret = i2c_pxa_do_xfer(i2c, msgs, num); | |
819 | if (ret != I2C_RETRY) | |
820 | goto out; | |
821 | ||
822 | if (i2c_debug) | |
6fd60fa9 | 823 | dev_dbg(&adap->dev, "Retrying transmission\n"); |
b652b438 RK |
824 | udelay(100); |
825 | } | |
826 | i2c_pxa_scream_blue_murder(i2c, "exhausted retries"); | |
827 | ret = -EREMOTEIO; | |
828 | out: | |
829 | i2c_pxa_set_slave(i2c, ret); | |
830 | return ret; | |
831 | } | |
832 | ||
da16e324 RK |
833 | static u32 i2c_pxa_functionality(struct i2c_adapter *adap) |
834 | { | |
835 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; | |
836 | } | |
837 | ||
8f9082c5 | 838 | static const struct i2c_algorithm i2c_pxa_algorithm = { |
b652b438 | 839 | .master_xfer = i2c_pxa_xfer, |
da16e324 | 840 | .functionality = i2c_pxa_functionality, |
b652b438 RK |
841 | }; |
842 | ||
a7b4e550 | 843 | #define res_len(r) ((r)->end - (r)->start + 1) |
3ae5eaec | 844 | static int i2c_pxa_probe(struct platform_device *dev) |
b652b438 | 845 | { |
6776f3d2 | 846 | struct pxa_i2c *i2c; |
a7b4e550 | 847 | struct resource *res; |
3ae5eaec | 848 | struct i2c_pxa_platform_data *plat = dev->dev.platform_data; |
b652b438 | 849 | int ret; |
a7b4e550 | 850 | int irq; |
b652b438 | 851 | |
a7b4e550 GL |
852 | res = platform_get_resource(dev, IORESOURCE_MEM, 0); |
853 | irq = platform_get_irq(dev, 0); | |
854 | if (res == NULL || irq < 0) | |
855 | return -ENODEV; | |
856 | ||
857 | if (!request_mem_region(res->start, res_len(res), res->name)) | |
858 | return -ENOMEM; | |
859 | ||
6776f3d2 | 860 | i2c = kzalloc(sizeof(struct pxa_i2c), GFP_KERNEL); |
a7b4e550 GL |
861 | if (!i2c) { |
862 | ret = -ENOMEM; | |
863 | goto emalloc; | |
864 | } | |
865 | ||
6776f3d2 ES |
866 | i2c->adap.owner = THIS_MODULE; |
867 | i2c->adap.algo = &i2c_pxa_algorithm; | |
868 | i2c->adap.retries = 5; | |
869 | ||
870 | spin_lock_init(&i2c->lock); | |
a7b4e550 | 871 | init_waitqueue_head(&i2c->wait); |
6776f3d2 ES |
872 | |
873 | sprintf(i2c->adap.name, "pxa_i2c-i2c.%u", dev->id); | |
a7b4e550 | 874 | |
c3cef3f3 RK |
875 | i2c->clk = clk_get(&dev->dev, "I2CCLK"); |
876 | if (IS_ERR(i2c->clk)) { | |
877 | ret = PTR_ERR(i2c->clk); | |
878 | goto eclk; | |
879 | } | |
880 | ||
a7b4e550 GL |
881 | i2c->reg_base = ioremap(res->start, res_len(res)); |
882 | if (!i2c->reg_base) { | |
883 | ret = -EIO; | |
884 | goto eremap; | |
885 | } | |
886 | ||
887 | i2c->iobase = res->start; | |
888 | i2c->iosize = res_len(res); | |
889 | ||
890 | i2c->irq = irq; | |
b652b438 RK |
891 | |
892 | i2c->slave_addr = I2C_PXA_SLAVE_ADDR; | |
893 | ||
894 | #ifdef CONFIG_I2C_PXA_SLAVE | |
b652b438 RK |
895 | if (plat) { |
896 | i2c->slave_addr = plat->slave_addr; | |
beea494d | 897 | i2c->slave = plat->slave; |
b652b438 RK |
898 | } |
899 | #endif | |
900 | ||
c3cef3f3 RK |
901 | clk_enable(i2c->clk); |
902 | #ifdef CONFIG_PXA27x | |
a7b4e550 GL |
903 | switch (dev->id) { |
904 | case 0: | |
a7b4e550 GL |
905 | pxa_gpio_mode(GPIO117_I2CSCL_MD); |
906 | pxa_gpio_mode(GPIO118_I2CSDA_MD); | |
a7b4e550 | 907 | break; |
a7b4e550 GL |
908 | case 1: |
909 | local_irq_disable(); | |
910 | PCFR |= PCFR_PI2CEN; | |
911 | local_irq_enable(); | |
a7b4e550 | 912 | } |
c3cef3f3 | 913 | #endif |
a7b4e550 GL |
914 | |
915 | ret = request_irq(irq, i2c_pxa_handler, IRQF_DISABLED, | |
916 | i2c->adap.name, i2c); | |
b652b438 | 917 | if (ret) |
a7b4e550 GL |
918 | goto ereqirq; |
919 | ||
b652b438 RK |
920 | |
921 | i2c_pxa_reset(i2c); | |
922 | ||
923 | i2c->adap.algo_data = i2c; | |
3ae5eaec | 924 | i2c->adap.dev.parent = &dev->dev; |
b652b438 | 925 | |
a79220b7 MK |
926 | if (plat) { |
927 | i2c->adap.class = plat->class; | |
928 | } | |
929 | ||
066af983 RG |
930 | /* |
931 | * If "dev->id" is negative we consider it as zero. | |
932 | * The reason to do so is to avoid sysfs names that only make | |
933 | * sense when there are multiple adapters. | |
934 | */ | |
51e5709a | 935 | i2c->adap.nr = dev->id != -1 ? dev->id : 0; |
066af983 RG |
936 | |
937 | ret = i2c_add_numbered_adapter(&i2c->adap); | |
b652b438 RK |
938 | if (ret < 0) { |
939 | printk(KERN_INFO "I2C: Failed to add bus\n"); | |
a7b4e550 | 940 | goto eadapt; |
b652b438 RK |
941 | } |
942 | ||
3ae5eaec | 943 | platform_set_drvdata(dev, i2c); |
b652b438 RK |
944 | |
945 | #ifdef CONFIG_I2C_PXA_SLAVE | |
946 | printk(KERN_INFO "I2C: %s: PXA I2C adapter, slave address %d\n", | |
947 | i2c->adap.dev.bus_id, i2c->slave_addr); | |
948 | #else | |
949 | printk(KERN_INFO "I2C: %s: PXA I2C adapter\n", | |
950 | i2c->adap.dev.bus_id); | |
951 | #endif | |
952 | return 0; | |
953 | ||
a7b4e550 GL |
954 | eadapt: |
955 | free_irq(irq, i2c); | |
956 | ereqirq: | |
c3cef3f3 RK |
957 | clk_disable(i2c->clk); |
958 | ||
a7b4e550 | 959 | #ifdef CONFIG_PXA27x |
c3cef3f3 | 960 | if (dev->id == 1) { |
a7b4e550 GL |
961 | local_irq_disable(); |
962 | PCFR &= ~PCFR_PI2CEN; | |
963 | local_irq_enable(); | |
a7b4e550 | 964 | } |
c3cef3f3 | 965 | #endif |
a7b4e550 | 966 | eremap: |
c3cef3f3 RK |
967 | clk_put(i2c->clk); |
968 | eclk: | |
a7b4e550 GL |
969 | kfree(i2c); |
970 | emalloc: | |
971 | release_mem_region(res->start, res_len(res)); | |
b652b438 RK |
972 | return ret; |
973 | } | |
974 | ||
3ae5eaec | 975 | static int i2c_pxa_remove(struct platform_device *dev) |
b652b438 | 976 | { |
3ae5eaec | 977 | struct pxa_i2c *i2c = platform_get_drvdata(dev); |
b652b438 | 978 | |
3ae5eaec | 979 | platform_set_drvdata(dev, NULL); |
b652b438 RK |
980 | |
981 | i2c_del_adapter(&i2c->adap); | |
a7b4e550 | 982 | free_irq(i2c->irq, i2c); |
c3cef3f3 RK |
983 | |
984 | clk_disable(i2c->clk); | |
985 | clk_put(i2c->clk); | |
986 | ||
a7b4e550 | 987 | #ifdef CONFIG_PXA27x |
c3cef3f3 | 988 | if (dev->id == 1) { |
a7b4e550 GL |
989 | local_irq_disable(); |
990 | PCFR &= ~PCFR_PI2CEN; | |
991 | local_irq_enable(); | |
a7b4e550 | 992 | } |
c3cef3f3 RK |
993 | #endif |
994 | ||
a7b4e550 GL |
995 | release_mem_region(i2c->iobase, i2c->iosize); |
996 | kfree(i2c); | |
b652b438 RK |
997 | |
998 | return 0; | |
999 | } | |
1000 | ||
3ae5eaec | 1001 | static struct platform_driver i2c_pxa_driver = { |
b652b438 RK |
1002 | .probe = i2c_pxa_probe, |
1003 | .remove = i2c_pxa_remove, | |
3ae5eaec RK |
1004 | .driver = { |
1005 | .name = "pxa2xx-i2c", | |
1006 | }, | |
b652b438 RK |
1007 | }; |
1008 | ||
1009 | static int __init i2c_adap_pxa_init(void) | |
1010 | { | |
3ae5eaec | 1011 | return platform_driver_register(&i2c_pxa_driver); |
b652b438 RK |
1012 | } |
1013 | ||
1014 | static void i2c_adap_pxa_exit(void) | |
1015 | { | |
3ae5eaec | 1016 | return platform_driver_unregister(&i2c_pxa_driver); |
b652b438 RK |
1017 | } |
1018 | ||
ece5f7b3 RP |
1019 | MODULE_LICENSE("GPL"); |
1020 | ||
b652b438 RK |
1021 | module_init(i2c_adap_pxa_init); |
1022 | module_exit(i2c_adap_pxa_exit); |