Commit | Line | Data |
---|---|---|
6ccbe607 | 1 | /* |
3d99beab | 2 | * Driver for the Renesas RCar I2C unit |
6ccbe607 | 3 | * |
3c2b1ff3 WS |
4 | * Copyright (C) 2014-15 Wolfram Sang <wsa@sang-engineering.com> |
5 | * Copyright (C) 2011-2015 Renesas Electronics Corporation | |
3d99beab WS |
6 | * |
7 | * Copyright (C) 2012-14 Renesas Solutions Corp. | |
6ccbe607 KM |
8 | * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> |
9 | * | |
10 | * This file is based on the drivers/i2c/busses/i2c-sh7760.c | |
11 | * (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com> | |
12 | * | |
6ccbe607 KM |
13 | * This program is free software; you can redistribute it and/or modify |
14 | * it under the terms of the GNU General Public License as published by | |
3d99beab | 15 | * the Free Software Foundation; version 2 of the License. |
6ccbe607 KM |
16 | * |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
6ccbe607 KM |
21 | */ |
22 | #include <linux/clk.h> | |
23 | #include <linux/delay.h> | |
73e8b052 NS |
24 | #include <linux/dmaengine.h> |
25 | #include <linux/dma-mapping.h> | |
6ccbe607 | 26 | #include <linux/err.h> |
6ccbe607 KM |
27 | #include <linux/interrupt.h> |
28 | #include <linux/io.h> | |
29 | #include <linux/i2c.h> | |
6ccbe607 KM |
30 | #include <linux/kernel.h> |
31 | #include <linux/module.h> | |
7679c0e1 | 32 | #include <linux/of_device.h> |
6ccbe607 KM |
33 | #include <linux/platform_device.h> |
34 | #include <linux/pm_runtime.h> | |
35 | #include <linux/slab.h> | |
6ccbe607 KM |
36 | |
37 | /* register offsets */ | |
38 | #define ICSCR 0x00 /* slave ctrl */ | |
39 | #define ICMCR 0x04 /* master ctrl */ | |
40 | #define ICSSR 0x08 /* slave status */ | |
41 | #define ICMSR 0x0C /* master status */ | |
42 | #define ICSIER 0x10 /* slave irq enable */ | |
43 | #define ICMIER 0x14 /* master irq enable */ | |
44 | #define ICCCR 0x18 /* clock dividers */ | |
45 | #define ICSAR 0x1C /* slave address */ | |
46 | #define ICMAR 0x20 /* master address */ | |
47 | #define ICRXTX 0x24 /* data port */ | |
73e8b052 NS |
48 | #define ICDMAER 0x3c /* DMA enable */ |
49 | #define ICFBSCR 0x38 /* first bit setup cycle */ | |
6ccbe607 | 50 | |
de20d185 WS |
51 | /* ICSCR */ |
52 | #define SDBS (1 << 3) /* slave data buffer select */ | |
53 | #define SIE (1 << 2) /* slave interface enable */ | |
54 | #define GCAE (1 << 1) /* general call address enable */ | |
55 | #define FNA (1 << 0) /* forced non acknowledgment */ | |
56 | ||
6ccbe607 KM |
57 | /* ICMCR */ |
58 | #define MDBS (1 << 7) /* non-fifo mode switch */ | |
59 | #define FSCL (1 << 6) /* override SCL pin */ | |
60 | #define FSDA (1 << 5) /* override SDA pin */ | |
61 | #define OBPC (1 << 4) /* override pins */ | |
62 | #define MIE (1 << 3) /* master if enable */ | |
63 | #define TSBE (1 << 2) | |
64 | #define FSB (1 << 1) /* force stop bit */ | |
65 | #define ESG (1 << 0) /* en startbit gen */ | |
66 | ||
de20d185 WS |
67 | /* ICSSR (also for ICSIER) */ |
68 | #define GCAR (1 << 6) /* general call received */ | |
69 | #define STM (1 << 5) /* slave transmit mode */ | |
70 | #define SSR (1 << 4) /* stop received */ | |
71 | #define SDE (1 << 3) /* slave data empty */ | |
72 | #define SDT (1 << 2) /* slave data transmitted */ | |
73 | #define SDR (1 << 1) /* slave data received */ | |
74 | #define SAR (1 << 0) /* slave addr received */ | |
75 | ||
3e3aabac | 76 | /* ICMSR (also for ICMIE) */ |
6ccbe607 KM |
77 | #define MNR (1 << 6) /* nack received */ |
78 | #define MAL (1 << 5) /* arbitration lost */ | |
79 | #define MST (1 << 4) /* sent a stop */ | |
80 | #define MDE (1 << 3) | |
81 | #define MDT (1 << 2) | |
82 | #define MDR (1 << 1) | |
83 | #define MAT (1 << 0) /* slave addr xfer done */ | |
84 | ||
73e8b052 NS |
85 | /* ICDMAER */ |
86 | #define RSDMAE (1 << 3) /* DMA Slave Received Enable */ | |
87 | #define TSDMAE (1 << 2) /* DMA Slave Transmitted Enable */ | |
88 | #define RMDMAE (1 << 1) /* DMA Master Received Enable */ | |
89 | #define TMDMAE (1 << 0) /* DMA Master Transmitted Enable */ | |
90 | ||
91 | /* ICFBSCR */ | |
92 | #define TCYC06 0x04 /* 6*Tcyc delay 1st bit between SDA and SCL */ | |
93 | #define TCYC17 0x0f /* 17*Tcyc delay 1st bit between SDA and SCL */ | |
94 | ||
6ccbe607 | 95 | |
4f443a8a WS |
96 | #define RCAR_BUS_PHASE_START (MDBS | MIE | ESG) |
97 | #define RCAR_BUS_PHASE_DATA (MDBS | MIE) | |
52df445f | 98 | #define RCAR_BUS_MASK_DATA (~(ESG | FSB) & 0xFF) |
4f443a8a | 99 | #define RCAR_BUS_PHASE_STOP (MDBS | MIE | FSB) |
6ccbe607 | 100 | |
3e3aabac WS |
101 | #define RCAR_IRQ_SEND (MNR | MAL | MST | MAT | MDE) |
102 | #define RCAR_IRQ_RECV (MNR | MAL | MST | MAT | MDR) | |
103 | #define RCAR_IRQ_STOP (MST) | |
6ccbe607 | 104 | |
938916fb SS |
105 | #define RCAR_IRQ_ACK_SEND (~(MAT | MDE) & 0xFF) |
106 | #define RCAR_IRQ_ACK_RECV (~(MAT | MDR) & 0xFF) | |
3c95de67 | 107 | |
6ccbe607 | 108 | #define ID_LAST_MSG (1 << 0) |
e49865d1 | 109 | #define ID_FIRST_MSG (1 << 1) |
6ccbe607 KM |
110 | #define ID_DONE (1 << 2) |
111 | #define ID_ARBLOST (1 << 3) | |
112 | #define ID_NACK (1 << 4) | |
7ee24eb5 WS |
113 | /* persistent flags */ |
114 | #define ID_P_PM_BLOCKED (1 << 31) | |
115 | #define ID_P_MASK ID_P_PM_BLOCKED | |
6ccbe607 | 116 | |
b720423a | 117 | enum rcar_i2c_type { |
043a3f11 KM |
118 | I2C_RCAR_GEN1, |
119 | I2C_RCAR_GEN2, | |
e7db0d34 | 120 | I2C_RCAR_GEN3, |
b720423a NVD |
121 | }; |
122 | ||
6ccbe607 KM |
123 | struct rcar_i2c_priv { |
124 | void __iomem *io; | |
125 | struct i2c_adapter adap; | |
b9d0684c WS |
126 | struct i2c_msg *msg; |
127 | int msgs_left; | |
bc8120f1 | 128 | struct clk *clk; |
6ccbe607 | 129 | |
6ccbe607 KM |
130 | wait_queue_head_t wait; |
131 | ||
132 | int pos; | |
6ccbe607 KM |
133 | u32 icccr; |
134 | u32 flags; | |
51371cdc | 135 | enum rcar_i2c_type devtype; |
de20d185 | 136 | struct i2c_client *slave; |
73e8b052 NS |
137 | |
138 | struct resource *res; | |
139 | struct dma_chan *dma_tx; | |
140 | struct dma_chan *dma_rx; | |
141 | struct scatterlist sg; | |
142 | enum dma_data_direction dma_direction; | |
6ccbe607 KM |
143 | }; |
144 | ||
145 | #define rcar_i2c_priv_to_dev(p) ((p)->adap.dev.parent) | |
146 | #define rcar_i2c_is_recv(p) ((p)->msg->flags & I2C_M_RD) | |
147 | ||
6ccbe607 KM |
148 | #define LOOP_TIMEOUT 1024 |
149 | ||
51371cdc | 150 | |
6ccbe607 KM |
151 | static void rcar_i2c_write(struct rcar_i2c_priv *priv, int reg, u32 val) |
152 | { | |
153 | writel(val, priv->io + reg); | |
154 | } | |
155 | ||
156 | static u32 rcar_i2c_read(struct rcar_i2c_priv *priv, int reg) | |
157 | { | |
158 | return readl(priv->io + reg); | |
159 | } | |
160 | ||
161 | static void rcar_i2c_init(struct rcar_i2c_priv *priv) | |
162 | { | |
6ccbe607 KM |
163 | /* reset master mode */ |
164 | rcar_i2c_write(priv, ICMIER, 0); | |
2c78cdc1 | 165 | rcar_i2c_write(priv, ICMCR, MDBS); |
6ccbe607 | 166 | rcar_i2c_write(priv, ICMSR, 0); |
2c78cdc1 WS |
167 | /* start clock */ |
168 | rcar_i2c_write(priv, ICCCR, priv->icccr); | |
6ccbe607 KM |
169 | } |
170 | ||
6ccbe607 KM |
171 | static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv) |
172 | { | |
173 | int i; | |
174 | ||
175 | for (i = 0; i < LOOP_TIMEOUT; i++) { | |
176 | /* make sure that bus is not busy */ | |
177 | if (!(rcar_i2c_read(priv, ICMCR) & FSDA)) | |
178 | return 0; | |
179 | udelay(1); | |
180 | } | |
181 | ||
182 | return -EBUSY; | |
183 | } | |
184 | ||
c7881871 | 185 | static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv, struct i2c_timings *t) |
6ccbe607 | 186 | { |
ca68eade | 187 | u32 scgd, cdf, round, ick, sum, scl, cdf_width; |
8d049403 | 188 | unsigned long rate; |
f9c9d31b | 189 | struct device *dev = rcar_i2c_priv_to_dev(priv); |
6ccbe607 | 190 | |
c7881871 WS |
191 | /* Fall back to previously used values if not supplied */ |
192 | t->bus_freq_hz = t->bus_freq_hz ?: 100000; | |
ca68eade WS |
193 | t->scl_fall_ns = t->scl_fall_ns ?: 35; |
194 | t->scl_rise_ns = t->scl_rise_ns ?: 200; | |
195 | t->scl_int_delay_ns = t->scl_int_delay_ns ?: 50; | |
6ccbe607 | 196 | |
b720423a | 197 | switch (priv->devtype) { |
043a3f11 | 198 | case I2C_RCAR_GEN1: |
b720423a NVD |
199 | cdf_width = 2; |
200 | break; | |
043a3f11 | 201 | case I2C_RCAR_GEN2: |
e7db0d34 | 202 | case I2C_RCAR_GEN3: |
b720423a NVD |
203 | cdf_width = 3; |
204 | break; | |
205 | default: | |
206 | dev_err(dev, "device type error\n"); | |
207 | return -EIO; | |
208 | } | |
209 | ||
6ccbe607 KM |
210 | /* |
211 | * calculate SCL clock | |
212 | * see | |
213 | * ICCCR | |
214 | * | |
215 | * ick = clkp / (1 + CDF) | |
216 | * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick]) | |
217 | * | |
218 | * ick : I2C internal clock < 20 MHz | |
ca68eade WS |
219 | * ticf : I2C SCL falling time |
220 | * tr : I2C SCL rising time | |
221 | * intd : LSI internal delay | |
6ccbe607 KM |
222 | * clkp : peripheral_clk |
223 | * F[] : integer up-valuation | |
224 | */ | |
bc8120f1 | 225 | rate = clk_get_rate(priv->clk); |
8d049403 | 226 | cdf = rate / 20000000; |
22762ccb | 227 | if (cdf >= 1U << cdf_width) { |
8d049403 GL |
228 | dev_err(dev, "Input clock %lu too high\n", rate); |
229 | return -EIO; | |
6ccbe607 | 230 | } |
8d049403 | 231 | ick = rate / (cdf + 1); |
6ccbe607 | 232 | |
6ccbe607 KM |
233 | /* |
234 | * it is impossible to calculate large scale | |
235 | * number on u32. separate it | |
236 | * | |
ca68eade WS |
237 | * F[(ticf + tr + intd) * ick] with sum = (ticf + tr + intd) |
238 | * = F[sum * ick / 1000000000] | |
239 | * = F[(ick / 1000000) * sum / 1000] | |
6ccbe607 | 240 | */ |
ca68eade WS |
241 | sum = t->scl_fall_ns + t->scl_rise_ns + t->scl_int_delay_ns; |
242 | round = (ick + 500000) / 1000000 * sum; | |
6ccbe607 KM |
243 | round = (round + 500) / 1000; |
244 | ||
245 | /* | |
246 | * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick]) | |
247 | * | |
248 | * Calculation result (= SCL) should be less than | |
249 | * bus_speed for hardware safety | |
8d049403 GL |
250 | * |
251 | * We could use something along the lines of | |
252 | * div = ick / (bus_speed + 1) + 1; | |
253 | * scgd = (div - 20 - round + 7) / 8; | |
254 | * scl = ick / (20 + (scgd * 8) + round); | |
255 | * (not fully verified) but that would get pretty involved | |
6ccbe607 KM |
256 | */ |
257 | for (scgd = 0; scgd < 0x40; scgd++) { | |
258 | scl = ick / (20 + (scgd * 8) + round); | |
c7881871 | 259 | if (scl <= t->bus_freq_hz) |
6ccbe607 KM |
260 | goto scgd_find; |
261 | } | |
262 | dev_err(dev, "it is impossible to calculate best SCL\n"); | |
263 | return -EIO; | |
264 | ||
265 | scgd_find: | |
266 | dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n", | |
c7881871 | 267 | scl, t->bus_freq_hz, clk_get_rate(priv->clk), round, cdf, scgd); |
6ccbe607 | 268 | |
3c2b1ff3 | 269 | /* keep icccr value */ |
14d32f17 | 270 | priv->icccr = scgd << cdf_width | cdf; |
6ccbe607 KM |
271 | |
272 | return 0; | |
273 | } | |
274 | ||
7c7117ff | 275 | static void rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv) |
6ccbe607 | 276 | { |
386babf8 | 277 | int read = !!rcar_i2c_is_recv(priv); |
6ccbe607 | 278 | |
b9d0684c | 279 | priv->pos = 0; |
b9d0684c | 280 | if (priv->msgs_left == 1) |
42c0783b | 281 | priv->flags |= ID_LAST_MSG; |
b9d0684c | 282 | |
386babf8 | 283 | rcar_i2c_write(priv, ICMAR, (priv->msg->addr << 1) | read); |
e49865d1 WS |
284 | /* |
285 | * We don't have a testcase but the HW engineers say that the write order | |
286 | * of ICMSR and ICMCR depends on whether we issue START or REP_START. Since | |
287 | * it didn't cause a drawback for me, let's rather be safe than sorry. | |
288 | */ | |
42c0783b | 289 | if (priv->flags & ID_FIRST_MSG) { |
e49865d1 WS |
290 | rcar_i2c_write(priv, ICMSR, 0); |
291 | rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START); | |
292 | } else { | |
293 | rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START); | |
294 | rcar_i2c_write(priv, ICMSR, 0); | |
295 | } | |
386babf8 | 296 | rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND); |
6ccbe607 KM |
297 | } |
298 | ||
cc21d0b4 WS |
299 | static void rcar_i2c_next_msg(struct rcar_i2c_priv *priv) |
300 | { | |
301 | priv->msg++; | |
302 | priv->msgs_left--; | |
7ee24eb5 | 303 | priv->flags &= ID_P_MASK; |
cc21d0b4 WS |
304 | rcar_i2c_prepare_msg(priv); |
305 | } | |
306 | ||
6ccbe607 KM |
307 | /* |
308 | * interrupt functions | |
309 | */ | |
73e8b052 NS |
310 | static void rcar_i2c_dma_unmap(struct rcar_i2c_priv *priv) |
311 | { | |
312 | struct dma_chan *chan = priv->dma_direction == DMA_FROM_DEVICE | |
313 | ? priv->dma_rx : priv->dma_tx; | |
314 | ||
315 | /* Disable DMA Master Received/Transmitted */ | |
316 | rcar_i2c_write(priv, ICDMAER, 0); | |
317 | ||
318 | /* Reset default delay */ | |
319 | rcar_i2c_write(priv, ICFBSCR, TCYC06); | |
320 | ||
321 | dma_unmap_single(chan->device->dev, sg_dma_address(&priv->sg), | |
322 | priv->msg->len, priv->dma_direction); | |
323 | ||
324 | priv->dma_direction = DMA_NONE; | |
325 | } | |
326 | ||
327 | static void rcar_i2c_cleanup_dma(struct rcar_i2c_priv *priv) | |
328 | { | |
329 | if (priv->dma_direction == DMA_NONE) | |
330 | return; | |
331 | else if (priv->dma_direction == DMA_FROM_DEVICE) | |
332 | dmaengine_terminate_all(priv->dma_rx); | |
333 | else if (priv->dma_direction == DMA_TO_DEVICE) | |
334 | dmaengine_terminate_all(priv->dma_tx); | |
335 | ||
336 | rcar_i2c_dma_unmap(priv); | |
337 | } | |
338 | ||
339 | static void rcar_i2c_dma_callback(void *data) | |
340 | { | |
341 | struct rcar_i2c_priv *priv = data; | |
342 | ||
343 | priv->pos += sg_dma_len(&priv->sg); | |
344 | ||
345 | rcar_i2c_dma_unmap(priv); | |
346 | } | |
347 | ||
348 | static void rcar_i2c_dma(struct rcar_i2c_priv *priv) | |
349 | { | |
350 | struct device *dev = rcar_i2c_priv_to_dev(priv); | |
351 | struct i2c_msg *msg = priv->msg; | |
352 | bool read = msg->flags & I2C_M_RD; | |
353 | enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE; | |
354 | struct dma_chan *chan = read ? priv->dma_rx : priv->dma_tx; | |
355 | struct dma_async_tx_descriptor *txdesc; | |
356 | dma_addr_t dma_addr; | |
357 | dma_cookie_t cookie; | |
358 | unsigned char *buf; | |
359 | int len; | |
360 | ||
361 | /* Do not use DMA if it's not available or for messages < 8 bytes */ | |
362 | if (IS_ERR(chan) || msg->len < 8) | |
363 | return; | |
364 | ||
365 | if (read) { | |
366 | /* | |
367 | * The last two bytes needs to be fetched using PIO in | |
368 | * order for the STOP phase to work. | |
369 | */ | |
370 | buf = priv->msg->buf; | |
371 | len = priv->msg->len - 2; | |
372 | } else { | |
373 | /* | |
374 | * First byte in message was sent using PIO. | |
375 | */ | |
376 | buf = priv->msg->buf + 1; | |
377 | len = priv->msg->len - 1; | |
378 | } | |
379 | ||
380 | dma_addr = dma_map_single(chan->device->dev, buf, len, dir); | |
c13c2918 | 381 | if (dma_mapping_error(chan->device->dev, dma_addr)) { |
73e8b052 NS |
382 | dev_dbg(dev, "dma map failed, using PIO\n"); |
383 | return; | |
384 | } | |
385 | ||
386 | sg_dma_len(&priv->sg) = len; | |
387 | sg_dma_address(&priv->sg) = dma_addr; | |
388 | ||
389 | priv->dma_direction = dir; | |
390 | ||
391 | txdesc = dmaengine_prep_slave_sg(chan, &priv->sg, 1, | |
392 | read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV, | |
393 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
394 | if (!txdesc) { | |
395 | dev_dbg(dev, "dma prep slave sg failed, using PIO\n"); | |
396 | rcar_i2c_cleanup_dma(priv); | |
397 | return; | |
398 | } | |
399 | ||
400 | txdesc->callback = rcar_i2c_dma_callback; | |
401 | txdesc->callback_param = priv; | |
402 | ||
403 | cookie = dmaengine_submit(txdesc); | |
404 | if (dma_submit_error(cookie)) { | |
405 | dev_dbg(dev, "submitting dma failed, using PIO\n"); | |
406 | rcar_i2c_cleanup_dma(priv); | |
407 | return; | |
408 | } | |
409 | ||
410 | /* Set delay for DMA operations */ | |
411 | rcar_i2c_write(priv, ICFBSCR, TCYC17); | |
412 | ||
413 | /* Enable DMA Master Received/Transmitted */ | |
414 | if (read) | |
415 | rcar_i2c_write(priv, ICDMAER, RMDMAE); | |
416 | else | |
417 | rcar_i2c_write(priv, ICDMAER, TMDMAE); | |
418 | ||
419 | dma_async_issue_pending(chan); | |
420 | } | |
421 | ||
cc21d0b4 | 422 | static void rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr) |
6ccbe607 KM |
423 | { |
424 | struct i2c_msg *msg = priv->msg; | |
425 | ||
3c2b1ff3 | 426 | /* FIXME: sometimes, unknown interrupt happened. Do nothing */ |
6ccbe607 | 427 | if (!(msr & MDE)) |
cc21d0b4 | 428 | return; |
6ccbe607 KM |
429 | |
430 | if (priv->pos < msg->len) { | |
431 | /* | |
432 | * Prepare next data to ICRXTX register. | |
433 | * This data will go to _SHIFT_ register. | |
434 | * | |
435 | * * | |
436 | * [ICRXTX] -> [SHIFT] -> [I2C bus] | |
437 | */ | |
438 | rcar_i2c_write(priv, ICRXTX, msg->buf[priv->pos]); | |
439 | priv->pos++; | |
440 | ||
73e8b052 NS |
441 | /* |
442 | * Try to use DMA to transmit the rest of the data if | |
443 | * address transfer pashe just finished. | |
444 | */ | |
445 | if (msr & MAT) | |
446 | rcar_i2c_dma(priv); | |
6ccbe607 KM |
447 | } else { |
448 | /* | |
449 | * The last data was pushed to ICRXTX on _PREV_ empty irq. | |
450 | * It is on _SHIFT_ register, and will sent to I2C bus. | |
451 | * | |
452 | * * | |
453 | * [ICRXTX] -> [SHIFT] -> [I2C bus] | |
454 | */ | |
455 | ||
cc21d0b4 | 456 | if (priv->flags & ID_LAST_MSG) { |
6ccbe607 KM |
457 | /* |
458 | * If current msg is the _LAST_ msg, | |
459 | * prepare stop condition here. | |
460 | * ID_DONE will be set on STOP irq. | |
461 | */ | |
4f443a8a | 462 | rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP); |
cc21d0b4 WS |
463 | } else { |
464 | rcar_i2c_next_msg(priv); | |
465 | return; | |
466 | } | |
6ccbe607 KM |
467 | } |
468 | ||
3c95de67 | 469 | rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_SEND); |
6ccbe607 KM |
470 | } |
471 | ||
cc21d0b4 | 472 | static void rcar_i2c_irq_recv(struct rcar_i2c_priv *priv, u32 msr) |
6ccbe607 KM |
473 | { |
474 | struct i2c_msg *msg = priv->msg; | |
475 | ||
3c2b1ff3 | 476 | /* FIXME: sometimes, unknown interrupt happened. Do nothing */ |
6ccbe607 | 477 | if (!(msr & MDR)) |
cc21d0b4 | 478 | return; |
6ccbe607 KM |
479 | |
480 | if (msr & MAT) { | |
73e8b052 NS |
481 | /* |
482 | * Address transfer phase finished, but no data at this point. | |
483 | * Try to use DMA to receive data. | |
484 | */ | |
485 | rcar_i2c_dma(priv); | |
6ccbe607 | 486 | } else if (priv->pos < msg->len) { |
3c2b1ff3 | 487 | /* get received data */ |
6ccbe607 KM |
488 | msg->buf[priv->pos] = rcar_i2c_read(priv, ICRXTX); |
489 | priv->pos++; | |
490 | } | |
491 | ||
492 | /* | |
3c2b1ff3 WS |
493 | * If next received data is the _LAST_, go to STOP phase. Might be |
494 | * overwritten by REP START when setting up a new msg. Not elegant | |
495 | * but the only stable sequence for REP START I have found so far. | |
6ccbe607 KM |
496 | */ |
497 | if (priv->pos + 1 >= msg->len) | |
4f443a8a | 498 | rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP); |
6ccbe607 | 499 | |
cc21d0b4 WS |
500 | if (priv->pos == msg->len && !(priv->flags & ID_LAST_MSG)) |
501 | rcar_i2c_next_msg(priv); | |
502 | else | |
503 | rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_RECV); | |
6ccbe607 KM |
504 | } |
505 | ||
de20d185 WS |
506 | static bool rcar_i2c_slave_irq(struct rcar_i2c_priv *priv) |
507 | { | |
508 | u32 ssr_raw, ssr_filtered; | |
509 | u8 value; | |
510 | ||
511 | ssr_raw = rcar_i2c_read(priv, ICSSR) & 0xff; | |
512 | ssr_filtered = ssr_raw & rcar_i2c_read(priv, ICSIER); | |
513 | ||
514 | if (!ssr_filtered) | |
515 | return false; | |
516 | ||
517 | /* address detected */ | |
518 | if (ssr_filtered & SAR) { | |
519 | /* read or write request */ | |
520 | if (ssr_raw & STM) { | |
5b77d162 | 521 | i2c_slave_event(priv->slave, I2C_SLAVE_READ_REQUESTED, &value); |
de20d185 WS |
522 | rcar_i2c_write(priv, ICRXTX, value); |
523 | rcar_i2c_write(priv, ICSIER, SDE | SSR | SAR); | |
524 | } else { | |
5b77d162 | 525 | i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_REQUESTED, &value); |
de20d185 WS |
526 | rcar_i2c_read(priv, ICRXTX); /* dummy read */ |
527 | rcar_i2c_write(priv, ICSIER, SDR | SSR | SAR); | |
528 | } | |
529 | ||
530 | rcar_i2c_write(priv, ICSSR, ~SAR & 0xff); | |
531 | } | |
532 | ||
533 | /* master sent stop */ | |
534 | if (ssr_filtered & SSR) { | |
535 | i2c_slave_event(priv->slave, I2C_SLAVE_STOP, &value); | |
536 | rcar_i2c_write(priv, ICSIER, SAR | SSR); | |
537 | rcar_i2c_write(priv, ICSSR, ~SSR & 0xff); | |
538 | } | |
539 | ||
540 | /* master wants to write to us */ | |
541 | if (ssr_filtered & SDR) { | |
542 | int ret; | |
543 | ||
544 | value = rcar_i2c_read(priv, ICRXTX); | |
5b77d162 | 545 | ret = i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_RECEIVED, &value); |
de20d185 WS |
546 | /* Send NACK in case of error */ |
547 | rcar_i2c_write(priv, ICSCR, SIE | SDBS | (ret < 0 ? FNA : 0)); | |
de20d185 WS |
548 | rcar_i2c_write(priv, ICSSR, ~SDR & 0xff); |
549 | } | |
550 | ||
551 | /* master wants to read from us */ | |
552 | if (ssr_filtered & SDE) { | |
5b77d162 | 553 | i2c_slave_event(priv->slave, I2C_SLAVE_READ_PROCESSED, &value); |
de20d185 WS |
554 | rcar_i2c_write(priv, ICRXTX, value); |
555 | rcar_i2c_write(priv, ICSSR, ~SDE & 0xff); | |
556 | } | |
557 | ||
558 | return true; | |
559 | } | |
560 | ||
6ccbe607 KM |
561 | static irqreturn_t rcar_i2c_irq(int irq, void *ptr) |
562 | { | |
563 | struct rcar_i2c_priv *priv = ptr; | |
52df445f | 564 | u32 msr, val; |
91bfe298 | 565 | |
52df445f WS |
566 | /* Clear START or STOP as soon as we can */ |
567 | val = rcar_i2c_read(priv, ICMCR); | |
568 | rcar_i2c_write(priv, ICMCR, val & RCAR_BUS_MASK_DATA); | |
de20d185 | 569 | |
1c176d53 | 570 | msr = rcar_i2c_read(priv, ICMSR); |
6ccbe607 | 571 | |
dd318b0d SS |
572 | /* Only handle interrupts that are currently enabled */ |
573 | msr &= rcar_i2c_read(priv, ICMIER); | |
aa5beaf6 | 574 | if (!msr) { |
c3be0af1 WS |
575 | if (rcar_i2c_slave_irq(priv)) |
576 | return IRQ_HANDLED; | |
577 | ||
578 | return IRQ_NONE; | |
aa5beaf6 | 579 | } |
dd318b0d | 580 | |
51371cdc | 581 | /* Arbitration lost */ |
6ccbe607 | 582 | if (msr & MAL) { |
42c0783b | 583 | priv->flags |= ID_DONE | ID_ARBLOST; |
6ccbe607 KM |
584 | goto out; |
585 | } | |
586 | ||
51371cdc | 587 | /* Nack */ |
6ccbe607 | 588 | if (msr & MNR) { |
d89667b1 | 589 | /* HW automatically sends STOP after received NACK */ |
f2382249 | 590 | rcar_i2c_write(priv, ICMIER, RCAR_IRQ_STOP); |
42c0783b | 591 | priv->flags |= ID_NACK; |
6ccbe607 KM |
592 | goto out; |
593 | } | |
594 | ||
dd318b0d SS |
595 | /* Stop */ |
596 | if (msr & MST) { | |
cc21d0b4 | 597 | priv->msgs_left--; /* The last message also made it */ |
42c0783b | 598 | priv->flags |= ID_DONE; |
dd318b0d SS |
599 | goto out; |
600 | } | |
601 | ||
6ccbe607 | 602 | if (rcar_i2c_is_recv(priv)) |
cc21d0b4 | 603 | rcar_i2c_irq_recv(priv, msr); |
6ccbe607 | 604 | else |
cc21d0b4 | 605 | rcar_i2c_irq_send(priv, msr); |
6ccbe607 KM |
606 | |
607 | out: | |
42c0783b | 608 | if (priv->flags & ID_DONE) { |
f2382249 | 609 | rcar_i2c_write(priv, ICMIER, 0); |
3c95de67 | 610 | rcar_i2c_write(priv, ICMSR, 0); |
6ccbe607 KM |
611 | wake_up(&priv->wait); |
612 | } | |
613 | ||
c3be0af1 | 614 | return IRQ_HANDLED; |
6ccbe607 KM |
615 | } |
616 | ||
73e8b052 NS |
617 | static struct dma_chan *rcar_i2c_request_dma_chan(struct device *dev, |
618 | enum dma_transfer_direction dir, | |
619 | dma_addr_t port_addr) | |
620 | { | |
621 | struct dma_chan *chan; | |
622 | struct dma_slave_config cfg; | |
623 | char *chan_name = dir == DMA_MEM_TO_DEV ? "tx" : "rx"; | |
624 | int ret; | |
625 | ||
6aabf9d0 | 626 | chan = dma_request_chan(dev, chan_name); |
73e8b052 NS |
627 | if (IS_ERR(chan)) { |
628 | ret = PTR_ERR(chan); | |
629 | dev_dbg(dev, "request_channel failed for %s (%d)\n", | |
630 | chan_name, ret); | |
631 | return chan; | |
632 | } | |
633 | ||
634 | memset(&cfg, 0, sizeof(cfg)); | |
635 | cfg.direction = dir; | |
636 | if (dir == DMA_MEM_TO_DEV) { | |
637 | cfg.dst_addr = port_addr; | |
638 | cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
639 | } else { | |
640 | cfg.src_addr = port_addr; | |
641 | cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
642 | } | |
643 | ||
644 | ret = dmaengine_slave_config(chan, &cfg); | |
645 | if (ret) { | |
646 | dev_dbg(dev, "slave_config failed for %s (%d)\n", | |
647 | chan_name, ret); | |
648 | dma_release_channel(chan); | |
649 | return ERR_PTR(ret); | |
650 | } | |
651 | ||
652 | dev_dbg(dev, "got DMA channel for %s\n", chan_name); | |
653 | return chan; | |
654 | } | |
655 | ||
656 | static void rcar_i2c_request_dma(struct rcar_i2c_priv *priv, | |
657 | struct i2c_msg *msg) | |
658 | { | |
659 | struct device *dev = rcar_i2c_priv_to_dev(priv); | |
660 | bool read; | |
661 | struct dma_chan *chan; | |
662 | enum dma_transfer_direction dir; | |
663 | ||
664 | read = msg->flags & I2C_M_RD; | |
665 | ||
666 | chan = read ? priv->dma_rx : priv->dma_tx; | |
667 | if (PTR_ERR(chan) != -EPROBE_DEFER) | |
668 | return; | |
669 | ||
670 | dir = read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV; | |
671 | chan = rcar_i2c_request_dma_chan(dev, dir, priv->res->start + ICRXTX); | |
672 | ||
673 | if (read) | |
674 | priv->dma_rx = chan; | |
675 | else | |
676 | priv->dma_tx = chan; | |
677 | } | |
678 | ||
679 | static void rcar_i2c_release_dma(struct rcar_i2c_priv *priv) | |
680 | { | |
681 | if (!IS_ERR(priv->dma_tx)) { | |
682 | dma_release_channel(priv->dma_tx); | |
683 | priv->dma_tx = ERR_PTR(-EPROBE_DEFER); | |
684 | } | |
685 | ||
686 | if (!IS_ERR(priv->dma_rx)) { | |
687 | dma_release_channel(priv->dma_rx); | |
688 | priv->dma_rx = ERR_PTR(-EPROBE_DEFER); | |
689 | } | |
690 | } | |
691 | ||
6ccbe607 KM |
692 | static int rcar_i2c_master_xfer(struct i2c_adapter *adap, |
693 | struct i2c_msg *msgs, | |
694 | int num) | |
695 | { | |
696 | struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); | |
697 | struct device *dev = rcar_i2c_priv_to_dev(priv); | |
b6763d0d | 698 | int i, ret; |
ff2316b8 | 699 | long time_left; |
6ccbe607 KM |
700 | |
701 | pm_runtime_get_sync(dev); | |
702 | ||
3f7de22e WS |
703 | ret = rcar_i2c_bus_barrier(priv); |
704 | if (ret < 0) | |
705 | goto out; | |
706 | ||
6ccbe607 | 707 | for (i = 0; i < num; i++) { |
d7653964 WS |
708 | /* This HW can't send STOP after address phase */ |
709 | if (msgs[i].len == 0) { | |
710 | ret = -EOPNOTSUPP; | |
cc21d0b4 | 711 | goto out; |
6ccbe607 | 712 | } |
73e8b052 | 713 | rcar_i2c_request_dma(priv, msgs + i); |
cc21d0b4 | 714 | } |
6ccbe607 | 715 | |
e49865d1 | 716 | /* init first message */ |
cc21d0b4 WS |
717 | priv->msg = msgs; |
718 | priv->msgs_left = num; | |
7ee24eb5 | 719 | priv->flags = (priv->flags & ID_P_MASK) | ID_FIRST_MSG; |
cc21d0b4 WS |
720 | rcar_i2c_prepare_msg(priv); |
721 | ||
42c0783b | 722 | time_left = wait_event_timeout(priv->wait, priv->flags & ID_DONE, |
cc21d0b4 WS |
723 | num * adap->timeout); |
724 | if (!time_left) { | |
73e8b052 | 725 | rcar_i2c_cleanup_dma(priv); |
cc21d0b4 WS |
726 | rcar_i2c_init(priv); |
727 | ret = -ETIMEDOUT; | |
42c0783b | 728 | } else if (priv->flags & ID_NACK) { |
cc21d0b4 | 729 | ret = -ENXIO; |
42c0783b | 730 | } else if (priv->flags & ID_ARBLOST) { |
cc21d0b4 WS |
731 | ret = -EAGAIN; |
732 | } else { | |
733 | ret = num - priv->msgs_left; /* The number of transfer */ | |
6ccbe607 | 734 | } |
3f7de22e | 735 | out: |
6ccbe607 KM |
736 | pm_runtime_put(dev); |
737 | ||
6ff4b105 | 738 | if (ret < 0 && ret != -ENXIO) |
6ccbe607 KM |
739 | dev_err(dev, "error %d : %x\n", ret, priv->flags); |
740 | ||
741 | return ret; | |
742 | } | |
743 | ||
de20d185 WS |
744 | static int rcar_reg_slave(struct i2c_client *slave) |
745 | { | |
746 | struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter); | |
747 | ||
748 | if (priv->slave) | |
749 | return -EBUSY; | |
750 | ||
751 | if (slave->flags & I2C_CLIENT_TEN) | |
752 | return -EAFNOSUPPORT; | |
753 | ||
b4cd08aa | 754 | pm_runtime_get_sync(rcar_i2c_priv_to_dev(priv)); |
de20d185 WS |
755 | |
756 | priv->slave = slave; | |
757 | rcar_i2c_write(priv, ICSAR, slave->addr); | |
758 | rcar_i2c_write(priv, ICSSR, 0); | |
759 | rcar_i2c_write(priv, ICSIER, SAR | SSR); | |
760 | rcar_i2c_write(priv, ICSCR, SIE | SDBS); | |
761 | ||
762 | return 0; | |
763 | } | |
764 | ||
765 | static int rcar_unreg_slave(struct i2c_client *slave) | |
766 | { | |
767 | struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter); | |
768 | ||
769 | WARN_ON(!priv->slave); | |
770 | ||
771 | rcar_i2c_write(priv, ICSIER, 0); | |
772 | rcar_i2c_write(priv, ICSCR, 0); | |
773 | ||
774 | priv->slave = NULL; | |
775 | ||
b4cd08aa | 776 | pm_runtime_put(rcar_i2c_priv_to_dev(priv)); |
de20d185 WS |
777 | |
778 | return 0; | |
779 | } | |
780 | ||
6ccbe607 KM |
781 | static u32 rcar_i2c_func(struct i2c_adapter *adap) |
782 | { | |
d7653964 | 783 | /* This HW can't do SMBUS_QUICK and NOSTART */ |
1fb2ad95 WS |
784 | return I2C_FUNC_I2C | I2C_FUNC_SLAVE | |
785 | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); | |
6ccbe607 KM |
786 | } |
787 | ||
788 | static const struct i2c_algorithm rcar_i2c_algo = { | |
789 | .master_xfer = rcar_i2c_master_xfer, | |
790 | .functionality = rcar_i2c_func, | |
de20d185 WS |
791 | .reg_slave = rcar_reg_slave, |
792 | .unreg_slave = rcar_unreg_slave, | |
6ccbe607 KM |
793 | }; |
794 | ||
7679c0e1 | 795 | static const struct of_device_id rcar_i2c_dt_ids[] = { |
043a3f11 KM |
796 | { .compatible = "renesas,i2c-rcar", .data = (void *)I2C_RCAR_GEN1 }, |
797 | { .compatible = "renesas,i2c-r8a7778", .data = (void *)I2C_RCAR_GEN1 }, | |
798 | { .compatible = "renesas,i2c-r8a7779", .data = (void *)I2C_RCAR_GEN1 }, | |
799 | { .compatible = "renesas,i2c-r8a7790", .data = (void *)I2C_RCAR_GEN2 }, | |
e8936455 | 800 | { .compatible = "renesas,i2c-r8a7791", .data = (void *)I2C_RCAR_GEN2 }, |
819a3951 WS |
801 | { .compatible = "renesas,i2c-r8a7792", .data = (void *)I2C_RCAR_GEN2 }, |
802 | { .compatible = "renesas,i2c-r8a7793", .data = (void *)I2C_RCAR_GEN2 }, | |
803 | { .compatible = "renesas,i2c-r8a7794", .data = (void *)I2C_RCAR_GEN2 }, | |
e7db0d34 | 804 | { .compatible = "renesas,i2c-r8a7795", .data = (void *)I2C_RCAR_GEN3 }, |
7679c0e1 GL |
805 | {}, |
806 | }; | |
807 | MODULE_DEVICE_TABLE(of, rcar_i2c_dt_ids); | |
808 | ||
0b255e92 | 809 | static int rcar_i2c_probe(struct platform_device *pdev) |
6ccbe607 | 810 | { |
6ccbe607 KM |
811 | struct rcar_i2c_priv *priv; |
812 | struct i2c_adapter *adap; | |
6ccbe607 | 813 | struct device *dev = &pdev->dev; |
c7881871 | 814 | struct i2c_timings i2c_t; |
93e953d3 | 815 | int irq, ret; |
6ccbe607 | 816 | |
6ccbe607 | 817 | priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL); |
46797a2a | 818 | if (!priv) |
6ccbe607 | 819 | return -ENOMEM; |
6ccbe607 | 820 | |
bc8120f1 BD |
821 | priv->clk = devm_clk_get(dev, NULL); |
822 | if (IS_ERR(priv->clk)) { | |
823 | dev_err(dev, "cannot get clock\n"); | |
824 | return PTR_ERR(priv->clk); | |
825 | } | |
826 | ||
73e8b052 NS |
827 | priv->res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
828 | ||
829 | priv->io = devm_ioremap_resource(dev, priv->res); | |
84dbf809 TR |
830 | if (IS_ERR(priv->io)) |
831 | return PTR_ERR(priv->io); | |
6ccbe607 | 832 | |
69e558fa | 833 | priv->devtype = (enum rcar_i2c_type)of_device_get_match_data(dev); |
6ccbe607 | 834 | init_waitqueue_head(&priv->wait); |
6ccbe607 | 835 | |
929e3aba WS |
836 | adap = &priv->adap; |
837 | adap->nr = pdev->id; | |
838 | adap->algo = &rcar_i2c_algo; | |
839 | adap->class = I2C_CLASS_DEPRECATED; | |
840 | adap->retries = 3; | |
841 | adap->dev.parent = dev; | |
842 | adap->dev.of_node = dev->of_node; | |
6ccbe607 KM |
843 | i2c_set_adapdata(adap, priv); |
844 | strlcpy(adap->name, pdev->name, sizeof(adap->name)); | |
845 | ||
c7881871 | 846 | i2c_parse_fw_timings(dev, &i2c_t, false); |
f9c9d31b | 847 | |
73e8b052 NS |
848 | /* Init DMA */ |
849 | sg_init_table(&priv->sg, 1); | |
850 | priv->dma_direction = DMA_NONE; | |
851 | priv->dma_rx = priv->dma_tx = ERR_PTR(-EPROBE_DEFER); | |
852 | ||
f9c9d31b WS |
853 | pm_runtime_enable(dev); |
854 | pm_runtime_get_sync(dev); | |
c7881871 | 855 | ret = rcar_i2c_clock_calculate(priv, &i2c_t); |
f9c9d31b WS |
856 | if (ret < 0) |
857 | goto out_pm_put; | |
858 | ||
859 | rcar_i2c_init(priv); | |
7ee24eb5 WS |
860 | |
861 | /* Don't suspend when multi-master to keep arbitration working */ | |
862 | if (of_property_read_bool(dev->of_node, "multi-master")) | |
863 | priv->flags |= ID_P_PM_BLOCKED; | |
864 | else | |
865 | pm_runtime_put(dev); | |
866 | ||
f9c9d31b WS |
867 | |
868 | irq = platform_get_irq(pdev, 0); | |
869 | ret = devm_request_irq(dev, irq, rcar_i2c_irq, 0, dev_name(dev), priv); | |
6ccbe607 | 870 | if (ret < 0) { |
93e953d3 | 871 | dev_err(dev, "cannot get irq %d\n", irq); |
e43e0df1 | 872 | goto out_pm_disable; |
6ccbe607 KM |
873 | } |
874 | ||
4f7effdd WS |
875 | platform_set_drvdata(pdev, priv); |
876 | ||
6ccbe607 | 877 | ret = i2c_add_numbered_adapter(adap); |
ea734404 | 878 | if (ret < 0) |
e43e0df1 | 879 | goto out_pm_disable; |
6ccbe607 | 880 | |
6ccbe607 KM |
881 | dev_info(dev, "probed\n"); |
882 | ||
883 | return 0; | |
e43e0df1 WS |
884 | |
885 | out_pm_put: | |
886 | pm_runtime_put(dev); | |
887 | out_pm_disable: | |
888 | pm_runtime_disable(dev); | |
889 | return ret; | |
6ccbe607 KM |
890 | } |
891 | ||
0b255e92 | 892 | static int rcar_i2c_remove(struct platform_device *pdev) |
6ccbe607 KM |
893 | { |
894 | struct rcar_i2c_priv *priv = platform_get_drvdata(pdev); | |
895 | struct device *dev = &pdev->dev; | |
896 | ||
897 | i2c_del_adapter(&priv->adap); | |
73e8b052 | 898 | rcar_i2c_release_dma(priv); |
7ee24eb5 WS |
899 | if (priv->flags & ID_P_PM_BLOCKED) |
900 | pm_runtime_put(dev); | |
6ccbe607 KM |
901 | pm_runtime_disable(dev); |
902 | ||
903 | return 0; | |
904 | } | |
905 | ||
45fd5e4a | 906 | static struct platform_driver rcar_i2c_driver = { |
6ccbe607 KM |
907 | .driver = { |
908 | .name = "i2c-rcar", | |
7679c0e1 | 909 | .of_match_table = rcar_i2c_dt_ids, |
6ccbe607 KM |
910 | }, |
911 | .probe = rcar_i2c_probe, | |
0b255e92 | 912 | .remove = rcar_i2c_remove, |
6ccbe607 KM |
913 | }; |
914 | ||
45fd5e4a | 915 | module_platform_driver(rcar_i2c_driver); |
6ccbe607 | 916 | |
3d99beab | 917 | MODULE_LICENSE("GPL v2"); |
6ccbe607 KM |
918 | MODULE_DESCRIPTION("Renesas R-Car I2C bus driver"); |
919 | MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>"); |