[deliverable/linux.git] / drivers / i2c / busses / i2c-rcar.c

/*
 *  drivers/i2c/busses/i2c-rcar.c
 *
 * Copyright (C) 2012 Renesas Solutions Corp.
 * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
 *
 * This file is based on the drivers/i2c/busses/i2c-sh7760.c
 * (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com>
 *
 * This file used out-of-tree driver i2c-rcar.c
 * Copyright (C) 2011-2012 Renesas Electronics Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/i2c.h>
#include <linux/i2c/i2c-rcar.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/slab.h>

/* register offsets */
#define ICSCR	0x00	/* slave ctrl */
#define ICMCR	0x04	/* master ctrl */
#define ICSSR	0x08	/* slave status */
#define ICMSR	0x0C	/* master status */
#define ICSIER	0x10	/* slave irq enable */
#define ICMIER	0x14	/* master irq enable */
#define ICCCR	0x18	/* clock dividers */
#define ICSAR	0x1C	/* slave address */
#define ICMAR	0x20	/* master address */
#define ICRXTX	0x24	/* data port */

/* ICMCR */
#define MDBS	(1 << 7)	/* non-fifo mode switch */
#define FSCL	(1 << 6)	/* override SCL pin */
#define FSDA	(1 << 5)	/* override SDA pin */
#define OBPC	(1 << 4)	/* override pins */
#define MIE	(1 << 3)	/* master if enable */
#define TSBE	(1 << 2)
#define FSB	(1 << 1)	/* force stop bit */
#define ESG	(1 << 0)	/* en startbit gen */

/* ICMSR (also for ICMIE) */
#define MNR	(1 << 6)	/* nack received */
#define MAL	(1 << 5)	/* arbitration lost */
#define MST	(1 << 4)	/* sent a stop */
#define MDE	(1 << 3)
#define MDT	(1 << 2)
#define MDR	(1 << 1)
#define MAT	(1 << 0)	/* slave addr xfer done */


#define RCAR_BUS_PHASE_START	(MDBS | MIE | ESG)
#define RCAR_BUS_PHASE_DATA	(MDBS | MIE)
#define RCAR_BUS_PHASE_STOP	(MDBS | MIE | FSB)

#define RCAR_IRQ_SEND	(MNR | MAL | MST | MAT | MDE)
#define RCAR_IRQ_RECV	(MNR | MAL | MST | MAT | MDR)
#define RCAR_IRQ_STOP	(MST)

#define RCAR_IRQ_ACK_SEND	(~(MAT | MDE))
#define RCAR_IRQ_ACK_RECV	(~(MAT | MDR))

/*
 * flags
 */
#define ID_LAST_MSG	(1 << 0)
#define ID_IOERROR	(1 << 1)
#define ID_DONE		(1 << 2)
#define ID_ARBLOST	(1 << 3)
#define ID_NACK		(1 << 4)

enum rcar_i2c_type {
	I2C_RCAR_GEN1,
	I2C_RCAR_GEN2,
};

struct rcar_i2c_priv {
	void __iomem *io;
	struct i2c_adapter adap;
	struct i2c_msg	*msg;
	struct clk *clk;

	wait_queue_head_t wait;

	int pos;
	u32 icccr;
	u32 flags;
	enum rcar_i2c_type	devtype;
};

#define rcar_i2c_priv_to_dev(p)		((p)->adap.dev.parent)
#define rcar_i2c_is_recv(p)		((p)->msg->flags & I2C_M_RD)

#define rcar_i2c_flags_set(p, f)	((p)->flags |= (f))
#define rcar_i2c_flags_has(p, f)	((p)->flags & (f))

#define LOOP_TIMEOUT	1024

/*
 *		basic functions
 */
static void rcar_i2c_write(struct rcar_i2c_priv *priv, int reg, u32 val)
{
	writel(val, priv->io + reg);
}

static u32 rcar_i2c_read(struct rcar_i2c_priv *priv, int reg)
{
	return readl(priv->io + reg);
}

static void rcar_i2c_init(struct rcar_i2c_priv *priv)
{
	/*
	 * reset slave mode.
	 * slave mode is not used on this driver
	 */
	rcar_i2c_write(priv, ICSIER, 0);
	rcar_i2c_write(priv, ICSAR, 0);
	rcar_i2c_write(priv, ICSCR, 0);
	rcar_i2c_write(priv, ICSSR, 0);

	/* reset master mode */
	rcar_i2c_write(priv, ICMIER, 0);
	rcar_i2c_write(priv, ICMCR, 0);
	rcar_i2c_write(priv, ICMSR, 0);
	rcar_i2c_write(priv, ICMAR, 0);
}

/*
 *		bus control functions
 */
static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv)
{
	int i;

	for (i = 0; i < LOOP_TIMEOUT; i++) {
		/* make sure that bus is not busy */
		if (!(rcar_i2c_read(priv, ICMCR) & FSDA))
			return 0;
		udelay(1);
	}

	return -EBUSY;
}

/*
 *		clock function
 */
static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv,
				    u32 bus_speed,
				    struct device *dev)
{
	u32 scgd, cdf;
	u32 round, ick;
	u32 scl;
	u32 cdf_width;
	unsigned long rate;

	switch (priv->devtype) {
	case I2C_RCAR_GEN1:
		cdf_width = 2;
		break;
	case I2C_RCAR_GEN2:
		cdf_width = 3;
		break;
	default:
		dev_err(dev, "device type error\n");
		return -EIO;
	}

	/*
	 * calculate SCL clock
	 * see
	 *	ICCCR
	 *
	 * ick	= clkp / (1 + CDF)
	 * SCL	= ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
	 *
	 * ick  : I2C internal clock < 20 MHz
	 * ticf : I2C SCL falling time  =  35 ns here
	 * tr   : I2C SCL rising  time  = 200 ns here
	 * intd : LSI internal delay    =  50 ns here
	 * clkp : peripheral_clk
	 * F[]  : integer up-valuation
	 */
	rate = clk_get_rate(priv->clk);
	cdf = rate / 20000000;
	if (cdf >= 1 << cdf_width) {
		dev_err(dev, "Input clock %lu too high\n", rate);
		return -EIO;
	}
	ick = rate / (cdf + 1);

	/*
	 * it is impossible to calculate large scale
	 * number on u32. separate it
	 *
	 * F[(ticf + tr + intd) * ick]
	 *  = F[(35 + 200 + 50)ns * ick]
	 *  = F[285 * ick / 1000000000]
	 *  = F[(ick / 1000000) * 285 / 1000]
	 */
	round = (ick + 500000) / 1000000 * 285;
	round = (round + 500) / 1000;

	/*
	 * SCL	= ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
	 *
	 * Calculation result (= SCL) should be less than
	 * bus_speed for hardware safety
	 *
	 * We could use something along the lines of
	 *	div = ick / (bus_speed + 1) + 1;
	 *	scgd = (div - 20 - round + 7) / 8;
	 *	scl = ick / (20 + (scgd * 8) + round);
	 * (not fully verified) but that would get pretty involved
	 */
	for (scgd = 0; scgd < 0x40; scgd++) {
		scl = ick / (20 + (scgd * 8) + round);
		if (scl <= bus_speed)
			goto scgd_find;
	}
	dev_err(dev, "it is impossible to calculate best SCL\n");
	return -EIO;

scgd_find:
	dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n",
		scl, bus_speed, clk_get_rate(priv->clk), round, cdf, scgd);

	/*
	 * keep icccr value
	 */
	priv->icccr = scgd << cdf_width | cdf;

	return 0;
}

/*
 *		status functions
 */

static int rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv)
{
	int read = !!rcar_i2c_is_recv(priv);

	rcar_i2c_write(priv, ICMAR, (priv->msg->addr << 1) | read);
	rcar_i2c_write(priv, ICMSR, 0);
	rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
	rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND);

	return 0;
}

/*
 *		interrupt functions
 */
static int rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr)
{
	struct i2c_msg *msg = priv->msg;

	/*
	 * FIXME
	 * sometimes, unknown interrupt happened.
	 * Do nothing
	 */
	if (!(msr & MDE))
		return 0;

	/*
	 * If address transfer phase finished,
	 * goto data phase.
	 */
	if (msr & MAT)
		rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA);

	if (priv->pos < msg->len) {
		/*
		 * Prepare next data to ICRXTX register.
		 * This data will go to _SHIFT_ register.
		 *
		 *    *
		 * [ICRXTX] -> [SHIFT] -> [I2C bus]
		 */
		rcar_i2c_write(priv, ICRXTX, msg->buf[priv->pos]);
		priv->pos++;

	} else {
		/*
		 * The last data was pushed to ICRXTX on _PREV_ empty irq.
		 * It is on _SHIFT_ register, and will sent to I2C bus.
		 *
		 *		  *
		 * [ICRXTX] -> [SHIFT] -> [I2C bus]
		 */

		if (priv->flags & ID_LAST_MSG)
			/*
			 * If current msg is the _LAST_ msg,
			 * prepare stop condition here.
			 * ID_DONE will be set on STOP irq.
			 */
			rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
		else
			/*
			 * If current msg is _NOT_ last msg,
			 * it doesn't call stop phase.
			 * thus, there is no STOP irq.
			 * return ID_DONE here.
			 */
			return ID_DONE;
	}

	rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_SEND);

	return 0;
}

static int rcar_i2c_irq_recv(struct rcar_i2c_priv *priv, u32 msr)
{
	struct i2c_msg *msg = priv->msg;

	/*
	 * FIXME
	 * sometimes, unknown interrupt happened.
	 * Do nothing
	 */
	if (!(msr & MDR))
		return 0;

	if (msr & MAT) {
		/*
		 * Address transfer phase finished,
		 * but, there is no data at this point.
		 * Do nothing.
		 */
	} else if (priv->pos < msg->len) {
		/*
		 * get received data
		 */
		msg->buf[priv->pos] = rcar_i2c_read(priv, ICRXTX);
		priv->pos++;
	}

	/*
	 * If next received data is the _LAST_,
	 * go to STOP phase,
	 * otherwise, go to DATA phase.
	 */
	if (priv->pos + 1 >= msg->len)
		rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
	else
		rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA);

	rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_RECV);

	return 0;
}

static irqreturn_t rcar_i2c_irq(int irq, void *ptr)
{
	struct rcar_i2c_priv *priv = ptr;
	struct device *dev = rcar_i2c_priv_to_dev(priv);
	u32 msr;

	msr = rcar_i2c_read(priv, ICMSR);

	/*
	 * Arbitration lost
	 */
	if (msr & MAL) {
		/*
		 * CAUTION
		 *
		 * When arbitration lost, device become _slave_ mode.
		 */
		dev_dbg(dev, "Arbitration Lost\n");
		rcar_i2c_flags_set(priv, (ID_DONE | ID_ARBLOST));
		goto out;
	}

	/*
	 * Stop
	 */
	if (msr & MST) {
		dev_dbg(dev, "Stop\n");
		rcar_i2c_flags_set(priv, ID_DONE);
		goto out;
	}

	/*
	 * Nack
	 */
	if (msr & MNR) {
		dev_dbg(dev, "Nack\n");

		/* go to stop phase */
		rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
		rcar_i2c_write(priv, ICMIER, RCAR_IRQ_STOP);
		rcar_i2c_flags_set(priv, ID_NACK);
		goto out;
	}

	/*
	 * recv/send
	 */
	if (rcar_i2c_is_recv(priv))
		rcar_i2c_flags_set(priv, rcar_i2c_irq_recv(priv, msr));
	else
		rcar_i2c_flags_set(priv, rcar_i2c_irq_send(priv, msr));

out:
	if (rcar_i2c_flags_has(priv, ID_DONE)) {
		rcar_i2c_write(priv, ICMIER, 0);
		rcar_i2c_write(priv, ICMSR, 0);
		wake_up(&priv->wait);
	}

	return IRQ_HANDLED;
}

static int rcar_i2c_master_xfer(struct i2c_adapter *adap,
				struct i2c_msg *msgs,
				int num)
{
	struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
	struct device *dev = rcar_i2c_priv_to_dev(priv);
	int i, ret, timeout;

	pm_runtime_get_sync(dev);

	rcar_i2c_init(priv);
	/* start clock */
	rcar_i2c_write(priv, ICCCR, priv->icccr);

	ret = rcar_i2c_bus_barrier(priv);
	if (ret < 0)
		goto out;

	for (i = 0; i < num; i++) {
		/* This HW can't send STOP after address phase */
		if (msgs[i].len == 0) {
			ret = -EOPNOTSUPP;
			break;
		}

		/* init each data */
		priv->msg	= &msgs[i];
		priv->pos	= 0;
		priv->flags	= 0;
		if (priv->msg == &msgs[num - 1])
			rcar_i2c_flags_set(priv, ID_LAST_MSG);

		ret = rcar_i2c_prepare_msg(priv);

		if (ret < 0)
			break;

		/*
		 * wait result
		 */
		timeout = wait_event_timeout(priv->wait,
					     rcar_i2c_flags_has(priv, ID_DONE),
					     5 * HZ);
		if (!timeout) {
			ret = -ETIMEDOUT;
			break;
		}

		/*
		 * error handling
		 */
		if (rcar_i2c_flags_has(priv, ID_NACK)) {
			ret = -ENXIO;
			break;
		}

		if (rcar_i2c_flags_has(priv, ID_ARBLOST)) {
			ret = -EAGAIN;
			break;
		}

		if (rcar_i2c_flags_has(priv, ID_IOERROR)) {
			ret = -EIO;
			break;
		}

		ret = i + 1; /* The number of transfer */
	}
out:
	pm_runtime_put(dev);

	if (ret < 0 && ret != -ENXIO)
		dev_err(dev, "error %d : %x\n", ret, priv->flags);

	return ret;
}

static u32 rcar_i2c_func(struct i2c_adapter *adap)
{
	/* This HW can't do SMBUS_QUICK and NOSTART */
	return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
}

static const struct i2c_algorithm rcar_i2c_algo = {
	.master_xfer	= rcar_i2c_master_xfer,
	.functionality	= rcar_i2c_func,
};

static const struct of_device_id rcar_i2c_dt_ids[] = {
	{ .compatible = "renesas,i2c-rcar", .data = (void *)I2C_RCAR_GEN1 },
	{ .compatible = "renesas,i2c-r8a7778", .data = (void *)I2C_RCAR_GEN1 },
	{ .compatible = "renesas,i2c-r8a7779", .data = (void *)I2C_RCAR_GEN1 },
	{ .compatible = "renesas,i2c-r8a7790", .data = (void *)I2C_RCAR_GEN2 },
	{ .compatible = "renesas,i2c-r8a7791", .data = (void *)I2C_RCAR_GEN2 },
	{ .compatible = "renesas,i2c-r8a7792", .data = (void *)I2C_RCAR_GEN2 },
	{ .compatible = "renesas,i2c-r8a7793", .data = (void *)I2C_RCAR_GEN2 },
	{ .compatible = "renesas,i2c-r8a7794", .data = (void *)I2C_RCAR_GEN2 },
	{},
};
MODULE_DEVICE_TABLE(of, rcar_i2c_dt_ids);

static int rcar_i2c_probe(struct platform_device *pdev)
{
	struct i2c_rcar_platform_data *pdata = dev_get_platdata(&pdev->dev);
	struct rcar_i2c_priv *priv;
	struct i2c_adapter *adap;
	struct resource *res;
	struct device *dev = &pdev->dev;
	u32 bus_speed;
	int irq, ret;

	priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL);
	if (!priv) {
		dev_err(dev, "no mem for private data\n");
		return -ENOMEM;
	}

	priv->clk = devm_clk_get(dev, NULL);
	if (IS_ERR(priv->clk)) {
		dev_err(dev, "cannot get clock\n");
		return PTR_ERR(priv->clk);
	}

	bus_speed = 100000; /* default 100 kHz */
	ret = of_property_read_u32(dev->of_node, "clock-frequency", &bus_speed);
	if (ret < 0 && pdata && pdata->bus_speed)
		bus_speed = pdata->bus_speed;

	if (pdev->dev.of_node)
		priv->devtype = (long)of_match_device(rcar_i2c_dt_ids,
						      dev)->data;
	else
		priv->devtype = platform_get_device_id(pdev)->driver_data;

	ret = rcar_i2c_clock_calculate(priv, bus_speed, dev);
	if (ret < 0)
		return ret;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	priv->io = devm_ioremap_resource(dev, res);
	if (IS_ERR(priv->io))
		return PTR_ERR(priv->io);

	irq = platform_get_irq(pdev, 0);
	init_waitqueue_head(&priv->wait);

	adap			= &priv->adap;
	adap->nr		= pdev->id;
	adap->algo		= &rcar_i2c_algo;
	adap->class		= I2C_CLASS_HWMON | I2C_CLASS_SPD | I2C_CLASS_DEPRECATED;
	adap->retries		= 3;
	adap->dev.parent	= dev;
	adap->dev.of_node	= dev->of_node;
	i2c_set_adapdata(adap, priv);
	strlcpy(adap->name, pdev->name, sizeof(adap->name));

	ret = devm_request_irq(dev, irq, rcar_i2c_irq, 0,
			       dev_name(dev), priv);
	if (ret < 0) {
		dev_err(dev, "cannot get irq %d\n", irq);
		return ret;
	}

	ret = i2c_add_numbered_adapter(adap);
	if (ret < 0) {
		dev_err(dev, "reg adap failed: %d\n", ret);
		return ret;
	}

	pm_runtime_enable(dev);
	platform_set_drvdata(pdev, priv);

	dev_info(dev, "probed\n");

	return 0;
}

static int rcar_i2c_remove(struct platform_device *pdev)
{
	struct rcar_i2c_priv *priv = platform_get_drvdata(pdev);
	struct device *dev = &pdev->dev;

	i2c_del_adapter(&priv->adap);
	pm_runtime_disable(dev);

	return 0;
}

static struct platform_device_id rcar_i2c_id_table[] = {
	{ "i2c-rcar",		I2C_RCAR_GEN1 },
	{ "i2c-rcar_gen1",	I2C_RCAR_GEN1 },
	{ "i2c-rcar_gen2",	I2C_RCAR_GEN2 },
	{},
};
MODULE_DEVICE_TABLE(platform, rcar_i2c_id_table);

static struct platform_driver rcar_i2c_driver = {
	.driver	= {
		.name	= "i2c-rcar",
		.owner	= THIS_MODULE,
		.of_match_table = rcar_i2c_dt_ids,
	},
	.probe		= rcar_i2c_probe,
	.remove		= rcar_i2c_remove,
	.id_table	= rcar_i2c_id_table,
};

module_platform_driver(rcar_i2c_driver);

MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Renesas R-Car I2C bus driver");
MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>");
Commit	Line	Data
6ccbe607 KM	1	/*
	2	* drivers/i2c/busses/i2c-rcar.c
	3	*
	4	* Copyright (C) 2012 Renesas Solutions Corp.
	5	* Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
	6	*
	7	* This file is based on the drivers/i2c/busses/i2c-sh7760.c
	8	* (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com>
	9	*
	10	* This file used out-of-tree driver i2c-rcar.c
	11	* Copyright (C) 2011-2012 Renesas Electronics Corporation
	12	*
	13	* This program is free software; you can redistribute it and/or modify
	14	* it under the terms of the GNU General Public License as published by
	15	* the Free Software Foundation; either version 2 of the License
	16	*
	17	* This program is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	* GNU General Public License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; if not, write to the Free Software
	24	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	25	*/
	26	#include <linux/clk.h>
	27	#include <linux/delay.h>
	28	#include <linux/err.h>
6ccbe607 KM	29	#include <linux/interrupt.h>
	30	#include <linux/io.h>
	31	#include <linux/i2c.h>
	32	#include <linux/i2c/i2c-rcar.h>
	33	#include <linux/kernel.h>
	34	#include <linux/module.h>
7679c0e1	35	#include <linux/of_device.h>
6ccbe607 KM	36	#include <linux/platform_device.h>
	37	#include <linux/pm_runtime.h>
	38	#include <linux/slab.h>
6ccbe607 KM	39
	40	/* register offsets */
	41	#define ICSCR 0x00 /* slave ctrl */
	42	#define ICMCR 0x04 /* master ctrl */
	43	#define ICSSR 0x08 /* slave status */
	44	#define ICMSR 0x0C /* master status */
	45	#define ICSIER 0x10 /* slave irq enable */
	46	#define ICMIER 0x14 /* master irq enable */
	47	#define ICCCR 0x18 /* clock dividers */
	48	#define ICSAR 0x1C /* slave address */
	49	#define ICMAR 0x20 /* master address */
	50	#define ICRXTX 0x24 /* data port */
	51
	52	/* ICMCR */
	53	#define MDBS (1 << 7) /* non-fifo mode switch */
	54	#define FSCL (1 << 6) /* override SCL pin */
	55	#define FSDA (1 << 5) /* override SDA pin */
	56	#define OBPC (1 << 4) /* override pins */
	57	#define MIE (1 << 3) /* master if enable */
	58	#define TSBE (1 << 2)
	59	#define FSB (1 << 1) /* force stop bit */
	60	#define ESG (1 << 0) /* en startbit gen */
	61
3e3aabac	62	/* ICMSR (also for ICMIE) */
6ccbe607 KM	63	#define MNR (1 << 6) /* nack received */
	64	#define MAL (1 << 5) /* arbitration lost */
	65	#define MST (1 << 4) /* sent a stop */
	66	#define MDE (1 << 3)
	67	#define MDT (1 << 2)
	68	#define MDR (1 << 1)
	69	#define MAT (1 << 0) /* slave addr xfer done */
	70
6ccbe607	71
4f443a8a WS	72	#define RCAR_BUS_PHASE_START (MDBS \| MIE \| ESG)
	73	#define RCAR_BUS_PHASE_DATA (MDBS \| MIE)
	74	#define RCAR_BUS_PHASE_STOP (MDBS \| MIE \| FSB)
6ccbe607	75
3e3aabac WS	76	#define RCAR_IRQ_SEND (MNR \| MAL \| MST \| MAT \| MDE)
	77	#define RCAR_IRQ_RECV (MNR \| MAL \| MST \| MAT \| MDR)
	78	#define RCAR_IRQ_STOP (MST)
6ccbe607	79
3c95de67 WS	80	#define RCAR_IRQ_ACK_SEND (~(MAT \| MDE))
	81	#define RCAR_IRQ_ACK_RECV (~(MAT \| MDR))
	82
6ccbe607 KM	83	/*
	84	* flags
	85	*/
	86	#define ID_LAST_MSG (1 << 0)
	87	#define ID_IOERROR (1 << 1)
	88	#define ID_DONE (1 << 2)
	89	#define ID_ARBLOST (1 << 3)
	90	#define ID_NACK (1 << 4)
	91
b720423a	92	enum rcar_i2c_type {
043a3f11 KM	93	I2C_RCAR_GEN1,
043a3f11 KM	94	I2C_RCAR_GEN2,
b720423a NVD	95	};
b720423a NVD	96
6ccbe607 KM	97	struct rcar_i2c_priv {
	98	void __iomem *io;
	99	struct i2c_adapter adap;
	100	struct i2c_msg *msg;
bc8120f1	101	struct clk *clk;
6ccbe607	102
6ccbe607 KM	103	wait_queue_head_t wait;
	104
	105	int pos;
6ccbe607 KM	106	u32 icccr;
6ccbe607 KM	107	u32 flags;
b720423a	108	enum rcar_i2c_type devtype;
6ccbe607 KM	109	};
	110
	111	#define rcar_i2c_priv_to_dev(p) ((p)->adap.dev.parent)
	112	#define rcar_i2c_is_recv(p) ((p)->msg->flags & I2C_M_RD)
	113
	114	#define rcar_i2c_flags_set(p, f) ((p)->flags \|= (f))
	115	#define rcar_i2c_flags_has(p, f) ((p)->flags & (f))
	116
	117	#define LOOP_TIMEOUT 1024
	118
	119	/*
	120	* basic functions
	121	*/
	122	static void rcar_i2c_write(struct rcar_i2c_priv *priv, int reg, u32 val)
	123	{
	124	writel(val, priv->io + reg);
	125	}
	126
	127	static u32 rcar_i2c_read(struct rcar_i2c_priv *priv, int reg)
	128	{
	129	return readl(priv->io + reg);
	130	}
	131
	132	static void rcar_i2c_init(struct rcar_i2c_priv *priv)
	133	{
	134	/*
	135	* reset slave mode.
	136	* slave mode is not used on this driver
	137	*/
	138	rcar_i2c_write(priv, ICSIER, 0);
	139	rcar_i2c_write(priv, ICSAR, 0);
	140	rcar_i2c_write(priv, ICSCR, 0);
	141	rcar_i2c_write(priv, ICSSR, 0);
	142
	143	/* reset master mode */
	144	rcar_i2c_write(priv, ICMIER, 0);
	145	rcar_i2c_write(priv, ICMCR, 0);
	146	rcar_i2c_write(priv, ICMSR, 0);
	147	rcar_i2c_write(priv, ICMAR, 0);
	148	}
	149
6ccbe607 KM	150	/*
	151	* bus control functions
	152	*/
	153	static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv)
	154	{
	155	int i;
	156
	157	for (i = 0; i < LOOP_TIMEOUT; i++) {
	158	/* make sure that bus is not busy */
	159	if (!(rcar_i2c_read(priv, ICMCR) & FSDA))
	160	return 0;
	161	udelay(1);
	162	}
	163
	164	return -EBUSY;
	165	}
	166
6ccbe607 KM	167	/*
	168	* clock function
	169	*/
	170	static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv,
	171	u32 bus_speed,
	172	struct device *dev)
	173	{
6ccbe607 KM	174	u32 scgd, cdf;
	175	u32 round, ick;
	176	u32 scl;
b720423a	177	u32 cdf_width;
8d049403	178	unsigned long rate;
6ccbe607	179
b720423a	180	switch (priv->devtype) {
043a3f11	181	case I2C_RCAR_GEN1:
b720423a NVD	182	cdf_width = 2;
b720423a NVD	183	break;
043a3f11	184	case I2C_RCAR_GEN2:
b720423a NVD	185	cdf_width = 3;
	186	break;
	187	default:
	188	dev_err(dev, "device type error\n");
	189	return -EIO;
	190	}
	191
6ccbe607 KM	192	/*
	193	* calculate SCL clock
	194	* see
	195	* ICCCR
	196	*
	197	* ick = clkp / (1 + CDF)
	198	* SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
	199	*
	200	* ick : I2C internal clock < 20 MHz
	201	* ticf : I2C SCL falling time = 35 ns here
	202	* tr : I2C SCL rising time = 200 ns here
	203	* intd : LSI internal delay = 50 ns here
	204	* clkp : peripheral_clk
	205	* F[] : integer up-valuation
	206	*/
bc8120f1	207	rate = clk_get_rate(priv->clk);
8d049403 GL	208	cdf = rate / 20000000;
	209	if (cdf >= 1 << cdf_width) {
	210	dev_err(dev, "Input clock %lu too high\n", rate);
	211	return -EIO;
6ccbe607	212	}
8d049403	213	ick = rate / (cdf + 1);
6ccbe607	214
6ccbe607 KM	215	/*
	216	* it is impossible to calculate large scale
	217	* number on u32. separate it
	218	*
	219	* F[(ticf + tr + intd) * ick]
	220	* = F[(35 + 200 + 50)ns * ick]
	221	* = F[285 * ick / 1000000000]
	222	* = F[(ick / 1000000) * 285 / 1000]
	223	*/
	224	round = (ick + 500000) / 1000000 * 285;
	225	round = (round + 500) / 1000;
	226
	227	/*
	228	* SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
	229	*
	230	* Calculation result (= SCL) should be less than
	231	* bus_speed for hardware safety
8d049403 GL	232	*
	233	* We could use something along the lines of
	234	* div = ick / (bus_speed + 1) + 1;
	235	* scgd = (div - 20 - round + 7) / 8;
	236	* scl = ick / (20 + (scgd * 8) + round);
	237	* (not fully verified) but that would get pretty involved
6ccbe607 KM	238	*/
	239	for (scgd = 0; scgd < 0x40; scgd++) {
	240	scl = ick / (20 + (scgd * 8) + round);
	241	if (scl <= bus_speed)
	242	goto scgd_find;
	243	}
	244	dev_err(dev, "it is impossible to calculate best SCL\n");
	245	return -EIO;
	246
	247	scgd_find:
	248	dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n",
bc8120f1	249	scl, bus_speed, clk_get_rate(priv->clk), round, cdf, scgd);
6ccbe607 KM	250
	251	/*
	252	* keep icccr value
	253	*/
14d32f17	254	priv->icccr = scgd << cdf_width \| cdf;
6ccbe607 KM	255
	256	return 0;
	257	}
	258
6ccbe607 KM	259	/*
	260	* status functions
	261	*/
6ccbe607	262
386babf8	263	static int rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv)
6ccbe607	264	{
386babf8	265	int read = !!rcar_i2c_is_recv(priv);
6ccbe607	266
386babf8	267	rcar_i2c_write(priv, ICMAR, (priv->msg->addr << 1) \| read);
3c95de67	268	rcar_i2c_write(priv, ICMSR, 0);
4f443a8a	269	rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
386babf8	270	rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND);
6ccbe607 KM	271
	272	return 0;
	273	}
	274
6ccbe607 KM	275	/*
	276	* interrupt functions
	277	*/
	278	static int rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr)
	279	{
	280	struct i2c_msg *msg = priv->msg;
	281
	282	/*
	283	* FIXME
	284	* sometimes, unknown interrupt happened.
	285	* Do nothing
	286	*/
	287	if (!(msr & MDE))
	288	return 0;
	289
	290	/*
	291	* If address transfer phase finished,
	292	* goto data phase.
	293	*/
	294	if (msr & MAT)
4f443a8a	295	rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA);
6ccbe607 KM	296
	297	if (priv->pos < msg->len) {
	298	/*
	299	* Prepare next data to ICRXTX register.
	300	* This data will go to _SHIFT_ register.
	301	*
	302	* *
	303	* [ICRXTX] -> [SHIFT] -> [I2C bus]
	304	*/
	305	rcar_i2c_write(priv, ICRXTX, msg->buf[priv->pos]);
	306	priv->pos++;
	307
	308	} else {
	309	/*
	310	* The last data was pushed to ICRXTX on _PREV_ empty irq.
	311	* It is on _SHIFT_ register, and will sent to I2C bus.
	312	*
	313	* *
	314	* [ICRXTX] -> [SHIFT] -> [I2C bus]
	315	*/
	316
	317	if (priv->flags & ID_LAST_MSG)
	318	/*
	319	* If current msg is the _LAST_ msg,
	320	* prepare stop condition here.
	321	* ID_DONE will be set on STOP irq.
	322	*/
4f443a8a	323	rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
6ccbe607 KM	324	else
	325	/*
	326	* If current msg is _NOT_ last msg,
	327	* it doesn't call stop phase.
	328	* thus, there is no STOP irq.
	329	* return ID_DONE here.
	330	*/
	331	return ID_DONE;
	332	}
	333
3c95de67	334	rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_SEND);
6ccbe607 KM	335
	336	return 0;
	337	}
	338
	339	static int rcar_i2c_irq_recv(struct rcar_i2c_priv *priv, u32 msr)
	340	{
	341	struct i2c_msg *msg = priv->msg;
	342
	343	/*
	344	* FIXME
	345	* sometimes, unknown interrupt happened.
	346	* Do nothing
	347	*/
	348	if (!(msr & MDR))
	349	return 0;
	350
	351	if (msr & MAT) {
	352	/*
	353	* Address transfer phase finished,
	354	* but, there is no data at this point.
	355	* Do nothing.
	356	*/
	357	} else if (priv->pos < msg->len) {
	358	/*
	359	* get received data
	360	*/
	361	msg->buf[priv->pos] = rcar_i2c_read(priv, ICRXTX);
	362	priv->pos++;
	363	}
	364
	365	/*
	366	* If next received data is the _LAST_,
	367	* go to STOP phase,
	368	* otherwise, go to DATA phase.
	369	*/
	370	if (priv->pos + 1 >= msg->len)
4f443a8a	371	rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
6ccbe607	372	else
4f443a8a	373	rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA);
6ccbe607	374
3c95de67	375	rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_RECV);
6ccbe607 KM	376
	377	return 0;
	378	}
	379
	380	static irqreturn_t rcar_i2c_irq(int irq, void *ptr)
	381	{
	382	struct rcar_i2c_priv *priv = ptr;
	383	struct device *dev = rcar_i2c_priv_to_dev(priv);
	384	u32 msr;
	385
1c176d53	386	msr = rcar_i2c_read(priv, ICMSR);
6ccbe607 KM	387
	388	/*
	389	* Arbitration lost
	390	*/
	391	if (msr & MAL) {
	392	/*
	393	* CAUTION
	394	*
	395	* When arbitration lost, device become _slave_ mode.
	396	*/
	397	dev_dbg(dev, "Arbitration Lost\n");
	398	rcar_i2c_flags_set(priv, (ID_DONE \| ID_ARBLOST));
	399	goto out;
	400	}
	401
	402	/*
	403	* Stop
	404	*/
	405	if (msr & MST) {
	406	dev_dbg(dev, "Stop\n");
	407	rcar_i2c_flags_set(priv, ID_DONE);
	408	goto out;
	409	}
	410
	411	/*
	412	* Nack
	413	*/
	414	if (msr & MNR) {
	415	dev_dbg(dev, "Nack\n");
	416
	417	/* go to stop phase */
4f443a8a	418	rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
f2382249	419	rcar_i2c_write(priv, ICMIER, RCAR_IRQ_STOP);
6ccbe607 KM	420	rcar_i2c_flags_set(priv, ID_NACK);
	421	goto out;
	422	}
	423
	424	/*
	425	* recv/send
	426	*/
	427	if (rcar_i2c_is_recv(priv))
	428	rcar_i2c_flags_set(priv, rcar_i2c_irq_recv(priv, msr));
	429	else
	430	rcar_i2c_flags_set(priv, rcar_i2c_irq_send(priv, msr));
	431
	432	out:
	433	if (rcar_i2c_flags_has(priv, ID_DONE)) {
f2382249	434	rcar_i2c_write(priv, ICMIER, 0);
3c95de67	435	rcar_i2c_write(priv, ICMSR, 0);
6ccbe607 KM	436	wake_up(&priv->wait);
	437	}
	438
6ccbe607 KM	439	return IRQ_HANDLED;
	440	}
	441
	442	static int rcar_i2c_master_xfer(struct i2c_adapter *adap,
	443	struct i2c_msg *msgs,
	444	int num)
	445	{
	446	struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
	447	struct device *dev = rcar_i2c_priv_to_dev(priv);
6ccbe607 KM	448	int i, ret, timeout;
	449
	450	pm_runtime_get_sync(dev);
	451
6ccbe607	452	rcar_i2c_init(priv);
1c176d53 WS	453	/* start clock */
1c176d53 WS	454	rcar_i2c_write(priv, ICCCR, priv->icccr);
6ccbe607	455
3f7de22e WS	456	ret = rcar_i2c_bus_barrier(priv);
	457	if (ret < 0)
	458	goto out;
	459
6ccbe607	460	for (i = 0; i < num; i++) {
d7653964 WS	461	/* This HW can't send STOP after address phase */
	462	if (msgs[i].len == 0) {
	463	ret = -EOPNOTSUPP;
	464	break;
	465	}
	466
6ccbe607 KM	467	/* init each data */
	468	priv->msg = &msgs[i];
	469	priv->pos = 0;
	470	priv->flags = 0;
	471	if (priv->msg == &msgs[num - 1])
	472	rcar_i2c_flags_set(priv, ID_LAST_MSG);
	473
386babf8	474	ret = rcar_i2c_prepare_msg(priv);
6ccbe607	475
6ccbe607 KM	476	if (ret < 0)
	477	break;
	478
	479	/*
	480	* wait result
	481	*/
	482	timeout = wait_event_timeout(priv->wait,
	483	rcar_i2c_flags_has(priv, ID_DONE),
	484	5 * HZ);
	485	if (!timeout) {
	486	ret = -ETIMEDOUT;
	487	break;
	488	}
	489
	490	/*
	491	* error handling
	492	*/
	493	if (rcar_i2c_flags_has(priv, ID_NACK)) {
6ff4b105	494	ret = -ENXIO;
6ccbe607 KM	495	break;
	496	}
	497
	498	if (rcar_i2c_flags_has(priv, ID_ARBLOST)) {
	499	ret = -EAGAIN;
	500	break;
	501	}
	502
	503	if (rcar_i2c_flags_has(priv, ID_IOERROR)) {
	504	ret = -EIO;
	505	break;
	506	}
	507
	508	ret = i + 1; /* The number of transfer */
	509	}
3f7de22e	510	out:
6ccbe607 KM	511	pm_runtime_put(dev);
6ccbe607 KM	512
6ff4b105	513	if (ret < 0 && ret != -ENXIO)
6ccbe607 KM	514	dev_err(dev, "error %d : %x\n", ret, priv->flags);
	515
	516	return ret;
	517	}
	518
	519	static u32 rcar_i2c_func(struct i2c_adapter *adap)
	520	{
d7653964 WS	521	/* This HW can't do SMBUS_QUICK and NOSTART */
d7653964 WS	522	return I2C_FUNC_I2C \| (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
6ccbe607 KM	523	}
	524
	525	static const struct i2c_algorithm rcar_i2c_algo = {
	526	.master_xfer = rcar_i2c_master_xfer,
	527	.functionality = rcar_i2c_func,
	528	};
	529
7679c0e1	530	static const struct of_device_id rcar_i2c_dt_ids[] = {
043a3f11 KM	531	{ .compatible = "renesas,i2c-rcar", .data = (void *)I2C_RCAR_GEN1 },
	532	{ .compatible = "renesas,i2c-r8a7778", .data = (void *)I2C_RCAR_GEN1 },
	533	{ .compatible = "renesas,i2c-r8a7779", .data = (void *)I2C_RCAR_GEN1 },
	534	{ .compatible = "renesas,i2c-r8a7790", .data = (void *)I2C_RCAR_GEN2 },
e8936455	535	{ .compatible = "renesas,i2c-r8a7791", .data = (void *)I2C_RCAR_GEN2 },
819a3951 WS	536	{ .compatible = "renesas,i2c-r8a7792", .data = (void *)I2C_RCAR_GEN2 },
	537	{ .compatible = "renesas,i2c-r8a7793", .data = (void *)I2C_RCAR_GEN2 },
	538	{ .compatible = "renesas,i2c-r8a7794", .data = (void *)I2C_RCAR_GEN2 },
7679c0e1 GL	539	{},
	540	};
	541	MODULE_DEVICE_TABLE(of, rcar_i2c_dt_ids);
	542
0b255e92	543	static int rcar_i2c_probe(struct platform_device *pdev)
6ccbe607	544	{
6d4028c6	545	struct i2c_rcar_platform_data *pdata = dev_get_platdata(&pdev->dev);
6ccbe607 KM	546	struct rcar_i2c_priv *priv;
	547	struct i2c_adapter *adap;
	548	struct resource *res;
	549	struct device *dev = &pdev->dev;
	550	u32 bus_speed;
93e953d3	551	int irq, ret;
6ccbe607	552
6ccbe607 KM	553	priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL);
	554	if (!priv) {
	555	dev_err(dev, "no mem for private data\n");
	556	return -ENOMEM;
	557	}
	558
bc8120f1 BD	559	priv->clk = devm_clk_get(dev, NULL);
	560	if (IS_ERR(priv->clk)) {
	561	dev_err(dev, "cannot get clock\n");
	562	return PTR_ERR(priv->clk);
	563	}
	564
6ccbe607	565	bus_speed = 100000; /* default 100 kHz */
7679c0e1 GL	566	ret = of_property_read_u32(dev->of_node, "clock-frequency", &bus_speed);
7679c0e1 GL	567	if (ret < 0 && pdata && pdata->bus_speed)
6ccbe607	568	bus_speed = pdata->bus_speed;
b720423a	569
7679c0e1 GL	570	if (pdev->dev.of_node)
	571	priv->devtype = (long)of_match_device(rcar_i2c_dt_ids,
	572	dev)->data;
	573	else
	574	priv->devtype = platform_get_device_id(pdev)->driver_data;
b720423a	575
6ccbe607 KM	576	ret = rcar_i2c_clock_calculate(priv, bus_speed, dev);
	577	if (ret < 0)
	578	return ret;
	579
3cc2d009	580	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
84dbf809 TR	581	priv->io = devm_ioremap_resource(dev, res);
	582	if (IS_ERR(priv->io))
	583	return PTR_ERR(priv->io);
6ccbe607	584
93e953d3	585	irq = platform_get_irq(pdev, 0);
6ccbe607	586	init_waitqueue_head(&priv->wait);
6ccbe607 KM	587
	588	adap = &priv->adap;
	589	adap->nr = pdev->id;
	590	adap->algo = &rcar_i2c_algo;
96c4b6bb	591	adap->class = I2C_CLASS_HWMON \| I2C_CLASS_SPD \| I2C_CLASS_DEPRECATED;
6ccbe607 KM	592	adap->retries = 3;
6ccbe607 KM	593	adap->dev.parent = dev;
7679c0e1	594	adap->dev.of_node = dev->of_node;
6ccbe607 KM	595	i2c_set_adapdata(adap, priv);
	596	strlcpy(adap->name, pdev->name, sizeof(adap->name));
	597
93e953d3	598	ret = devm_request_irq(dev, irq, rcar_i2c_irq, 0,
6ccbe607 KM	599	dev_name(dev), priv);
6ccbe607 KM	600	if (ret < 0) {
93e953d3	601	dev_err(dev, "cannot get irq %d\n", irq);
6ccbe607 KM	602	return ret;
	603	}
	604
	605	ret = i2c_add_numbered_adapter(adap);
	606	if (ret < 0) {
	607	dev_err(dev, "reg adap failed: %d\n", ret);
	608	return ret;
	609	}
	610
	611	pm_runtime_enable(dev);
	612	platform_set_drvdata(pdev, priv);
	613
	614	dev_info(dev, "probed\n");
	615
	616	return 0;
	617	}
	618
0b255e92	619	static int rcar_i2c_remove(struct platform_device *pdev)
6ccbe607 KM	620	{
	621	struct rcar_i2c_priv *priv = platform_get_drvdata(pdev);
	622	struct device *dev = &pdev->dev;
	623
	624	i2c_del_adapter(&priv->adap);
	625	pm_runtime_disable(dev);
	626
	627	return 0;
	628	}
	629
b720423a	630	static struct platform_device_id rcar_i2c_id_table[] = {
043a3f11 KM	631	{ "i2c-rcar", I2C_RCAR_GEN1 },
	632	{ "i2c-rcar_gen1", I2C_RCAR_GEN1 },
	633	{ "i2c-rcar_gen2", I2C_RCAR_GEN2 },
b720423a NVD	634	{},
	635	};
	636	MODULE_DEVICE_TABLE(platform, rcar_i2c_id_table);
	637
45fd5e4a	638	static struct platform_driver rcar_i2c_driver = {
6ccbe607 KM	639	.driver = {
	640	.name = "i2c-rcar",
	641	.owner = THIS_MODULE,
7679c0e1	642	.of_match_table = rcar_i2c_dt_ids,
6ccbe607 KM	643	},
6ccbe607 KM	644	.probe = rcar_i2c_probe,
0b255e92	645	.remove = rcar_i2c_remove,
b720423a	646	.id_table = rcar_i2c_id_table,
6ccbe607 KM	647	};
6ccbe607 KM	648
45fd5e4a	649	module_platform_driver(rcar_i2c_driver);
6ccbe607 KM	650
	651	MODULE_LICENSE("GPL");
	652	MODULE_DESCRIPTION("Renesas R-Car I2C bus driver");
	653	MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>");