[deliverable/linux.git] / drivers / i2c / busses / i2c-rcar.c

/*
 *  drivers/i2c/busses/i2c-rcar.c
 *
 * Copyright (C) 2012 Renesas Solutions Corp.
 * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
 *
 * This file is based on the drivers/i2c/busses/i2c-sh7760.c
 * (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com>
 *
 * This file used out-of-tree driver i2c-rcar.c
 * Copyright (C) 2011-2012 Renesas Electronics Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/i2c.h>
#include <linux/i2c/i2c-rcar.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/slab.h>
#include <linux/spinlock.h>

/* register offsets */
#define ICSCR	0x00	/* slave ctrl */
#define ICMCR	0x04	/* master ctrl */
#define ICSSR	0x08	/* slave status */
#define ICMSR	0x0C	/* master status */
#define ICSIER	0x10	/* slave irq enable */
#define ICMIER	0x14	/* master irq enable */
#define ICCCR	0x18	/* clock dividers */
#define ICSAR	0x1C	/* slave address */
#define ICMAR	0x20	/* master address */
#define ICRXTX	0x24	/* data port */

/* ICMCR */
#define MDBS	(1 << 7)	/* non-fifo mode switch */
#define FSCL	(1 << 6)	/* override SCL pin */
#define FSDA	(1 << 5)	/* override SDA pin */
#define OBPC	(1 << 4)	/* override pins */
#define MIE	(1 << 3)	/* master if enable */
#define TSBE	(1 << 2)
#define FSB	(1 << 1)	/* force stop bit */
#define ESG	(1 << 0)	/* en startbit gen */

/* ICMSR */
#define MNR	(1 << 6)	/* nack received */
#define MAL	(1 << 5)	/* arbitration lost */
#define MST	(1 << 4)	/* sent a stop */
#define MDE	(1 << 3)
#define MDT	(1 << 2)
#define MDR	(1 << 1)
#define MAT	(1 << 0)	/* slave addr xfer done */

/* ICMIE */
#define MNRE	(1 << 6)	/* nack irq en */
#define MALE	(1 << 5)	/* arblos irq en */
#define MSTE	(1 << 4)	/* stop irq en */
#define MDEE	(1 << 3)
#define MDTE	(1 << 2)
#define MDRE	(1 << 1)
#define MATE	(1 << 0)	/* address sent irq en */


#define RCAR_BUS_PHASE_START	(MDBS | MIE | ESG)
#define RCAR_BUS_PHASE_DATA	(MDBS | MIE)
#define RCAR_BUS_PHASE_STOP	(MDBS | MIE | FSB)

#define RCAR_IRQ_SEND	(MNRE | MALE | MSTE | MATE | MDEE)
#define RCAR_IRQ_RECV	(MNRE | MALE | MSTE | MATE | MDRE)
#define RCAR_IRQ_STOP	(MSTE)

/*
 * flags
 */
#define ID_LAST_MSG	(1 << 0)
#define ID_IOERROR	(1 << 1)
#define ID_DONE		(1 << 2)
#define ID_ARBLOST	(1 << 3)
#define ID_NACK		(1 << 4)

enum rcar_i2c_type {
	I2C_RCAR_GEN1,
	I2C_RCAR_GEN2,
};

struct rcar_i2c_priv {
	void __iomem *io;
	struct i2c_adapter adap;
	struct i2c_msg	*msg;
	struct clk *clk;

	spinlock_t lock;
	wait_queue_head_t wait;

	int pos;
	u32 icccr;
	u32 flags;
	enum rcar_i2c_type	devtype;
};

#define rcar_i2c_priv_to_dev(p)		((p)->adap.dev.parent)
#define rcar_i2c_is_recv(p)		((p)->msg->flags & I2C_M_RD)

#define rcar_i2c_flags_set(p, f)	((p)->flags |= (f))
#define rcar_i2c_flags_has(p, f)	((p)->flags & (f))

#define LOOP_TIMEOUT	1024

/*
 *		basic functions
 */
static void rcar_i2c_write(struct rcar_i2c_priv *priv, int reg, u32 val)
{
	writel(val, priv->io + reg);
}

static u32 rcar_i2c_read(struct rcar_i2c_priv *priv, int reg)
{
	return readl(priv->io + reg);
}

static void rcar_i2c_init(struct rcar_i2c_priv *priv)
{
	/*
	 * reset slave mode.
	 * slave mode is not used on this driver
	 */
	rcar_i2c_write(priv, ICSIER, 0);
	rcar_i2c_write(priv, ICSAR, 0);
	rcar_i2c_write(priv, ICSCR, 0);
	rcar_i2c_write(priv, ICSSR, 0);

	/* reset master mode */
	rcar_i2c_write(priv, ICMIER, 0);
	rcar_i2c_write(priv, ICMCR, 0);
	rcar_i2c_write(priv, ICMSR, 0);
	rcar_i2c_write(priv, ICMAR, 0);
}

static void rcar_i2c_set_addr(struct rcar_i2c_priv *priv, u32 recv)
{
	rcar_i2c_write(priv, ICMAR, (priv->msg->addr << 1) | recv);
}

/*
 *		bus control functions
 */
static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv)
{
	int i;

	for (i = 0; i < LOOP_TIMEOUT; i++) {
		/* make sure that bus is not busy */
		if (!(rcar_i2c_read(priv, ICMCR) & FSDA))
			return 0;
		udelay(1);
	}

	return -EBUSY;
}

/*
 *		clock function
 */
static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv,
				    u32 bus_speed,
				    struct device *dev)
{
	u32 scgd, cdf;
	u32 round, ick;
	u32 scl;
	u32 cdf_width;
	unsigned long rate;

	switch (priv->devtype) {
	case I2C_RCAR_GEN1:
		cdf_width = 2;
		break;
	case I2C_RCAR_GEN2:
		cdf_width = 3;
		break;
	default:
		dev_err(dev, "device type error\n");
		return -EIO;
	}

	/*
	 * calculate SCL clock
	 * see
	 *	ICCCR
	 *
	 * ick	= clkp / (1 + CDF)
	 * SCL	= ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
	 *
	 * ick  : I2C internal clock < 20 MHz
	 * ticf : I2C SCL falling time  =  35 ns here
	 * tr   : I2C SCL rising  time  = 200 ns here
	 * intd : LSI internal delay    =  50 ns here
	 * clkp : peripheral_clk
	 * F[]  : integer up-valuation
	 */
	rate = clk_get_rate(priv->clk);
	cdf = rate / 20000000;
	if (cdf >= 1 << cdf_width) {
		dev_err(dev, "Input clock %lu too high\n", rate);
		return -EIO;
	}
	ick = rate / (cdf + 1);

	/*
	 * it is impossible to calculate large scale
	 * number on u32. separate it
	 *
	 * F[(ticf + tr + intd) * ick]
	 *  = F[(35 + 200 + 50)ns * ick]
	 *  = F[285 * ick / 1000000000]
	 *  = F[(ick / 1000000) * 285 / 1000]
	 */
	round = (ick + 500000) / 1000000 * 285;
	round = (round + 500) / 1000;

	/*
	 * SCL	= ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
	 *
	 * Calculation result (= SCL) should be less than
	 * bus_speed for hardware safety
	 *
	 * We could use something along the lines of
	 *	div = ick / (bus_speed + 1) + 1;
	 *	scgd = (div - 20 - round + 7) / 8;
	 *	scl = ick / (20 + (scgd * 8) + round);
	 * (not fully verified) but that would get pretty involved
	 */
	for (scgd = 0; scgd < 0x40; scgd++) {
		scl = ick / (20 + (scgd * 8) + round);
		if (scl <= bus_speed)
			goto scgd_find;
	}
	dev_err(dev, "it is impossible to calculate best SCL\n");
	return -EIO;

scgd_find:
	dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n",
		scl, bus_speed, clk_get_rate(priv->clk), round, cdf, scgd);

	/*
	 * keep icccr value
	 */
	priv->icccr = scgd << cdf_width | cdf;

	return 0;
}

/*
 *		status functions
 */

#define rcar_i2c_status_clear(priv) rcar_i2c_status_bit_clear(priv, 0xffffffff)
static void rcar_i2c_status_bit_clear(struct rcar_i2c_priv *priv, u32 bit)
{
	rcar_i2c_write(priv, ICMSR, ~bit);
}

/*
 *		recv/send functions
 */
static int rcar_i2c_recv(struct rcar_i2c_priv *priv)
{
	rcar_i2c_set_addr(priv, 1);
	rcar_i2c_status_clear(priv);
	rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
	rcar_i2c_write(priv, ICMIER, RCAR_IRQ_RECV);

	return 0;
}

static int rcar_i2c_send(struct rcar_i2c_priv *priv)
{
	rcar_i2c_set_addr(priv, 0);
	rcar_i2c_status_clear(priv);
	rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
	rcar_i2c_write(priv, ICMIER, RCAR_IRQ_SEND);

	return 0;
}

#define rcar_i2c_send_restart(priv) rcar_i2c_status_bit_clear(priv, (MAT | MDE))
#define rcar_i2c_recv_restart(priv) rcar_i2c_status_bit_clear(priv, (MAT | MDR))

/*
 *		interrupt functions
 */
static int rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr)
{
	struct i2c_msg *msg = priv->msg;

	/*
	 * FIXME
	 * sometimes, unknown interrupt happened.
	 * Do nothing
	 */
	if (!(msr & MDE))
		return 0;

	/*
	 * If address transfer phase finished,
	 * goto data phase.
	 */
	if (msr & MAT)
		rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA);

	if (priv->pos < msg->len) {
		/*
		 * Prepare next data to ICRXTX register.
		 * This data will go to _SHIFT_ register.
		 *
		 *    *
		 * [ICRXTX] -> [SHIFT] -> [I2C bus]
		 */
		rcar_i2c_write(priv, ICRXTX, msg->buf[priv->pos]);
		priv->pos++;

	} else {
		/*
		 * The last data was pushed to ICRXTX on _PREV_ empty irq.
		 * It is on _SHIFT_ register, and will sent to I2C bus.
		 *
		 *		  *
		 * [ICRXTX] -> [SHIFT] -> [I2C bus]
		 */

		if (priv->flags & ID_LAST_MSG)
			/*
			 * If current msg is the _LAST_ msg,
			 * prepare stop condition here.
			 * ID_DONE will be set on STOP irq.
			 */
			rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
		else
			/*
			 * If current msg is _NOT_ last msg,
			 * it doesn't call stop phase.
			 * thus, there is no STOP irq.
			 * return ID_DONE here.
			 */
			return ID_DONE;
	}

	rcar_i2c_send_restart(priv);

	return 0;
}

static int rcar_i2c_irq_recv(struct rcar_i2c_priv *priv, u32 msr)
{
	struct i2c_msg *msg = priv->msg;

	/*
	 * FIXME
	 * sometimes, unknown interrupt happened.
	 * Do nothing
	 */
	if (!(msr & MDR))
		return 0;

	if (msr & MAT) {
		/*
		 * Address transfer phase finished,
		 * but, there is no data at this point.
		 * Do nothing.
		 */
	} else if (priv->pos < msg->len) {
		/*
		 * get received data
		 */
		msg->buf[priv->pos] = rcar_i2c_read(priv, ICRXTX);
		priv->pos++;
	}

	/*
	 * If next received data is the _LAST_,
	 * go to STOP phase,
	 * otherwise, go to DATA phase.
	 */
	if (priv->pos + 1 >= msg->len)
		rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
	else
		rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA);

	rcar_i2c_recv_restart(priv);

	return 0;
}

static irqreturn_t rcar_i2c_irq(int irq, void *ptr)
{
	struct rcar_i2c_priv *priv = ptr;
	struct device *dev = rcar_i2c_priv_to_dev(priv);
	u32 msr;

	/*-------------- spin lock -----------------*/
	spin_lock(&priv->lock);

	msr = rcar_i2c_read(priv, ICMSR);

	/*
	 * Arbitration lost
	 */
	if (msr & MAL) {
		/*
		 * CAUTION
		 *
		 * When arbitration lost, device become _slave_ mode.
		 */
		dev_dbg(dev, "Arbitration Lost\n");
		rcar_i2c_flags_set(priv, (ID_DONE | ID_ARBLOST));
		goto out;
	}

	/*
	 * Stop
	 */
	if (msr & MST) {
		dev_dbg(dev, "Stop\n");
		rcar_i2c_flags_set(priv, ID_DONE);
		goto out;
	}

	/*
	 * Nack
	 */
	if (msr & MNR) {
		dev_dbg(dev, "Nack\n");

		/* go to stop phase */
		rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
		rcar_i2c_write(priv, ICMIER, RCAR_IRQ_STOP);
		rcar_i2c_flags_set(priv, ID_NACK);
		goto out;
	}

	/*
	 * recv/send
	 */
	if (rcar_i2c_is_recv(priv))
		rcar_i2c_flags_set(priv, rcar_i2c_irq_recv(priv, msr));
	else
		rcar_i2c_flags_set(priv, rcar_i2c_irq_send(priv, msr));

out:
	if (rcar_i2c_flags_has(priv, ID_DONE)) {
		rcar_i2c_write(priv, ICMIER, 0);
		rcar_i2c_status_clear(priv);
		wake_up(&priv->wait);
	}

	spin_unlock(&priv->lock);
	/*-------------- spin unlock -----------------*/

	return IRQ_HANDLED;
}

static int rcar_i2c_master_xfer(struct i2c_adapter *adap,
				struct i2c_msg *msgs,
				int num)
{
	struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
	struct device *dev = rcar_i2c_priv_to_dev(priv);
	unsigned long flags;
	int i, ret, timeout;

	pm_runtime_get_sync(dev);

	/*-------------- spin lock -----------------*/
	spin_lock_irqsave(&priv->lock, flags);

	rcar_i2c_init(priv);
	/* start clock */
	rcar_i2c_write(priv, ICCCR, priv->icccr);

	spin_unlock_irqrestore(&priv->lock, flags);
	/*-------------- spin unlock -----------------*/

	ret = rcar_i2c_bus_barrier(priv);
	if (ret < 0)
		goto out;

	for (i = 0; i < num; i++) {
		/* This HW can't send STOP after address phase */
		if (msgs[i].len == 0) {
			ret = -EOPNOTSUPP;
			break;
		}

		/*-------------- spin lock -----------------*/
		spin_lock_irqsave(&priv->lock, flags);

		/* init each data */
		priv->msg	= &msgs[i];
		priv->pos	= 0;
		priv->flags	= 0;
		if (priv->msg == &msgs[num - 1])
			rcar_i2c_flags_set(priv, ID_LAST_MSG);

		/* start send/recv */
		if (rcar_i2c_is_recv(priv))
			ret = rcar_i2c_recv(priv);
		else
			ret = rcar_i2c_send(priv);

		spin_unlock_irqrestore(&priv->lock, flags);
		/*-------------- spin unlock -----------------*/

		if (ret < 0)
			break;

		/*
		 * wait result
		 */
		timeout = wait_event_timeout(priv->wait,
					     rcar_i2c_flags_has(priv, ID_DONE),
					     5 * HZ);
		if (!timeout) {
			ret = -ETIMEDOUT;
			break;
		}

		/*
		 * error handling
		 */
		if (rcar_i2c_flags_has(priv, ID_NACK)) {
			ret = -ENXIO;
			break;
		}

		if (rcar_i2c_flags_has(priv, ID_ARBLOST)) {
			ret = -EAGAIN;
			break;
		}

		if (rcar_i2c_flags_has(priv, ID_IOERROR)) {
			ret = -EIO;
			break;
		}

		ret = i + 1; /* The number of transfer */
	}
out:
	pm_runtime_put(dev);

	if (ret < 0 && ret != -ENXIO)
		dev_err(dev, "error %d : %x\n", ret, priv->flags);

	return ret;
}

static u32 rcar_i2c_func(struct i2c_adapter *adap)
{
	/* This HW can't do SMBUS_QUICK and NOSTART */
	return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
}

static const struct i2c_algorithm rcar_i2c_algo = {
	.master_xfer	= rcar_i2c_master_xfer,
	.functionality	= rcar_i2c_func,
};

static const struct of_device_id rcar_i2c_dt_ids[] = {
	{ .compatible = "renesas,i2c-rcar", .data = (void *)I2C_RCAR_GEN1 },
	{ .compatible = "renesas,i2c-r8a7778", .data = (void *)I2C_RCAR_GEN1 },
	{ .compatible = "renesas,i2c-r8a7779", .data = (void *)I2C_RCAR_GEN1 },
	{ .compatible = "renesas,i2c-r8a7790", .data = (void *)I2C_RCAR_GEN2 },
	{ .compatible = "renesas,i2c-r8a7791", .data = (void *)I2C_RCAR_GEN2 },
	{ .compatible = "renesas,i2c-r8a7792", .data = (void *)I2C_RCAR_GEN2 },
	{ .compatible = "renesas,i2c-r8a7793", .data = (void *)I2C_RCAR_GEN2 },
	{ .compatible = "renesas,i2c-r8a7794", .data = (void *)I2C_RCAR_GEN2 },
	{},
};
MODULE_DEVICE_TABLE(of, rcar_i2c_dt_ids);

static int rcar_i2c_probe(struct platform_device *pdev)
{
	struct i2c_rcar_platform_data *pdata = dev_get_platdata(&pdev->dev);
	struct rcar_i2c_priv *priv;
	struct i2c_adapter *adap;
	struct resource *res;
	struct device *dev = &pdev->dev;
	u32 bus_speed;
	int irq, ret;

	priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL);
	if (!priv) {
		dev_err(dev, "no mem for private data\n");
		return -ENOMEM;
	}

	priv->clk = devm_clk_get(dev, NULL);
	if (IS_ERR(priv->clk)) {
		dev_err(dev, "cannot get clock\n");
		return PTR_ERR(priv->clk);
	}

	bus_speed = 100000; /* default 100 kHz */
	ret = of_property_read_u32(dev->of_node, "clock-frequency", &bus_speed);
	if (ret < 0 && pdata && pdata->bus_speed)
		bus_speed = pdata->bus_speed;

	if (pdev->dev.of_node)
		priv->devtype = (long)of_match_device(rcar_i2c_dt_ids,
						      dev)->data;
	else
		priv->devtype = platform_get_device_id(pdev)->driver_data;

	ret = rcar_i2c_clock_calculate(priv, bus_speed, dev);
	if (ret < 0)
		return ret;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	priv->io = devm_ioremap_resource(dev, res);
	if (IS_ERR(priv->io))
		return PTR_ERR(priv->io);

	irq = platform_get_irq(pdev, 0);
	init_waitqueue_head(&priv->wait);
	spin_lock_init(&priv->lock);

	adap			= &priv->adap;
	adap->nr		= pdev->id;
	adap->algo		= &rcar_i2c_algo;
	adap->class		= I2C_CLASS_HWMON | I2C_CLASS_SPD | I2C_CLASS_DEPRECATED;
	adap->retries		= 3;
	adap->dev.parent	= dev;
	adap->dev.of_node	= dev->of_node;
	i2c_set_adapdata(adap, priv);
	strlcpy(adap->name, pdev->name, sizeof(adap->name));

	ret = devm_request_irq(dev, irq, rcar_i2c_irq, 0,
			       dev_name(dev), priv);
	if (ret < 0) {
		dev_err(dev, "cannot get irq %d\n", irq);
		return ret;
	}

	ret = i2c_add_numbered_adapter(adap);
	if (ret < 0) {
		dev_err(dev, "reg adap failed: %d\n", ret);
		return ret;
	}

	pm_runtime_enable(dev);
	platform_set_drvdata(pdev, priv);

	dev_info(dev, "probed\n");

	return 0;
}

static int rcar_i2c_remove(struct platform_device *pdev)
{
	struct rcar_i2c_priv *priv = platform_get_drvdata(pdev);
	struct device *dev = &pdev->dev;

	i2c_del_adapter(&priv->adap);
	pm_runtime_disable(dev);

	return 0;
}

static struct platform_device_id rcar_i2c_id_table[] = {
	{ "i2c-rcar",		I2C_RCAR_GEN1 },
	{ "i2c-rcar_gen1",	I2C_RCAR_GEN1 },
	{ "i2c-rcar_gen2",	I2C_RCAR_GEN2 },
	{},
};
MODULE_DEVICE_TABLE(platform, rcar_i2c_id_table);

static struct platform_driver rcar_i2c_driver = {
	.driver	= {
		.name	= "i2c-rcar",
		.owner	= THIS_MODULE,
		.of_match_table = rcar_i2c_dt_ids,
	},
	.probe		= rcar_i2c_probe,
	.remove		= rcar_i2c_remove,
	.id_table	= rcar_i2c_id_table,
};

module_platform_driver(rcar_i2c_driver);

MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Renesas R-Car I2C bus driver");
MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>");
Commit	Line	Data
6ccbe607 KM	1	/*
	2	* drivers/i2c/busses/i2c-rcar.c
	3	*
	4	* Copyright (C) 2012 Renesas Solutions Corp.
	5	* Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
	6	*
	7	* This file is based on the drivers/i2c/busses/i2c-sh7760.c
	8	* (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com>
	9	*
	10	* This file used out-of-tree driver i2c-rcar.c
	11	* Copyright (C) 2011-2012 Renesas Electronics Corporation
	12	*
	13	* This program is free software; you can redistribute it and/or modify
	14	* it under the terms of the GNU General Public License as published by
	15	* the Free Software Foundation; either version 2 of the License
	16	*
	17	* This program is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	* GNU General Public License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; if not, write to the Free Software
	24	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	25	*/
	26	#include <linux/clk.h>
	27	#include <linux/delay.h>
	28	#include <linux/err.h>
6ccbe607 KM	29	#include <linux/interrupt.h>
	30	#include <linux/io.h>
	31	#include <linux/i2c.h>
	32	#include <linux/i2c/i2c-rcar.h>
	33	#include <linux/kernel.h>
	34	#include <linux/module.h>
7679c0e1	35	#include <linux/of_device.h>
6ccbe607 KM	36	#include <linux/platform_device.h>
	37	#include <linux/pm_runtime.h>
	38	#include <linux/slab.h>
	39	#include <linux/spinlock.h>
	40
	41	/* register offsets */
	42	#define ICSCR 0x00 /* slave ctrl */
	43	#define ICMCR 0x04 /* master ctrl */
	44	#define ICSSR 0x08 /* slave status */
	45	#define ICMSR 0x0C /* master status */
	46	#define ICSIER 0x10 /* slave irq enable */
	47	#define ICMIER 0x14 /* master irq enable */
	48	#define ICCCR 0x18 /* clock dividers */
	49	#define ICSAR 0x1C /* slave address */
	50	#define ICMAR 0x20 /* master address */
	51	#define ICRXTX 0x24 /* data port */
	52
	53	/* ICMCR */
	54	#define MDBS (1 << 7) /* non-fifo mode switch */
	55	#define FSCL (1 << 6) /* override SCL pin */
	56	#define FSDA (1 << 5) /* override SDA pin */
	57	#define OBPC (1 << 4) /* override pins */
	58	#define MIE (1 << 3) /* master if enable */
	59	#define TSBE (1 << 2)
	60	#define FSB (1 << 1) /* force stop bit */
	61	#define ESG (1 << 0) /* en startbit gen */
	62
	63	/* ICMSR */
	64	#define MNR (1 << 6) /* nack received */
	65	#define MAL (1 << 5) /* arbitration lost */
	66	#define MST (1 << 4) /* sent a stop */
	67	#define MDE (1 << 3)
	68	#define MDT (1 << 2)
	69	#define MDR (1 << 1)
	70	#define MAT (1 << 0) /* slave addr xfer done */
	71
	72	/* ICMIE */
	73	#define MNRE (1 << 6) /* nack irq en */
	74	#define MALE (1 << 5) /* arblos irq en */
	75	#define MSTE (1 << 4) /* stop irq en */
	76	#define MDEE (1 << 3)
	77	#define MDTE (1 << 2)
	78	#define MDRE (1 << 1)
	79	#define MATE (1 << 0) /* address sent irq en */
	80
	81
4f443a8a WS	82	#define RCAR_BUS_PHASE_START (MDBS \| MIE \| ESG)
	83	#define RCAR_BUS_PHASE_DATA (MDBS \| MIE)
	84	#define RCAR_BUS_PHASE_STOP (MDBS \| MIE \| FSB)
6ccbe607	85
f2382249 WS	86	#define RCAR_IRQ_SEND (MNRE \| MALE \| MSTE \| MATE \| MDEE)
	87	#define RCAR_IRQ_RECV (MNRE \| MALE \| MSTE \| MATE \| MDRE)
	88	#define RCAR_IRQ_STOP (MSTE)
6ccbe607 KM	89
	90	/*
	91	* flags
	92	*/
	93	#define ID_LAST_MSG (1 << 0)
	94	#define ID_IOERROR (1 << 1)
	95	#define ID_DONE (1 << 2)
	96	#define ID_ARBLOST (1 << 3)
	97	#define ID_NACK (1 << 4)
	98
b720423a	99	enum rcar_i2c_type {
043a3f11 KM	100	I2C_RCAR_GEN1,
043a3f11 KM	101	I2C_RCAR_GEN2,
b720423a NVD	102	};
b720423a NVD	103
6ccbe607 KM	104	struct rcar_i2c_priv {
	105	void __iomem *io;
	106	struct i2c_adapter adap;
	107	struct i2c_msg *msg;
bc8120f1	108	struct clk *clk;
6ccbe607 KM	109
	110	spinlock_t lock;
	111	wait_queue_head_t wait;
	112
	113	int pos;
6ccbe607 KM	114	u32 icccr;
6ccbe607 KM	115	u32 flags;
b720423a	116	enum rcar_i2c_type devtype;
6ccbe607 KM	117	};
	118
	119	#define rcar_i2c_priv_to_dev(p) ((p)->adap.dev.parent)
	120	#define rcar_i2c_is_recv(p) ((p)->msg->flags & I2C_M_RD)
	121
	122	#define rcar_i2c_flags_set(p, f) ((p)->flags \|= (f))
	123	#define rcar_i2c_flags_has(p, f) ((p)->flags & (f))
	124
	125	#define LOOP_TIMEOUT 1024
	126
	127	/*
	128	* basic functions
	129	*/
	130	static void rcar_i2c_write(struct rcar_i2c_priv *priv, int reg, u32 val)
	131	{
	132	writel(val, priv->io + reg);
	133	}
	134
	135	static u32 rcar_i2c_read(struct rcar_i2c_priv *priv, int reg)
	136	{
	137	return readl(priv->io + reg);
	138	}
	139
	140	static void rcar_i2c_init(struct rcar_i2c_priv *priv)
	141	{
	142	/*
	143	* reset slave mode.
	144	* slave mode is not used on this driver
	145	*/
	146	rcar_i2c_write(priv, ICSIER, 0);
	147	rcar_i2c_write(priv, ICSAR, 0);
	148	rcar_i2c_write(priv, ICSCR, 0);
	149	rcar_i2c_write(priv, ICSSR, 0);
	150
	151	/* reset master mode */
	152	rcar_i2c_write(priv, ICMIER, 0);
	153	rcar_i2c_write(priv, ICMCR, 0);
	154	rcar_i2c_write(priv, ICMSR, 0);
	155	rcar_i2c_write(priv, ICMAR, 0);
	156	}
	157
6ccbe607 KM	158	static void rcar_i2c_set_addr(struct rcar_i2c_priv *priv, u32 recv)
	159	{
	160	rcar_i2c_write(priv, ICMAR, (priv->msg->addr << 1) \| recv);
	161	}
	162
	163	/*
	164	* bus control functions
	165	*/
	166	static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv)
	167	{
	168	int i;
	169
	170	for (i = 0; i < LOOP_TIMEOUT; i++) {
	171	/* make sure that bus is not busy */
	172	if (!(rcar_i2c_read(priv, ICMCR) & FSDA))
	173	return 0;
	174	udelay(1);
	175	}
	176
	177	return -EBUSY;
	178	}
	179
6ccbe607 KM	180	/*
	181	* clock function
	182	*/
	183	static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv,
	184	u32 bus_speed,
	185	struct device *dev)
	186	{
6ccbe607 KM	187	u32 scgd, cdf;
	188	u32 round, ick;
	189	u32 scl;
b720423a	190	u32 cdf_width;
8d049403	191	unsigned long rate;
6ccbe607	192
b720423a	193	switch (priv->devtype) {
043a3f11	194	case I2C_RCAR_GEN1:
b720423a NVD	195	cdf_width = 2;
b720423a NVD	196	break;
043a3f11	197	case I2C_RCAR_GEN2:
b720423a NVD	198	cdf_width = 3;
	199	break;
	200	default:
	201	dev_err(dev, "device type error\n");
	202	return -EIO;
	203	}
	204
6ccbe607 KM	205	/*
	206	* calculate SCL clock
	207	* see
	208	* ICCCR
	209	*
	210	* ick = clkp / (1 + CDF)
	211	* SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
	212	*
	213	* ick : I2C internal clock < 20 MHz
	214	* ticf : I2C SCL falling time = 35 ns here
	215	* tr : I2C SCL rising time = 200 ns here
	216	* intd : LSI internal delay = 50 ns here
	217	* clkp : peripheral_clk
	218	* F[] : integer up-valuation
	219	*/
bc8120f1	220	rate = clk_get_rate(priv->clk);
8d049403 GL	221	cdf = rate / 20000000;
	222	if (cdf >= 1 << cdf_width) {
	223	dev_err(dev, "Input clock %lu too high\n", rate);
	224	return -EIO;
6ccbe607	225	}
8d049403	226	ick = rate / (cdf + 1);
6ccbe607	227
6ccbe607 KM	228	/*
	229	* it is impossible to calculate large scale
	230	* number on u32. separate it
	231	*
	232	* F[(ticf + tr + intd) * ick]
	233	* = F[(35 + 200 + 50)ns * ick]
	234	* = F[285 * ick / 1000000000]
	235	* = F[(ick / 1000000) * 285 / 1000]
	236	*/
	237	round = (ick + 500000) / 1000000 * 285;
	238	round = (round + 500) / 1000;
	239
	240	/*
	241	* SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
	242	*
	243	* Calculation result (= SCL) should be less than
	244	* bus_speed for hardware safety
8d049403 GL	245	*
	246	* We could use something along the lines of
	247	* div = ick / (bus_speed + 1) + 1;
	248	* scgd = (div - 20 - round + 7) / 8;
	249	* scl = ick / (20 + (scgd * 8) + round);
	250	* (not fully verified) but that would get pretty involved
6ccbe607 KM	251	*/
	252	for (scgd = 0; scgd < 0x40; scgd++) {
	253	scl = ick / (20 + (scgd * 8) + round);
	254	if (scl <= bus_speed)
	255	goto scgd_find;
	256	}
	257	dev_err(dev, "it is impossible to calculate best SCL\n");
	258	return -EIO;
	259
	260	scgd_find:
	261	dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n",
bc8120f1	262	scl, bus_speed, clk_get_rate(priv->clk), round, cdf, scgd);
6ccbe607 KM	263
	264	/*
	265	* keep icccr value
	266	*/
14d32f17	267	priv->icccr = scgd << cdf_width \| cdf;
6ccbe607 KM	268
	269	return 0;
	270	}
	271
6ccbe607 KM	272	/*
	273	* status functions
	274	*/
6ccbe607 KM	275
	276	#define rcar_i2c_status_clear(priv) rcar_i2c_status_bit_clear(priv, 0xffffffff)
	277	static void rcar_i2c_status_bit_clear(struct rcar_i2c_priv *priv, u32 bit)
	278	{
	279	rcar_i2c_write(priv, ICMSR, ~bit);
	280	}
	281
	282	/*
	283	* recv/send functions
	284	*/
	285	static int rcar_i2c_recv(struct rcar_i2c_priv *priv)
	286	{
	287	rcar_i2c_set_addr(priv, 1);
	288	rcar_i2c_status_clear(priv);
4f443a8a	289	rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
f2382249	290	rcar_i2c_write(priv, ICMIER, RCAR_IRQ_RECV);
6ccbe607 KM	291
	292	return 0;
	293	}
	294
	295	static int rcar_i2c_send(struct rcar_i2c_priv *priv)
	296	{
6ccbe607 KM	297	rcar_i2c_set_addr(priv, 0);
6ccbe607 KM	298	rcar_i2c_status_clear(priv);
4f443a8a	299	rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
f2382249	300	rcar_i2c_write(priv, ICMIER, RCAR_IRQ_SEND);
6ccbe607 KM	301
	302	return 0;
	303	}
	304
	305	#define rcar_i2c_send_restart(priv) rcar_i2c_status_bit_clear(priv, (MAT \| MDE))
	306	#define rcar_i2c_recv_restart(priv) rcar_i2c_status_bit_clear(priv, (MAT \| MDR))
	307
	308	/*
	309	* interrupt functions
	310	*/
	311	static int rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr)
	312	{
	313	struct i2c_msg *msg = priv->msg;
	314
	315	/*
	316	* FIXME
	317	* sometimes, unknown interrupt happened.
	318	* Do nothing
	319	*/
	320	if (!(msr & MDE))
	321	return 0;
	322
	323	/*
	324	* If address transfer phase finished,
	325	* goto data phase.
	326	*/
	327	if (msr & MAT)
4f443a8a	328	rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA);
6ccbe607 KM	329
	330	if (priv->pos < msg->len) {
	331	/*
	332	* Prepare next data to ICRXTX register.
	333	* This data will go to _SHIFT_ register.
	334	*
	335	* *
	336	* [ICRXTX] -> [SHIFT] -> [I2C bus]
	337	*/
	338	rcar_i2c_write(priv, ICRXTX, msg->buf[priv->pos]);
	339	priv->pos++;
	340
	341	} else {
	342	/*
	343	* The last data was pushed to ICRXTX on _PREV_ empty irq.
	344	* It is on _SHIFT_ register, and will sent to I2C bus.
	345	*
	346	* *
	347	* [ICRXTX] -> [SHIFT] -> [I2C bus]
	348	*/
	349
	350	if (priv->flags & ID_LAST_MSG)
	351	/*
	352	* If current msg is the _LAST_ msg,
	353	* prepare stop condition here.
	354	* ID_DONE will be set on STOP irq.
	355	*/
4f443a8a	356	rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
6ccbe607 KM	357	else
	358	/*
	359	* If current msg is _NOT_ last msg,
	360	* it doesn't call stop phase.
	361	* thus, there is no STOP irq.
	362	* return ID_DONE here.
	363	*/
	364	return ID_DONE;
	365	}
	366
	367	rcar_i2c_send_restart(priv);
	368
	369	return 0;
	370	}
	371
	372	static int rcar_i2c_irq_recv(struct rcar_i2c_priv *priv, u32 msr)
	373	{
	374	struct i2c_msg *msg = priv->msg;
	375
	376	/*
	377	* FIXME
	378	* sometimes, unknown interrupt happened.
	379	* Do nothing
	380	*/
	381	if (!(msr & MDR))
	382	return 0;
	383
	384	if (msr & MAT) {
	385	/*
	386	* Address transfer phase finished,
	387	* but, there is no data at this point.
	388	* Do nothing.
	389	*/
	390	} else if (priv->pos < msg->len) {
	391	/*
	392	* get received data
	393	*/
	394	msg->buf[priv->pos] = rcar_i2c_read(priv, ICRXTX);
	395	priv->pos++;
	396	}
	397
	398	/*
	399	* If next received data is the _LAST_,
	400	* go to STOP phase,
	401	* otherwise, go to DATA phase.
	402	*/
	403	if (priv->pos + 1 >= msg->len)
4f443a8a	404	rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
6ccbe607	405	else
4f443a8a	406	rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA);
6ccbe607 KM	407
	408	rcar_i2c_recv_restart(priv);
	409
	410	return 0;
	411	}
	412
	413	static irqreturn_t rcar_i2c_irq(int irq, void *ptr)
	414	{
	415	struct rcar_i2c_priv *priv = ptr;
	416	struct device *dev = rcar_i2c_priv_to_dev(priv);
	417	u32 msr;
	418
	419	/-------------- spin lock -----------------/
	420	spin_lock(&priv->lock);
	421
1c176d53	422	msr = rcar_i2c_read(priv, ICMSR);
6ccbe607 KM	423
	424	/*
	425	* Arbitration lost
	426	*/
	427	if (msr & MAL) {
	428	/*
	429	* CAUTION
	430	*
	431	* When arbitration lost, device become _slave_ mode.
	432	*/
	433	dev_dbg(dev, "Arbitration Lost\n");
	434	rcar_i2c_flags_set(priv, (ID_DONE \| ID_ARBLOST));
	435	goto out;
	436	}
	437
	438	/*
	439	* Stop
	440	*/
	441	if (msr & MST) {
	442	dev_dbg(dev, "Stop\n");
	443	rcar_i2c_flags_set(priv, ID_DONE);
	444	goto out;
	445	}
	446
	447	/*
	448	* Nack
	449	*/
	450	if (msr & MNR) {
	451	dev_dbg(dev, "Nack\n");
	452
	453	/* go to stop phase */
4f443a8a	454	rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
f2382249	455	rcar_i2c_write(priv, ICMIER, RCAR_IRQ_STOP);
6ccbe607 KM	456	rcar_i2c_flags_set(priv, ID_NACK);
	457	goto out;
	458	}
	459
	460	/*
	461	* recv/send
	462	*/
	463	if (rcar_i2c_is_recv(priv))
	464	rcar_i2c_flags_set(priv, rcar_i2c_irq_recv(priv, msr));
	465	else
	466	rcar_i2c_flags_set(priv, rcar_i2c_irq_send(priv, msr));
	467
	468	out:
	469	if (rcar_i2c_flags_has(priv, ID_DONE)) {
f2382249	470	rcar_i2c_write(priv, ICMIER, 0);
6ccbe607 KM	471	rcar_i2c_status_clear(priv);
	472	wake_up(&priv->wait);
	473	}
	474
	475	spin_unlock(&priv->lock);
	476	/-------------- spin unlock -----------------/
	477
	478	return IRQ_HANDLED;
	479	}
	480
	481	static int rcar_i2c_master_xfer(struct i2c_adapter *adap,
	482	struct i2c_msg *msgs,
	483	int num)
	484	{
	485	struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
	486	struct device *dev = rcar_i2c_priv_to_dev(priv);
	487	unsigned long flags;
	488	int i, ret, timeout;
	489
	490	pm_runtime_get_sync(dev);
	491
	492	/-------------- spin lock -----------------/
	493	spin_lock_irqsave(&priv->lock, flags);
	494
	495	rcar_i2c_init(priv);
1c176d53 WS	496	/* start clock */
1c176d53 WS	497	rcar_i2c_write(priv, ICCCR, priv->icccr);
6ccbe607 KM	498
	499	spin_unlock_irqrestore(&priv->lock, flags);
	500	/-------------- spin unlock -----------------/
	501
3f7de22e WS	502	ret = rcar_i2c_bus_barrier(priv);
	503	if (ret < 0)
	504	goto out;
	505
6ccbe607	506	for (i = 0; i < num; i++) {
d7653964 WS	507	/* This HW can't send STOP after address phase */
	508	if (msgs[i].len == 0) {
	509	ret = -EOPNOTSUPP;
	510	break;
	511	}
	512
6ccbe607 KM	513	/-------------- spin lock -----------------/
	514	spin_lock_irqsave(&priv->lock, flags);
	515
	516	/* init each data */
	517	priv->msg = &msgs[i];
	518	priv->pos = 0;
	519	priv->flags = 0;
	520	if (priv->msg == &msgs[num - 1])
	521	rcar_i2c_flags_set(priv, ID_LAST_MSG);
	522
	523	/* start send/recv */
	524	if (rcar_i2c_is_recv(priv))
	525	ret = rcar_i2c_recv(priv);
	526	else
	527	ret = rcar_i2c_send(priv);
	528
	529	spin_unlock_irqrestore(&priv->lock, flags);
	530	/-------------- spin unlock -----------------/
	531
	532	if (ret < 0)
	533	break;
	534
	535	/*
	536	* wait result
	537	*/
	538	timeout = wait_event_timeout(priv->wait,
	539	rcar_i2c_flags_has(priv, ID_DONE),
	540	5 * HZ);
	541	if (!timeout) {
	542	ret = -ETIMEDOUT;
	543	break;
	544	}
	545
	546	/*
	547	* error handling
	548	*/
	549	if (rcar_i2c_flags_has(priv, ID_NACK)) {
6ff4b105	550	ret = -ENXIO;
6ccbe607 KM	551	break;
	552	}
	553
	554	if (rcar_i2c_flags_has(priv, ID_ARBLOST)) {
	555	ret = -EAGAIN;
	556	break;
	557	}
	558
	559	if (rcar_i2c_flags_has(priv, ID_IOERROR)) {
	560	ret = -EIO;
	561	break;
	562	}
	563
	564	ret = i + 1; /* The number of transfer */
	565	}
3f7de22e	566	out:
6ccbe607 KM	567	pm_runtime_put(dev);
6ccbe607 KM	568
6ff4b105	569	if (ret < 0 && ret != -ENXIO)
6ccbe607 KM	570	dev_err(dev, "error %d : %x\n", ret, priv->flags);
	571
	572	return ret;
	573	}
	574
	575	static u32 rcar_i2c_func(struct i2c_adapter *adap)
	576	{
d7653964 WS	577	/* This HW can't do SMBUS_QUICK and NOSTART */
d7653964 WS	578	return I2C_FUNC_I2C \| (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
6ccbe607 KM	579	}
	580
	581	static const struct i2c_algorithm rcar_i2c_algo = {
	582	.master_xfer = rcar_i2c_master_xfer,
	583	.functionality = rcar_i2c_func,
	584	};
	585
7679c0e1	586	static const struct of_device_id rcar_i2c_dt_ids[] = {
043a3f11 KM	587	{ .compatible = "renesas,i2c-rcar", .data = (void *)I2C_RCAR_GEN1 },
	588	{ .compatible = "renesas,i2c-r8a7778", .data = (void *)I2C_RCAR_GEN1 },
	589	{ .compatible = "renesas,i2c-r8a7779", .data = (void *)I2C_RCAR_GEN1 },
	590	{ .compatible = "renesas,i2c-r8a7790", .data = (void *)I2C_RCAR_GEN2 },
e8936455	591	{ .compatible = "renesas,i2c-r8a7791", .data = (void *)I2C_RCAR_GEN2 },
819a3951 WS	592	{ .compatible = "renesas,i2c-r8a7792", .data = (void *)I2C_RCAR_GEN2 },
	593	{ .compatible = "renesas,i2c-r8a7793", .data = (void *)I2C_RCAR_GEN2 },
	594	{ .compatible = "renesas,i2c-r8a7794", .data = (void *)I2C_RCAR_GEN2 },
7679c0e1 GL	595	{},
	596	};
	597	MODULE_DEVICE_TABLE(of, rcar_i2c_dt_ids);
	598
0b255e92	599	static int rcar_i2c_probe(struct platform_device *pdev)
6ccbe607	600	{
6d4028c6	601	struct i2c_rcar_platform_data *pdata = dev_get_platdata(&pdev->dev);
6ccbe607 KM	602	struct rcar_i2c_priv *priv;
	603	struct i2c_adapter *adap;
	604	struct resource *res;
	605	struct device *dev = &pdev->dev;
	606	u32 bus_speed;
93e953d3	607	int irq, ret;
6ccbe607	608
6ccbe607 KM	609	priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL);
	610	if (!priv) {
	611	dev_err(dev, "no mem for private data\n");
	612	return -ENOMEM;
	613	}
	614
bc8120f1 BD	615	priv->clk = devm_clk_get(dev, NULL);
	616	if (IS_ERR(priv->clk)) {
	617	dev_err(dev, "cannot get clock\n");
	618	return PTR_ERR(priv->clk);
	619	}
	620
6ccbe607	621	bus_speed = 100000; /* default 100 kHz */
7679c0e1 GL	622	ret = of_property_read_u32(dev->of_node, "clock-frequency", &bus_speed);
7679c0e1 GL	623	if (ret < 0 && pdata && pdata->bus_speed)
6ccbe607	624	bus_speed = pdata->bus_speed;
b720423a	625
7679c0e1 GL	626	if (pdev->dev.of_node)
	627	priv->devtype = (long)of_match_device(rcar_i2c_dt_ids,
	628	dev)->data;
	629	else
	630	priv->devtype = platform_get_device_id(pdev)->driver_data;
b720423a	631
6ccbe607 KM	632	ret = rcar_i2c_clock_calculate(priv, bus_speed, dev);
	633	if (ret < 0)
	634	return ret;
	635
3cc2d009	636	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
84dbf809 TR	637	priv->io = devm_ioremap_resource(dev, res);
	638	if (IS_ERR(priv->io))
	639	return PTR_ERR(priv->io);
6ccbe607	640
93e953d3	641	irq = platform_get_irq(pdev, 0);
6ccbe607 KM	642	init_waitqueue_head(&priv->wait);
	643	spin_lock_init(&priv->lock);
	644
	645	adap = &priv->adap;
	646	adap->nr = pdev->id;
	647	adap->algo = &rcar_i2c_algo;
96c4b6bb	648	adap->class = I2C_CLASS_HWMON \| I2C_CLASS_SPD \| I2C_CLASS_DEPRECATED;
6ccbe607 KM	649	adap->retries = 3;
6ccbe607 KM	650	adap->dev.parent = dev;
7679c0e1	651	adap->dev.of_node = dev->of_node;
6ccbe607 KM	652	i2c_set_adapdata(adap, priv);
	653	strlcpy(adap->name, pdev->name, sizeof(adap->name));
	654
93e953d3	655	ret = devm_request_irq(dev, irq, rcar_i2c_irq, 0,
6ccbe607 KM	656	dev_name(dev), priv);
6ccbe607 KM	657	if (ret < 0) {
93e953d3	658	dev_err(dev, "cannot get irq %d\n", irq);
6ccbe607 KM	659	return ret;
	660	}
	661
	662	ret = i2c_add_numbered_adapter(adap);
	663	if (ret < 0) {
	664	dev_err(dev, "reg adap failed: %d\n", ret);
	665	return ret;
	666	}
	667
	668	pm_runtime_enable(dev);
	669	platform_set_drvdata(pdev, priv);
	670
	671	dev_info(dev, "probed\n");
	672
	673	return 0;
	674	}
	675
0b255e92	676	static int rcar_i2c_remove(struct platform_device *pdev)
6ccbe607 KM	677	{
	678	struct rcar_i2c_priv *priv = platform_get_drvdata(pdev);
	679	struct device *dev = &pdev->dev;
	680
	681	i2c_del_adapter(&priv->adap);
	682	pm_runtime_disable(dev);
	683
	684	return 0;
	685	}
	686
b720423a	687	static struct platform_device_id rcar_i2c_id_table[] = {
043a3f11 KM	688	{ "i2c-rcar", I2C_RCAR_GEN1 },
	689	{ "i2c-rcar_gen1", I2C_RCAR_GEN1 },
	690	{ "i2c-rcar_gen2", I2C_RCAR_GEN2 },
b720423a NVD	691	{},
	692	};
	693	MODULE_DEVICE_TABLE(platform, rcar_i2c_id_table);
	694
45fd5e4a	695	static struct platform_driver rcar_i2c_driver = {
6ccbe607 KM	696	.driver = {
	697	.name = "i2c-rcar",
	698	.owner = THIS_MODULE,
7679c0e1	699	.of_match_table = rcar_i2c_dt_ids,
6ccbe607 KM	700	},
6ccbe607 KM	701	.probe = rcar_i2c_probe,
0b255e92	702	.remove = rcar_i2c_remove,
b720423a	703	.id_table = rcar_i2c_id_table,
6ccbe607 KM	704	};
6ccbe607 KM	705
45fd5e4a	706	module_platform_driver(rcar_i2c_driver);
6ccbe607 KM	707
	708	MODULE_LICENSE("GPL");
	709	MODULE_DESCRIPTION("Renesas R-Car I2C bus driver");
	710	MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>");