Commit | Line | Data |
---|---|---|
6ccbe607 | 1 | /* |
3d99beab | 2 | * Driver for the Renesas RCar I2C unit |
6ccbe607 | 3 | * |
3d99beab WS |
4 | * Copyright (C) 2014 Wolfram Sang <wsa@sang-engineering.com> |
5 | * | |
6 | * Copyright (C) 2012-14 Renesas Solutions Corp. | |
6ccbe607 KM |
7 | * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> |
8 | * | |
9 | * This file is based on the drivers/i2c/busses/i2c-sh7760.c | |
10 | * (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com> | |
11 | * | |
12 | * This file used out-of-tree driver i2c-rcar.c | |
13 | * Copyright (C) 2011-2012 Renesas Electronics Corporation | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or modify | |
16 | * it under the terms of the GNU General Public License as published by | |
3d99beab | 17 | * the Free Software Foundation; version 2 of the License. |
6ccbe607 KM |
18 | * |
19 | * This program is distributed in the hope that it will be useful, | |
20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
22 | * GNU General Public License for more details. | |
6ccbe607 KM |
23 | */ |
24 | #include <linux/clk.h> | |
25 | #include <linux/delay.h> | |
26 | #include <linux/err.h> | |
6ccbe607 KM |
27 | #include <linux/interrupt.h> |
28 | #include <linux/io.h> | |
29 | #include <linux/i2c.h> | |
6ccbe607 KM |
30 | #include <linux/kernel.h> |
31 | #include <linux/module.h> | |
7679c0e1 | 32 | #include <linux/of_device.h> |
6ccbe607 KM |
33 | #include <linux/platform_device.h> |
34 | #include <linux/pm_runtime.h> | |
35 | #include <linux/slab.h> | |
6ccbe607 KM |
36 | |
37 | /* register offsets */ | |
38 | #define ICSCR 0x00 /* slave ctrl */ | |
39 | #define ICMCR 0x04 /* master ctrl */ | |
40 | #define ICSSR 0x08 /* slave status */ | |
41 | #define ICMSR 0x0C /* master status */ | |
42 | #define ICSIER 0x10 /* slave irq enable */ | |
43 | #define ICMIER 0x14 /* master irq enable */ | |
44 | #define ICCCR 0x18 /* clock dividers */ | |
45 | #define ICSAR 0x1C /* slave address */ | |
46 | #define ICMAR 0x20 /* master address */ | |
47 | #define ICRXTX 0x24 /* data port */ | |
48 | ||
de20d185 WS |
49 | /* ICSCR */ |
50 | #define SDBS (1 << 3) /* slave data buffer select */ | |
51 | #define SIE (1 << 2) /* slave interface enable */ | |
52 | #define GCAE (1 << 1) /* general call address enable */ | |
53 | #define FNA (1 << 0) /* forced non acknowledgment */ | |
54 | ||
6ccbe607 KM |
55 | /* ICMCR */ |
56 | #define MDBS (1 << 7) /* non-fifo mode switch */ | |
57 | #define FSCL (1 << 6) /* override SCL pin */ | |
58 | #define FSDA (1 << 5) /* override SDA pin */ | |
59 | #define OBPC (1 << 4) /* override pins */ | |
60 | #define MIE (1 << 3) /* master if enable */ | |
61 | #define TSBE (1 << 2) | |
62 | #define FSB (1 << 1) /* force stop bit */ | |
63 | #define ESG (1 << 0) /* en startbit gen */ | |
64 | ||
de20d185 WS |
65 | /* ICSSR (also for ICSIER) */ |
66 | #define GCAR (1 << 6) /* general call received */ | |
67 | #define STM (1 << 5) /* slave transmit mode */ | |
68 | #define SSR (1 << 4) /* stop received */ | |
69 | #define SDE (1 << 3) /* slave data empty */ | |
70 | #define SDT (1 << 2) /* slave data transmitted */ | |
71 | #define SDR (1 << 1) /* slave data received */ | |
72 | #define SAR (1 << 0) /* slave addr received */ | |
73 | ||
3e3aabac | 74 | /* ICMSR (also for ICMIE) */ |
6ccbe607 KM |
75 | #define MNR (1 << 6) /* nack received */ |
76 | #define MAL (1 << 5) /* arbitration lost */ | |
77 | #define MST (1 << 4) /* sent a stop */ | |
78 | #define MDE (1 << 3) | |
79 | #define MDT (1 << 2) | |
80 | #define MDR (1 << 1) | |
81 | #define MAT (1 << 0) /* slave addr xfer done */ | |
82 | ||
6ccbe607 | 83 | |
4f443a8a WS |
84 | #define RCAR_BUS_PHASE_START (MDBS | MIE | ESG) |
85 | #define RCAR_BUS_PHASE_DATA (MDBS | MIE) | |
86 | #define RCAR_BUS_PHASE_STOP (MDBS | MIE | FSB) | |
6ccbe607 | 87 | |
3e3aabac WS |
88 | #define RCAR_IRQ_SEND (MNR | MAL | MST | MAT | MDE) |
89 | #define RCAR_IRQ_RECV (MNR | MAL | MST | MAT | MDR) | |
90 | #define RCAR_IRQ_STOP (MST) | |
6ccbe607 | 91 | |
938916fb SS |
92 | #define RCAR_IRQ_ACK_SEND (~(MAT | MDE) & 0xFF) |
93 | #define RCAR_IRQ_ACK_RECV (~(MAT | MDR) & 0xFF) | |
3c95de67 | 94 | |
6ccbe607 | 95 | #define ID_LAST_MSG (1 << 0) |
6ccbe607 KM |
96 | #define ID_DONE (1 << 2) |
97 | #define ID_ARBLOST (1 << 3) | |
98 | #define ID_NACK (1 << 4) | |
99 | ||
b720423a | 100 | enum rcar_i2c_type { |
043a3f11 KM |
101 | I2C_RCAR_GEN1, |
102 | I2C_RCAR_GEN2, | |
e7db0d34 | 103 | I2C_RCAR_GEN3, |
b720423a NVD |
104 | }; |
105 | ||
6ccbe607 KM |
106 | struct rcar_i2c_priv { |
107 | void __iomem *io; | |
108 | struct i2c_adapter adap; | |
b9d0684c WS |
109 | struct i2c_msg *msg; |
110 | int msgs_left; | |
bc8120f1 | 111 | struct clk *clk; |
6ccbe607 | 112 | |
6ccbe607 KM |
113 | wait_queue_head_t wait; |
114 | ||
115 | int pos; | |
6ccbe607 KM |
116 | u32 icccr; |
117 | u32 flags; | |
51371cdc | 118 | enum rcar_i2c_type devtype; |
de20d185 | 119 | struct i2c_client *slave; |
6ccbe607 KM |
120 | }; |
121 | ||
122 | #define rcar_i2c_priv_to_dev(p) ((p)->adap.dev.parent) | |
123 | #define rcar_i2c_is_recv(p) ((p)->msg->flags & I2C_M_RD) | |
124 | ||
125 | #define rcar_i2c_flags_set(p, f) ((p)->flags |= (f)) | |
126 | #define rcar_i2c_flags_has(p, f) ((p)->flags & (f)) | |
127 | ||
128 | #define LOOP_TIMEOUT 1024 | |
129 | ||
51371cdc | 130 | |
6ccbe607 KM |
131 | static void rcar_i2c_write(struct rcar_i2c_priv *priv, int reg, u32 val) |
132 | { | |
133 | writel(val, priv->io + reg); | |
134 | } | |
135 | ||
136 | static u32 rcar_i2c_read(struct rcar_i2c_priv *priv, int reg) | |
137 | { | |
138 | return readl(priv->io + reg); | |
139 | } | |
140 | ||
141 | static void rcar_i2c_init(struct rcar_i2c_priv *priv) | |
142 | { | |
6ccbe607 KM |
143 | /* reset master mode */ |
144 | rcar_i2c_write(priv, ICMIER, 0); | |
2c78cdc1 | 145 | rcar_i2c_write(priv, ICMCR, MDBS); |
6ccbe607 | 146 | rcar_i2c_write(priv, ICMSR, 0); |
2c78cdc1 WS |
147 | /* start clock */ |
148 | rcar_i2c_write(priv, ICCCR, priv->icccr); | |
6ccbe607 KM |
149 | } |
150 | ||
6ccbe607 KM |
151 | static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv) |
152 | { | |
153 | int i; | |
154 | ||
155 | for (i = 0; i < LOOP_TIMEOUT; i++) { | |
156 | /* make sure that bus is not busy */ | |
157 | if (!(rcar_i2c_read(priv, ICMCR) & FSDA)) | |
158 | return 0; | |
159 | udelay(1); | |
160 | } | |
161 | ||
162 | return -EBUSY; | |
163 | } | |
164 | ||
6ccbe607 KM |
165 | static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv, |
166 | u32 bus_speed, | |
167 | struct device *dev) | |
168 | { | |
6ccbe607 KM |
169 | u32 scgd, cdf; |
170 | u32 round, ick; | |
171 | u32 scl; | |
b720423a | 172 | u32 cdf_width; |
8d049403 | 173 | unsigned long rate; |
6ccbe607 | 174 | |
b720423a | 175 | switch (priv->devtype) { |
043a3f11 | 176 | case I2C_RCAR_GEN1: |
b720423a NVD |
177 | cdf_width = 2; |
178 | break; | |
043a3f11 | 179 | case I2C_RCAR_GEN2: |
e7db0d34 | 180 | case I2C_RCAR_GEN3: |
b720423a NVD |
181 | cdf_width = 3; |
182 | break; | |
183 | default: | |
184 | dev_err(dev, "device type error\n"); | |
185 | return -EIO; | |
186 | } | |
187 | ||
6ccbe607 KM |
188 | /* |
189 | * calculate SCL clock | |
190 | * see | |
191 | * ICCCR | |
192 | * | |
193 | * ick = clkp / (1 + CDF) | |
194 | * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick]) | |
195 | * | |
196 | * ick : I2C internal clock < 20 MHz | |
197 | * ticf : I2C SCL falling time = 35 ns here | |
198 | * tr : I2C SCL rising time = 200 ns here | |
199 | * intd : LSI internal delay = 50 ns here | |
200 | * clkp : peripheral_clk | |
201 | * F[] : integer up-valuation | |
202 | */ | |
bc8120f1 | 203 | rate = clk_get_rate(priv->clk); |
8d049403 | 204 | cdf = rate / 20000000; |
22762ccb | 205 | if (cdf >= 1U << cdf_width) { |
8d049403 GL |
206 | dev_err(dev, "Input clock %lu too high\n", rate); |
207 | return -EIO; | |
6ccbe607 | 208 | } |
8d049403 | 209 | ick = rate / (cdf + 1); |
6ccbe607 | 210 | |
6ccbe607 KM |
211 | /* |
212 | * it is impossible to calculate large scale | |
213 | * number on u32. separate it | |
214 | * | |
215 | * F[(ticf + tr + intd) * ick] | |
216 | * = F[(35 + 200 + 50)ns * ick] | |
217 | * = F[285 * ick / 1000000000] | |
218 | * = F[(ick / 1000000) * 285 / 1000] | |
219 | */ | |
220 | round = (ick + 500000) / 1000000 * 285; | |
221 | round = (round + 500) / 1000; | |
222 | ||
223 | /* | |
224 | * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick]) | |
225 | * | |
226 | * Calculation result (= SCL) should be less than | |
227 | * bus_speed for hardware safety | |
8d049403 GL |
228 | * |
229 | * We could use something along the lines of | |
230 | * div = ick / (bus_speed + 1) + 1; | |
231 | * scgd = (div - 20 - round + 7) / 8; | |
232 | * scl = ick / (20 + (scgd * 8) + round); | |
233 | * (not fully verified) but that would get pretty involved | |
6ccbe607 KM |
234 | */ |
235 | for (scgd = 0; scgd < 0x40; scgd++) { | |
236 | scl = ick / (20 + (scgd * 8) + round); | |
237 | if (scl <= bus_speed) | |
238 | goto scgd_find; | |
239 | } | |
240 | dev_err(dev, "it is impossible to calculate best SCL\n"); | |
241 | return -EIO; | |
242 | ||
243 | scgd_find: | |
244 | dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n", | |
bc8120f1 | 245 | scl, bus_speed, clk_get_rate(priv->clk), round, cdf, scgd); |
6ccbe607 KM |
246 | |
247 | /* | |
248 | * keep icccr value | |
249 | */ | |
14d32f17 | 250 | priv->icccr = scgd << cdf_width | cdf; |
6ccbe607 KM |
251 | |
252 | return 0; | |
253 | } | |
254 | ||
7c7117ff | 255 | static void rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv) |
6ccbe607 | 256 | { |
386babf8 | 257 | int read = !!rcar_i2c_is_recv(priv); |
6ccbe607 | 258 | |
b9d0684c WS |
259 | priv->pos = 0; |
260 | priv->flags = 0; | |
261 | if (priv->msgs_left == 1) | |
262 | rcar_i2c_flags_set(priv, ID_LAST_MSG); | |
263 | ||
386babf8 | 264 | rcar_i2c_write(priv, ICMAR, (priv->msg->addr << 1) | read); |
3c95de67 | 265 | rcar_i2c_write(priv, ICMSR, 0); |
4f443a8a | 266 | rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START); |
386babf8 | 267 | rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND); |
6ccbe607 KM |
268 | } |
269 | ||
6ccbe607 KM |
270 | /* |
271 | * interrupt functions | |
272 | */ | |
273 | static int rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr) | |
274 | { | |
275 | struct i2c_msg *msg = priv->msg; | |
276 | ||
277 | /* | |
278 | * FIXME | |
279 | * sometimes, unknown interrupt happened. | |
280 | * Do nothing | |
281 | */ | |
282 | if (!(msr & MDE)) | |
283 | return 0; | |
284 | ||
285 | /* | |
286 | * If address transfer phase finished, | |
287 | * goto data phase. | |
288 | */ | |
289 | if (msr & MAT) | |
4f443a8a | 290 | rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA); |
6ccbe607 KM |
291 | |
292 | if (priv->pos < msg->len) { | |
293 | /* | |
294 | * Prepare next data to ICRXTX register. | |
295 | * This data will go to _SHIFT_ register. | |
296 | * | |
297 | * * | |
298 | * [ICRXTX] -> [SHIFT] -> [I2C bus] | |
299 | */ | |
300 | rcar_i2c_write(priv, ICRXTX, msg->buf[priv->pos]); | |
301 | priv->pos++; | |
302 | ||
303 | } else { | |
304 | /* | |
305 | * The last data was pushed to ICRXTX on _PREV_ empty irq. | |
306 | * It is on _SHIFT_ register, and will sent to I2C bus. | |
307 | * | |
308 | * * | |
309 | * [ICRXTX] -> [SHIFT] -> [I2C bus] | |
310 | */ | |
311 | ||
312 | if (priv->flags & ID_LAST_MSG) | |
313 | /* | |
314 | * If current msg is the _LAST_ msg, | |
315 | * prepare stop condition here. | |
316 | * ID_DONE will be set on STOP irq. | |
317 | */ | |
4f443a8a | 318 | rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP); |
6ccbe607 KM |
319 | else |
320 | /* | |
321 | * If current msg is _NOT_ last msg, | |
322 | * it doesn't call stop phase. | |
323 | * thus, there is no STOP irq. | |
324 | * return ID_DONE here. | |
325 | */ | |
326 | return ID_DONE; | |
327 | } | |
328 | ||
3c95de67 | 329 | rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_SEND); |
6ccbe607 KM |
330 | |
331 | return 0; | |
332 | } | |
333 | ||
334 | static int rcar_i2c_irq_recv(struct rcar_i2c_priv *priv, u32 msr) | |
335 | { | |
336 | struct i2c_msg *msg = priv->msg; | |
337 | ||
338 | /* | |
339 | * FIXME | |
340 | * sometimes, unknown interrupt happened. | |
341 | * Do nothing | |
342 | */ | |
343 | if (!(msr & MDR)) | |
344 | return 0; | |
345 | ||
346 | if (msr & MAT) { | |
347 | /* | |
348 | * Address transfer phase finished, | |
349 | * but, there is no data at this point. | |
350 | * Do nothing. | |
351 | */ | |
352 | } else if (priv->pos < msg->len) { | |
353 | /* | |
354 | * get received data | |
355 | */ | |
356 | msg->buf[priv->pos] = rcar_i2c_read(priv, ICRXTX); | |
357 | priv->pos++; | |
358 | } | |
359 | ||
360 | /* | |
361 | * If next received data is the _LAST_, | |
362 | * go to STOP phase, | |
363 | * otherwise, go to DATA phase. | |
364 | */ | |
365 | if (priv->pos + 1 >= msg->len) | |
4f443a8a | 366 | rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP); |
6ccbe607 | 367 | else |
4f443a8a | 368 | rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA); |
6ccbe607 | 369 | |
3c95de67 | 370 | rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_RECV); |
6ccbe607 KM |
371 | |
372 | return 0; | |
373 | } | |
374 | ||
de20d185 WS |
375 | static bool rcar_i2c_slave_irq(struct rcar_i2c_priv *priv) |
376 | { | |
377 | u32 ssr_raw, ssr_filtered; | |
378 | u8 value; | |
379 | ||
380 | ssr_raw = rcar_i2c_read(priv, ICSSR) & 0xff; | |
381 | ssr_filtered = ssr_raw & rcar_i2c_read(priv, ICSIER); | |
382 | ||
383 | if (!ssr_filtered) | |
384 | return false; | |
385 | ||
386 | /* address detected */ | |
387 | if (ssr_filtered & SAR) { | |
388 | /* read or write request */ | |
389 | if (ssr_raw & STM) { | |
5b77d162 | 390 | i2c_slave_event(priv->slave, I2C_SLAVE_READ_REQUESTED, &value); |
de20d185 WS |
391 | rcar_i2c_write(priv, ICRXTX, value); |
392 | rcar_i2c_write(priv, ICSIER, SDE | SSR | SAR); | |
393 | } else { | |
5b77d162 | 394 | i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_REQUESTED, &value); |
de20d185 WS |
395 | rcar_i2c_read(priv, ICRXTX); /* dummy read */ |
396 | rcar_i2c_write(priv, ICSIER, SDR | SSR | SAR); | |
397 | } | |
398 | ||
399 | rcar_i2c_write(priv, ICSSR, ~SAR & 0xff); | |
400 | } | |
401 | ||
402 | /* master sent stop */ | |
403 | if (ssr_filtered & SSR) { | |
404 | i2c_slave_event(priv->slave, I2C_SLAVE_STOP, &value); | |
405 | rcar_i2c_write(priv, ICSIER, SAR | SSR); | |
406 | rcar_i2c_write(priv, ICSSR, ~SSR & 0xff); | |
407 | } | |
408 | ||
409 | /* master wants to write to us */ | |
410 | if (ssr_filtered & SDR) { | |
411 | int ret; | |
412 | ||
413 | value = rcar_i2c_read(priv, ICRXTX); | |
5b77d162 | 414 | ret = i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_RECEIVED, &value); |
de20d185 WS |
415 | /* Send NACK in case of error */ |
416 | rcar_i2c_write(priv, ICSCR, SIE | SDBS | (ret < 0 ? FNA : 0)); | |
de20d185 WS |
417 | rcar_i2c_write(priv, ICSSR, ~SDR & 0xff); |
418 | } | |
419 | ||
420 | /* master wants to read from us */ | |
421 | if (ssr_filtered & SDE) { | |
5b77d162 | 422 | i2c_slave_event(priv->slave, I2C_SLAVE_READ_PROCESSED, &value); |
de20d185 WS |
423 | rcar_i2c_write(priv, ICRXTX, value); |
424 | rcar_i2c_write(priv, ICSSR, ~SDE & 0xff); | |
425 | } | |
426 | ||
427 | return true; | |
428 | } | |
429 | ||
6ccbe607 KM |
430 | static irqreturn_t rcar_i2c_irq(int irq, void *ptr) |
431 | { | |
432 | struct rcar_i2c_priv *priv = ptr; | |
aa5beaf6 | 433 | irqreturn_t result = IRQ_HANDLED; |
6ccbe607 KM |
434 | u32 msr; |
435 | ||
de20d185 WS |
436 | if (rcar_i2c_slave_irq(priv)) |
437 | goto exit; | |
438 | ||
1c176d53 | 439 | msr = rcar_i2c_read(priv, ICMSR); |
6ccbe607 | 440 | |
dd318b0d SS |
441 | /* Only handle interrupts that are currently enabled */ |
442 | msr &= rcar_i2c_read(priv, ICMIER); | |
aa5beaf6 SS |
443 | if (!msr) { |
444 | result = IRQ_NONE; | |
445 | goto exit; | |
446 | } | |
dd318b0d | 447 | |
51371cdc | 448 | /* Arbitration lost */ |
6ccbe607 | 449 | if (msr & MAL) { |
6ccbe607 KM |
450 | rcar_i2c_flags_set(priv, (ID_DONE | ID_ARBLOST)); |
451 | goto out; | |
452 | } | |
453 | ||
51371cdc | 454 | /* Nack */ |
6ccbe607 | 455 | if (msr & MNR) { |
6ccbe607 | 456 | /* go to stop phase */ |
4f443a8a | 457 | rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP); |
f2382249 | 458 | rcar_i2c_write(priv, ICMIER, RCAR_IRQ_STOP); |
6ccbe607 KM |
459 | rcar_i2c_flags_set(priv, ID_NACK); |
460 | goto out; | |
461 | } | |
462 | ||
dd318b0d SS |
463 | /* Stop */ |
464 | if (msr & MST) { | |
465 | rcar_i2c_flags_set(priv, ID_DONE); | |
466 | goto out; | |
467 | } | |
468 | ||
6ccbe607 KM |
469 | if (rcar_i2c_is_recv(priv)) |
470 | rcar_i2c_flags_set(priv, rcar_i2c_irq_recv(priv, msr)); | |
471 | else | |
472 | rcar_i2c_flags_set(priv, rcar_i2c_irq_send(priv, msr)); | |
473 | ||
474 | out: | |
475 | if (rcar_i2c_flags_has(priv, ID_DONE)) { | |
f2382249 | 476 | rcar_i2c_write(priv, ICMIER, 0); |
3c95de67 | 477 | rcar_i2c_write(priv, ICMSR, 0); |
6ccbe607 KM |
478 | wake_up(&priv->wait); |
479 | } | |
480 | ||
aa5beaf6 | 481 | exit: |
aa5beaf6 | 482 | return result; |
6ccbe607 KM |
483 | } |
484 | ||
485 | static int rcar_i2c_master_xfer(struct i2c_adapter *adap, | |
486 | struct i2c_msg *msgs, | |
487 | int num) | |
488 | { | |
489 | struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); | |
490 | struct device *dev = rcar_i2c_priv_to_dev(priv); | |
b6763d0d | 491 | int i, ret; |
ff2316b8 | 492 | long time_left; |
6ccbe607 KM |
493 | |
494 | pm_runtime_get_sync(dev); | |
495 | ||
3f7de22e WS |
496 | ret = rcar_i2c_bus_barrier(priv); |
497 | if (ret < 0) | |
498 | goto out; | |
499 | ||
6ccbe607 | 500 | for (i = 0; i < num; i++) { |
d7653964 WS |
501 | /* This HW can't send STOP after address phase */ |
502 | if (msgs[i].len == 0) { | |
503 | ret = -EOPNOTSUPP; | |
504 | break; | |
505 | } | |
506 | ||
6ccbe607 | 507 | /* init each data */ |
b9d0684c WS |
508 | priv->msg = &msgs[i]; |
509 | priv->msgs_left = num - i; | |
6ccbe607 | 510 | |
7c7117ff | 511 | rcar_i2c_prepare_msg(priv); |
6ccbe607 | 512 | |
ff2316b8 | 513 | time_left = wait_event_timeout(priv->wait, |
6ccbe607 | 514 | rcar_i2c_flags_has(priv, ID_DONE), |
efd2c611 | 515 | adap->timeout); |
ff2316b8 WS |
516 | if (!time_left) { |
517 | rcar_i2c_init(priv); | |
6ccbe607 KM |
518 | ret = -ETIMEDOUT; |
519 | break; | |
520 | } | |
521 | ||
6ccbe607 | 522 | if (rcar_i2c_flags_has(priv, ID_NACK)) { |
6ff4b105 | 523 | ret = -ENXIO; |
6ccbe607 KM |
524 | break; |
525 | } | |
526 | ||
527 | if (rcar_i2c_flags_has(priv, ID_ARBLOST)) { | |
528 | ret = -EAGAIN; | |
529 | break; | |
530 | } | |
531 | ||
6ccbe607 KM |
532 | ret = i + 1; /* The number of transfer */ |
533 | } | |
3f7de22e | 534 | out: |
6ccbe607 KM |
535 | pm_runtime_put(dev); |
536 | ||
6ff4b105 | 537 | if (ret < 0 && ret != -ENXIO) |
6ccbe607 KM |
538 | dev_err(dev, "error %d : %x\n", ret, priv->flags); |
539 | ||
540 | return ret; | |
541 | } | |
542 | ||
de20d185 WS |
543 | static int rcar_reg_slave(struct i2c_client *slave) |
544 | { | |
545 | struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter); | |
546 | ||
547 | if (priv->slave) | |
548 | return -EBUSY; | |
549 | ||
550 | if (slave->flags & I2C_CLIENT_TEN) | |
551 | return -EAFNOSUPPORT; | |
552 | ||
553 | pm_runtime_forbid(rcar_i2c_priv_to_dev(priv)); | |
554 | ||
555 | priv->slave = slave; | |
556 | rcar_i2c_write(priv, ICSAR, slave->addr); | |
557 | rcar_i2c_write(priv, ICSSR, 0); | |
558 | rcar_i2c_write(priv, ICSIER, SAR | SSR); | |
559 | rcar_i2c_write(priv, ICSCR, SIE | SDBS); | |
560 | ||
561 | return 0; | |
562 | } | |
563 | ||
564 | static int rcar_unreg_slave(struct i2c_client *slave) | |
565 | { | |
566 | struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter); | |
567 | ||
568 | WARN_ON(!priv->slave); | |
569 | ||
570 | rcar_i2c_write(priv, ICSIER, 0); | |
571 | rcar_i2c_write(priv, ICSCR, 0); | |
572 | ||
573 | priv->slave = NULL; | |
574 | ||
575 | pm_runtime_allow(rcar_i2c_priv_to_dev(priv)); | |
576 | ||
577 | return 0; | |
578 | } | |
579 | ||
6ccbe607 KM |
580 | static u32 rcar_i2c_func(struct i2c_adapter *adap) |
581 | { | |
d7653964 | 582 | /* This HW can't do SMBUS_QUICK and NOSTART */ |
1fb2ad95 WS |
583 | return I2C_FUNC_I2C | I2C_FUNC_SLAVE | |
584 | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); | |
6ccbe607 KM |
585 | } |
586 | ||
587 | static const struct i2c_algorithm rcar_i2c_algo = { | |
588 | .master_xfer = rcar_i2c_master_xfer, | |
589 | .functionality = rcar_i2c_func, | |
de20d185 WS |
590 | .reg_slave = rcar_reg_slave, |
591 | .unreg_slave = rcar_unreg_slave, | |
6ccbe607 KM |
592 | }; |
593 | ||
7679c0e1 | 594 | static const struct of_device_id rcar_i2c_dt_ids[] = { |
043a3f11 KM |
595 | { .compatible = "renesas,i2c-rcar", .data = (void *)I2C_RCAR_GEN1 }, |
596 | { .compatible = "renesas,i2c-r8a7778", .data = (void *)I2C_RCAR_GEN1 }, | |
597 | { .compatible = "renesas,i2c-r8a7779", .data = (void *)I2C_RCAR_GEN1 }, | |
598 | { .compatible = "renesas,i2c-r8a7790", .data = (void *)I2C_RCAR_GEN2 }, | |
e8936455 | 599 | { .compatible = "renesas,i2c-r8a7791", .data = (void *)I2C_RCAR_GEN2 }, |
819a3951 WS |
600 | { .compatible = "renesas,i2c-r8a7792", .data = (void *)I2C_RCAR_GEN2 }, |
601 | { .compatible = "renesas,i2c-r8a7793", .data = (void *)I2C_RCAR_GEN2 }, | |
602 | { .compatible = "renesas,i2c-r8a7794", .data = (void *)I2C_RCAR_GEN2 }, | |
e7db0d34 | 603 | { .compatible = "renesas,i2c-r8a7795", .data = (void *)I2C_RCAR_GEN3 }, |
7679c0e1 GL |
604 | {}, |
605 | }; | |
606 | MODULE_DEVICE_TABLE(of, rcar_i2c_dt_ids); | |
607 | ||
0b255e92 | 608 | static int rcar_i2c_probe(struct platform_device *pdev) |
6ccbe607 | 609 | { |
6ccbe607 KM |
610 | struct rcar_i2c_priv *priv; |
611 | struct i2c_adapter *adap; | |
612 | struct resource *res; | |
613 | struct device *dev = &pdev->dev; | |
614 | u32 bus_speed; | |
93e953d3 | 615 | int irq, ret; |
6ccbe607 | 616 | |
6ccbe607 | 617 | priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL); |
46797a2a | 618 | if (!priv) |
6ccbe607 | 619 | return -ENOMEM; |
6ccbe607 | 620 | |
bc8120f1 BD |
621 | priv->clk = devm_clk_get(dev, NULL); |
622 | if (IS_ERR(priv->clk)) { | |
623 | dev_err(dev, "cannot get clock\n"); | |
624 | return PTR_ERR(priv->clk); | |
625 | } | |
626 | ||
e43e0df1 WS |
627 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
628 | priv->io = devm_ioremap_resource(dev, res); | |
629 | if (IS_ERR(priv->io)) | |
630 | return PTR_ERR(priv->io); | |
631 | ||
6ccbe607 | 632 | bus_speed = 100000; /* default 100 kHz */ |
c6f18913 | 633 | of_property_read_u32(dev->of_node, "clock-frequency", &bus_speed); |
b720423a | 634 | |
c6f18913 | 635 | priv->devtype = (enum rcar_i2c_type)of_match_device(rcar_i2c_dt_ids, dev)->data; |
b720423a | 636 | |
e43e0df1 WS |
637 | pm_runtime_enable(dev); |
638 | pm_runtime_get_sync(dev); | |
6ccbe607 KM |
639 | ret = rcar_i2c_clock_calculate(priv, bus_speed, dev); |
640 | if (ret < 0) | |
e43e0df1 | 641 | goto out_pm_put; |
6ccbe607 | 642 | |
2c78cdc1 | 643 | rcar_i2c_init(priv); |
e43e0df1 | 644 | pm_runtime_put(dev); |
6ccbe607 | 645 | |
93e953d3 | 646 | irq = platform_get_irq(pdev, 0); |
6ccbe607 | 647 | init_waitqueue_head(&priv->wait); |
6ccbe607 | 648 | |
929e3aba WS |
649 | adap = &priv->adap; |
650 | adap->nr = pdev->id; | |
651 | adap->algo = &rcar_i2c_algo; | |
652 | adap->class = I2C_CLASS_DEPRECATED; | |
653 | adap->retries = 3; | |
654 | adap->dev.parent = dev; | |
655 | adap->dev.of_node = dev->of_node; | |
6ccbe607 KM |
656 | i2c_set_adapdata(adap, priv); |
657 | strlcpy(adap->name, pdev->name, sizeof(adap->name)); | |
658 | ||
93e953d3 | 659 | ret = devm_request_irq(dev, irq, rcar_i2c_irq, 0, |
6ccbe607 KM |
660 | dev_name(dev), priv); |
661 | if (ret < 0) { | |
93e953d3 | 662 | dev_err(dev, "cannot get irq %d\n", irq); |
e43e0df1 | 663 | goto out_pm_disable; |
6ccbe607 KM |
664 | } |
665 | ||
4f7effdd WS |
666 | platform_set_drvdata(pdev, priv); |
667 | ||
6ccbe607 KM |
668 | ret = i2c_add_numbered_adapter(adap); |
669 | if (ret < 0) { | |
670 | dev_err(dev, "reg adap failed: %d\n", ret); | |
e43e0df1 | 671 | goto out_pm_disable; |
6ccbe607 KM |
672 | } |
673 | ||
6ccbe607 KM |
674 | dev_info(dev, "probed\n"); |
675 | ||
676 | return 0; | |
e43e0df1 WS |
677 | |
678 | out_pm_put: | |
679 | pm_runtime_put(dev); | |
680 | out_pm_disable: | |
681 | pm_runtime_disable(dev); | |
682 | return ret; | |
6ccbe607 KM |
683 | } |
684 | ||
0b255e92 | 685 | static int rcar_i2c_remove(struct platform_device *pdev) |
6ccbe607 KM |
686 | { |
687 | struct rcar_i2c_priv *priv = platform_get_drvdata(pdev); | |
688 | struct device *dev = &pdev->dev; | |
689 | ||
690 | i2c_del_adapter(&priv->adap); | |
691 | pm_runtime_disable(dev); | |
692 | ||
693 | return 0; | |
694 | } | |
695 | ||
45fd5e4a | 696 | static struct platform_driver rcar_i2c_driver = { |
6ccbe607 KM |
697 | .driver = { |
698 | .name = "i2c-rcar", | |
7679c0e1 | 699 | .of_match_table = rcar_i2c_dt_ids, |
6ccbe607 KM |
700 | }, |
701 | .probe = rcar_i2c_probe, | |
0b255e92 | 702 | .remove = rcar_i2c_remove, |
6ccbe607 KM |
703 | }; |
704 | ||
45fd5e4a | 705 | module_platform_driver(rcar_i2c_driver); |
6ccbe607 | 706 | |
3d99beab | 707 | MODULE_LICENSE("GPL v2"); |
6ccbe607 KM |
708 | MODULE_DESCRIPTION("Renesas R-Car I2C bus driver"); |
709 | MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>"); |