Commit | Line | Data |
---|---|---|
6ccbe607 | 1 | /* |
3d99beab | 2 | * Driver for the Renesas RCar I2C unit |
6ccbe607 | 3 | * |
3c2b1ff3 WS |
4 | * Copyright (C) 2014-15 Wolfram Sang <wsa@sang-engineering.com> |
5 | * Copyright (C) 2011-2015 Renesas Electronics Corporation | |
3d99beab WS |
6 | * |
7 | * Copyright (C) 2012-14 Renesas Solutions Corp. | |
6ccbe607 KM |
8 | * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> |
9 | * | |
10 | * This file is based on the drivers/i2c/busses/i2c-sh7760.c | |
11 | * (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com> | |
12 | * | |
6ccbe607 KM |
13 | * This program is free software; you can redistribute it and/or modify |
14 | * it under the terms of the GNU General Public License as published by | |
3d99beab | 15 | * the Free Software Foundation; version 2 of the License. |
6ccbe607 KM |
16 | * |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
6ccbe607 KM |
21 | */ |
22 | #include <linux/clk.h> | |
23 | #include <linux/delay.h> | |
24 | #include <linux/err.h> | |
6ccbe607 KM |
25 | #include <linux/interrupt.h> |
26 | #include <linux/io.h> | |
27 | #include <linux/i2c.h> | |
6ccbe607 KM |
28 | #include <linux/kernel.h> |
29 | #include <linux/module.h> | |
7679c0e1 | 30 | #include <linux/of_device.h> |
6ccbe607 KM |
31 | #include <linux/platform_device.h> |
32 | #include <linux/pm_runtime.h> | |
33 | #include <linux/slab.h> | |
6ccbe607 KM |
34 | |
35 | /* register offsets */ | |
36 | #define ICSCR 0x00 /* slave ctrl */ | |
37 | #define ICMCR 0x04 /* master ctrl */ | |
38 | #define ICSSR 0x08 /* slave status */ | |
39 | #define ICMSR 0x0C /* master status */ | |
40 | #define ICSIER 0x10 /* slave irq enable */ | |
41 | #define ICMIER 0x14 /* master irq enable */ | |
42 | #define ICCCR 0x18 /* clock dividers */ | |
43 | #define ICSAR 0x1C /* slave address */ | |
44 | #define ICMAR 0x20 /* master address */ | |
45 | #define ICRXTX 0x24 /* data port */ | |
46 | ||
de20d185 WS |
47 | /* ICSCR */ |
48 | #define SDBS (1 << 3) /* slave data buffer select */ | |
49 | #define SIE (1 << 2) /* slave interface enable */ | |
50 | #define GCAE (1 << 1) /* general call address enable */ | |
51 | #define FNA (1 << 0) /* forced non acknowledgment */ | |
52 | ||
6ccbe607 KM |
53 | /* ICMCR */ |
54 | #define MDBS (1 << 7) /* non-fifo mode switch */ | |
55 | #define FSCL (1 << 6) /* override SCL pin */ | |
56 | #define FSDA (1 << 5) /* override SDA pin */ | |
57 | #define OBPC (1 << 4) /* override pins */ | |
58 | #define MIE (1 << 3) /* master if enable */ | |
59 | #define TSBE (1 << 2) | |
60 | #define FSB (1 << 1) /* force stop bit */ | |
61 | #define ESG (1 << 0) /* en startbit gen */ | |
62 | ||
de20d185 WS |
63 | /* ICSSR (also for ICSIER) */ |
64 | #define GCAR (1 << 6) /* general call received */ | |
65 | #define STM (1 << 5) /* slave transmit mode */ | |
66 | #define SSR (1 << 4) /* stop received */ | |
67 | #define SDE (1 << 3) /* slave data empty */ | |
68 | #define SDT (1 << 2) /* slave data transmitted */ | |
69 | #define SDR (1 << 1) /* slave data received */ | |
70 | #define SAR (1 << 0) /* slave addr received */ | |
71 | ||
3e3aabac | 72 | /* ICMSR (also for ICMIE) */ |
6ccbe607 KM |
73 | #define MNR (1 << 6) /* nack received */ |
74 | #define MAL (1 << 5) /* arbitration lost */ | |
75 | #define MST (1 << 4) /* sent a stop */ | |
76 | #define MDE (1 << 3) | |
77 | #define MDT (1 << 2) | |
78 | #define MDR (1 << 1) | |
79 | #define MAT (1 << 0) /* slave addr xfer done */ | |
80 | ||
6ccbe607 | 81 | |
4f443a8a WS |
82 | #define RCAR_BUS_PHASE_START (MDBS | MIE | ESG) |
83 | #define RCAR_BUS_PHASE_DATA (MDBS | MIE) | |
52df445f | 84 | #define RCAR_BUS_MASK_DATA (~(ESG | FSB) & 0xFF) |
4f443a8a | 85 | #define RCAR_BUS_PHASE_STOP (MDBS | MIE | FSB) |
6ccbe607 | 86 | |
3e3aabac WS |
87 | #define RCAR_IRQ_SEND (MNR | MAL | MST | MAT | MDE) |
88 | #define RCAR_IRQ_RECV (MNR | MAL | MST | MAT | MDR) | |
89 | #define RCAR_IRQ_STOP (MST) | |
6ccbe607 | 90 | |
938916fb SS |
91 | #define RCAR_IRQ_ACK_SEND (~(MAT | MDE) & 0xFF) |
92 | #define RCAR_IRQ_ACK_RECV (~(MAT | MDR) & 0xFF) | |
3c95de67 | 93 | |
6ccbe607 | 94 | #define ID_LAST_MSG (1 << 0) |
e49865d1 | 95 | #define ID_FIRST_MSG (1 << 1) |
6ccbe607 KM |
96 | #define ID_DONE (1 << 2) |
97 | #define ID_ARBLOST (1 << 3) | |
98 | #define ID_NACK (1 << 4) | |
99 | ||
b720423a | 100 | enum rcar_i2c_type { |
043a3f11 KM |
101 | I2C_RCAR_GEN1, |
102 | I2C_RCAR_GEN2, | |
e7db0d34 | 103 | I2C_RCAR_GEN3, |
b720423a NVD |
104 | }; |
105 | ||
6ccbe607 KM |
106 | struct rcar_i2c_priv { |
107 | void __iomem *io; | |
108 | struct i2c_adapter adap; | |
b9d0684c WS |
109 | struct i2c_msg *msg; |
110 | int msgs_left; | |
bc8120f1 | 111 | struct clk *clk; |
6ccbe607 | 112 | |
6ccbe607 KM |
113 | wait_queue_head_t wait; |
114 | ||
115 | int pos; | |
6ccbe607 KM |
116 | u32 icccr; |
117 | u32 flags; | |
51371cdc | 118 | enum rcar_i2c_type devtype; |
de20d185 | 119 | struct i2c_client *slave; |
6ccbe607 KM |
120 | }; |
121 | ||
122 | #define rcar_i2c_priv_to_dev(p) ((p)->adap.dev.parent) | |
123 | #define rcar_i2c_is_recv(p) ((p)->msg->flags & I2C_M_RD) | |
124 | ||
125 | #define rcar_i2c_flags_set(p, f) ((p)->flags |= (f)) | |
126 | #define rcar_i2c_flags_has(p, f) ((p)->flags & (f)) | |
127 | ||
128 | #define LOOP_TIMEOUT 1024 | |
129 | ||
51371cdc | 130 | |
6ccbe607 KM |
131 | static void rcar_i2c_write(struct rcar_i2c_priv *priv, int reg, u32 val) |
132 | { | |
133 | writel(val, priv->io + reg); | |
134 | } | |
135 | ||
136 | static u32 rcar_i2c_read(struct rcar_i2c_priv *priv, int reg) | |
137 | { | |
138 | return readl(priv->io + reg); | |
139 | } | |
140 | ||
141 | static void rcar_i2c_init(struct rcar_i2c_priv *priv) | |
142 | { | |
6ccbe607 KM |
143 | /* reset master mode */ |
144 | rcar_i2c_write(priv, ICMIER, 0); | |
2c78cdc1 | 145 | rcar_i2c_write(priv, ICMCR, MDBS); |
6ccbe607 | 146 | rcar_i2c_write(priv, ICMSR, 0); |
2c78cdc1 WS |
147 | /* start clock */ |
148 | rcar_i2c_write(priv, ICCCR, priv->icccr); | |
6ccbe607 KM |
149 | } |
150 | ||
6ccbe607 KM |
151 | static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv) |
152 | { | |
153 | int i; | |
154 | ||
155 | for (i = 0; i < LOOP_TIMEOUT; i++) { | |
156 | /* make sure that bus is not busy */ | |
157 | if (!(rcar_i2c_read(priv, ICMCR) & FSDA)) | |
158 | return 0; | |
159 | udelay(1); | |
160 | } | |
161 | ||
162 | return -EBUSY; | |
163 | } | |
164 | ||
c7881871 | 165 | static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv, struct i2c_timings *t) |
6ccbe607 | 166 | { |
f9c9d31b | 167 | u32 scgd, cdf, round, ick, scl, cdf_width; |
8d049403 | 168 | unsigned long rate; |
f9c9d31b | 169 | struct device *dev = rcar_i2c_priv_to_dev(priv); |
6ccbe607 | 170 | |
c7881871 WS |
171 | /* Fall back to previously used values if not supplied */ |
172 | t->bus_freq_hz = t->bus_freq_hz ?: 100000; | |
173 | ||
b720423a | 174 | switch (priv->devtype) { |
043a3f11 | 175 | case I2C_RCAR_GEN1: |
b720423a NVD |
176 | cdf_width = 2; |
177 | break; | |
043a3f11 | 178 | case I2C_RCAR_GEN2: |
e7db0d34 | 179 | case I2C_RCAR_GEN3: |
b720423a NVD |
180 | cdf_width = 3; |
181 | break; | |
182 | default: | |
183 | dev_err(dev, "device type error\n"); | |
184 | return -EIO; | |
185 | } | |
186 | ||
6ccbe607 KM |
187 | /* |
188 | * calculate SCL clock | |
189 | * see | |
190 | * ICCCR | |
191 | * | |
192 | * ick = clkp / (1 + CDF) | |
193 | * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick]) | |
194 | * | |
195 | * ick : I2C internal clock < 20 MHz | |
196 | * ticf : I2C SCL falling time = 35 ns here | |
197 | * tr : I2C SCL rising time = 200 ns here | |
198 | * intd : LSI internal delay = 50 ns here | |
199 | * clkp : peripheral_clk | |
200 | * F[] : integer up-valuation | |
201 | */ | |
bc8120f1 | 202 | rate = clk_get_rate(priv->clk); |
8d049403 | 203 | cdf = rate / 20000000; |
22762ccb | 204 | if (cdf >= 1U << cdf_width) { |
8d049403 GL |
205 | dev_err(dev, "Input clock %lu too high\n", rate); |
206 | return -EIO; | |
6ccbe607 | 207 | } |
8d049403 | 208 | ick = rate / (cdf + 1); |
6ccbe607 | 209 | |
6ccbe607 KM |
210 | /* |
211 | * it is impossible to calculate large scale | |
212 | * number on u32. separate it | |
213 | * | |
214 | * F[(ticf + tr + intd) * ick] | |
215 | * = F[(35 + 200 + 50)ns * ick] | |
216 | * = F[285 * ick / 1000000000] | |
217 | * = F[(ick / 1000000) * 285 / 1000] | |
218 | */ | |
219 | round = (ick + 500000) / 1000000 * 285; | |
220 | round = (round + 500) / 1000; | |
221 | ||
222 | /* | |
223 | * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick]) | |
224 | * | |
225 | * Calculation result (= SCL) should be less than | |
226 | * bus_speed for hardware safety | |
8d049403 GL |
227 | * |
228 | * We could use something along the lines of | |
229 | * div = ick / (bus_speed + 1) + 1; | |
230 | * scgd = (div - 20 - round + 7) / 8; | |
231 | * scl = ick / (20 + (scgd * 8) + round); | |
232 | * (not fully verified) but that would get pretty involved | |
6ccbe607 KM |
233 | */ |
234 | for (scgd = 0; scgd < 0x40; scgd++) { | |
235 | scl = ick / (20 + (scgd * 8) + round); | |
c7881871 | 236 | if (scl <= t->bus_freq_hz) |
6ccbe607 KM |
237 | goto scgd_find; |
238 | } | |
239 | dev_err(dev, "it is impossible to calculate best SCL\n"); | |
240 | return -EIO; | |
241 | ||
242 | scgd_find: | |
243 | dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n", | |
c7881871 | 244 | scl, t->bus_freq_hz, clk_get_rate(priv->clk), round, cdf, scgd); |
6ccbe607 | 245 | |
3c2b1ff3 | 246 | /* keep icccr value */ |
14d32f17 | 247 | priv->icccr = scgd << cdf_width | cdf; |
6ccbe607 KM |
248 | |
249 | return 0; | |
250 | } | |
251 | ||
7c7117ff | 252 | static void rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv) |
6ccbe607 | 253 | { |
386babf8 | 254 | int read = !!rcar_i2c_is_recv(priv); |
6ccbe607 | 255 | |
b9d0684c | 256 | priv->pos = 0; |
b9d0684c WS |
257 | if (priv->msgs_left == 1) |
258 | rcar_i2c_flags_set(priv, ID_LAST_MSG); | |
259 | ||
386babf8 | 260 | rcar_i2c_write(priv, ICMAR, (priv->msg->addr << 1) | read); |
e49865d1 WS |
261 | /* |
262 | * We don't have a testcase but the HW engineers say that the write order | |
263 | * of ICMSR and ICMCR depends on whether we issue START or REP_START. Since | |
264 | * it didn't cause a drawback for me, let's rather be safe than sorry. | |
265 | */ | |
266 | if (rcar_i2c_flags_has(priv, ID_FIRST_MSG)) { | |
267 | rcar_i2c_write(priv, ICMSR, 0); | |
268 | rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START); | |
269 | } else { | |
270 | rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START); | |
271 | rcar_i2c_write(priv, ICMSR, 0); | |
272 | } | |
386babf8 | 273 | rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND); |
6ccbe607 KM |
274 | } |
275 | ||
cc21d0b4 WS |
276 | static void rcar_i2c_next_msg(struct rcar_i2c_priv *priv) |
277 | { | |
278 | priv->msg++; | |
279 | priv->msgs_left--; | |
e49865d1 | 280 | priv->flags = 0; |
cc21d0b4 WS |
281 | rcar_i2c_prepare_msg(priv); |
282 | } | |
283 | ||
6ccbe607 KM |
284 | /* |
285 | * interrupt functions | |
286 | */ | |
cc21d0b4 | 287 | static void rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr) |
6ccbe607 KM |
288 | { |
289 | struct i2c_msg *msg = priv->msg; | |
290 | ||
3c2b1ff3 | 291 | /* FIXME: sometimes, unknown interrupt happened. Do nothing */ |
6ccbe607 | 292 | if (!(msr & MDE)) |
cc21d0b4 | 293 | return; |
6ccbe607 | 294 | |
6ccbe607 KM |
295 | if (priv->pos < msg->len) { |
296 | /* | |
297 | * Prepare next data to ICRXTX register. | |
298 | * This data will go to _SHIFT_ register. | |
299 | * | |
300 | * * | |
301 | * [ICRXTX] -> [SHIFT] -> [I2C bus] | |
302 | */ | |
303 | rcar_i2c_write(priv, ICRXTX, msg->buf[priv->pos]); | |
304 | priv->pos++; | |
305 | ||
306 | } else { | |
307 | /* | |
308 | * The last data was pushed to ICRXTX on _PREV_ empty irq. | |
309 | * It is on _SHIFT_ register, and will sent to I2C bus. | |
310 | * | |
311 | * * | |
312 | * [ICRXTX] -> [SHIFT] -> [I2C bus] | |
313 | */ | |
314 | ||
cc21d0b4 | 315 | if (priv->flags & ID_LAST_MSG) { |
6ccbe607 KM |
316 | /* |
317 | * If current msg is the _LAST_ msg, | |
318 | * prepare stop condition here. | |
319 | * ID_DONE will be set on STOP irq. | |
320 | */ | |
4f443a8a | 321 | rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP); |
cc21d0b4 WS |
322 | } else { |
323 | rcar_i2c_next_msg(priv); | |
324 | return; | |
325 | } | |
6ccbe607 KM |
326 | } |
327 | ||
3c95de67 | 328 | rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_SEND); |
6ccbe607 KM |
329 | } |
330 | ||
cc21d0b4 | 331 | static void rcar_i2c_irq_recv(struct rcar_i2c_priv *priv, u32 msr) |
6ccbe607 KM |
332 | { |
333 | struct i2c_msg *msg = priv->msg; | |
334 | ||
3c2b1ff3 | 335 | /* FIXME: sometimes, unknown interrupt happened. Do nothing */ |
6ccbe607 | 336 | if (!(msr & MDR)) |
cc21d0b4 | 337 | return; |
6ccbe607 KM |
338 | |
339 | if (msr & MAT) { | |
52df445f | 340 | /* Address transfer phase finished, but no data at this point. */ |
6ccbe607 | 341 | } else if (priv->pos < msg->len) { |
3c2b1ff3 | 342 | /* get received data */ |
6ccbe607 KM |
343 | msg->buf[priv->pos] = rcar_i2c_read(priv, ICRXTX); |
344 | priv->pos++; | |
345 | } | |
346 | ||
347 | /* | |
3c2b1ff3 WS |
348 | * If next received data is the _LAST_, go to STOP phase. Might be |
349 | * overwritten by REP START when setting up a new msg. Not elegant | |
350 | * but the only stable sequence for REP START I have found so far. | |
6ccbe607 KM |
351 | */ |
352 | if (priv->pos + 1 >= msg->len) | |
4f443a8a | 353 | rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP); |
6ccbe607 | 354 | |
cc21d0b4 WS |
355 | if (priv->pos == msg->len && !(priv->flags & ID_LAST_MSG)) |
356 | rcar_i2c_next_msg(priv); | |
357 | else | |
358 | rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_RECV); | |
6ccbe607 KM |
359 | } |
360 | ||
de20d185 WS |
361 | static bool rcar_i2c_slave_irq(struct rcar_i2c_priv *priv) |
362 | { | |
363 | u32 ssr_raw, ssr_filtered; | |
364 | u8 value; | |
365 | ||
366 | ssr_raw = rcar_i2c_read(priv, ICSSR) & 0xff; | |
367 | ssr_filtered = ssr_raw & rcar_i2c_read(priv, ICSIER); | |
368 | ||
369 | if (!ssr_filtered) | |
370 | return false; | |
371 | ||
372 | /* address detected */ | |
373 | if (ssr_filtered & SAR) { | |
374 | /* read or write request */ | |
375 | if (ssr_raw & STM) { | |
5b77d162 | 376 | i2c_slave_event(priv->slave, I2C_SLAVE_READ_REQUESTED, &value); |
de20d185 WS |
377 | rcar_i2c_write(priv, ICRXTX, value); |
378 | rcar_i2c_write(priv, ICSIER, SDE | SSR | SAR); | |
379 | } else { | |
5b77d162 | 380 | i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_REQUESTED, &value); |
de20d185 WS |
381 | rcar_i2c_read(priv, ICRXTX); /* dummy read */ |
382 | rcar_i2c_write(priv, ICSIER, SDR | SSR | SAR); | |
383 | } | |
384 | ||
385 | rcar_i2c_write(priv, ICSSR, ~SAR & 0xff); | |
386 | } | |
387 | ||
388 | /* master sent stop */ | |
389 | if (ssr_filtered & SSR) { | |
390 | i2c_slave_event(priv->slave, I2C_SLAVE_STOP, &value); | |
391 | rcar_i2c_write(priv, ICSIER, SAR | SSR); | |
392 | rcar_i2c_write(priv, ICSSR, ~SSR & 0xff); | |
393 | } | |
394 | ||
395 | /* master wants to write to us */ | |
396 | if (ssr_filtered & SDR) { | |
397 | int ret; | |
398 | ||
399 | value = rcar_i2c_read(priv, ICRXTX); | |
5b77d162 | 400 | ret = i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_RECEIVED, &value); |
de20d185 WS |
401 | /* Send NACK in case of error */ |
402 | rcar_i2c_write(priv, ICSCR, SIE | SDBS | (ret < 0 ? FNA : 0)); | |
de20d185 WS |
403 | rcar_i2c_write(priv, ICSSR, ~SDR & 0xff); |
404 | } | |
405 | ||
406 | /* master wants to read from us */ | |
407 | if (ssr_filtered & SDE) { | |
5b77d162 | 408 | i2c_slave_event(priv->slave, I2C_SLAVE_READ_PROCESSED, &value); |
de20d185 WS |
409 | rcar_i2c_write(priv, ICRXTX, value); |
410 | rcar_i2c_write(priv, ICSSR, ~SDE & 0xff); | |
411 | } | |
412 | ||
413 | return true; | |
414 | } | |
415 | ||
6ccbe607 KM |
416 | static irqreturn_t rcar_i2c_irq(int irq, void *ptr) |
417 | { | |
418 | struct rcar_i2c_priv *priv = ptr; | |
52df445f WS |
419 | u32 msr, val; |
420 | ||
421 | /* Clear START or STOP as soon as we can */ | |
422 | val = rcar_i2c_read(priv, ICMCR); | |
423 | rcar_i2c_write(priv, ICMCR, val & RCAR_BUS_MASK_DATA); | |
6ccbe607 | 424 | |
1c176d53 | 425 | msr = rcar_i2c_read(priv, ICMSR); |
6ccbe607 | 426 | |
dd318b0d SS |
427 | /* Only handle interrupts that are currently enabled */ |
428 | msr &= rcar_i2c_read(priv, ICMIER); | |
aa5beaf6 | 429 | if (!msr) { |
c3be0af1 WS |
430 | if (rcar_i2c_slave_irq(priv)) |
431 | return IRQ_HANDLED; | |
432 | ||
433 | return IRQ_NONE; | |
aa5beaf6 | 434 | } |
dd318b0d | 435 | |
51371cdc | 436 | /* Arbitration lost */ |
6ccbe607 | 437 | if (msr & MAL) { |
6ccbe607 KM |
438 | rcar_i2c_flags_set(priv, (ID_DONE | ID_ARBLOST)); |
439 | goto out; | |
440 | } | |
441 | ||
51371cdc | 442 | /* Nack */ |
6ccbe607 | 443 | if (msr & MNR) { |
d89667b1 | 444 | /* HW automatically sends STOP after received NACK */ |
f2382249 | 445 | rcar_i2c_write(priv, ICMIER, RCAR_IRQ_STOP); |
6ccbe607 KM |
446 | rcar_i2c_flags_set(priv, ID_NACK); |
447 | goto out; | |
448 | } | |
449 | ||
dd318b0d SS |
450 | /* Stop */ |
451 | if (msr & MST) { | |
cc21d0b4 | 452 | priv->msgs_left--; /* The last message also made it */ |
dd318b0d SS |
453 | rcar_i2c_flags_set(priv, ID_DONE); |
454 | goto out; | |
455 | } | |
456 | ||
6ccbe607 | 457 | if (rcar_i2c_is_recv(priv)) |
cc21d0b4 | 458 | rcar_i2c_irq_recv(priv, msr); |
6ccbe607 | 459 | else |
cc21d0b4 | 460 | rcar_i2c_irq_send(priv, msr); |
6ccbe607 KM |
461 | |
462 | out: | |
463 | if (rcar_i2c_flags_has(priv, ID_DONE)) { | |
f2382249 | 464 | rcar_i2c_write(priv, ICMIER, 0); |
3c95de67 | 465 | rcar_i2c_write(priv, ICMSR, 0); |
6ccbe607 KM |
466 | wake_up(&priv->wait); |
467 | } | |
468 | ||
c3be0af1 | 469 | return IRQ_HANDLED; |
6ccbe607 KM |
470 | } |
471 | ||
472 | static int rcar_i2c_master_xfer(struct i2c_adapter *adap, | |
473 | struct i2c_msg *msgs, | |
474 | int num) | |
475 | { | |
476 | struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); | |
477 | struct device *dev = rcar_i2c_priv_to_dev(priv); | |
b6763d0d | 478 | int i, ret; |
ff2316b8 | 479 | long time_left; |
6ccbe607 KM |
480 | |
481 | pm_runtime_get_sync(dev); | |
482 | ||
3f7de22e WS |
483 | ret = rcar_i2c_bus_barrier(priv); |
484 | if (ret < 0) | |
485 | goto out; | |
486 | ||
6ccbe607 | 487 | for (i = 0; i < num; i++) { |
d7653964 WS |
488 | /* This HW can't send STOP after address phase */ |
489 | if (msgs[i].len == 0) { | |
490 | ret = -EOPNOTSUPP; | |
cc21d0b4 | 491 | goto out; |
6ccbe607 | 492 | } |
cc21d0b4 | 493 | } |
6ccbe607 | 494 | |
e49865d1 | 495 | /* init first message */ |
cc21d0b4 WS |
496 | priv->msg = msgs; |
497 | priv->msgs_left = num; | |
e49865d1 | 498 | priv->flags = ID_FIRST_MSG; |
cc21d0b4 WS |
499 | rcar_i2c_prepare_msg(priv); |
500 | ||
501 | time_left = wait_event_timeout(priv->wait, | |
502 | rcar_i2c_flags_has(priv, ID_DONE), | |
503 | num * adap->timeout); | |
504 | if (!time_left) { | |
505 | rcar_i2c_init(priv); | |
506 | ret = -ETIMEDOUT; | |
507 | } else if (rcar_i2c_flags_has(priv, ID_NACK)) { | |
508 | ret = -ENXIO; | |
509 | } else if (rcar_i2c_flags_has(priv, ID_ARBLOST)) { | |
510 | ret = -EAGAIN; | |
511 | } else { | |
512 | ret = num - priv->msgs_left; /* The number of transfer */ | |
6ccbe607 | 513 | } |
3f7de22e | 514 | out: |
6ccbe607 KM |
515 | pm_runtime_put(dev); |
516 | ||
6ff4b105 | 517 | if (ret < 0 && ret != -ENXIO) |
6ccbe607 KM |
518 | dev_err(dev, "error %d : %x\n", ret, priv->flags); |
519 | ||
520 | return ret; | |
521 | } | |
522 | ||
de20d185 WS |
523 | static int rcar_reg_slave(struct i2c_client *slave) |
524 | { | |
525 | struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter); | |
526 | ||
527 | if (priv->slave) | |
528 | return -EBUSY; | |
529 | ||
530 | if (slave->flags & I2C_CLIENT_TEN) | |
531 | return -EAFNOSUPPORT; | |
532 | ||
533 | pm_runtime_forbid(rcar_i2c_priv_to_dev(priv)); | |
534 | ||
535 | priv->slave = slave; | |
536 | rcar_i2c_write(priv, ICSAR, slave->addr); | |
537 | rcar_i2c_write(priv, ICSSR, 0); | |
538 | rcar_i2c_write(priv, ICSIER, SAR | SSR); | |
539 | rcar_i2c_write(priv, ICSCR, SIE | SDBS); | |
540 | ||
541 | return 0; | |
542 | } | |
543 | ||
544 | static int rcar_unreg_slave(struct i2c_client *slave) | |
545 | { | |
546 | struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter); | |
547 | ||
548 | WARN_ON(!priv->slave); | |
549 | ||
550 | rcar_i2c_write(priv, ICSIER, 0); | |
551 | rcar_i2c_write(priv, ICSCR, 0); | |
552 | ||
553 | priv->slave = NULL; | |
554 | ||
555 | pm_runtime_allow(rcar_i2c_priv_to_dev(priv)); | |
556 | ||
557 | return 0; | |
558 | } | |
559 | ||
6ccbe607 KM |
560 | static u32 rcar_i2c_func(struct i2c_adapter *adap) |
561 | { | |
d7653964 | 562 | /* This HW can't do SMBUS_QUICK and NOSTART */ |
1fb2ad95 WS |
563 | return I2C_FUNC_I2C | I2C_FUNC_SLAVE | |
564 | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); | |
6ccbe607 KM |
565 | } |
566 | ||
567 | static const struct i2c_algorithm rcar_i2c_algo = { | |
568 | .master_xfer = rcar_i2c_master_xfer, | |
569 | .functionality = rcar_i2c_func, | |
de20d185 WS |
570 | .reg_slave = rcar_reg_slave, |
571 | .unreg_slave = rcar_unreg_slave, | |
6ccbe607 KM |
572 | }; |
573 | ||
7679c0e1 | 574 | static const struct of_device_id rcar_i2c_dt_ids[] = { |
043a3f11 KM |
575 | { .compatible = "renesas,i2c-rcar", .data = (void *)I2C_RCAR_GEN1 }, |
576 | { .compatible = "renesas,i2c-r8a7778", .data = (void *)I2C_RCAR_GEN1 }, | |
577 | { .compatible = "renesas,i2c-r8a7779", .data = (void *)I2C_RCAR_GEN1 }, | |
578 | { .compatible = "renesas,i2c-r8a7790", .data = (void *)I2C_RCAR_GEN2 }, | |
e8936455 | 579 | { .compatible = "renesas,i2c-r8a7791", .data = (void *)I2C_RCAR_GEN2 }, |
819a3951 WS |
580 | { .compatible = "renesas,i2c-r8a7792", .data = (void *)I2C_RCAR_GEN2 }, |
581 | { .compatible = "renesas,i2c-r8a7793", .data = (void *)I2C_RCAR_GEN2 }, | |
582 | { .compatible = "renesas,i2c-r8a7794", .data = (void *)I2C_RCAR_GEN2 }, | |
e7db0d34 | 583 | { .compatible = "renesas,i2c-r8a7795", .data = (void *)I2C_RCAR_GEN3 }, |
7679c0e1 GL |
584 | {}, |
585 | }; | |
586 | MODULE_DEVICE_TABLE(of, rcar_i2c_dt_ids); | |
587 | ||
0b255e92 | 588 | static int rcar_i2c_probe(struct platform_device *pdev) |
6ccbe607 | 589 | { |
6ccbe607 KM |
590 | struct rcar_i2c_priv *priv; |
591 | struct i2c_adapter *adap; | |
592 | struct resource *res; | |
593 | struct device *dev = &pdev->dev; | |
c7881871 | 594 | struct i2c_timings i2c_t; |
93e953d3 | 595 | int irq, ret; |
6ccbe607 | 596 | |
6ccbe607 | 597 | priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL); |
46797a2a | 598 | if (!priv) |
6ccbe607 | 599 | return -ENOMEM; |
6ccbe607 | 600 | |
bc8120f1 BD |
601 | priv->clk = devm_clk_get(dev, NULL); |
602 | if (IS_ERR(priv->clk)) { | |
603 | dev_err(dev, "cannot get clock\n"); | |
604 | return PTR_ERR(priv->clk); | |
605 | } | |
606 | ||
e43e0df1 WS |
607 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
608 | priv->io = devm_ioremap_resource(dev, res); | |
609 | if (IS_ERR(priv->io)) | |
610 | return PTR_ERR(priv->io); | |
611 | ||
c6f18913 | 612 | priv->devtype = (enum rcar_i2c_type)of_match_device(rcar_i2c_dt_ids, dev)->data; |
6ccbe607 | 613 | init_waitqueue_head(&priv->wait); |
6ccbe607 | 614 | |
929e3aba WS |
615 | adap = &priv->adap; |
616 | adap->nr = pdev->id; | |
617 | adap->algo = &rcar_i2c_algo; | |
618 | adap->class = I2C_CLASS_DEPRECATED; | |
619 | adap->retries = 3; | |
620 | adap->dev.parent = dev; | |
621 | adap->dev.of_node = dev->of_node; | |
6ccbe607 KM |
622 | i2c_set_adapdata(adap, priv); |
623 | strlcpy(adap->name, pdev->name, sizeof(adap->name)); | |
624 | ||
c7881871 | 625 | i2c_parse_fw_timings(dev, &i2c_t, false); |
f9c9d31b WS |
626 | |
627 | pm_runtime_enable(dev); | |
628 | pm_runtime_get_sync(dev); | |
c7881871 | 629 | ret = rcar_i2c_clock_calculate(priv, &i2c_t); |
f9c9d31b WS |
630 | if (ret < 0) |
631 | goto out_pm_put; | |
632 | ||
633 | rcar_i2c_init(priv); | |
634 | pm_runtime_put(dev); | |
635 | ||
636 | irq = platform_get_irq(pdev, 0); | |
637 | ret = devm_request_irq(dev, irq, rcar_i2c_irq, 0, dev_name(dev), priv); | |
6ccbe607 | 638 | if (ret < 0) { |
93e953d3 | 639 | dev_err(dev, "cannot get irq %d\n", irq); |
e43e0df1 | 640 | goto out_pm_disable; |
6ccbe607 KM |
641 | } |
642 | ||
4f7effdd WS |
643 | platform_set_drvdata(pdev, priv); |
644 | ||
6ccbe607 KM |
645 | ret = i2c_add_numbered_adapter(adap); |
646 | if (ret < 0) { | |
647 | dev_err(dev, "reg adap failed: %d\n", ret); | |
e43e0df1 | 648 | goto out_pm_disable; |
6ccbe607 KM |
649 | } |
650 | ||
6ccbe607 KM |
651 | dev_info(dev, "probed\n"); |
652 | ||
653 | return 0; | |
e43e0df1 WS |
654 | |
655 | out_pm_put: | |
656 | pm_runtime_put(dev); | |
657 | out_pm_disable: | |
658 | pm_runtime_disable(dev); | |
659 | return ret; | |
6ccbe607 KM |
660 | } |
661 | ||
0b255e92 | 662 | static int rcar_i2c_remove(struct platform_device *pdev) |
6ccbe607 KM |
663 | { |
664 | struct rcar_i2c_priv *priv = platform_get_drvdata(pdev); | |
665 | struct device *dev = &pdev->dev; | |
666 | ||
667 | i2c_del_adapter(&priv->adap); | |
668 | pm_runtime_disable(dev); | |
669 | ||
670 | return 0; | |
671 | } | |
672 | ||
45fd5e4a | 673 | static struct platform_driver rcar_i2c_driver = { |
6ccbe607 KM |
674 | .driver = { |
675 | .name = "i2c-rcar", | |
7679c0e1 | 676 | .of_match_table = rcar_i2c_dt_ids, |
6ccbe607 KM |
677 | }, |
678 | .probe = rcar_i2c_probe, | |
0b255e92 | 679 | .remove = rcar_i2c_remove, |
6ccbe607 KM |
680 | }; |
681 | ||
45fd5e4a | 682 | module_platform_driver(rcar_i2c_driver); |
6ccbe607 | 683 | |
3d99beab | 684 | MODULE_LICENSE("GPL v2"); |
6ccbe607 KM |
685 | MODULE_DESCRIPTION("Renesas R-Car I2C bus driver"); |
686 | MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>"); |