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Linux 3.17-rc7
[deliverable/linux.git] / drivers / i2c / busses / i2c-rk3x.c
CommitLineData
c41aa3ce
MS		 1/*
2 * Driver for I2C adapter in Rockchip RK3xxx SoC
3 *
4 * Max Schwarz <max.schwarz@online.de>
5 * based on the patches by Rockchip Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/i2c.h>
15#include <linux/interrupt.h>
16#include <linux/errno.h>
17#include <linux/err.h>
18#include <linux/platform_device.h>
19#include <linux/io.h>
20#include <linux/of_address.h>
21#include <linux/of_irq.h>
22#include <linux/spinlock.h>
23#include <linux/clk.h>
24#include <linux/wait.h>
25#include <linux/mfd/syscon.h>
26#include <linux/regmap.h>
27
28
29/* Register Map */
30#define REG_CON 0x00 /* control register */
31#define REG_CLKDIV 0x04 /* clock divisor register */
32#define REG_MRXADDR 0x08 /* slave address for REGISTER_TX */
33#define REG_MRXRADDR 0x0c /* slave register address for REGISTER_TX */
34#define REG_MTXCNT 0x10 /* number of bytes to be transmitted */
35#define REG_MRXCNT 0x14 /* number of bytes to be received */
36#define REG_IEN 0x18 /* interrupt enable */
37#define REG_IPD 0x1c /* interrupt pending */
38#define REG_FCNT 0x20 /* finished count */
39
40/* Data buffer offsets */
41#define TXBUFFER_BASE 0x100
42#define RXBUFFER_BASE 0x200
43
44/* REG_CON bits */
45#define REG_CON_EN BIT(0)
46enum {
47 REG_CON_MOD_TX = 0, /* transmit data */
48 REG_CON_MOD_REGISTER_TX, /* select register and restart */
49 REG_CON_MOD_RX, /* receive data */
50 REG_CON_MOD_REGISTER_RX, /* broken: transmits read addr AND writes
51 * register addr */
52};
53#define REG_CON_MOD(mod) ((mod) << 1)
54#define REG_CON_MOD_MASK (BIT(1) | BIT(2))
55#define REG_CON_START BIT(3)
56#define REG_CON_STOP BIT(4)
57#define REG_CON_LASTACK BIT(5) /* 1: send NACK after last received byte */
58#define REG_CON_ACTACK BIT(6) /* 1: stop if NACK is received */
59
60/* REG_MRXADDR bits */
61#define REG_MRXADDR_VALID(x) BIT(24 + (x)) /* [x*8+7:x*8] of MRX[R]ADDR valid */
62
63/* REG_IEN/REG_IPD bits */
64#define REG_INT_BTF BIT(0) /* a byte was transmitted */
65#define REG_INT_BRF BIT(1) /* a byte was received */
66#define REG_INT_MBTF BIT(2) /* master data transmit finished */
67#define REG_INT_MBRF BIT(3) /* master data receive finished */
68#define REG_INT_START BIT(4) /* START condition generated */
69#define REG_INT_STOP BIT(5) /* STOP condition generated */
70#define REG_INT_NAKRCV BIT(6) /* NACK received */
71#define REG_INT_ALL 0x7f
72
73/* Constants */
74#define WAIT_TIMEOUT 200 /* ms */
75#define DEFAULT_SCL_RATE (100 * 1000) /* Hz */
76
77enum rk3x_i2c_state {
78 STATE_IDLE,
79 STATE_START,
80 STATE_READ,
81 STATE_WRITE,
82 STATE_STOP
83};
84
85/**
86 * @grf_offset: offset inside the grf regmap for setting the i2c type
87 */
88struct rk3x_i2c_soc_data {
89 int grf_offset;
90};
91
92struct rk3x_i2c {
93 struct i2c_adapter adap;
94 struct device *dev;
95 struct rk3x_i2c_soc_data *soc_data;
96
97 /* Hardware resources */
98 void __iomem *regs;
99 struct clk *clk;
100
101 /* Settings */
102 unsigned int scl_frequency;
103
104 /* Synchronization & notification */
105 spinlock_t lock;
106 wait_queue_head_t wait;
107 bool busy;
108
109 /* Current message */
110 struct i2c_msg *msg;
111 u8 addr;
112 unsigned int mode;
113 bool is_last_msg;
114
115 /* I2C state machine */
116 enum rk3x_i2c_state state;
117 unsigned int processed; /* sent/received bytes */
118 int error;
119};
120
121static inline void i2c_writel(struct rk3x_i2c *i2c, u32 value,
122 unsigned int offset)
123{
124 writel(value, i2c->regs + offset);
125}
126
127static inline u32 i2c_readl(struct rk3x_i2c *i2c, unsigned int offset)
128{
129 return readl(i2c->regs + offset);
130}
131
132/* Reset all interrupt pending bits */
133static inline void rk3x_i2c_clean_ipd(struct rk3x_i2c *i2c)
134{
135 i2c_writel(i2c, REG_INT_ALL, REG_IPD);
136}
137
138/**
139 * Generate a START condition, which triggers a REG_INT_START interrupt.
140 */
141static void rk3x_i2c_start(struct rk3x_i2c *i2c)
142{
143 u32 val;
144
145 rk3x_i2c_clean_ipd(i2c);
146 i2c_writel(i2c, REG_INT_START, REG_IEN);
147
148 /* enable adapter with correct mode, send START condition */
149 val = REG_CON_EN | REG_CON_MOD(i2c->mode) | REG_CON_START;
150
151 /* if we want to react to NACK, set ACTACK bit */
152 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK))
153 val |= REG_CON_ACTACK;
154
155 i2c_writel(i2c, val, REG_CON);
156}
157
158/**
159 * Generate a STOP condition, which triggers a REG_INT_STOP interrupt.
160 *
161 * @error: Error code to return in rk3x_i2c_xfer
162 */
163static void rk3x_i2c_stop(struct rk3x_i2c *i2c, int error)
164{
165 unsigned int ctrl;
166
167 i2c->processed = 0;
168 i2c->msg = NULL;
169 i2c->error = error;
170
171 if (i2c->is_last_msg) {
172 /* Enable stop interrupt */
173 i2c_writel(i2c, REG_INT_STOP, REG_IEN);
174
175 i2c->state = STATE_STOP;
176
177 ctrl = i2c_readl(i2c, REG_CON);
178 ctrl |= REG_CON_STOP;
179 i2c_writel(i2c, ctrl, REG_CON);
180 } else {
181 /* Signal rk3x_i2c_xfer to start the next message. */
182 i2c->busy = false;
183 i2c->state = STATE_IDLE;
184
185 /*
186 * The HW is actually not capable of REPEATED START. But we can
187 * get the intended effect by resetting its internal state
188 * and issuing an ordinary START.
189 */
190 i2c_writel(i2c, 0, REG_CON);
191
192 /* signal that we are finished with the current msg */
193 wake_up(&i2c->wait);
194 }
195}
196
197/**
198 * Setup a read according to i2c->msg
199 */
200static void rk3x_i2c_prepare_read(struct rk3x_i2c *i2c)
201{
202 unsigned int len = i2c->msg->len - i2c->processed;
203 u32 con;
204
205 con = i2c_readl(i2c, REG_CON);
206
207 /*
208 * The hw can read up to 32 bytes at a time. If we need more than one
209 * chunk, send an ACK after the last byte of the current chunk.
210 */
211 if (unlikely(len > 32)) {
212 len = 32;
213 con &= ~REG_CON_LASTACK;
214 } else {
215 con |= REG_CON_LASTACK;
216 }
217
218 /* make sure we are in plain RX mode if we read a second chunk */
219 if (i2c->processed != 0) {
220 con &= ~REG_CON_MOD_MASK;
221 con |= REG_CON_MOD(REG_CON_MOD_RX);
222 }
223
224 i2c_writel(i2c, con, REG_CON);
225 i2c_writel(i2c, len, REG_MRXCNT);
226}
227
228/**
229 * Fill the transmit buffer with data from i2c->msg
230 */
231static void rk3x_i2c_fill_transmit_buf(struct rk3x_i2c *i2c)
232{
233 unsigned int i, j;
234 u32 cnt = 0;
235 u32 val;
236 u8 byte;
237
238 for (i = 0; i < 8; ++i) {
239 val = 0;
240 for (j = 0; j < 4; ++j) {
241 if (i2c->processed == i2c->msg->len)
242 break;
243
244 if (i2c->processed == 0 && cnt == 0)
245 byte = (i2c->addr & 0x7f) << 1;
246 else
247 byte = i2c->msg->buf[i2c->processed++];
248
249 val |= byte << (j * 8);
250 cnt++;
251 }
252
253 i2c_writel(i2c, val, TXBUFFER_BASE + 4 * i);
254
255 if (i2c->processed == i2c->msg->len)
256 break;
257 }
258
259 i2c_writel(i2c, cnt, REG_MTXCNT);
260}
261
262
263/* IRQ handlers for individual states */
264
265static void rk3x_i2c_handle_start(struct rk3x_i2c *i2c, unsigned int ipd)
266{
267 if (!(ipd & REG_INT_START)) {
268 rk3x_i2c_stop(i2c, -EIO);
269 dev_warn(i2c->dev, "unexpected irq in START: 0x%x\n", ipd);
270 rk3x_i2c_clean_ipd(i2c);
271 return;
272 }
273
274 /* ack interrupt */
275 i2c_writel(i2c, REG_INT_START, REG_IPD);
276
277 /* disable start bit */
278 i2c_writel(i2c, i2c_readl(i2c, REG_CON) & ~REG_CON_START, REG_CON);
279
280 /* enable appropriate interrupts and transition */
281 if (i2c->mode == REG_CON_MOD_TX) {
282 i2c_writel(i2c, REG_INT_MBTF | REG_INT_NAKRCV, REG_IEN);
283 i2c->state = STATE_WRITE;
284 rk3x_i2c_fill_transmit_buf(i2c);
285 } else {
286 /* in any other case, we are going to be reading. */
287 i2c_writel(i2c, REG_INT_MBRF | REG_INT_NAKRCV, REG_IEN);
288 i2c->state = STATE_READ;
289 rk3x_i2c_prepare_read(i2c);
290 }
291}
292
293static void rk3x_i2c_handle_write(struct rk3x_i2c *i2c, unsigned int ipd)
294{
295 if (!(ipd & REG_INT_MBTF)) {
296 rk3x_i2c_stop(i2c, -EIO);
297 dev_err(i2c->dev, "unexpected irq in WRITE: 0x%x\n", ipd);
298 rk3x_i2c_clean_ipd(i2c);
299 return;
300 }
301
302 /* ack interrupt */
303 i2c_writel(i2c, REG_INT_MBTF, REG_IPD);
304
305 /* are we finished? */
306 if (i2c->processed == i2c->msg->len)
307 rk3x_i2c_stop(i2c, i2c->error);
308 else
309 rk3x_i2c_fill_transmit_buf(i2c);
310}
311
312static void rk3x_i2c_handle_read(struct rk3x_i2c *i2c, unsigned int ipd)
313{
314 unsigned int i;
315 unsigned int len = i2c->msg->len - i2c->processed;
316 u32 uninitialized_var(val);
317 u8 byte;
318
319 /* we only care for MBRF here. */
320 if (!(ipd & REG_INT_MBRF))
321 return;
322
323 /* ack interrupt */
324 i2c_writel(i2c, REG_INT_MBRF, REG_IPD);
325
5da4309f 326 /* Can only handle a maximum of 32 bytes at a time */
327 if (len > 32)
328 len = 32;
329
c41aa3ce
MS		 330 /* read the data from receive buffer */
331 for (i = 0; i < len; ++i) {
332 if (i % 4 == 0)
333 val = i2c_readl(i2c, RXBUFFER_BASE + (i / 4) * 4);
334
335 byte = (val >> ((i % 4) * 8)) & 0xff;
336 i2c->msg->buf[i2c->processed++] = byte;
337 }
338
339 /* are we finished? */
340 if (i2c->processed == i2c->msg->len)
341 rk3x_i2c_stop(i2c, i2c->error);
342 else
343 rk3x_i2c_prepare_read(i2c);
344}
345
346static void rk3x_i2c_handle_stop(struct rk3x_i2c *i2c, unsigned int ipd)
347{
348 unsigned int con;
349
350 if (!(ipd & REG_INT_STOP)) {
351 rk3x_i2c_stop(i2c, -EIO);
352 dev_err(i2c->dev, "unexpected irq in STOP: 0x%x\n", ipd);
353 rk3x_i2c_clean_ipd(i2c);
354 return;
355 }
356
357 /* ack interrupt */
358 i2c_writel(i2c, REG_INT_STOP, REG_IPD);
359
360 /* disable STOP bit */
361 con = i2c_readl(i2c, REG_CON);
362 con &= ~REG_CON_STOP;
363 i2c_writel(i2c, con, REG_CON);
364
365 i2c->busy = false;
366 i2c->state = STATE_IDLE;
367
368 /* signal rk3x_i2c_xfer that we are finished */
369 wake_up(&i2c->wait);
370}
371
372static irqreturn_t rk3x_i2c_irq(int irqno, void *dev_id)
373{
374 struct rk3x_i2c *i2c = dev_id;
375 unsigned int ipd;
376
377 spin_lock(&i2c->lock);
378
379 ipd = i2c_readl(i2c, REG_IPD);
380 if (i2c->state == STATE_IDLE) {
381 dev_warn(i2c->dev, "irq in STATE_IDLE, ipd = 0x%x\n", ipd);
382 rk3x_i2c_clean_ipd(i2c);
383 goto out;
384 }
385
386 dev_dbg(i2c->dev, "IRQ: state %d, ipd: %x\n", i2c->state, ipd);
387
388 /* Clean interrupt bits we don't care about */
389 ipd &= ~(REG_INT_BRF | REG_INT_BTF);
390
391 if (ipd & REG_INT_NAKRCV) {
392 /*
393 * We got a NACK in the last operation. Depending on whether
394 * IGNORE_NAK is set, we have to stop the operation and report
395 * an error.
396 */
397 i2c_writel(i2c, REG_INT_NAKRCV, REG_IPD);
398
399 ipd &= ~REG_INT_NAKRCV;
400
401 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK))
402 rk3x_i2c_stop(i2c, -ENXIO);
403 }
404
405 /* is there anything left to handle? */
9c5f7cad 406 if (unlikely((ipd & REG_INT_ALL) == 0))
c41aa3ce
MS		 407 goto out;
408
409 switch (i2c->state) {
410 case STATE_START:
411 rk3x_i2c_handle_start(i2c, ipd);
412 break;
413 case STATE_WRITE:
414 rk3x_i2c_handle_write(i2c, ipd);
415 break;
416 case STATE_READ:
417 rk3x_i2c_handle_read(i2c, ipd);
418 break;
419 case STATE_STOP:
420 rk3x_i2c_handle_stop(i2c, ipd);
421 break;
422 case STATE_IDLE:
423 break;
424 }
425
426out:
427 spin_unlock(&i2c->lock);
428 return IRQ_HANDLED;
429}
430
431static void rk3x_i2c_set_scl_rate(struct rk3x_i2c *i2c, unsigned long scl_rate)
432{
433 unsigned long i2c_rate = clk_get_rate(i2c->clk);
434 unsigned int div;
435
b4a7bd7a 436 /* set DIV = DIVH = DIVL
437 * SCL rate = (clk rate) / (8 * (DIVH + 1 + DIVL + 1))
438 * = (clk rate) / (16 * (DIV + 1))
439 */
440 div = DIV_ROUND_UP(i2c_rate, scl_rate * 16) - 1;
c41aa3ce
MS		 441
442 i2c_writel(i2c, (div << 16) | (div & 0xffff), REG_CLKDIV);
443}
444
445/**
446 * Setup I2C registers for an I2C operation specified by msgs, num.
447 *
448 * Must be called with i2c->lock held.
449 *
450 * @msgs: I2C msgs to process
451 * @num: Number of msgs
452 *
453 * returns: Number of I2C msgs processed or negative in case of error
454 */
455static int rk3x_i2c_setup(struct rk3x_i2c *i2c, struct i2c_msg *msgs, int num)
456{
457 u32 addr = (msgs[0].addr & 0x7f) << 1;
458 int ret = 0;
459
460 /*
461 * The I2C adapter can issue a small (len < 4) write packet before
462 * reading. This speeds up SMBus-style register reads.
463 * The MRXADDR/MRXRADDR hold the slave address and the slave register
464 * address in this case.
465 */
466
467 if (num >= 2 && msgs[0].len < 4 &&
468 !(msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD)) {
469 u32 reg_addr = 0;
470 int i;
471
472 dev_dbg(i2c->dev, "Combined write/read from addr 0x%x\n",
473 addr >> 1);
474
475 /* Fill MRXRADDR with the register address(es) */
476 for (i = 0; i < msgs[0].len; ++i) {
477 reg_addr |= msgs[0].buf[i] << (i * 8);
478 reg_addr |= REG_MRXADDR_VALID(i);
479 }
480
481 /* msgs[0] is handled by hw. */
482 i2c->msg = &msgs[1];
483
484 i2c->mode = REG_CON_MOD_REGISTER_TX;
485
486 i2c_writel(i2c, addr | REG_MRXADDR_VALID(0), REG_MRXADDR);
487 i2c_writel(i2c, reg_addr, REG_MRXRADDR);
488
489 ret = 2;
490 } else {
491 /*
492 * We'll have to do it the boring way and process the msgs
493 * one-by-one.
494 */
495
496 if (msgs[0].flags & I2C_M_RD) {
497 addr |= 1; /* set read bit */
498
499 /*
500 * We have to transmit the slave addr first. Use
501 * MOD_REGISTER_TX for that purpose.
502 */
503 i2c->mode = REG_CON_MOD_REGISTER_TX;
504 i2c_writel(i2c, addr | REG_MRXADDR_VALID(0),
505 REG_MRXADDR);
506 i2c_writel(i2c, 0, REG_MRXRADDR);
507 } else {
508 i2c->mode = REG_CON_MOD_TX;
509 }
510
511 i2c->msg = &msgs[0];
512
513 ret = 1;
514 }
515
516 i2c->addr = msgs[0].addr;
517 i2c->busy = true;
518 i2c->state = STATE_START;
519 i2c->processed = 0;
520 i2c->error = 0;
521
522 rk3x_i2c_clean_ipd(i2c);
523
524 return ret;
525}
526
527static int rk3x_i2c_xfer(struct i2c_adapter *adap,
528 struct i2c_msg *msgs, int num)
529{
530 struct rk3x_i2c *i2c = (struct rk3x_i2c *)adap->algo_data;
531 unsigned long timeout, flags;
532 int ret = 0;
533 int i;
534
535 spin_lock_irqsave(&i2c->lock, flags);
536
537 clk_enable(i2c->clk);
538
539 /* The clock rate might have changed, so setup the divider again */
540 rk3x_i2c_set_scl_rate(i2c, i2c->scl_frequency);
541
542 i2c->is_last_msg = false;
543
544 /*
545 * Process msgs. We can handle more than one message at once (see
546 * rk3x_i2c_setup()).
547 */
548 for (i = 0; i < num; i += ret) {
549 ret = rk3x_i2c_setup(i2c, msgs + i, num - i);
550
551 if (ret < 0) {
552 dev_err(i2c->dev, "rk3x_i2c_setup() failed\n");
553 break;
554 }
555
556 if (i + ret >= num)
557 i2c->is_last_msg = true;
558
559 spin_unlock_irqrestore(&i2c->lock, flags);
560
561 rk3x_i2c_start(i2c);
562
563 timeout = wait_event_timeout(i2c->wait, !i2c->busy,
564 msecs_to_jiffies(WAIT_TIMEOUT));
565
566 spin_lock_irqsave(&i2c->lock, flags);
567
568 if (timeout == 0) {
569 dev_err(i2c->dev, "timeout, ipd: 0x%02x, state: %d\n",
570 i2c_readl(i2c, REG_IPD), i2c->state);
571
572 /* Force a STOP condition without interrupt */
573 i2c_writel(i2c, 0, REG_IEN);
574 i2c_writel(i2c, REG_CON_EN | REG_CON_STOP, REG_CON);
575
576 i2c->state = STATE_IDLE;
577
578 ret = -ETIMEDOUT;
579 break;
580 }
581
582 if (i2c->error) {
583 ret = i2c->error;
584 break;
585 }
586 }
587
588 clk_disable(i2c->clk);
589 spin_unlock_irqrestore(&i2c->lock, flags);
590
591 return ret;
592}
593
594static u32 rk3x_i2c_func(struct i2c_adapter *adap)
595{
596 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
597}
598
599static const struct i2c_algorithm rk3x_i2c_algorithm = {
600 .master_xfer = rk3x_i2c_xfer,
601 .functionality = rk3x_i2c_func,
602};
603
604static struct rk3x_i2c_soc_data soc_data[3] = {
605 { .grf_offset = 0x154 }, /* rk3066 */
606 { .grf_offset = 0x0a4 }, /* rk3188 */
607 { .grf_offset = -1 }, /* no I2C switching needed */
608};
609
610static const struct of_device_id rk3x_i2c_match[] = {
611 { .compatible = "rockchip,rk3066-i2c", .data = (void *)&soc_data[0] },
612 { .compatible = "rockchip,rk3188-i2c", .data = (void *)&soc_data[1] },
613 { .compatible = "rockchip,rk3288-i2c", .data = (void *)&soc_data[2] },
c51bd6ac 614 {},
c41aa3ce
MS		 615};
616
617static int rk3x_i2c_probe(struct platform_device *pdev)
618{
619 struct device_node *np = pdev->dev.of_node;
620 const struct of_device_id *match;
621 struct rk3x_i2c *i2c;
622 struct resource *mem;
623 int ret = 0;
624 int bus_nr;
625 u32 value;
626 int irq;
627
628 i2c = devm_kzalloc(&pdev->dev, sizeof(struct rk3x_i2c), GFP_KERNEL);
629 if (!i2c)
630 return -ENOMEM;
631
632 match = of_match_node(rk3x_i2c_match, np);
633 i2c->soc_data = (struct rk3x_i2c_soc_data *)match->data;
634
635 if (of_property_read_u32(pdev->dev.of_node, "clock-frequency",
636 &i2c->scl_frequency)) {
637 dev_info(&pdev->dev, "using default SCL frequency: %d\n",
638 DEFAULT_SCL_RATE);
639 i2c->scl_frequency = DEFAULT_SCL_RATE;
640 }
641
642 if (i2c->scl_frequency == 0 || i2c->scl_frequency > 400 * 1000) {
643 dev_warn(&pdev->dev, "invalid SCL frequency specified.\n");
644 dev_warn(&pdev->dev, "using default SCL frequency: %d\n",
645 DEFAULT_SCL_RATE);
646 i2c->scl_frequency = DEFAULT_SCL_RATE;
647 }
648
649 strlcpy(i2c->adap.name, "rk3x-i2c", sizeof(i2c->adap.name));
650 i2c->adap.owner = THIS_MODULE;
651 i2c->adap.algo = &rk3x_i2c_algorithm;
652 i2c->adap.retries = 3;
653 i2c->adap.dev.of_node = np;
654 i2c->adap.algo_data = i2c;
655 i2c->adap.dev.parent = &pdev->dev;
656
657 i2c->dev = &pdev->dev;
658
659 spin_lock_init(&i2c->lock);
660 init_waitqueue_head(&i2c->wait);
661
662 i2c->clk = devm_clk_get(&pdev->dev, NULL);
663 if (IS_ERR(i2c->clk)) {
664 dev_err(&pdev->dev, "cannot get clock\n");
665 return PTR_ERR(i2c->clk);
666 }
667
668 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
669 i2c->regs = devm_ioremap_resource(&pdev->dev, mem);
670 if (IS_ERR(i2c->regs))
671 return PTR_ERR(i2c->regs);
672
673 /* Try to set the I2C adapter number from dt */
674 bus_nr = of_alias_get_id(np, "i2c");
675
676 /*
677 * Switch to new interface if the SoC also offers the old one.
678 * The control bit is located in the GRF register space.
679 */
680 if (i2c->soc_data->grf_offset >= 0) {
681 struct regmap *grf;
682
683 grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
684 if (IS_ERR(grf)) {
685 dev_err(&pdev->dev,
686 "rk3x-i2c needs 'rockchip,grf' property\n");
687 return PTR_ERR(grf);
688 }
689
690 if (bus_nr < 0) {
691 dev_err(&pdev->dev, "rk3x-i2c needs i2cX alias");
692 return -EINVAL;
693 }
694
695 /* 27+i: write mask, 11+i: value */
696 value = BIT(27 + bus_nr) | BIT(11 + bus_nr);
697
698 ret = regmap_write(grf, i2c->soc_data->grf_offset, value);
699 if (ret != 0) {
700 dev_err(i2c->dev, "Could not write to GRF: %d\n", ret);
701 return ret;
702 }
703 }
704
705 /* IRQ setup */
706 irq = platform_get_irq(pdev, 0);
707 if (irq < 0) {
708 dev_err(&pdev->dev, "cannot find rk3x IRQ\n");
709 return irq;
710 }
711
712 ret = devm_request_irq(&pdev->dev, irq, rk3x_i2c_irq,
713 0, dev_name(&pdev->dev), i2c);
714 if (ret < 0) {
715 dev_err(&pdev->dev, "cannot request IRQ\n");
716 return ret;
717 }
718
719 platform_set_drvdata(pdev, i2c);
720
721 ret = clk_prepare(i2c->clk);
722 if (ret < 0) {
723 dev_err(&pdev->dev, "Could not prepare clock\n");
724 return ret;
725 }
726
727 ret = i2c_add_adapter(&i2c->adap);
728 if (ret < 0) {
729 dev_err(&pdev->dev, "Could not register adapter\n");
730 goto err_clk;
731 }
732
733 dev_info(&pdev->dev, "Initialized RK3xxx I2C bus at %p\n", i2c->regs);
734
735 return 0;
736
737err_clk:
738 clk_unprepare(i2c->clk);
739 return ret;
740}
741
742static int rk3x_i2c_remove(struct platform_device *pdev)
743{
744 struct rk3x_i2c *i2c = platform_get_drvdata(pdev);
745
746 i2c_del_adapter(&i2c->adap);
747 clk_unprepare(i2c->clk);
748
749 return 0;
750}
751
752static struct platform_driver rk3x_i2c_driver = {
753 .probe = rk3x_i2c_probe,
754 .remove = rk3x_i2c_remove,
755 .driver = {
756 .owner = THIS_MODULE,
757 .name = "rk3x-i2c",
758 .of_match_table = rk3x_i2c_match,
759 },
760};
761
762module_platform_driver(rk3x_i2c_driver);
763
764MODULE_DESCRIPTION("Rockchip RK3xxx I2C Bus driver");
765MODULE_AUTHOR("Max Schwarz <max.schwarz@online.de>");
766MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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