Commit | Line | Data |
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1da177e4 LT |
1 | /* linux/drivers/i2c/busses/i2c-s3c2410.c |
2 | * | |
c564e6ae | 3 | * Copyright (C) 2004,2005,2009 Simtec Electronics |
1da177e4 LT |
4 | * Ben Dooks <ben@simtec.co.uk> |
5 | * | |
6 | * S3C2410 I2C Controller | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | #include <linux/kernel.h> | |
24 | #include <linux/module.h> | |
25 | ||
26 | #include <linux/i2c.h> | |
1da177e4 LT |
27 | #include <linux/init.h> |
28 | #include <linux/time.h> | |
29 | #include <linux/interrupt.h> | |
1da177e4 LT |
30 | #include <linux/delay.h> |
31 | #include <linux/errno.h> | |
32 | #include <linux/err.h> | |
d052d1be | 33 | #include <linux/platform_device.h> |
c62c3ca5 | 34 | #include <linux/pm_runtime.h> |
f8ce2547 | 35 | #include <linux/clk.h> |
61c7cff8 | 36 | #include <linux/cpufreq.h> |
5a0e3ad6 | 37 | #include <linux/slab.h> |
21782180 | 38 | #include <linux/io.h> |
5a5f5080 TA |
39 | #include <linux/of_i2c.h> |
40 | #include <linux/of_gpio.h> | |
1da177e4 | 41 | |
1da177e4 | 42 | #include <asm/irq.h> |
1da177e4 | 43 | |
9498cb79 BD |
44 | #include <plat/regs-iic.h> |
45 | #include <plat/iic.h> | |
1da177e4 | 46 | |
27452498 KL |
47 | /* Treat S3C2410 as baseline hardware, anything else is supported via quirks */ |
48 | #define QUIRK_S3C2440 (1 << 0) | |
1da177e4 | 49 | |
27452498 | 50 | /* i2c controller state */ |
1da177e4 LT |
51 | enum s3c24xx_i2c_state { |
52 | STATE_IDLE, | |
53 | STATE_START, | |
54 | STATE_READ, | |
55 | STATE_WRITE, | |
56 | STATE_STOP | |
57 | }; | |
58 | ||
59 | struct s3c24xx_i2c { | |
60 | spinlock_t lock; | |
61 | wait_queue_head_t wait; | |
27452498 | 62 | unsigned int quirks; |
be44f01e | 63 | unsigned int suspended:1; |
1da177e4 LT |
64 | |
65 | struct i2c_msg *msg; | |
66 | unsigned int msg_num; | |
67 | unsigned int msg_idx; | |
68 | unsigned int msg_ptr; | |
69 | ||
e00a8cdf | 70 | unsigned int tx_setup; |
e0d1ec97 | 71 | unsigned int irq; |
e00a8cdf | 72 | |
1da177e4 | 73 | enum s3c24xx_i2c_state state; |
61c7cff8 | 74 | unsigned long clkrate; |
1da177e4 LT |
75 | |
76 | void __iomem *regs; | |
77 | struct clk *clk; | |
78 | struct device *dev; | |
1da177e4 LT |
79 | struct resource *ioarea; |
80 | struct i2c_adapter adap; | |
61c7cff8 | 81 | |
4fd81eb2 | 82 | struct s3c2410_platform_i2c *pdata; |
5a5f5080 | 83 | int gpios[2]; |
61c7cff8 BD |
84 | #ifdef CONFIG_CPU_FREQ |
85 | struct notifier_block freq_transition; | |
86 | #endif | |
1da177e4 LT |
87 | }; |
88 | ||
27452498 KL |
89 | static struct platform_device_id s3c24xx_driver_ids[] = { |
90 | { | |
91 | .name = "s3c2410-i2c", | |
92 | .driver_data = 0, | |
93 | }, { | |
94 | .name = "s3c2440-i2c", | |
95 | .driver_data = QUIRK_S3C2440, | |
96 | }, { }, | |
97 | }; | |
98 | MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids); | |
99 | ||
100 | #ifdef CONFIG_OF | |
101 | static const struct of_device_id s3c24xx_i2c_match[] = { | |
102 | { .compatible = "samsung,s3c2410-i2c", .data = (void *)0 }, | |
103 | { .compatible = "samsung,s3c2440-i2c", .data = (void *)QUIRK_S3C2440 }, | |
104 | {}, | |
105 | }; | |
106 | MODULE_DEVICE_TABLE(of, s3c24xx_i2c_match); | |
107 | #endif | |
1da177e4 | 108 | |
27452498 | 109 | /* s3c24xx_get_device_quirks |
1da177e4 | 110 | * |
27452498 | 111 | * Get controller type either from device tree or platform device variant. |
1da177e4 LT |
112 | */ |
113 | ||
27452498 | 114 | static inline unsigned int s3c24xx_get_device_quirks(struct platform_device *pdev) |
1da177e4 | 115 | { |
27452498 KL |
116 | if (pdev->dev.of_node) { |
117 | const struct of_device_id *match; | |
118 | match = of_match_node(&s3c24xx_i2c_match, pdev->dev.of_node); | |
119 | return (unsigned int)match->data; | |
120 | } | |
5a5f5080 | 121 | |
27452498 | 122 | return platform_get_device_id(pdev)->driver_data; |
1da177e4 LT |
123 | } |
124 | ||
1da177e4 LT |
125 | /* s3c24xx_i2c_master_complete |
126 | * | |
127 | * complete the message and wake up the caller, using the given return code, | |
128 | * or zero to mean ok. | |
129 | */ | |
130 | ||
131 | static inline void s3c24xx_i2c_master_complete(struct s3c24xx_i2c *i2c, int ret) | |
132 | { | |
133 | dev_dbg(i2c->dev, "master_complete %d\n", ret); | |
134 | ||
135 | i2c->msg_ptr = 0; | |
136 | i2c->msg = NULL; | |
3d0911bf | 137 | i2c->msg_idx++; |
1da177e4 LT |
138 | i2c->msg_num = 0; |
139 | if (ret) | |
140 | i2c->msg_idx = ret; | |
141 | ||
142 | wake_up(&i2c->wait); | |
143 | } | |
144 | ||
145 | static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c) | |
146 | { | |
147 | unsigned long tmp; | |
3d0911bf | 148 | |
1da177e4 LT |
149 | tmp = readl(i2c->regs + S3C2410_IICCON); |
150 | writel(tmp & ~S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON); | |
1da177e4 LT |
151 | } |
152 | ||
153 | static inline void s3c24xx_i2c_enable_ack(struct s3c24xx_i2c *i2c) | |
154 | { | |
155 | unsigned long tmp; | |
3d0911bf | 156 | |
1da177e4 LT |
157 | tmp = readl(i2c->regs + S3C2410_IICCON); |
158 | writel(tmp | S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON); | |
1da177e4 LT |
159 | } |
160 | ||
161 | /* irq enable/disable functions */ | |
162 | ||
163 | static inline void s3c24xx_i2c_disable_irq(struct s3c24xx_i2c *i2c) | |
164 | { | |
165 | unsigned long tmp; | |
3d0911bf | 166 | |
1da177e4 LT |
167 | tmp = readl(i2c->regs + S3C2410_IICCON); |
168 | writel(tmp & ~S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON); | |
169 | } | |
170 | ||
171 | static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c *i2c) | |
172 | { | |
173 | unsigned long tmp; | |
3d0911bf | 174 | |
1da177e4 LT |
175 | tmp = readl(i2c->regs + S3C2410_IICCON); |
176 | writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON); | |
177 | } | |
178 | ||
179 | ||
180 | /* s3c24xx_i2c_message_start | |
181 | * | |
3d0911bf | 182 | * put the start of a message onto the bus |
1da177e4 LT |
183 | */ |
184 | ||
3d0911bf | 185 | static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c, |
1da177e4 LT |
186 | struct i2c_msg *msg) |
187 | { | |
188 | unsigned int addr = (msg->addr & 0x7f) << 1; | |
189 | unsigned long stat; | |
190 | unsigned long iiccon; | |
191 | ||
192 | stat = 0; | |
193 | stat |= S3C2410_IICSTAT_TXRXEN; | |
194 | ||
195 | if (msg->flags & I2C_M_RD) { | |
196 | stat |= S3C2410_IICSTAT_MASTER_RX; | |
197 | addr |= 1; | |
198 | } else | |
199 | stat |= S3C2410_IICSTAT_MASTER_TX; | |
200 | ||
201 | if (msg->flags & I2C_M_REV_DIR_ADDR) | |
202 | addr ^= 1; | |
203 | ||
3d0911bf | 204 | /* todo - check for wether ack wanted or not */ |
1da177e4 LT |
205 | s3c24xx_i2c_enable_ack(i2c); |
206 | ||
207 | iiccon = readl(i2c->regs + S3C2410_IICCON); | |
208 | writel(stat, i2c->regs + S3C2410_IICSTAT); | |
3d0911bf | 209 | |
1da177e4 LT |
210 | dev_dbg(i2c->dev, "START: %08lx to IICSTAT, %02x to DS\n", stat, addr); |
211 | writeb(addr, i2c->regs + S3C2410_IICDS); | |
3d0911bf | 212 | |
e00a8cdf BD |
213 | /* delay here to ensure the data byte has gotten onto the bus |
214 | * before the transaction is started */ | |
215 | ||
216 | ndelay(i2c->tx_setup); | |
217 | ||
1da177e4 LT |
218 | dev_dbg(i2c->dev, "iiccon, %08lx\n", iiccon); |
219 | writel(iiccon, i2c->regs + S3C2410_IICCON); | |
3d0911bf BD |
220 | |
221 | stat |= S3C2410_IICSTAT_START; | |
1da177e4 LT |
222 | writel(stat, i2c->regs + S3C2410_IICSTAT); |
223 | } | |
224 | ||
225 | static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c *i2c, int ret) | |
226 | { | |
227 | unsigned long iicstat = readl(i2c->regs + S3C2410_IICSTAT); | |
228 | ||
229 | dev_dbg(i2c->dev, "STOP\n"); | |
230 | ||
231 | /* stop the transfer */ | |
3d0911bf | 232 | iicstat &= ~S3C2410_IICSTAT_START; |
1da177e4 | 233 | writel(iicstat, i2c->regs + S3C2410_IICSTAT); |
3d0911bf | 234 | |
1da177e4 | 235 | i2c->state = STATE_STOP; |
3d0911bf | 236 | |
1da177e4 LT |
237 | s3c24xx_i2c_master_complete(i2c, ret); |
238 | s3c24xx_i2c_disable_irq(i2c); | |
239 | } | |
240 | ||
241 | /* helper functions to determine the current state in the set of | |
242 | * messages we are sending */ | |
243 | ||
244 | /* is_lastmsg() | |
245 | * | |
3d0911bf | 246 | * returns TRUE if the current message is the last in the set |
1da177e4 LT |
247 | */ |
248 | ||
249 | static inline int is_lastmsg(struct s3c24xx_i2c *i2c) | |
250 | { | |
251 | return i2c->msg_idx >= (i2c->msg_num - 1); | |
252 | } | |
253 | ||
254 | /* is_msglast | |
255 | * | |
256 | * returns TRUE if we this is the last byte in the current message | |
257 | */ | |
258 | ||
259 | static inline int is_msglast(struct s3c24xx_i2c *i2c) | |
260 | { | |
261 | return i2c->msg_ptr == i2c->msg->len-1; | |
262 | } | |
263 | ||
264 | /* is_msgend | |
265 | * | |
266 | * returns TRUE if we reached the end of the current message | |
267 | */ | |
268 | ||
269 | static inline int is_msgend(struct s3c24xx_i2c *i2c) | |
270 | { | |
271 | return i2c->msg_ptr >= i2c->msg->len; | |
272 | } | |
273 | ||
19820510 | 274 | /* i2c_s3c_irq_nextbyte |
1da177e4 LT |
275 | * |
276 | * process an interrupt and work out what to do | |
277 | */ | |
278 | ||
19820510 | 279 | static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat) |
1da177e4 LT |
280 | { |
281 | unsigned long tmp; | |
282 | unsigned char byte; | |
283 | int ret = 0; | |
284 | ||
285 | switch (i2c->state) { | |
286 | ||
287 | case STATE_IDLE: | |
08882d20 | 288 | dev_err(i2c->dev, "%s: called in STATE_IDLE\n", __func__); |
1da177e4 | 289 | goto out; |
1da177e4 LT |
290 | |
291 | case STATE_STOP: | |
08882d20 | 292 | dev_err(i2c->dev, "%s: called in STATE_STOP\n", __func__); |
3d0911bf | 293 | s3c24xx_i2c_disable_irq(i2c); |
1da177e4 LT |
294 | goto out_ack; |
295 | ||
296 | case STATE_START: | |
297 | /* last thing we did was send a start condition on the | |
298 | * bus, or started a new i2c message | |
299 | */ | |
3d0911bf | 300 | |
63f5c289 | 301 | if (iicstat & S3C2410_IICSTAT_LASTBIT && |
1da177e4 LT |
302 | !(i2c->msg->flags & I2C_M_IGNORE_NAK)) { |
303 | /* ack was not received... */ | |
304 | ||
305 | dev_dbg(i2c->dev, "ack was not received\n"); | |
63f5c289 | 306 | s3c24xx_i2c_stop(i2c, -ENXIO); |
1da177e4 LT |
307 | goto out_ack; |
308 | } | |
309 | ||
310 | if (i2c->msg->flags & I2C_M_RD) | |
311 | i2c->state = STATE_READ; | |
312 | else | |
313 | i2c->state = STATE_WRITE; | |
314 | ||
315 | /* terminate the transfer if there is nothing to do | |
63f5c289 | 316 | * as this is used by the i2c probe to find devices. */ |
1da177e4 LT |
317 | |
318 | if (is_lastmsg(i2c) && i2c->msg->len == 0) { | |
319 | s3c24xx_i2c_stop(i2c, 0); | |
320 | goto out_ack; | |
321 | } | |
322 | ||
323 | if (i2c->state == STATE_READ) | |
324 | goto prepare_read; | |
325 | ||
3d0911bf | 326 | /* fall through to the write state, as we will need to |
1da177e4 LT |
327 | * send a byte as well */ |
328 | ||
329 | case STATE_WRITE: | |
330 | /* we are writing data to the device... check for the | |
331 | * end of the message, and if so, work out what to do | |
332 | */ | |
333 | ||
2709781b BD |
334 | if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) { |
335 | if (iicstat & S3C2410_IICSTAT_LASTBIT) { | |
336 | dev_dbg(i2c->dev, "WRITE: No Ack\n"); | |
337 | ||
338 | s3c24xx_i2c_stop(i2c, -ECONNREFUSED); | |
339 | goto out_ack; | |
340 | } | |
341 | } | |
342 | ||
3d0911bf | 343 | retry_write: |
2709781b | 344 | |
1da177e4 LT |
345 | if (!is_msgend(i2c)) { |
346 | byte = i2c->msg->buf[i2c->msg_ptr++]; | |
347 | writeb(byte, i2c->regs + S3C2410_IICDS); | |
e00a8cdf BD |
348 | |
349 | /* delay after writing the byte to allow the | |
350 | * data setup time on the bus, as writing the | |
351 | * data to the register causes the first bit | |
352 | * to appear on SDA, and SCL will change as | |
353 | * soon as the interrupt is acknowledged */ | |
354 | ||
355 | ndelay(i2c->tx_setup); | |
356 | ||
1da177e4 LT |
357 | } else if (!is_lastmsg(i2c)) { |
358 | /* we need to go to the next i2c message */ | |
359 | ||
360 | dev_dbg(i2c->dev, "WRITE: Next Message\n"); | |
361 | ||
362 | i2c->msg_ptr = 0; | |
3d0911bf | 363 | i2c->msg_idx++; |
1da177e4 | 364 | i2c->msg++; |
3d0911bf | 365 | |
1da177e4 LT |
366 | /* check to see if we need to do another message */ |
367 | if (i2c->msg->flags & I2C_M_NOSTART) { | |
368 | ||
369 | if (i2c->msg->flags & I2C_M_RD) { | |
370 | /* cannot do this, the controller | |
371 | * forces us to send a new START | |
372 | * when we change direction */ | |
373 | ||
374 | s3c24xx_i2c_stop(i2c, -EINVAL); | |
375 | } | |
376 | ||
377 | goto retry_write; | |
378 | } else { | |
1da177e4 LT |
379 | /* send the new start */ |
380 | s3c24xx_i2c_message_start(i2c, i2c->msg); | |
381 | i2c->state = STATE_START; | |
382 | } | |
383 | ||
384 | } else { | |
385 | /* send stop */ | |
386 | ||
387 | s3c24xx_i2c_stop(i2c, 0); | |
388 | } | |
389 | break; | |
390 | ||
391 | case STATE_READ: | |
3d0911bf | 392 | /* we have a byte of data in the data register, do |
1da177e4 LT |
393 | * something with it, and then work out wether we are |
394 | * going to do any more read/write | |
395 | */ | |
396 | ||
1da177e4 LT |
397 | byte = readb(i2c->regs + S3C2410_IICDS); |
398 | i2c->msg->buf[i2c->msg_ptr++] = byte; | |
399 | ||
3d0911bf | 400 | prepare_read: |
1da177e4 LT |
401 | if (is_msglast(i2c)) { |
402 | /* last byte of buffer */ | |
403 | ||
404 | if (is_lastmsg(i2c)) | |
405 | s3c24xx_i2c_disable_ack(i2c); | |
3d0911bf | 406 | |
1da177e4 LT |
407 | } else if (is_msgend(i2c)) { |
408 | /* ok, we've read the entire buffer, see if there | |
409 | * is anything else we need to do */ | |
410 | ||
411 | if (is_lastmsg(i2c)) { | |
412 | /* last message, send stop and complete */ | |
413 | dev_dbg(i2c->dev, "READ: Send Stop\n"); | |
414 | ||
415 | s3c24xx_i2c_stop(i2c, 0); | |
416 | } else { | |
417 | /* go to the next transfer */ | |
418 | dev_dbg(i2c->dev, "READ: Next Transfer\n"); | |
419 | ||
420 | i2c->msg_ptr = 0; | |
421 | i2c->msg_idx++; | |
422 | i2c->msg++; | |
423 | } | |
424 | } | |
425 | ||
426 | break; | |
427 | } | |
428 | ||
429 | /* acknowlegde the IRQ and get back on with the work */ | |
430 | ||
431 | out_ack: | |
3d0911bf | 432 | tmp = readl(i2c->regs + S3C2410_IICCON); |
1da177e4 LT |
433 | tmp &= ~S3C2410_IICCON_IRQPEND; |
434 | writel(tmp, i2c->regs + S3C2410_IICCON); | |
435 | out: | |
436 | return ret; | |
437 | } | |
438 | ||
439 | /* s3c24xx_i2c_irq | |
440 | * | |
441 | * top level IRQ servicing routine | |
442 | */ | |
443 | ||
7d12e780 | 444 | static irqreturn_t s3c24xx_i2c_irq(int irqno, void *dev_id) |
1da177e4 LT |
445 | { |
446 | struct s3c24xx_i2c *i2c = dev_id; | |
447 | unsigned long status; | |
448 | unsigned long tmp; | |
449 | ||
450 | status = readl(i2c->regs + S3C2410_IICSTAT); | |
451 | ||
452 | if (status & S3C2410_IICSTAT_ARBITR) { | |
3d0911bf | 453 | /* deal with arbitration loss */ |
1da177e4 LT |
454 | dev_err(i2c->dev, "deal with arbitration loss\n"); |
455 | } | |
456 | ||
457 | if (i2c->state == STATE_IDLE) { | |
458 | dev_dbg(i2c->dev, "IRQ: error i2c->state == IDLE\n"); | |
459 | ||
3d0911bf | 460 | tmp = readl(i2c->regs + S3C2410_IICCON); |
1da177e4 LT |
461 | tmp &= ~S3C2410_IICCON_IRQPEND; |
462 | writel(tmp, i2c->regs + S3C2410_IICCON); | |
463 | goto out; | |
464 | } | |
3d0911bf | 465 | |
1da177e4 LT |
466 | /* pretty much this leaves us with the fact that we've |
467 | * transmitted or received whatever byte we last sent */ | |
468 | ||
19820510 | 469 | i2c_s3c_irq_nextbyte(i2c, status); |
1da177e4 LT |
470 | |
471 | out: | |
472 | return IRQ_HANDLED; | |
473 | } | |
474 | ||
475 | ||
476 | /* s3c24xx_i2c_set_master | |
477 | * | |
478 | * get the i2c bus for a master transaction | |
479 | */ | |
480 | ||
481 | static int s3c24xx_i2c_set_master(struct s3c24xx_i2c *i2c) | |
482 | { | |
483 | unsigned long iicstat; | |
484 | int timeout = 400; | |
485 | ||
486 | while (timeout-- > 0) { | |
487 | iicstat = readl(i2c->regs + S3C2410_IICSTAT); | |
3d0911bf | 488 | |
1da177e4 LT |
489 | if (!(iicstat & S3C2410_IICSTAT_BUSBUSY)) |
490 | return 0; | |
491 | ||
492 | msleep(1); | |
493 | } | |
494 | ||
1da177e4 LT |
495 | return -ETIMEDOUT; |
496 | } | |
497 | ||
498 | /* s3c24xx_i2c_doxfer | |
499 | * | |
500 | * this starts an i2c transfer | |
501 | */ | |
502 | ||
3d0911bf BD |
503 | static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c, |
504 | struct i2c_msg *msgs, int num) | |
1da177e4 | 505 | { |
1bc2962e MB |
506 | unsigned long iicstat, timeout; |
507 | int spins = 20; | |
1da177e4 LT |
508 | int ret; |
509 | ||
be44f01e | 510 | if (i2c->suspended) |
61c7cff8 BD |
511 | return -EIO; |
512 | ||
1da177e4 LT |
513 | ret = s3c24xx_i2c_set_master(i2c); |
514 | if (ret != 0) { | |
515 | dev_err(i2c->dev, "cannot get bus (error %d)\n", ret); | |
516 | ret = -EAGAIN; | |
517 | goto out; | |
518 | } | |
519 | ||
520 | spin_lock_irq(&i2c->lock); | |
521 | ||
522 | i2c->msg = msgs; | |
523 | i2c->msg_num = num; | |
524 | i2c->msg_ptr = 0; | |
525 | i2c->msg_idx = 0; | |
526 | i2c->state = STATE_START; | |
527 | ||
528 | s3c24xx_i2c_enable_irq(i2c); | |
529 | s3c24xx_i2c_message_start(i2c, msgs); | |
530 | spin_unlock_irq(&i2c->lock); | |
3d0911bf | 531 | |
1da177e4 LT |
532 | timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5); |
533 | ||
534 | ret = i2c->msg_idx; | |
535 | ||
3d0911bf | 536 | /* having these next two as dev_err() makes life very |
1da177e4 LT |
537 | * noisy when doing an i2cdetect */ |
538 | ||
539 | if (timeout == 0) | |
540 | dev_dbg(i2c->dev, "timeout\n"); | |
541 | else if (ret != num) | |
542 | dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret); | |
543 | ||
544 | /* ensure the stop has been through the bus */ | |
545 | ||
1bc2962e MB |
546 | dev_dbg(i2c->dev, "waiting for bus idle\n"); |
547 | ||
548 | /* first, try busy waiting briefly */ | |
549 | do { | |
37de03ea | 550 | cpu_relax(); |
1bc2962e MB |
551 | iicstat = readl(i2c->regs + S3C2410_IICSTAT); |
552 | } while ((iicstat & S3C2410_IICSTAT_START) && --spins); | |
553 | ||
554 | /* if that timed out sleep */ | |
555 | if (!spins) { | |
556 | msleep(1); | |
557 | iicstat = readl(i2c->regs + S3C2410_IICSTAT); | |
558 | } | |
559 | ||
560 | if (iicstat & S3C2410_IICSTAT_START) | |
561 | dev_warn(i2c->dev, "timeout waiting for bus idle\n"); | |
1da177e4 LT |
562 | |
563 | out: | |
564 | return ret; | |
565 | } | |
566 | ||
567 | /* s3c24xx_i2c_xfer | |
568 | * | |
569 | * first port of call from the i2c bus code when an message needs | |
44bbe87e | 570 | * transferring across the i2c bus. |
1da177e4 LT |
571 | */ |
572 | ||
573 | static int s3c24xx_i2c_xfer(struct i2c_adapter *adap, | |
574 | struct i2c_msg *msgs, int num) | |
575 | { | |
576 | struct s3c24xx_i2c *i2c = (struct s3c24xx_i2c *)adap->algo_data; | |
577 | int retry; | |
578 | int ret; | |
579 | ||
c62c3ca5 | 580 | pm_runtime_get_sync(&adap->dev); |
d2360b8e APR |
581 | clk_enable(i2c->clk); |
582 | ||
1da177e4 LT |
583 | for (retry = 0; retry < adap->retries; retry++) { |
584 | ||
585 | ret = s3c24xx_i2c_doxfer(i2c, msgs, num); | |
586 | ||
d2360b8e APR |
587 | if (ret != -EAGAIN) { |
588 | clk_disable(i2c->clk); | |
c62c3ca5 | 589 | pm_runtime_put_sync(&adap->dev); |
1da177e4 | 590 | return ret; |
d2360b8e | 591 | } |
1da177e4 LT |
592 | |
593 | dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry); | |
594 | ||
595 | udelay(100); | |
596 | } | |
597 | ||
d2360b8e | 598 | clk_disable(i2c->clk); |
c62c3ca5 | 599 | pm_runtime_put_sync(&adap->dev); |
1da177e4 LT |
600 | return -EREMOTEIO; |
601 | } | |
602 | ||
603 | /* declare our i2c functionality */ | |
604 | static u32 s3c24xx_i2c_func(struct i2c_adapter *adap) | |
605 | { | |
606 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING; | |
607 | } | |
608 | ||
609 | /* i2c bus registration info */ | |
610 | ||
8f9082c5 | 611 | static const struct i2c_algorithm s3c24xx_i2c_algorithm = { |
1da177e4 LT |
612 | .master_xfer = s3c24xx_i2c_xfer, |
613 | .functionality = s3c24xx_i2c_func, | |
614 | }; | |
615 | ||
1da177e4 LT |
616 | /* s3c24xx_i2c_calcdivisor |
617 | * | |
618 | * return the divisor settings for a given frequency | |
619 | */ | |
620 | ||
621 | static int s3c24xx_i2c_calcdivisor(unsigned long clkin, unsigned int wanted, | |
622 | unsigned int *div1, unsigned int *divs) | |
623 | { | |
624 | unsigned int calc_divs = clkin / wanted; | |
625 | unsigned int calc_div1; | |
626 | ||
627 | if (calc_divs > (16*16)) | |
628 | calc_div1 = 512; | |
629 | else | |
630 | calc_div1 = 16; | |
631 | ||
632 | calc_divs += calc_div1-1; | |
633 | calc_divs /= calc_div1; | |
634 | ||
635 | if (calc_divs == 0) | |
636 | calc_divs = 1; | |
637 | if (calc_divs > 17) | |
638 | calc_divs = 17; | |
639 | ||
640 | *divs = calc_divs; | |
641 | *div1 = calc_div1; | |
642 | ||
643 | return clkin / (calc_divs * calc_div1); | |
644 | } | |
645 | ||
61c7cff8 | 646 | /* s3c24xx_i2c_clockrate |
1da177e4 LT |
647 | * |
648 | * work out a divisor for the user requested frequency setting, | |
649 | * either by the requested frequency, or scanning the acceptable | |
650 | * range of frequencies until something is found | |
651 | */ | |
652 | ||
61c7cff8 | 653 | static int s3c24xx_i2c_clockrate(struct s3c24xx_i2c *i2c, unsigned int *got) |
1da177e4 | 654 | { |
4fd81eb2 | 655 | struct s3c2410_platform_i2c *pdata = i2c->pdata; |
1da177e4 | 656 | unsigned long clkin = clk_get_rate(i2c->clk); |
1da177e4 | 657 | unsigned int divs, div1; |
c564e6ae | 658 | unsigned long target_frequency; |
61c7cff8 | 659 | u32 iiccon; |
1da177e4 | 660 | int freq; |
1da177e4 | 661 | |
61c7cff8 | 662 | i2c->clkrate = clkin; |
1da177e4 | 663 | clkin /= 1000; /* clkin now in KHz */ |
3d0911bf | 664 | |
c564e6ae | 665 | dev_dbg(i2c->dev, "pdata desired frequency %lu\n", pdata->frequency); |
1da177e4 | 666 | |
c564e6ae | 667 | target_frequency = pdata->frequency ? pdata->frequency : 100000; |
1da177e4 | 668 | |
c564e6ae | 669 | target_frequency /= 1000; /* Target frequency now in KHz */ |
1da177e4 | 670 | |
c564e6ae | 671 | freq = s3c24xx_i2c_calcdivisor(clkin, target_frequency, &div1, &divs); |
1da177e4 | 672 | |
c564e6ae DS |
673 | if (freq > target_frequency) { |
674 | dev_err(i2c->dev, | |
675 | "Unable to achieve desired frequency %luKHz." \ | |
676 | " Lowest achievable %dKHz\n", target_frequency, freq); | |
677 | return -EINVAL; | |
1da177e4 LT |
678 | } |
679 | ||
1da177e4 | 680 | *got = freq; |
61c7cff8 BD |
681 | |
682 | iiccon = readl(i2c->regs + S3C2410_IICCON); | |
683 | iiccon &= ~(S3C2410_IICCON_SCALEMASK | S3C2410_IICCON_TXDIV_512); | |
684 | iiccon |= (divs-1); | |
685 | ||
686 | if (div1 == 512) | |
687 | iiccon |= S3C2410_IICCON_TXDIV_512; | |
688 | ||
689 | writel(iiccon, i2c->regs + S3C2410_IICCON); | |
690 | ||
27452498 | 691 | if (i2c->quirks & QUIRK_S3C2440) { |
a192f715 BD |
692 | unsigned long sda_delay; |
693 | ||
694 | if (pdata->sda_delay) { | |
7031307a MH |
695 | sda_delay = clkin * pdata->sda_delay; |
696 | sda_delay = DIV_ROUND_UP(sda_delay, 1000000); | |
a192f715 BD |
697 | sda_delay = DIV_ROUND_UP(sda_delay, 5); |
698 | if (sda_delay > 3) | |
699 | sda_delay = 3; | |
700 | sda_delay |= S3C2410_IICLC_FILTER_ON; | |
701 | } else | |
702 | sda_delay = 0; | |
703 | ||
704 | dev_dbg(i2c->dev, "IICLC=%08lx\n", sda_delay); | |
705 | writel(sda_delay, i2c->regs + S3C2440_IICLC); | |
706 | } | |
707 | ||
61c7cff8 BD |
708 | return 0; |
709 | } | |
710 | ||
711 | #ifdef CONFIG_CPU_FREQ | |
712 | ||
713 | #define freq_to_i2c(_n) container_of(_n, struct s3c24xx_i2c, freq_transition) | |
714 | ||
715 | static int s3c24xx_i2c_cpufreq_transition(struct notifier_block *nb, | |
716 | unsigned long val, void *data) | |
717 | { | |
718 | struct s3c24xx_i2c *i2c = freq_to_i2c(nb); | |
719 | unsigned long flags; | |
720 | unsigned int got; | |
721 | int delta_f; | |
722 | int ret; | |
723 | ||
724 | delta_f = clk_get_rate(i2c->clk) - i2c->clkrate; | |
725 | ||
726 | /* if we're post-change and the input clock has slowed down | |
727 | * or at pre-change and the clock is about to speed up, then | |
728 | * adjust our clock rate. <0 is slow, >0 speedup. | |
729 | */ | |
730 | ||
731 | if ((val == CPUFREQ_POSTCHANGE && delta_f < 0) || | |
732 | (val == CPUFREQ_PRECHANGE && delta_f > 0)) { | |
733 | spin_lock_irqsave(&i2c->lock, flags); | |
734 | ret = s3c24xx_i2c_clockrate(i2c, &got); | |
735 | spin_unlock_irqrestore(&i2c->lock, flags); | |
736 | ||
737 | if (ret < 0) | |
738 | dev_err(i2c->dev, "cannot find frequency\n"); | |
739 | else | |
740 | dev_info(i2c->dev, "setting freq %d\n", got); | |
741 | } | |
742 | ||
1da177e4 LT |
743 | return 0; |
744 | } | |
745 | ||
61c7cff8 BD |
746 | static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c) |
747 | { | |
748 | i2c->freq_transition.notifier_call = s3c24xx_i2c_cpufreq_transition; | |
749 | ||
750 | return cpufreq_register_notifier(&i2c->freq_transition, | |
751 | CPUFREQ_TRANSITION_NOTIFIER); | |
752 | } | |
753 | ||
754 | static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c) | |
755 | { | |
756 | cpufreq_unregister_notifier(&i2c->freq_transition, | |
757 | CPUFREQ_TRANSITION_NOTIFIER); | |
758 | } | |
759 | ||
760 | #else | |
761 | static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c) | |
762 | { | |
1da177e4 LT |
763 | return 0; |
764 | } | |
765 | ||
61c7cff8 BD |
766 | static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c) |
767 | { | |
768 | } | |
769 | #endif | |
770 | ||
5a5f5080 TA |
771 | #ifdef CONFIG_OF |
772 | static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c *i2c) | |
773 | { | |
774 | int idx, gpio, ret; | |
775 | ||
776 | for (idx = 0; idx < 2; idx++) { | |
777 | gpio = of_get_gpio(i2c->dev->of_node, idx); | |
778 | if (!gpio_is_valid(gpio)) { | |
779 | dev_err(i2c->dev, "invalid gpio[%d]: %d\n", idx, gpio); | |
780 | goto free_gpio; | |
781 | } | |
782 | ||
783 | ret = gpio_request(gpio, "i2c-bus"); | |
784 | if (ret) { | |
785 | dev_err(i2c->dev, "gpio [%d] request failed\n", gpio); | |
786 | goto free_gpio; | |
787 | } | |
788 | } | |
789 | return 0; | |
790 | ||
791 | free_gpio: | |
792 | while (--idx >= 0) | |
793 | gpio_free(i2c->gpios[idx]); | |
794 | return -EINVAL; | |
795 | } | |
796 | ||
797 | static void s3c24xx_i2c_dt_gpio_free(struct s3c24xx_i2c *i2c) | |
798 | { | |
799 | unsigned int idx; | |
800 | for (idx = 0; idx < 2; idx++) | |
801 | gpio_free(i2c->gpios[idx]); | |
802 | } | |
803 | #else | |
804 | static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c *i2c) | |
805 | { | |
8ebe661d | 806 | return 0; |
5a5f5080 TA |
807 | } |
808 | ||
809 | static void s3c24xx_i2c_dt_gpio_free(struct s3c24xx_i2c *i2c) | |
810 | { | |
811 | } | |
812 | #endif | |
813 | ||
1da177e4 LT |
814 | /* s3c24xx_i2c_init |
815 | * | |
3d0911bf | 816 | * initialise the controller, set the IO lines and frequency |
1da177e4 LT |
817 | */ |
818 | ||
819 | static int s3c24xx_i2c_init(struct s3c24xx_i2c *i2c) | |
820 | { | |
821 | unsigned long iicon = S3C2410_IICCON_IRQEN | S3C2410_IICCON_ACKEN; | |
822 | struct s3c2410_platform_i2c *pdata; | |
823 | unsigned int freq; | |
824 | ||
825 | /* get the plafrom data */ | |
826 | ||
4fd81eb2 | 827 | pdata = i2c->pdata; |
1da177e4 LT |
828 | |
829 | /* inititalise the gpio */ | |
830 | ||
8be310a6 BD |
831 | if (pdata->cfg_gpio) |
832 | pdata->cfg_gpio(to_platform_device(i2c->dev)); | |
5a5f5080 TA |
833 | else |
834 | if (s3c24xx_i2c_parse_dt_gpio(i2c)) | |
835 | return -EINVAL; | |
1da177e4 LT |
836 | |
837 | /* write slave address */ | |
3d0911bf | 838 | |
1da177e4 LT |
839 | writeb(pdata->slave_addr, i2c->regs + S3C2410_IICADD); |
840 | ||
841 | dev_info(i2c->dev, "slave address 0x%02x\n", pdata->slave_addr); | |
842 | ||
61c7cff8 BD |
843 | writel(iicon, i2c->regs + S3C2410_IICCON); |
844 | ||
1da177e4 LT |
845 | /* we need to work out the divisors for the clock... */ |
846 | ||
61c7cff8 BD |
847 | if (s3c24xx_i2c_clockrate(i2c, &freq) != 0) { |
848 | writel(0, i2c->regs + S3C2410_IICCON); | |
1da177e4 LT |
849 | dev_err(i2c->dev, "cannot meet bus frequency required\n"); |
850 | return -EINVAL; | |
851 | } | |
852 | ||
853 | /* todo - check that the i2c lines aren't being dragged anywhere */ | |
854 | ||
855 | dev_info(i2c->dev, "bus frequency set to %d KHz\n", freq); | |
856 | dev_dbg(i2c->dev, "S3C2410_IICCON=0x%02lx\n", iicon); | |
1da177e4 | 857 | |
1da177e4 LT |
858 | return 0; |
859 | } | |
860 | ||
5a5f5080 TA |
861 | #ifdef CONFIG_OF |
862 | /* s3c24xx_i2c_parse_dt | |
863 | * | |
864 | * Parse the device tree node and retreive the platform data. | |
865 | */ | |
866 | ||
867 | static void | |
868 | s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c) | |
869 | { | |
870 | struct s3c2410_platform_i2c *pdata = i2c->pdata; | |
871 | ||
872 | if (!np) | |
873 | return; | |
874 | ||
875 | pdata->bus_num = -1; /* i2c bus number is dynamically assigned */ | |
876 | of_property_read_u32(np, "samsung,i2c-sda-delay", &pdata->sda_delay); | |
877 | of_property_read_u32(np, "samsung,i2c-slave-addr", &pdata->slave_addr); | |
878 | of_property_read_u32(np, "samsung,i2c-max-bus-freq", | |
879 | (u32 *)&pdata->frequency); | |
880 | } | |
881 | #else | |
882 | static void | |
883 | s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c) | |
884 | { | |
885 | return; | |
886 | } | |
887 | #endif | |
888 | ||
1da177e4 LT |
889 | /* s3c24xx_i2c_probe |
890 | * | |
891 | * called by the bus driver when a suitable device is found | |
892 | */ | |
893 | ||
3ae5eaec | 894 | static int s3c24xx_i2c_probe(struct platform_device *pdev) |
1da177e4 | 895 | { |
692acbd3 | 896 | struct s3c24xx_i2c *i2c; |
4fd81eb2 | 897 | struct s3c2410_platform_i2c *pdata = NULL; |
1da177e4 LT |
898 | struct resource *res; |
899 | int ret; | |
900 | ||
5a5f5080 TA |
901 | if (!pdev->dev.of_node) { |
902 | pdata = pdev->dev.platform_data; | |
903 | if (!pdata) { | |
904 | dev_err(&pdev->dev, "no platform data\n"); | |
905 | return -EINVAL; | |
906 | } | |
6a039cab | 907 | } |
399dee23 | 908 | |
4ea1557f | 909 | i2c = devm_kzalloc(&pdev->dev, sizeof(struct s3c24xx_i2c), GFP_KERNEL); |
692acbd3 BD |
910 | if (!i2c) { |
911 | dev_err(&pdev->dev, "no memory for state\n"); | |
912 | return -ENOMEM; | |
913 | } | |
914 | ||
4fd81eb2 TA |
915 | i2c->pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); |
916 | if (!i2c->pdata) { | |
917 | ret = -ENOMEM; | |
918 | goto err_noclk; | |
919 | } | |
920 | ||
27452498 | 921 | i2c->quirks = s3c24xx_get_device_quirks(pdev); |
4fd81eb2 TA |
922 | if (pdata) |
923 | memcpy(i2c->pdata, pdata, sizeof(*pdata)); | |
5a5f5080 TA |
924 | else |
925 | s3c24xx_i2c_parse_dt(pdev->dev.of_node, i2c); | |
4fd81eb2 | 926 | |
692acbd3 BD |
927 | strlcpy(i2c->adap.name, "s3c2410-i2c", sizeof(i2c->adap.name)); |
928 | i2c->adap.owner = THIS_MODULE; | |
929 | i2c->adap.algo = &s3c24xx_i2c_algorithm; | |
930 | i2c->adap.retries = 2; | |
931 | i2c->adap.class = I2C_CLASS_HWMON | I2C_CLASS_SPD; | |
932 | i2c->tx_setup = 50; | |
933 | ||
934 | spin_lock_init(&i2c->lock); | |
935 | init_waitqueue_head(&i2c->wait); | |
399dee23 | 936 | |
1da177e4 LT |
937 | /* find the clock and enable it */ |
938 | ||
3ae5eaec RK |
939 | i2c->dev = &pdev->dev; |
940 | i2c->clk = clk_get(&pdev->dev, "i2c"); | |
1da177e4 | 941 | if (IS_ERR(i2c->clk)) { |
3ae5eaec | 942 | dev_err(&pdev->dev, "cannot get clock\n"); |
1da177e4 | 943 | ret = -ENOENT; |
5b68790c | 944 | goto err_noclk; |
1da177e4 LT |
945 | } |
946 | ||
3ae5eaec | 947 | dev_dbg(&pdev->dev, "clock source %p\n", i2c->clk); |
1da177e4 | 948 | |
1da177e4 LT |
949 | clk_enable(i2c->clk); |
950 | ||
951 | /* map the registers */ | |
952 | ||
953 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
954 | if (res == NULL) { | |
3ae5eaec | 955 | dev_err(&pdev->dev, "cannot find IO resource\n"); |
1da177e4 | 956 | ret = -ENOENT; |
5b68790c | 957 | goto err_clk; |
1da177e4 LT |
958 | } |
959 | ||
933a2aec | 960 | i2c->ioarea = request_mem_region(res->start, resource_size(res), |
1da177e4 LT |
961 | pdev->name); |
962 | ||
963 | if (i2c->ioarea == NULL) { | |
3ae5eaec | 964 | dev_err(&pdev->dev, "cannot request IO\n"); |
1da177e4 | 965 | ret = -ENXIO; |
5b68790c | 966 | goto err_clk; |
1da177e4 LT |
967 | } |
968 | ||
933a2aec | 969 | i2c->regs = ioremap(res->start, resource_size(res)); |
1da177e4 LT |
970 | |
971 | if (i2c->regs == NULL) { | |
3ae5eaec | 972 | dev_err(&pdev->dev, "cannot map IO\n"); |
1da177e4 | 973 | ret = -ENXIO; |
5b68790c | 974 | goto err_ioarea; |
1da177e4 LT |
975 | } |
976 | ||
3d0911bf BD |
977 | dev_dbg(&pdev->dev, "registers %p (%p, %p)\n", |
978 | i2c->regs, i2c->ioarea, res); | |
1da177e4 LT |
979 | |
980 | /* setup info block for the i2c core */ | |
981 | ||
982 | i2c->adap.algo_data = i2c; | |
3ae5eaec | 983 | i2c->adap.dev.parent = &pdev->dev; |
1da177e4 LT |
984 | |
985 | /* initialise the i2c controller */ | |
986 | ||
987 | ret = s3c24xx_i2c_init(i2c); | |
988 | if (ret != 0) | |
5b68790c | 989 | goto err_iomap; |
1da177e4 LT |
990 | |
991 | /* find the IRQ for this unit (note, this relies on the init call to | |
3d0911bf | 992 | * ensure no current IRQs pending |
1da177e4 LT |
993 | */ |
994 | ||
e0d1ec97 BD |
995 | i2c->irq = ret = platform_get_irq(pdev, 0); |
996 | if (ret <= 0) { | |
3ae5eaec | 997 | dev_err(&pdev->dev, "cannot find IRQ\n"); |
5b68790c | 998 | goto err_iomap; |
1da177e4 LT |
999 | } |
1000 | ||
4311051c | 1001 | ret = request_irq(i2c->irq, s3c24xx_i2c_irq, 0, |
e0d1ec97 | 1002 | dev_name(&pdev->dev), i2c); |
1da177e4 LT |
1003 | |
1004 | if (ret != 0) { | |
e0d1ec97 | 1005 | dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq); |
5b68790c | 1006 | goto err_iomap; |
1da177e4 LT |
1007 | } |
1008 | ||
61c7cff8 | 1009 | ret = s3c24xx_i2c_register_cpufreq(i2c); |
1da177e4 | 1010 | if (ret < 0) { |
61c7cff8 | 1011 | dev_err(&pdev->dev, "failed to register cpufreq notifier\n"); |
5b68790c | 1012 | goto err_irq; |
1da177e4 LT |
1013 | } |
1014 | ||
399dee23 BD |
1015 | /* Note, previous versions of the driver used i2c_add_adapter() |
1016 | * to add the bus at any number. We now pass the bus number via | |
1017 | * the platform data, so if unset it will now default to always | |
1018 | * being bus 0. | |
1019 | */ | |
1020 | ||
4fd81eb2 | 1021 | i2c->adap.nr = i2c->pdata->bus_num; |
5a5f5080 | 1022 | i2c->adap.dev.of_node = pdev->dev.of_node; |
399dee23 BD |
1023 | |
1024 | ret = i2c_add_numbered_adapter(&i2c->adap); | |
1da177e4 | 1025 | if (ret < 0) { |
3ae5eaec | 1026 | dev_err(&pdev->dev, "failed to add bus to i2c core\n"); |
61c7cff8 | 1027 | goto err_cpufreq; |
1da177e4 LT |
1028 | } |
1029 | ||
5a5f5080 | 1030 | of_i2c_register_devices(&i2c->adap); |
3ae5eaec | 1031 | platform_set_drvdata(pdev, i2c); |
1da177e4 | 1032 | |
c62c3ca5 MB |
1033 | pm_runtime_enable(&pdev->dev); |
1034 | pm_runtime_enable(&i2c->adap.dev); | |
1035 | ||
22e965c2 | 1036 | dev_info(&pdev->dev, "%s: S3C I2C adapter\n", dev_name(&i2c->adap.dev)); |
d2360b8e | 1037 | clk_disable(i2c->clk); |
5b68790c | 1038 | return 0; |
1da177e4 | 1039 | |
61c7cff8 BD |
1040 | err_cpufreq: |
1041 | s3c24xx_i2c_deregister_cpufreq(i2c); | |
1042 | ||
5b68790c | 1043 | err_irq: |
e0d1ec97 | 1044 | free_irq(i2c->irq, i2c); |
5b68790c BD |
1045 | |
1046 | err_iomap: | |
1047 | iounmap(i2c->regs); | |
1048 | ||
1049 | err_ioarea: | |
1050 | release_resource(i2c->ioarea); | |
1051 | kfree(i2c->ioarea); | |
1052 | ||
1053 | err_clk: | |
1054 | clk_disable(i2c->clk); | |
1055 | clk_put(i2c->clk); | |
1da177e4 | 1056 | |
5b68790c | 1057 | err_noclk: |
1da177e4 LT |
1058 | return ret; |
1059 | } | |
1060 | ||
1061 | /* s3c24xx_i2c_remove | |
1062 | * | |
1063 | * called when device is removed from the bus | |
1064 | */ | |
1065 | ||
3ae5eaec | 1066 | static int s3c24xx_i2c_remove(struct platform_device *pdev) |
1da177e4 | 1067 | { |
3ae5eaec | 1068 | struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev); |
5b68790c | 1069 | |
c62c3ca5 MB |
1070 | pm_runtime_disable(&i2c->adap.dev); |
1071 | pm_runtime_disable(&pdev->dev); | |
1072 | ||
61c7cff8 BD |
1073 | s3c24xx_i2c_deregister_cpufreq(i2c); |
1074 | ||
5b68790c | 1075 | i2c_del_adapter(&i2c->adap); |
e0d1ec97 | 1076 | free_irq(i2c->irq, i2c); |
5b68790c BD |
1077 | |
1078 | clk_disable(i2c->clk); | |
1079 | clk_put(i2c->clk); | |
1080 | ||
1081 | iounmap(i2c->regs); | |
1082 | ||
1083 | release_resource(i2c->ioarea); | |
5a5f5080 | 1084 | s3c24xx_i2c_dt_gpio_free(i2c); |
5b68790c | 1085 | kfree(i2c->ioarea); |
1da177e4 LT |
1086 | |
1087 | return 0; | |
1088 | } | |
1089 | ||
1090 | #ifdef CONFIG_PM | |
6a6c6189 | 1091 | static int s3c24xx_i2c_suspend_noirq(struct device *dev) |
be44f01e | 1092 | { |
6a6c6189 MD |
1093 | struct platform_device *pdev = to_platform_device(dev); |
1094 | struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev); | |
1095 | ||
be44f01e | 1096 | i2c->suspended = 1; |
6a6c6189 | 1097 | |
be44f01e BD |
1098 | return 0; |
1099 | } | |
1100 | ||
6a6c6189 | 1101 | static int s3c24xx_i2c_resume(struct device *dev) |
1da177e4 | 1102 | { |
6a6c6189 MD |
1103 | struct platform_device *pdev = to_platform_device(dev); |
1104 | struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev); | |
9480e307 | 1105 | |
be44f01e | 1106 | i2c->suspended = 0; |
d2360b8e | 1107 | clk_enable(i2c->clk); |
be44f01e | 1108 | s3c24xx_i2c_init(i2c); |
d2360b8e | 1109 | clk_disable(i2c->clk); |
1da177e4 LT |
1110 | |
1111 | return 0; | |
1112 | } | |
1113 | ||
47145210 | 1114 | static const struct dev_pm_ops s3c24xx_i2c_dev_pm_ops = { |
6a6c6189 MD |
1115 | .suspend_noirq = s3c24xx_i2c_suspend_noirq, |
1116 | .resume = s3c24xx_i2c_resume, | |
1117 | }; | |
1118 | ||
1119 | #define S3C24XX_DEV_PM_OPS (&s3c24xx_i2c_dev_pm_ops) | |
1da177e4 | 1120 | #else |
6a6c6189 | 1121 | #define S3C24XX_DEV_PM_OPS NULL |
1da177e4 LT |
1122 | #endif |
1123 | ||
1124 | /* device driver for platform bus bits */ | |
1125 | ||
7d85ccd8 | 1126 | static struct platform_driver s3c24xx_i2c_driver = { |
1da177e4 LT |
1127 | .probe = s3c24xx_i2c_probe, |
1128 | .remove = s3c24xx_i2c_remove, | |
7d85ccd8 | 1129 | .id_table = s3c24xx_driver_ids, |
3ae5eaec RK |
1130 | .driver = { |
1131 | .owner = THIS_MODULE, | |
7d85ccd8 | 1132 | .name = "s3c-i2c", |
6a6c6189 | 1133 | .pm = S3C24XX_DEV_PM_OPS, |
9df7eadf | 1134 | .of_match_table = of_match_ptr(s3c24xx_i2c_match), |
3ae5eaec | 1135 | }, |
1da177e4 LT |
1136 | }; |
1137 | ||
1138 | static int __init i2c_adap_s3c_init(void) | |
1139 | { | |
7d85ccd8 | 1140 | return platform_driver_register(&s3c24xx_i2c_driver); |
1da177e4 | 1141 | } |
18dc83a6 | 1142 | subsys_initcall(i2c_adap_s3c_init); |
1da177e4 LT |
1143 | |
1144 | static void __exit i2c_adap_s3c_exit(void) | |
1145 | { | |
7d85ccd8 | 1146 | platform_driver_unregister(&s3c24xx_i2c_driver); |
1da177e4 | 1147 | } |
1da177e4 LT |
1148 | module_exit(i2c_adap_s3c_exit); |
1149 | ||
1150 | MODULE_DESCRIPTION("S3C24XX I2C Bus driver"); | |
1151 | MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>"); | |
1152 | MODULE_LICENSE("GPL"); |