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1da177e4 LT |
1 | /* linux/drivers/i2c/busses/i2c-s3c2410.c |
2 | * | |
c564e6ae | 3 | * Copyright (C) 2004,2005,2009 Simtec Electronics |
1da177e4 LT |
4 | * Ben Dooks <ben@simtec.co.uk> |
5 | * | |
6 | * S3C2410 I2C Controller | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | #include <linux/kernel.h> | |
24 | #include <linux/module.h> | |
25 | ||
26 | #include <linux/i2c.h> | |
1da177e4 LT |
27 | #include <linux/init.h> |
28 | #include <linux/time.h> | |
29 | #include <linux/interrupt.h> | |
1da177e4 LT |
30 | #include <linux/delay.h> |
31 | #include <linux/errno.h> | |
32 | #include <linux/err.h> | |
d052d1be | 33 | #include <linux/platform_device.h> |
f8ce2547 | 34 | #include <linux/clk.h> |
61c7cff8 | 35 | #include <linux/cpufreq.h> |
5a0e3ad6 | 36 | #include <linux/slab.h> |
21782180 | 37 | #include <linux/io.h> |
5a5f5080 TA |
38 | #include <linux/of_i2c.h> |
39 | #include <linux/of_gpio.h> | |
1da177e4 | 40 | |
1da177e4 | 41 | #include <asm/irq.h> |
1da177e4 | 42 | |
9498cb79 BD |
43 | #include <plat/regs-iic.h> |
44 | #include <plat/iic.h> | |
1da177e4 LT |
45 | |
46 | /* i2c controller state */ | |
47 | ||
48 | enum s3c24xx_i2c_state { | |
49 | STATE_IDLE, | |
50 | STATE_START, | |
51 | STATE_READ, | |
52 | STATE_WRITE, | |
53 | STATE_STOP | |
54 | }; | |
55 | ||
7d85ccd8 BD |
56 | enum s3c24xx_i2c_type { |
57 | TYPE_S3C2410, | |
58 | TYPE_S3C2440, | |
59 | }; | |
60 | ||
1da177e4 LT |
61 | struct s3c24xx_i2c { |
62 | spinlock_t lock; | |
63 | wait_queue_head_t wait; | |
be44f01e | 64 | unsigned int suspended:1; |
1da177e4 LT |
65 | |
66 | struct i2c_msg *msg; | |
67 | unsigned int msg_num; | |
68 | unsigned int msg_idx; | |
69 | unsigned int msg_ptr; | |
70 | ||
e00a8cdf | 71 | unsigned int tx_setup; |
e0d1ec97 | 72 | unsigned int irq; |
e00a8cdf | 73 | |
1da177e4 | 74 | enum s3c24xx_i2c_state state; |
61c7cff8 | 75 | unsigned long clkrate; |
1da177e4 LT |
76 | |
77 | void __iomem *regs; | |
78 | struct clk *clk; | |
79 | struct device *dev; | |
1da177e4 LT |
80 | struct resource *ioarea; |
81 | struct i2c_adapter adap; | |
61c7cff8 | 82 | |
4fd81eb2 | 83 | struct s3c2410_platform_i2c *pdata; |
5a5f5080 | 84 | int gpios[2]; |
61c7cff8 BD |
85 | #ifdef CONFIG_CPU_FREQ |
86 | struct notifier_block freq_transition; | |
87 | #endif | |
1da177e4 LT |
88 | }; |
89 | ||
6a039cab | 90 | /* default platform data removed, dev should always carry data. */ |
1da177e4 LT |
91 | |
92 | /* s3c24xx_i2c_is2440() | |
93 | * | |
94 | * return true is this is an s3c2440 | |
95 | */ | |
96 | ||
97 | static inline int s3c24xx_i2c_is2440(struct s3c24xx_i2c *i2c) | |
98 | { | |
99 | struct platform_device *pdev = to_platform_device(i2c->dev); | |
7d85ccd8 | 100 | enum s3c24xx_i2c_type type; |
1da177e4 | 101 | |
5a5f5080 TA |
102 | #ifdef CONFIG_OF |
103 | if (i2c->dev->of_node) | |
104 | return of_device_is_compatible(i2c->dev->of_node, | |
105 | "samsung,s3c2440-i2c"); | |
106 | #endif | |
107 | ||
7d85ccd8 BD |
108 | type = platform_get_device_id(pdev)->driver_data; |
109 | return type == TYPE_S3C2440; | |
1da177e4 LT |
110 | } |
111 | ||
1da177e4 LT |
112 | /* s3c24xx_i2c_master_complete |
113 | * | |
114 | * complete the message and wake up the caller, using the given return code, | |
115 | * or zero to mean ok. | |
116 | */ | |
117 | ||
118 | static inline void s3c24xx_i2c_master_complete(struct s3c24xx_i2c *i2c, int ret) | |
119 | { | |
120 | dev_dbg(i2c->dev, "master_complete %d\n", ret); | |
121 | ||
122 | i2c->msg_ptr = 0; | |
123 | i2c->msg = NULL; | |
3d0911bf | 124 | i2c->msg_idx++; |
1da177e4 LT |
125 | i2c->msg_num = 0; |
126 | if (ret) | |
127 | i2c->msg_idx = ret; | |
128 | ||
129 | wake_up(&i2c->wait); | |
130 | } | |
131 | ||
132 | static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c) | |
133 | { | |
134 | unsigned long tmp; | |
3d0911bf | 135 | |
1da177e4 LT |
136 | tmp = readl(i2c->regs + S3C2410_IICCON); |
137 | writel(tmp & ~S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON); | |
1da177e4 LT |
138 | } |
139 | ||
140 | static inline void s3c24xx_i2c_enable_ack(struct s3c24xx_i2c *i2c) | |
141 | { | |
142 | unsigned long tmp; | |
3d0911bf | 143 | |
1da177e4 LT |
144 | tmp = readl(i2c->regs + S3C2410_IICCON); |
145 | writel(tmp | S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON); | |
1da177e4 LT |
146 | } |
147 | ||
148 | /* irq enable/disable functions */ | |
149 | ||
150 | static inline void s3c24xx_i2c_disable_irq(struct s3c24xx_i2c *i2c) | |
151 | { | |
152 | unsigned long tmp; | |
3d0911bf | 153 | |
1da177e4 LT |
154 | tmp = readl(i2c->regs + S3C2410_IICCON); |
155 | writel(tmp & ~S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON); | |
156 | } | |
157 | ||
158 | static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c *i2c) | |
159 | { | |
160 | unsigned long tmp; | |
3d0911bf | 161 | |
1da177e4 LT |
162 | tmp = readl(i2c->regs + S3C2410_IICCON); |
163 | writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON); | |
164 | } | |
165 | ||
166 | ||
167 | /* s3c24xx_i2c_message_start | |
168 | * | |
3d0911bf | 169 | * put the start of a message onto the bus |
1da177e4 LT |
170 | */ |
171 | ||
3d0911bf | 172 | static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c, |
1da177e4 LT |
173 | struct i2c_msg *msg) |
174 | { | |
175 | unsigned int addr = (msg->addr & 0x7f) << 1; | |
176 | unsigned long stat; | |
177 | unsigned long iiccon; | |
178 | ||
179 | stat = 0; | |
180 | stat |= S3C2410_IICSTAT_TXRXEN; | |
181 | ||
182 | if (msg->flags & I2C_M_RD) { | |
183 | stat |= S3C2410_IICSTAT_MASTER_RX; | |
184 | addr |= 1; | |
185 | } else | |
186 | stat |= S3C2410_IICSTAT_MASTER_TX; | |
187 | ||
188 | if (msg->flags & I2C_M_REV_DIR_ADDR) | |
189 | addr ^= 1; | |
190 | ||
3d0911bf | 191 | /* todo - check for wether ack wanted or not */ |
1da177e4 LT |
192 | s3c24xx_i2c_enable_ack(i2c); |
193 | ||
194 | iiccon = readl(i2c->regs + S3C2410_IICCON); | |
195 | writel(stat, i2c->regs + S3C2410_IICSTAT); | |
3d0911bf | 196 | |
1da177e4 LT |
197 | dev_dbg(i2c->dev, "START: %08lx to IICSTAT, %02x to DS\n", stat, addr); |
198 | writeb(addr, i2c->regs + S3C2410_IICDS); | |
3d0911bf | 199 | |
e00a8cdf BD |
200 | /* delay here to ensure the data byte has gotten onto the bus |
201 | * before the transaction is started */ | |
202 | ||
203 | ndelay(i2c->tx_setup); | |
204 | ||
1da177e4 LT |
205 | dev_dbg(i2c->dev, "iiccon, %08lx\n", iiccon); |
206 | writel(iiccon, i2c->regs + S3C2410_IICCON); | |
3d0911bf BD |
207 | |
208 | stat |= S3C2410_IICSTAT_START; | |
1da177e4 LT |
209 | writel(stat, i2c->regs + S3C2410_IICSTAT); |
210 | } | |
211 | ||
212 | static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c *i2c, int ret) | |
213 | { | |
214 | unsigned long iicstat = readl(i2c->regs + S3C2410_IICSTAT); | |
215 | ||
216 | dev_dbg(i2c->dev, "STOP\n"); | |
217 | ||
218 | /* stop the transfer */ | |
3d0911bf | 219 | iicstat &= ~S3C2410_IICSTAT_START; |
1da177e4 | 220 | writel(iicstat, i2c->regs + S3C2410_IICSTAT); |
3d0911bf | 221 | |
1da177e4 | 222 | i2c->state = STATE_STOP; |
3d0911bf | 223 | |
1da177e4 LT |
224 | s3c24xx_i2c_master_complete(i2c, ret); |
225 | s3c24xx_i2c_disable_irq(i2c); | |
226 | } | |
227 | ||
228 | /* helper functions to determine the current state in the set of | |
229 | * messages we are sending */ | |
230 | ||
231 | /* is_lastmsg() | |
232 | * | |
3d0911bf | 233 | * returns TRUE if the current message is the last in the set |
1da177e4 LT |
234 | */ |
235 | ||
236 | static inline int is_lastmsg(struct s3c24xx_i2c *i2c) | |
237 | { | |
238 | return i2c->msg_idx >= (i2c->msg_num - 1); | |
239 | } | |
240 | ||
241 | /* is_msglast | |
242 | * | |
243 | * returns TRUE if we this is the last byte in the current message | |
244 | */ | |
245 | ||
246 | static inline int is_msglast(struct s3c24xx_i2c *i2c) | |
247 | { | |
248 | return i2c->msg_ptr == i2c->msg->len-1; | |
249 | } | |
250 | ||
251 | /* is_msgend | |
252 | * | |
253 | * returns TRUE if we reached the end of the current message | |
254 | */ | |
255 | ||
256 | static inline int is_msgend(struct s3c24xx_i2c *i2c) | |
257 | { | |
258 | return i2c->msg_ptr >= i2c->msg->len; | |
259 | } | |
260 | ||
19820510 | 261 | /* i2c_s3c_irq_nextbyte |
1da177e4 LT |
262 | * |
263 | * process an interrupt and work out what to do | |
264 | */ | |
265 | ||
19820510 | 266 | static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat) |
1da177e4 LT |
267 | { |
268 | unsigned long tmp; | |
269 | unsigned char byte; | |
270 | int ret = 0; | |
271 | ||
272 | switch (i2c->state) { | |
273 | ||
274 | case STATE_IDLE: | |
08882d20 | 275 | dev_err(i2c->dev, "%s: called in STATE_IDLE\n", __func__); |
1da177e4 | 276 | goto out; |
1da177e4 LT |
277 | |
278 | case STATE_STOP: | |
08882d20 | 279 | dev_err(i2c->dev, "%s: called in STATE_STOP\n", __func__); |
3d0911bf | 280 | s3c24xx_i2c_disable_irq(i2c); |
1da177e4 LT |
281 | goto out_ack; |
282 | ||
283 | case STATE_START: | |
284 | /* last thing we did was send a start condition on the | |
285 | * bus, or started a new i2c message | |
286 | */ | |
3d0911bf | 287 | |
63f5c289 | 288 | if (iicstat & S3C2410_IICSTAT_LASTBIT && |
1da177e4 LT |
289 | !(i2c->msg->flags & I2C_M_IGNORE_NAK)) { |
290 | /* ack was not received... */ | |
291 | ||
292 | dev_dbg(i2c->dev, "ack was not received\n"); | |
63f5c289 | 293 | s3c24xx_i2c_stop(i2c, -ENXIO); |
1da177e4 LT |
294 | goto out_ack; |
295 | } | |
296 | ||
297 | if (i2c->msg->flags & I2C_M_RD) | |
298 | i2c->state = STATE_READ; | |
299 | else | |
300 | i2c->state = STATE_WRITE; | |
301 | ||
302 | /* terminate the transfer if there is nothing to do | |
63f5c289 | 303 | * as this is used by the i2c probe to find devices. */ |
1da177e4 LT |
304 | |
305 | if (is_lastmsg(i2c) && i2c->msg->len == 0) { | |
306 | s3c24xx_i2c_stop(i2c, 0); | |
307 | goto out_ack; | |
308 | } | |
309 | ||
310 | if (i2c->state == STATE_READ) | |
311 | goto prepare_read; | |
312 | ||
3d0911bf | 313 | /* fall through to the write state, as we will need to |
1da177e4 LT |
314 | * send a byte as well */ |
315 | ||
316 | case STATE_WRITE: | |
317 | /* we are writing data to the device... check for the | |
318 | * end of the message, and if so, work out what to do | |
319 | */ | |
320 | ||
2709781b BD |
321 | if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) { |
322 | if (iicstat & S3C2410_IICSTAT_LASTBIT) { | |
323 | dev_dbg(i2c->dev, "WRITE: No Ack\n"); | |
324 | ||
325 | s3c24xx_i2c_stop(i2c, -ECONNREFUSED); | |
326 | goto out_ack; | |
327 | } | |
328 | } | |
329 | ||
3d0911bf | 330 | retry_write: |
2709781b | 331 | |
1da177e4 LT |
332 | if (!is_msgend(i2c)) { |
333 | byte = i2c->msg->buf[i2c->msg_ptr++]; | |
334 | writeb(byte, i2c->regs + S3C2410_IICDS); | |
e00a8cdf BD |
335 | |
336 | /* delay after writing the byte to allow the | |
337 | * data setup time on the bus, as writing the | |
338 | * data to the register causes the first bit | |
339 | * to appear on SDA, and SCL will change as | |
340 | * soon as the interrupt is acknowledged */ | |
341 | ||
342 | ndelay(i2c->tx_setup); | |
343 | ||
1da177e4 LT |
344 | } else if (!is_lastmsg(i2c)) { |
345 | /* we need to go to the next i2c message */ | |
346 | ||
347 | dev_dbg(i2c->dev, "WRITE: Next Message\n"); | |
348 | ||
349 | i2c->msg_ptr = 0; | |
3d0911bf | 350 | i2c->msg_idx++; |
1da177e4 | 351 | i2c->msg++; |
3d0911bf | 352 | |
1da177e4 LT |
353 | /* check to see if we need to do another message */ |
354 | if (i2c->msg->flags & I2C_M_NOSTART) { | |
355 | ||
356 | if (i2c->msg->flags & I2C_M_RD) { | |
357 | /* cannot do this, the controller | |
358 | * forces us to send a new START | |
359 | * when we change direction */ | |
360 | ||
361 | s3c24xx_i2c_stop(i2c, -EINVAL); | |
362 | } | |
363 | ||
364 | goto retry_write; | |
365 | } else { | |
1da177e4 LT |
366 | /* send the new start */ |
367 | s3c24xx_i2c_message_start(i2c, i2c->msg); | |
368 | i2c->state = STATE_START; | |
369 | } | |
370 | ||
371 | } else { | |
372 | /* send stop */ | |
373 | ||
374 | s3c24xx_i2c_stop(i2c, 0); | |
375 | } | |
376 | break; | |
377 | ||
378 | case STATE_READ: | |
3d0911bf | 379 | /* we have a byte of data in the data register, do |
1da177e4 LT |
380 | * something with it, and then work out wether we are |
381 | * going to do any more read/write | |
382 | */ | |
383 | ||
1da177e4 LT |
384 | byte = readb(i2c->regs + S3C2410_IICDS); |
385 | i2c->msg->buf[i2c->msg_ptr++] = byte; | |
386 | ||
3d0911bf | 387 | prepare_read: |
1da177e4 LT |
388 | if (is_msglast(i2c)) { |
389 | /* last byte of buffer */ | |
390 | ||
391 | if (is_lastmsg(i2c)) | |
392 | s3c24xx_i2c_disable_ack(i2c); | |
3d0911bf | 393 | |
1da177e4 LT |
394 | } else if (is_msgend(i2c)) { |
395 | /* ok, we've read the entire buffer, see if there | |
396 | * is anything else we need to do */ | |
397 | ||
398 | if (is_lastmsg(i2c)) { | |
399 | /* last message, send stop and complete */ | |
400 | dev_dbg(i2c->dev, "READ: Send Stop\n"); | |
401 | ||
402 | s3c24xx_i2c_stop(i2c, 0); | |
403 | } else { | |
404 | /* go to the next transfer */ | |
405 | dev_dbg(i2c->dev, "READ: Next Transfer\n"); | |
406 | ||
407 | i2c->msg_ptr = 0; | |
408 | i2c->msg_idx++; | |
409 | i2c->msg++; | |
410 | } | |
411 | } | |
412 | ||
413 | break; | |
414 | } | |
415 | ||
416 | /* acknowlegde the IRQ and get back on with the work */ | |
417 | ||
418 | out_ack: | |
3d0911bf | 419 | tmp = readl(i2c->regs + S3C2410_IICCON); |
1da177e4 LT |
420 | tmp &= ~S3C2410_IICCON_IRQPEND; |
421 | writel(tmp, i2c->regs + S3C2410_IICCON); | |
422 | out: | |
423 | return ret; | |
424 | } | |
425 | ||
426 | /* s3c24xx_i2c_irq | |
427 | * | |
428 | * top level IRQ servicing routine | |
429 | */ | |
430 | ||
7d12e780 | 431 | static irqreturn_t s3c24xx_i2c_irq(int irqno, void *dev_id) |
1da177e4 LT |
432 | { |
433 | struct s3c24xx_i2c *i2c = dev_id; | |
434 | unsigned long status; | |
435 | unsigned long tmp; | |
436 | ||
437 | status = readl(i2c->regs + S3C2410_IICSTAT); | |
438 | ||
439 | if (status & S3C2410_IICSTAT_ARBITR) { | |
3d0911bf | 440 | /* deal with arbitration loss */ |
1da177e4 LT |
441 | dev_err(i2c->dev, "deal with arbitration loss\n"); |
442 | } | |
443 | ||
444 | if (i2c->state == STATE_IDLE) { | |
445 | dev_dbg(i2c->dev, "IRQ: error i2c->state == IDLE\n"); | |
446 | ||
3d0911bf | 447 | tmp = readl(i2c->regs + S3C2410_IICCON); |
1da177e4 LT |
448 | tmp &= ~S3C2410_IICCON_IRQPEND; |
449 | writel(tmp, i2c->regs + S3C2410_IICCON); | |
450 | goto out; | |
451 | } | |
3d0911bf | 452 | |
1da177e4 LT |
453 | /* pretty much this leaves us with the fact that we've |
454 | * transmitted or received whatever byte we last sent */ | |
455 | ||
19820510 | 456 | i2c_s3c_irq_nextbyte(i2c, status); |
1da177e4 LT |
457 | |
458 | out: | |
459 | return IRQ_HANDLED; | |
460 | } | |
461 | ||
462 | ||
463 | /* s3c24xx_i2c_set_master | |
464 | * | |
465 | * get the i2c bus for a master transaction | |
466 | */ | |
467 | ||
468 | static int s3c24xx_i2c_set_master(struct s3c24xx_i2c *i2c) | |
469 | { | |
470 | unsigned long iicstat; | |
471 | int timeout = 400; | |
472 | ||
473 | while (timeout-- > 0) { | |
474 | iicstat = readl(i2c->regs + S3C2410_IICSTAT); | |
3d0911bf | 475 | |
1da177e4 LT |
476 | if (!(iicstat & S3C2410_IICSTAT_BUSBUSY)) |
477 | return 0; | |
478 | ||
479 | msleep(1); | |
480 | } | |
481 | ||
1da177e4 LT |
482 | return -ETIMEDOUT; |
483 | } | |
484 | ||
485 | /* s3c24xx_i2c_doxfer | |
486 | * | |
487 | * this starts an i2c transfer | |
488 | */ | |
489 | ||
3d0911bf BD |
490 | static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c, |
491 | struct i2c_msg *msgs, int num) | |
1da177e4 | 492 | { |
1bc2962e MB |
493 | unsigned long iicstat, timeout; |
494 | int spins = 20; | |
1da177e4 LT |
495 | int ret; |
496 | ||
be44f01e | 497 | if (i2c->suspended) |
61c7cff8 BD |
498 | return -EIO; |
499 | ||
1da177e4 LT |
500 | ret = s3c24xx_i2c_set_master(i2c); |
501 | if (ret != 0) { | |
502 | dev_err(i2c->dev, "cannot get bus (error %d)\n", ret); | |
503 | ret = -EAGAIN; | |
504 | goto out; | |
505 | } | |
506 | ||
507 | spin_lock_irq(&i2c->lock); | |
508 | ||
509 | i2c->msg = msgs; | |
510 | i2c->msg_num = num; | |
511 | i2c->msg_ptr = 0; | |
512 | i2c->msg_idx = 0; | |
513 | i2c->state = STATE_START; | |
514 | ||
515 | s3c24xx_i2c_enable_irq(i2c); | |
516 | s3c24xx_i2c_message_start(i2c, msgs); | |
517 | spin_unlock_irq(&i2c->lock); | |
3d0911bf | 518 | |
1da177e4 LT |
519 | timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5); |
520 | ||
521 | ret = i2c->msg_idx; | |
522 | ||
3d0911bf | 523 | /* having these next two as dev_err() makes life very |
1da177e4 LT |
524 | * noisy when doing an i2cdetect */ |
525 | ||
526 | if (timeout == 0) | |
527 | dev_dbg(i2c->dev, "timeout\n"); | |
528 | else if (ret != num) | |
529 | dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret); | |
530 | ||
531 | /* ensure the stop has been through the bus */ | |
532 | ||
1bc2962e MB |
533 | dev_dbg(i2c->dev, "waiting for bus idle\n"); |
534 | ||
535 | /* first, try busy waiting briefly */ | |
536 | do { | |
37de03ea | 537 | cpu_relax(); |
1bc2962e MB |
538 | iicstat = readl(i2c->regs + S3C2410_IICSTAT); |
539 | } while ((iicstat & S3C2410_IICSTAT_START) && --spins); | |
540 | ||
541 | /* if that timed out sleep */ | |
542 | if (!spins) { | |
543 | msleep(1); | |
544 | iicstat = readl(i2c->regs + S3C2410_IICSTAT); | |
545 | } | |
546 | ||
547 | if (iicstat & S3C2410_IICSTAT_START) | |
548 | dev_warn(i2c->dev, "timeout waiting for bus idle\n"); | |
1da177e4 LT |
549 | |
550 | out: | |
551 | return ret; | |
552 | } | |
553 | ||
554 | /* s3c24xx_i2c_xfer | |
555 | * | |
556 | * first port of call from the i2c bus code when an message needs | |
44bbe87e | 557 | * transferring across the i2c bus. |
1da177e4 LT |
558 | */ |
559 | ||
560 | static int s3c24xx_i2c_xfer(struct i2c_adapter *adap, | |
561 | struct i2c_msg *msgs, int num) | |
562 | { | |
563 | struct s3c24xx_i2c *i2c = (struct s3c24xx_i2c *)adap->algo_data; | |
564 | int retry; | |
565 | int ret; | |
566 | ||
d2360b8e APR |
567 | clk_enable(i2c->clk); |
568 | ||
1da177e4 LT |
569 | for (retry = 0; retry < adap->retries; retry++) { |
570 | ||
571 | ret = s3c24xx_i2c_doxfer(i2c, msgs, num); | |
572 | ||
d2360b8e APR |
573 | if (ret != -EAGAIN) { |
574 | clk_disable(i2c->clk); | |
1da177e4 | 575 | return ret; |
d2360b8e | 576 | } |
1da177e4 LT |
577 | |
578 | dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry); | |
579 | ||
580 | udelay(100); | |
581 | } | |
582 | ||
d2360b8e | 583 | clk_disable(i2c->clk); |
1da177e4 LT |
584 | return -EREMOTEIO; |
585 | } | |
586 | ||
587 | /* declare our i2c functionality */ | |
588 | static u32 s3c24xx_i2c_func(struct i2c_adapter *adap) | |
589 | { | |
590 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING; | |
591 | } | |
592 | ||
593 | /* i2c bus registration info */ | |
594 | ||
8f9082c5 | 595 | static const struct i2c_algorithm s3c24xx_i2c_algorithm = { |
1da177e4 LT |
596 | .master_xfer = s3c24xx_i2c_xfer, |
597 | .functionality = s3c24xx_i2c_func, | |
598 | }; | |
599 | ||
1da177e4 LT |
600 | /* s3c24xx_i2c_calcdivisor |
601 | * | |
602 | * return the divisor settings for a given frequency | |
603 | */ | |
604 | ||
605 | static int s3c24xx_i2c_calcdivisor(unsigned long clkin, unsigned int wanted, | |
606 | unsigned int *div1, unsigned int *divs) | |
607 | { | |
608 | unsigned int calc_divs = clkin / wanted; | |
609 | unsigned int calc_div1; | |
610 | ||
611 | if (calc_divs > (16*16)) | |
612 | calc_div1 = 512; | |
613 | else | |
614 | calc_div1 = 16; | |
615 | ||
616 | calc_divs += calc_div1-1; | |
617 | calc_divs /= calc_div1; | |
618 | ||
619 | if (calc_divs == 0) | |
620 | calc_divs = 1; | |
621 | if (calc_divs > 17) | |
622 | calc_divs = 17; | |
623 | ||
624 | *divs = calc_divs; | |
625 | *div1 = calc_div1; | |
626 | ||
627 | return clkin / (calc_divs * calc_div1); | |
628 | } | |
629 | ||
61c7cff8 | 630 | /* s3c24xx_i2c_clockrate |
1da177e4 LT |
631 | * |
632 | * work out a divisor for the user requested frequency setting, | |
633 | * either by the requested frequency, or scanning the acceptable | |
634 | * range of frequencies until something is found | |
635 | */ | |
636 | ||
61c7cff8 | 637 | static int s3c24xx_i2c_clockrate(struct s3c24xx_i2c *i2c, unsigned int *got) |
1da177e4 | 638 | { |
4fd81eb2 | 639 | struct s3c2410_platform_i2c *pdata = i2c->pdata; |
1da177e4 | 640 | unsigned long clkin = clk_get_rate(i2c->clk); |
1da177e4 | 641 | unsigned int divs, div1; |
c564e6ae | 642 | unsigned long target_frequency; |
61c7cff8 | 643 | u32 iiccon; |
1da177e4 | 644 | int freq; |
1da177e4 | 645 | |
61c7cff8 | 646 | i2c->clkrate = clkin; |
1da177e4 | 647 | clkin /= 1000; /* clkin now in KHz */ |
3d0911bf | 648 | |
c564e6ae | 649 | dev_dbg(i2c->dev, "pdata desired frequency %lu\n", pdata->frequency); |
1da177e4 | 650 | |
c564e6ae | 651 | target_frequency = pdata->frequency ? pdata->frequency : 100000; |
1da177e4 | 652 | |
c564e6ae | 653 | target_frequency /= 1000; /* Target frequency now in KHz */ |
1da177e4 | 654 | |
c564e6ae | 655 | freq = s3c24xx_i2c_calcdivisor(clkin, target_frequency, &div1, &divs); |
1da177e4 | 656 | |
c564e6ae DS |
657 | if (freq > target_frequency) { |
658 | dev_err(i2c->dev, | |
659 | "Unable to achieve desired frequency %luKHz." \ | |
660 | " Lowest achievable %dKHz\n", target_frequency, freq); | |
661 | return -EINVAL; | |
1da177e4 LT |
662 | } |
663 | ||
1da177e4 | 664 | *got = freq; |
61c7cff8 BD |
665 | |
666 | iiccon = readl(i2c->regs + S3C2410_IICCON); | |
667 | iiccon &= ~(S3C2410_IICCON_SCALEMASK | S3C2410_IICCON_TXDIV_512); | |
668 | iiccon |= (divs-1); | |
669 | ||
670 | if (div1 == 512) | |
671 | iiccon |= S3C2410_IICCON_TXDIV_512; | |
672 | ||
673 | writel(iiccon, i2c->regs + S3C2410_IICCON); | |
674 | ||
a192f715 BD |
675 | if (s3c24xx_i2c_is2440(i2c)) { |
676 | unsigned long sda_delay; | |
677 | ||
678 | if (pdata->sda_delay) { | |
7031307a MH |
679 | sda_delay = clkin * pdata->sda_delay; |
680 | sda_delay = DIV_ROUND_UP(sda_delay, 1000000); | |
a192f715 BD |
681 | sda_delay = DIV_ROUND_UP(sda_delay, 5); |
682 | if (sda_delay > 3) | |
683 | sda_delay = 3; | |
684 | sda_delay |= S3C2410_IICLC_FILTER_ON; | |
685 | } else | |
686 | sda_delay = 0; | |
687 | ||
688 | dev_dbg(i2c->dev, "IICLC=%08lx\n", sda_delay); | |
689 | writel(sda_delay, i2c->regs + S3C2440_IICLC); | |
690 | } | |
691 | ||
61c7cff8 BD |
692 | return 0; |
693 | } | |
694 | ||
695 | #ifdef CONFIG_CPU_FREQ | |
696 | ||
697 | #define freq_to_i2c(_n) container_of(_n, struct s3c24xx_i2c, freq_transition) | |
698 | ||
699 | static int s3c24xx_i2c_cpufreq_transition(struct notifier_block *nb, | |
700 | unsigned long val, void *data) | |
701 | { | |
702 | struct s3c24xx_i2c *i2c = freq_to_i2c(nb); | |
703 | unsigned long flags; | |
704 | unsigned int got; | |
705 | int delta_f; | |
706 | int ret; | |
707 | ||
708 | delta_f = clk_get_rate(i2c->clk) - i2c->clkrate; | |
709 | ||
710 | /* if we're post-change and the input clock has slowed down | |
711 | * or at pre-change and the clock is about to speed up, then | |
712 | * adjust our clock rate. <0 is slow, >0 speedup. | |
713 | */ | |
714 | ||
715 | if ((val == CPUFREQ_POSTCHANGE && delta_f < 0) || | |
716 | (val == CPUFREQ_PRECHANGE && delta_f > 0)) { | |
717 | spin_lock_irqsave(&i2c->lock, flags); | |
718 | ret = s3c24xx_i2c_clockrate(i2c, &got); | |
719 | spin_unlock_irqrestore(&i2c->lock, flags); | |
720 | ||
721 | if (ret < 0) | |
722 | dev_err(i2c->dev, "cannot find frequency\n"); | |
723 | else | |
724 | dev_info(i2c->dev, "setting freq %d\n", got); | |
725 | } | |
726 | ||
1da177e4 LT |
727 | return 0; |
728 | } | |
729 | ||
61c7cff8 BD |
730 | static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c) |
731 | { | |
732 | i2c->freq_transition.notifier_call = s3c24xx_i2c_cpufreq_transition; | |
733 | ||
734 | return cpufreq_register_notifier(&i2c->freq_transition, | |
735 | CPUFREQ_TRANSITION_NOTIFIER); | |
736 | } | |
737 | ||
738 | static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c) | |
739 | { | |
740 | cpufreq_unregister_notifier(&i2c->freq_transition, | |
741 | CPUFREQ_TRANSITION_NOTIFIER); | |
742 | } | |
743 | ||
744 | #else | |
745 | static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c) | |
746 | { | |
1da177e4 LT |
747 | return 0; |
748 | } | |
749 | ||
61c7cff8 BD |
750 | static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c) |
751 | { | |
752 | } | |
753 | #endif | |
754 | ||
5a5f5080 TA |
755 | #ifdef CONFIG_OF |
756 | static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c *i2c) | |
757 | { | |
758 | int idx, gpio, ret; | |
759 | ||
760 | for (idx = 0; idx < 2; idx++) { | |
761 | gpio = of_get_gpio(i2c->dev->of_node, idx); | |
762 | if (!gpio_is_valid(gpio)) { | |
763 | dev_err(i2c->dev, "invalid gpio[%d]: %d\n", idx, gpio); | |
764 | goto free_gpio; | |
765 | } | |
766 | ||
767 | ret = gpio_request(gpio, "i2c-bus"); | |
768 | if (ret) { | |
769 | dev_err(i2c->dev, "gpio [%d] request failed\n", gpio); | |
770 | goto free_gpio; | |
771 | } | |
772 | } | |
773 | return 0; | |
774 | ||
775 | free_gpio: | |
776 | while (--idx >= 0) | |
777 | gpio_free(i2c->gpios[idx]); | |
778 | return -EINVAL; | |
779 | } | |
780 | ||
781 | static void s3c24xx_i2c_dt_gpio_free(struct s3c24xx_i2c *i2c) | |
782 | { | |
783 | unsigned int idx; | |
784 | for (idx = 0; idx < 2; idx++) | |
785 | gpio_free(i2c->gpios[idx]); | |
786 | } | |
787 | #else | |
788 | static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c *i2c) | |
789 | { | |
8ebe661d | 790 | return 0; |
5a5f5080 TA |
791 | } |
792 | ||
793 | static void s3c24xx_i2c_dt_gpio_free(struct s3c24xx_i2c *i2c) | |
794 | { | |
795 | } | |
796 | #endif | |
797 | ||
1da177e4 LT |
798 | /* s3c24xx_i2c_init |
799 | * | |
3d0911bf | 800 | * initialise the controller, set the IO lines and frequency |
1da177e4 LT |
801 | */ |
802 | ||
803 | static int s3c24xx_i2c_init(struct s3c24xx_i2c *i2c) | |
804 | { | |
805 | unsigned long iicon = S3C2410_IICCON_IRQEN | S3C2410_IICCON_ACKEN; | |
806 | struct s3c2410_platform_i2c *pdata; | |
807 | unsigned int freq; | |
808 | ||
809 | /* get the plafrom data */ | |
810 | ||
4fd81eb2 | 811 | pdata = i2c->pdata; |
1da177e4 LT |
812 | |
813 | /* inititalise the gpio */ | |
814 | ||
8be310a6 BD |
815 | if (pdata->cfg_gpio) |
816 | pdata->cfg_gpio(to_platform_device(i2c->dev)); | |
5a5f5080 TA |
817 | else |
818 | if (s3c24xx_i2c_parse_dt_gpio(i2c)) | |
819 | return -EINVAL; | |
1da177e4 LT |
820 | |
821 | /* write slave address */ | |
3d0911bf | 822 | |
1da177e4 LT |
823 | writeb(pdata->slave_addr, i2c->regs + S3C2410_IICADD); |
824 | ||
825 | dev_info(i2c->dev, "slave address 0x%02x\n", pdata->slave_addr); | |
826 | ||
61c7cff8 BD |
827 | writel(iicon, i2c->regs + S3C2410_IICCON); |
828 | ||
1da177e4 LT |
829 | /* we need to work out the divisors for the clock... */ |
830 | ||
61c7cff8 BD |
831 | if (s3c24xx_i2c_clockrate(i2c, &freq) != 0) { |
832 | writel(0, i2c->regs + S3C2410_IICCON); | |
1da177e4 LT |
833 | dev_err(i2c->dev, "cannot meet bus frequency required\n"); |
834 | return -EINVAL; | |
835 | } | |
836 | ||
837 | /* todo - check that the i2c lines aren't being dragged anywhere */ | |
838 | ||
839 | dev_info(i2c->dev, "bus frequency set to %d KHz\n", freq); | |
840 | dev_dbg(i2c->dev, "S3C2410_IICCON=0x%02lx\n", iicon); | |
1da177e4 | 841 | |
1da177e4 LT |
842 | return 0; |
843 | } | |
844 | ||
5a5f5080 TA |
845 | #ifdef CONFIG_OF |
846 | /* s3c24xx_i2c_parse_dt | |
847 | * | |
848 | * Parse the device tree node and retreive the platform data. | |
849 | */ | |
850 | ||
851 | static void | |
852 | s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c) | |
853 | { | |
854 | struct s3c2410_platform_i2c *pdata = i2c->pdata; | |
855 | ||
856 | if (!np) | |
857 | return; | |
858 | ||
859 | pdata->bus_num = -1; /* i2c bus number is dynamically assigned */ | |
860 | of_property_read_u32(np, "samsung,i2c-sda-delay", &pdata->sda_delay); | |
861 | of_property_read_u32(np, "samsung,i2c-slave-addr", &pdata->slave_addr); | |
862 | of_property_read_u32(np, "samsung,i2c-max-bus-freq", | |
863 | (u32 *)&pdata->frequency); | |
864 | } | |
865 | #else | |
866 | static void | |
867 | s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c) | |
868 | { | |
869 | return; | |
870 | } | |
871 | #endif | |
872 | ||
1da177e4 LT |
873 | /* s3c24xx_i2c_probe |
874 | * | |
875 | * called by the bus driver when a suitable device is found | |
876 | */ | |
877 | ||
3ae5eaec | 878 | static int s3c24xx_i2c_probe(struct platform_device *pdev) |
1da177e4 | 879 | { |
692acbd3 | 880 | struct s3c24xx_i2c *i2c; |
4fd81eb2 | 881 | struct s3c2410_platform_i2c *pdata = NULL; |
1da177e4 LT |
882 | struct resource *res; |
883 | int ret; | |
884 | ||
5a5f5080 TA |
885 | if (!pdev->dev.of_node) { |
886 | pdata = pdev->dev.platform_data; | |
887 | if (!pdata) { | |
888 | dev_err(&pdev->dev, "no platform data\n"); | |
889 | return -EINVAL; | |
890 | } | |
6a039cab | 891 | } |
399dee23 | 892 | |
4ea1557f | 893 | i2c = devm_kzalloc(&pdev->dev, sizeof(struct s3c24xx_i2c), GFP_KERNEL); |
692acbd3 BD |
894 | if (!i2c) { |
895 | dev_err(&pdev->dev, "no memory for state\n"); | |
896 | return -ENOMEM; | |
897 | } | |
898 | ||
4fd81eb2 TA |
899 | i2c->pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); |
900 | if (!i2c->pdata) { | |
901 | ret = -ENOMEM; | |
902 | goto err_noclk; | |
903 | } | |
904 | ||
905 | if (pdata) | |
906 | memcpy(i2c->pdata, pdata, sizeof(*pdata)); | |
5a5f5080 TA |
907 | else |
908 | s3c24xx_i2c_parse_dt(pdev->dev.of_node, i2c); | |
4fd81eb2 | 909 | |
692acbd3 BD |
910 | strlcpy(i2c->adap.name, "s3c2410-i2c", sizeof(i2c->adap.name)); |
911 | i2c->adap.owner = THIS_MODULE; | |
912 | i2c->adap.algo = &s3c24xx_i2c_algorithm; | |
913 | i2c->adap.retries = 2; | |
914 | i2c->adap.class = I2C_CLASS_HWMON | I2C_CLASS_SPD; | |
915 | i2c->tx_setup = 50; | |
916 | ||
917 | spin_lock_init(&i2c->lock); | |
918 | init_waitqueue_head(&i2c->wait); | |
399dee23 | 919 | |
1da177e4 LT |
920 | /* find the clock and enable it */ |
921 | ||
3ae5eaec RK |
922 | i2c->dev = &pdev->dev; |
923 | i2c->clk = clk_get(&pdev->dev, "i2c"); | |
1da177e4 | 924 | if (IS_ERR(i2c->clk)) { |
3ae5eaec | 925 | dev_err(&pdev->dev, "cannot get clock\n"); |
1da177e4 | 926 | ret = -ENOENT; |
5b68790c | 927 | goto err_noclk; |
1da177e4 LT |
928 | } |
929 | ||
3ae5eaec | 930 | dev_dbg(&pdev->dev, "clock source %p\n", i2c->clk); |
1da177e4 | 931 | |
1da177e4 LT |
932 | clk_enable(i2c->clk); |
933 | ||
934 | /* map the registers */ | |
935 | ||
936 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
937 | if (res == NULL) { | |
3ae5eaec | 938 | dev_err(&pdev->dev, "cannot find IO resource\n"); |
1da177e4 | 939 | ret = -ENOENT; |
5b68790c | 940 | goto err_clk; |
1da177e4 LT |
941 | } |
942 | ||
933a2aec | 943 | i2c->ioarea = request_mem_region(res->start, resource_size(res), |
1da177e4 LT |
944 | pdev->name); |
945 | ||
946 | if (i2c->ioarea == NULL) { | |
3ae5eaec | 947 | dev_err(&pdev->dev, "cannot request IO\n"); |
1da177e4 | 948 | ret = -ENXIO; |
5b68790c | 949 | goto err_clk; |
1da177e4 LT |
950 | } |
951 | ||
933a2aec | 952 | i2c->regs = ioremap(res->start, resource_size(res)); |
1da177e4 LT |
953 | |
954 | if (i2c->regs == NULL) { | |
3ae5eaec | 955 | dev_err(&pdev->dev, "cannot map IO\n"); |
1da177e4 | 956 | ret = -ENXIO; |
5b68790c | 957 | goto err_ioarea; |
1da177e4 LT |
958 | } |
959 | ||
3d0911bf BD |
960 | dev_dbg(&pdev->dev, "registers %p (%p, %p)\n", |
961 | i2c->regs, i2c->ioarea, res); | |
1da177e4 LT |
962 | |
963 | /* setup info block for the i2c core */ | |
964 | ||
965 | i2c->adap.algo_data = i2c; | |
3ae5eaec | 966 | i2c->adap.dev.parent = &pdev->dev; |
1da177e4 LT |
967 | |
968 | /* initialise the i2c controller */ | |
969 | ||
970 | ret = s3c24xx_i2c_init(i2c); | |
971 | if (ret != 0) | |
5b68790c | 972 | goto err_iomap; |
1da177e4 LT |
973 | |
974 | /* find the IRQ for this unit (note, this relies on the init call to | |
3d0911bf | 975 | * ensure no current IRQs pending |
1da177e4 LT |
976 | */ |
977 | ||
e0d1ec97 BD |
978 | i2c->irq = ret = platform_get_irq(pdev, 0); |
979 | if (ret <= 0) { | |
3ae5eaec | 980 | dev_err(&pdev->dev, "cannot find IRQ\n"); |
5b68790c | 981 | goto err_iomap; |
1da177e4 LT |
982 | } |
983 | ||
4311051c | 984 | ret = request_irq(i2c->irq, s3c24xx_i2c_irq, 0, |
e0d1ec97 | 985 | dev_name(&pdev->dev), i2c); |
1da177e4 LT |
986 | |
987 | if (ret != 0) { | |
e0d1ec97 | 988 | dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq); |
5b68790c | 989 | goto err_iomap; |
1da177e4 LT |
990 | } |
991 | ||
61c7cff8 | 992 | ret = s3c24xx_i2c_register_cpufreq(i2c); |
1da177e4 | 993 | if (ret < 0) { |
61c7cff8 | 994 | dev_err(&pdev->dev, "failed to register cpufreq notifier\n"); |
5b68790c | 995 | goto err_irq; |
1da177e4 LT |
996 | } |
997 | ||
399dee23 BD |
998 | /* Note, previous versions of the driver used i2c_add_adapter() |
999 | * to add the bus at any number. We now pass the bus number via | |
1000 | * the platform data, so if unset it will now default to always | |
1001 | * being bus 0. | |
1002 | */ | |
1003 | ||
4fd81eb2 | 1004 | i2c->adap.nr = i2c->pdata->bus_num; |
5a5f5080 | 1005 | i2c->adap.dev.of_node = pdev->dev.of_node; |
399dee23 BD |
1006 | |
1007 | ret = i2c_add_numbered_adapter(&i2c->adap); | |
1da177e4 | 1008 | if (ret < 0) { |
3ae5eaec | 1009 | dev_err(&pdev->dev, "failed to add bus to i2c core\n"); |
61c7cff8 | 1010 | goto err_cpufreq; |
1da177e4 LT |
1011 | } |
1012 | ||
5a5f5080 | 1013 | of_i2c_register_devices(&i2c->adap); |
3ae5eaec | 1014 | platform_set_drvdata(pdev, i2c); |
1da177e4 | 1015 | |
22e965c2 | 1016 | dev_info(&pdev->dev, "%s: S3C I2C adapter\n", dev_name(&i2c->adap.dev)); |
d2360b8e | 1017 | clk_disable(i2c->clk); |
5b68790c | 1018 | return 0; |
1da177e4 | 1019 | |
61c7cff8 BD |
1020 | err_cpufreq: |
1021 | s3c24xx_i2c_deregister_cpufreq(i2c); | |
1022 | ||
5b68790c | 1023 | err_irq: |
e0d1ec97 | 1024 | free_irq(i2c->irq, i2c); |
5b68790c BD |
1025 | |
1026 | err_iomap: | |
1027 | iounmap(i2c->regs); | |
1028 | ||
1029 | err_ioarea: | |
1030 | release_resource(i2c->ioarea); | |
1031 | kfree(i2c->ioarea); | |
1032 | ||
1033 | err_clk: | |
1034 | clk_disable(i2c->clk); | |
1035 | clk_put(i2c->clk); | |
1da177e4 | 1036 | |
5b68790c | 1037 | err_noclk: |
1da177e4 LT |
1038 | return ret; |
1039 | } | |
1040 | ||
1041 | /* s3c24xx_i2c_remove | |
1042 | * | |
1043 | * called when device is removed from the bus | |
1044 | */ | |
1045 | ||
3ae5eaec | 1046 | static int s3c24xx_i2c_remove(struct platform_device *pdev) |
1da177e4 | 1047 | { |
3ae5eaec | 1048 | struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev); |
5b68790c | 1049 | |
61c7cff8 BD |
1050 | s3c24xx_i2c_deregister_cpufreq(i2c); |
1051 | ||
5b68790c | 1052 | i2c_del_adapter(&i2c->adap); |
e0d1ec97 | 1053 | free_irq(i2c->irq, i2c); |
5b68790c BD |
1054 | |
1055 | clk_disable(i2c->clk); | |
1056 | clk_put(i2c->clk); | |
1057 | ||
1058 | iounmap(i2c->regs); | |
1059 | ||
1060 | release_resource(i2c->ioarea); | |
5a5f5080 | 1061 | s3c24xx_i2c_dt_gpio_free(i2c); |
5b68790c | 1062 | kfree(i2c->ioarea); |
1da177e4 LT |
1063 | |
1064 | return 0; | |
1065 | } | |
1066 | ||
1067 | #ifdef CONFIG_PM | |
6a6c6189 | 1068 | static int s3c24xx_i2c_suspend_noirq(struct device *dev) |
be44f01e | 1069 | { |
6a6c6189 MD |
1070 | struct platform_device *pdev = to_platform_device(dev); |
1071 | struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev); | |
1072 | ||
be44f01e | 1073 | i2c->suspended = 1; |
6a6c6189 | 1074 | |
be44f01e BD |
1075 | return 0; |
1076 | } | |
1077 | ||
6a6c6189 | 1078 | static int s3c24xx_i2c_resume(struct device *dev) |
1da177e4 | 1079 | { |
6a6c6189 MD |
1080 | struct platform_device *pdev = to_platform_device(dev); |
1081 | struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev); | |
9480e307 | 1082 | |
be44f01e | 1083 | i2c->suspended = 0; |
d2360b8e | 1084 | clk_enable(i2c->clk); |
be44f01e | 1085 | s3c24xx_i2c_init(i2c); |
d2360b8e | 1086 | clk_disable(i2c->clk); |
1da177e4 LT |
1087 | |
1088 | return 0; | |
1089 | } | |
1090 | ||
47145210 | 1091 | static const struct dev_pm_ops s3c24xx_i2c_dev_pm_ops = { |
6a6c6189 MD |
1092 | .suspend_noirq = s3c24xx_i2c_suspend_noirq, |
1093 | .resume = s3c24xx_i2c_resume, | |
1094 | }; | |
1095 | ||
1096 | #define S3C24XX_DEV_PM_OPS (&s3c24xx_i2c_dev_pm_ops) | |
1da177e4 | 1097 | #else |
6a6c6189 | 1098 | #define S3C24XX_DEV_PM_OPS NULL |
1da177e4 LT |
1099 | #endif |
1100 | ||
1101 | /* device driver for platform bus bits */ | |
1102 | ||
7d85ccd8 BD |
1103 | static struct platform_device_id s3c24xx_driver_ids[] = { |
1104 | { | |
1105 | .name = "s3c2410-i2c", | |
1106 | .driver_data = TYPE_S3C2410, | |
1107 | }, { | |
1108 | .name = "s3c2440-i2c", | |
1109 | .driver_data = TYPE_S3C2440, | |
1110 | }, { }, | |
1da177e4 | 1111 | }; |
7d85ccd8 | 1112 | MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids); |
1da177e4 | 1113 | |
5a5f5080 TA |
1114 | #ifdef CONFIG_OF |
1115 | static const struct of_device_id s3c24xx_i2c_match[] = { | |
1116 | { .compatible = "samsung,s3c2410-i2c" }, | |
1117 | { .compatible = "samsung,s3c2440-i2c" }, | |
1118 | {}, | |
1119 | }; | |
1120 | MODULE_DEVICE_TABLE(of, s3c24xx_i2c_match); | |
1121 | #else | |
1122 | #define s3c24xx_i2c_match NULL | |
1123 | #endif | |
1124 | ||
7d85ccd8 | 1125 | static struct platform_driver s3c24xx_i2c_driver = { |
1da177e4 LT |
1126 | .probe = s3c24xx_i2c_probe, |
1127 | .remove = s3c24xx_i2c_remove, | |
7d85ccd8 | 1128 | .id_table = s3c24xx_driver_ids, |
3ae5eaec RK |
1129 | .driver = { |
1130 | .owner = THIS_MODULE, | |
7d85ccd8 | 1131 | .name = "s3c-i2c", |
6a6c6189 | 1132 | .pm = S3C24XX_DEV_PM_OPS, |
5a5f5080 | 1133 | .of_match_table = s3c24xx_i2c_match, |
3ae5eaec | 1134 | }, |
1da177e4 LT |
1135 | }; |
1136 | ||
1137 | static int __init i2c_adap_s3c_init(void) | |
1138 | { | |
7d85ccd8 | 1139 | return platform_driver_register(&s3c24xx_i2c_driver); |
1da177e4 | 1140 | } |
18dc83a6 | 1141 | subsys_initcall(i2c_adap_s3c_init); |
1da177e4 LT |
1142 | |
1143 | static void __exit i2c_adap_s3c_exit(void) | |
1144 | { | |
7d85ccd8 | 1145 | platform_driver_unregister(&s3c24xx_i2c_driver); |
1da177e4 | 1146 | } |
1da177e4 LT |
1147 | module_exit(i2c_adap_s3c_exit); |
1148 | ||
1149 | MODULE_DESCRIPTION("S3C24XX I2C Bus driver"); | |
1150 | MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>"); | |
1151 | MODULE_LICENSE("GPL"); |