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1da177e4 LT |
1 | /* linux/drivers/i2c/busses/i2c-s3c2410.c |
2 | * | |
c564e6ae | 3 | * Copyright (C) 2004,2005,2009 Simtec Electronics |
1da177e4 LT |
4 | * Ben Dooks <ben@simtec.co.uk> |
5 | * | |
6 | * S3C2410 I2C Controller | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | #include <linux/kernel.h> | |
24 | #include <linux/module.h> | |
25 | ||
26 | #include <linux/i2c.h> | |
1da177e4 LT |
27 | #include <linux/init.h> |
28 | #include <linux/time.h> | |
29 | #include <linux/interrupt.h> | |
1da177e4 LT |
30 | #include <linux/delay.h> |
31 | #include <linux/errno.h> | |
32 | #include <linux/err.h> | |
d052d1be | 33 | #include <linux/platform_device.h> |
c62c3ca5 | 34 | #include <linux/pm_runtime.h> |
f8ce2547 | 35 | #include <linux/clk.h> |
61c7cff8 | 36 | #include <linux/cpufreq.h> |
5a0e3ad6 | 37 | #include <linux/slab.h> |
21782180 | 38 | #include <linux/io.h> |
5a5f5080 TA |
39 | #include <linux/of_i2c.h> |
40 | #include <linux/of_gpio.h> | |
1da177e4 | 41 | |
1da177e4 | 42 | #include <asm/irq.h> |
1da177e4 | 43 | |
9498cb79 BD |
44 | #include <plat/regs-iic.h> |
45 | #include <plat/iic.h> | |
1da177e4 LT |
46 | |
47 | /* i2c controller state */ | |
48 | ||
49 | enum s3c24xx_i2c_state { | |
50 | STATE_IDLE, | |
51 | STATE_START, | |
52 | STATE_READ, | |
53 | STATE_WRITE, | |
54 | STATE_STOP | |
55 | }; | |
56 | ||
7d85ccd8 BD |
57 | enum s3c24xx_i2c_type { |
58 | TYPE_S3C2410, | |
59 | TYPE_S3C2440, | |
60 | }; | |
61 | ||
1da177e4 LT |
62 | struct s3c24xx_i2c { |
63 | spinlock_t lock; | |
64 | wait_queue_head_t wait; | |
be44f01e | 65 | unsigned int suspended:1; |
1da177e4 LT |
66 | |
67 | struct i2c_msg *msg; | |
68 | unsigned int msg_num; | |
69 | unsigned int msg_idx; | |
70 | unsigned int msg_ptr; | |
71 | ||
e00a8cdf | 72 | unsigned int tx_setup; |
e0d1ec97 | 73 | unsigned int irq; |
e00a8cdf | 74 | |
1da177e4 | 75 | enum s3c24xx_i2c_state state; |
61c7cff8 | 76 | unsigned long clkrate; |
1da177e4 LT |
77 | |
78 | void __iomem *regs; | |
79 | struct clk *clk; | |
80 | struct device *dev; | |
1da177e4 LT |
81 | struct resource *ioarea; |
82 | struct i2c_adapter adap; | |
61c7cff8 | 83 | |
4fd81eb2 | 84 | struct s3c2410_platform_i2c *pdata; |
5a5f5080 | 85 | int gpios[2]; |
61c7cff8 BD |
86 | #ifdef CONFIG_CPU_FREQ |
87 | struct notifier_block freq_transition; | |
88 | #endif | |
1da177e4 LT |
89 | }; |
90 | ||
6a039cab | 91 | /* default platform data removed, dev should always carry data. */ |
1da177e4 LT |
92 | |
93 | /* s3c24xx_i2c_is2440() | |
94 | * | |
95 | * return true is this is an s3c2440 | |
96 | */ | |
97 | ||
98 | static inline int s3c24xx_i2c_is2440(struct s3c24xx_i2c *i2c) | |
99 | { | |
100 | struct platform_device *pdev = to_platform_device(i2c->dev); | |
7d85ccd8 | 101 | enum s3c24xx_i2c_type type; |
1da177e4 | 102 | |
5a5f5080 TA |
103 | #ifdef CONFIG_OF |
104 | if (i2c->dev->of_node) | |
105 | return of_device_is_compatible(i2c->dev->of_node, | |
106 | "samsung,s3c2440-i2c"); | |
107 | #endif | |
108 | ||
7d85ccd8 BD |
109 | type = platform_get_device_id(pdev)->driver_data; |
110 | return type == TYPE_S3C2440; | |
1da177e4 LT |
111 | } |
112 | ||
1da177e4 LT |
113 | /* s3c24xx_i2c_master_complete |
114 | * | |
115 | * complete the message and wake up the caller, using the given return code, | |
116 | * or zero to mean ok. | |
117 | */ | |
118 | ||
119 | static inline void s3c24xx_i2c_master_complete(struct s3c24xx_i2c *i2c, int ret) | |
120 | { | |
121 | dev_dbg(i2c->dev, "master_complete %d\n", ret); | |
122 | ||
123 | i2c->msg_ptr = 0; | |
124 | i2c->msg = NULL; | |
3d0911bf | 125 | i2c->msg_idx++; |
1da177e4 LT |
126 | i2c->msg_num = 0; |
127 | if (ret) | |
128 | i2c->msg_idx = ret; | |
129 | ||
130 | wake_up(&i2c->wait); | |
131 | } | |
132 | ||
133 | static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c) | |
134 | { | |
135 | unsigned long tmp; | |
3d0911bf | 136 | |
1da177e4 LT |
137 | tmp = readl(i2c->regs + S3C2410_IICCON); |
138 | writel(tmp & ~S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON); | |
1da177e4 LT |
139 | } |
140 | ||
141 | static inline void s3c24xx_i2c_enable_ack(struct s3c24xx_i2c *i2c) | |
142 | { | |
143 | unsigned long tmp; | |
3d0911bf | 144 | |
1da177e4 LT |
145 | tmp = readl(i2c->regs + S3C2410_IICCON); |
146 | writel(tmp | S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON); | |
1da177e4 LT |
147 | } |
148 | ||
149 | /* irq enable/disable functions */ | |
150 | ||
151 | static inline void s3c24xx_i2c_disable_irq(struct s3c24xx_i2c *i2c) | |
152 | { | |
153 | unsigned long tmp; | |
3d0911bf | 154 | |
1da177e4 LT |
155 | tmp = readl(i2c->regs + S3C2410_IICCON); |
156 | writel(tmp & ~S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON); | |
157 | } | |
158 | ||
159 | static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c *i2c) | |
160 | { | |
161 | unsigned long tmp; | |
3d0911bf | 162 | |
1da177e4 LT |
163 | tmp = readl(i2c->regs + S3C2410_IICCON); |
164 | writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON); | |
165 | } | |
166 | ||
167 | ||
168 | /* s3c24xx_i2c_message_start | |
169 | * | |
3d0911bf | 170 | * put the start of a message onto the bus |
1da177e4 LT |
171 | */ |
172 | ||
3d0911bf | 173 | static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c, |
1da177e4 LT |
174 | struct i2c_msg *msg) |
175 | { | |
176 | unsigned int addr = (msg->addr & 0x7f) << 1; | |
177 | unsigned long stat; | |
178 | unsigned long iiccon; | |
179 | ||
180 | stat = 0; | |
181 | stat |= S3C2410_IICSTAT_TXRXEN; | |
182 | ||
183 | if (msg->flags & I2C_M_RD) { | |
184 | stat |= S3C2410_IICSTAT_MASTER_RX; | |
185 | addr |= 1; | |
186 | } else | |
187 | stat |= S3C2410_IICSTAT_MASTER_TX; | |
188 | ||
189 | if (msg->flags & I2C_M_REV_DIR_ADDR) | |
190 | addr ^= 1; | |
191 | ||
3d0911bf | 192 | /* todo - check for wether ack wanted or not */ |
1da177e4 LT |
193 | s3c24xx_i2c_enable_ack(i2c); |
194 | ||
195 | iiccon = readl(i2c->regs + S3C2410_IICCON); | |
196 | writel(stat, i2c->regs + S3C2410_IICSTAT); | |
3d0911bf | 197 | |
1da177e4 LT |
198 | dev_dbg(i2c->dev, "START: %08lx to IICSTAT, %02x to DS\n", stat, addr); |
199 | writeb(addr, i2c->regs + S3C2410_IICDS); | |
3d0911bf | 200 | |
e00a8cdf BD |
201 | /* delay here to ensure the data byte has gotten onto the bus |
202 | * before the transaction is started */ | |
203 | ||
204 | ndelay(i2c->tx_setup); | |
205 | ||
1da177e4 LT |
206 | dev_dbg(i2c->dev, "iiccon, %08lx\n", iiccon); |
207 | writel(iiccon, i2c->regs + S3C2410_IICCON); | |
3d0911bf BD |
208 | |
209 | stat |= S3C2410_IICSTAT_START; | |
1da177e4 LT |
210 | writel(stat, i2c->regs + S3C2410_IICSTAT); |
211 | } | |
212 | ||
213 | static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c *i2c, int ret) | |
214 | { | |
215 | unsigned long iicstat = readl(i2c->regs + S3C2410_IICSTAT); | |
216 | ||
217 | dev_dbg(i2c->dev, "STOP\n"); | |
218 | ||
219 | /* stop the transfer */ | |
3d0911bf | 220 | iicstat &= ~S3C2410_IICSTAT_START; |
1da177e4 | 221 | writel(iicstat, i2c->regs + S3C2410_IICSTAT); |
3d0911bf | 222 | |
1da177e4 | 223 | i2c->state = STATE_STOP; |
3d0911bf | 224 | |
1da177e4 LT |
225 | s3c24xx_i2c_master_complete(i2c, ret); |
226 | s3c24xx_i2c_disable_irq(i2c); | |
227 | } | |
228 | ||
229 | /* helper functions to determine the current state in the set of | |
230 | * messages we are sending */ | |
231 | ||
232 | /* is_lastmsg() | |
233 | * | |
3d0911bf | 234 | * returns TRUE if the current message is the last in the set |
1da177e4 LT |
235 | */ |
236 | ||
237 | static inline int is_lastmsg(struct s3c24xx_i2c *i2c) | |
238 | { | |
239 | return i2c->msg_idx >= (i2c->msg_num - 1); | |
240 | } | |
241 | ||
242 | /* is_msglast | |
243 | * | |
244 | * returns TRUE if we this is the last byte in the current message | |
245 | */ | |
246 | ||
247 | static inline int is_msglast(struct s3c24xx_i2c *i2c) | |
248 | { | |
249 | return i2c->msg_ptr == i2c->msg->len-1; | |
250 | } | |
251 | ||
252 | /* is_msgend | |
253 | * | |
254 | * returns TRUE if we reached the end of the current message | |
255 | */ | |
256 | ||
257 | static inline int is_msgend(struct s3c24xx_i2c *i2c) | |
258 | { | |
259 | return i2c->msg_ptr >= i2c->msg->len; | |
260 | } | |
261 | ||
19820510 | 262 | /* i2c_s3c_irq_nextbyte |
1da177e4 LT |
263 | * |
264 | * process an interrupt and work out what to do | |
265 | */ | |
266 | ||
19820510 | 267 | static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat) |
1da177e4 LT |
268 | { |
269 | unsigned long tmp; | |
270 | unsigned char byte; | |
271 | int ret = 0; | |
272 | ||
273 | switch (i2c->state) { | |
274 | ||
275 | case STATE_IDLE: | |
08882d20 | 276 | dev_err(i2c->dev, "%s: called in STATE_IDLE\n", __func__); |
1da177e4 | 277 | goto out; |
1da177e4 LT |
278 | |
279 | case STATE_STOP: | |
08882d20 | 280 | dev_err(i2c->dev, "%s: called in STATE_STOP\n", __func__); |
3d0911bf | 281 | s3c24xx_i2c_disable_irq(i2c); |
1da177e4 LT |
282 | goto out_ack; |
283 | ||
284 | case STATE_START: | |
285 | /* last thing we did was send a start condition on the | |
286 | * bus, or started a new i2c message | |
287 | */ | |
3d0911bf | 288 | |
63f5c289 | 289 | if (iicstat & S3C2410_IICSTAT_LASTBIT && |
1da177e4 LT |
290 | !(i2c->msg->flags & I2C_M_IGNORE_NAK)) { |
291 | /* ack was not received... */ | |
292 | ||
293 | dev_dbg(i2c->dev, "ack was not received\n"); | |
63f5c289 | 294 | s3c24xx_i2c_stop(i2c, -ENXIO); |
1da177e4 LT |
295 | goto out_ack; |
296 | } | |
297 | ||
298 | if (i2c->msg->flags & I2C_M_RD) | |
299 | i2c->state = STATE_READ; | |
300 | else | |
301 | i2c->state = STATE_WRITE; | |
302 | ||
303 | /* terminate the transfer if there is nothing to do | |
63f5c289 | 304 | * as this is used by the i2c probe to find devices. */ |
1da177e4 LT |
305 | |
306 | if (is_lastmsg(i2c) && i2c->msg->len == 0) { | |
307 | s3c24xx_i2c_stop(i2c, 0); | |
308 | goto out_ack; | |
309 | } | |
310 | ||
311 | if (i2c->state == STATE_READ) | |
312 | goto prepare_read; | |
313 | ||
3d0911bf | 314 | /* fall through to the write state, as we will need to |
1da177e4 LT |
315 | * send a byte as well */ |
316 | ||
317 | case STATE_WRITE: | |
318 | /* we are writing data to the device... check for the | |
319 | * end of the message, and if so, work out what to do | |
320 | */ | |
321 | ||
2709781b BD |
322 | if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) { |
323 | if (iicstat & S3C2410_IICSTAT_LASTBIT) { | |
324 | dev_dbg(i2c->dev, "WRITE: No Ack\n"); | |
325 | ||
326 | s3c24xx_i2c_stop(i2c, -ECONNREFUSED); | |
327 | goto out_ack; | |
328 | } | |
329 | } | |
330 | ||
3d0911bf | 331 | retry_write: |
2709781b | 332 | |
1da177e4 LT |
333 | if (!is_msgend(i2c)) { |
334 | byte = i2c->msg->buf[i2c->msg_ptr++]; | |
335 | writeb(byte, i2c->regs + S3C2410_IICDS); | |
e00a8cdf BD |
336 | |
337 | /* delay after writing the byte to allow the | |
338 | * data setup time on the bus, as writing the | |
339 | * data to the register causes the first bit | |
340 | * to appear on SDA, and SCL will change as | |
341 | * soon as the interrupt is acknowledged */ | |
342 | ||
343 | ndelay(i2c->tx_setup); | |
344 | ||
1da177e4 LT |
345 | } else if (!is_lastmsg(i2c)) { |
346 | /* we need to go to the next i2c message */ | |
347 | ||
348 | dev_dbg(i2c->dev, "WRITE: Next Message\n"); | |
349 | ||
350 | i2c->msg_ptr = 0; | |
3d0911bf | 351 | i2c->msg_idx++; |
1da177e4 | 352 | i2c->msg++; |
3d0911bf | 353 | |
1da177e4 LT |
354 | /* check to see if we need to do another message */ |
355 | if (i2c->msg->flags & I2C_M_NOSTART) { | |
356 | ||
357 | if (i2c->msg->flags & I2C_M_RD) { | |
358 | /* cannot do this, the controller | |
359 | * forces us to send a new START | |
360 | * when we change direction */ | |
361 | ||
362 | s3c24xx_i2c_stop(i2c, -EINVAL); | |
363 | } | |
364 | ||
365 | goto retry_write; | |
366 | } else { | |
1da177e4 LT |
367 | /* send the new start */ |
368 | s3c24xx_i2c_message_start(i2c, i2c->msg); | |
369 | i2c->state = STATE_START; | |
370 | } | |
371 | ||
372 | } else { | |
373 | /* send stop */ | |
374 | ||
375 | s3c24xx_i2c_stop(i2c, 0); | |
376 | } | |
377 | break; | |
378 | ||
379 | case STATE_READ: | |
3d0911bf | 380 | /* we have a byte of data in the data register, do |
1da177e4 LT |
381 | * something with it, and then work out wether we are |
382 | * going to do any more read/write | |
383 | */ | |
384 | ||
1da177e4 LT |
385 | byte = readb(i2c->regs + S3C2410_IICDS); |
386 | i2c->msg->buf[i2c->msg_ptr++] = byte; | |
387 | ||
3d0911bf | 388 | prepare_read: |
1da177e4 LT |
389 | if (is_msglast(i2c)) { |
390 | /* last byte of buffer */ | |
391 | ||
392 | if (is_lastmsg(i2c)) | |
393 | s3c24xx_i2c_disable_ack(i2c); | |
3d0911bf | 394 | |
1da177e4 LT |
395 | } else if (is_msgend(i2c)) { |
396 | /* ok, we've read the entire buffer, see if there | |
397 | * is anything else we need to do */ | |
398 | ||
399 | if (is_lastmsg(i2c)) { | |
400 | /* last message, send stop and complete */ | |
401 | dev_dbg(i2c->dev, "READ: Send Stop\n"); | |
402 | ||
403 | s3c24xx_i2c_stop(i2c, 0); | |
404 | } else { | |
405 | /* go to the next transfer */ | |
406 | dev_dbg(i2c->dev, "READ: Next Transfer\n"); | |
407 | ||
408 | i2c->msg_ptr = 0; | |
409 | i2c->msg_idx++; | |
410 | i2c->msg++; | |
411 | } | |
412 | } | |
413 | ||
414 | break; | |
415 | } | |
416 | ||
417 | /* acknowlegde the IRQ and get back on with the work */ | |
418 | ||
419 | out_ack: | |
3d0911bf | 420 | tmp = readl(i2c->regs + S3C2410_IICCON); |
1da177e4 LT |
421 | tmp &= ~S3C2410_IICCON_IRQPEND; |
422 | writel(tmp, i2c->regs + S3C2410_IICCON); | |
423 | out: | |
424 | return ret; | |
425 | } | |
426 | ||
427 | /* s3c24xx_i2c_irq | |
428 | * | |
429 | * top level IRQ servicing routine | |
430 | */ | |
431 | ||
7d12e780 | 432 | static irqreturn_t s3c24xx_i2c_irq(int irqno, void *dev_id) |
1da177e4 LT |
433 | { |
434 | struct s3c24xx_i2c *i2c = dev_id; | |
435 | unsigned long status; | |
436 | unsigned long tmp; | |
437 | ||
438 | status = readl(i2c->regs + S3C2410_IICSTAT); | |
439 | ||
440 | if (status & S3C2410_IICSTAT_ARBITR) { | |
3d0911bf | 441 | /* deal with arbitration loss */ |
1da177e4 LT |
442 | dev_err(i2c->dev, "deal with arbitration loss\n"); |
443 | } | |
444 | ||
445 | if (i2c->state == STATE_IDLE) { | |
446 | dev_dbg(i2c->dev, "IRQ: error i2c->state == IDLE\n"); | |
447 | ||
3d0911bf | 448 | tmp = readl(i2c->regs + S3C2410_IICCON); |
1da177e4 LT |
449 | tmp &= ~S3C2410_IICCON_IRQPEND; |
450 | writel(tmp, i2c->regs + S3C2410_IICCON); | |
451 | goto out; | |
452 | } | |
3d0911bf | 453 | |
1da177e4 LT |
454 | /* pretty much this leaves us with the fact that we've |
455 | * transmitted or received whatever byte we last sent */ | |
456 | ||
19820510 | 457 | i2c_s3c_irq_nextbyte(i2c, status); |
1da177e4 LT |
458 | |
459 | out: | |
460 | return IRQ_HANDLED; | |
461 | } | |
462 | ||
463 | ||
464 | /* s3c24xx_i2c_set_master | |
465 | * | |
466 | * get the i2c bus for a master transaction | |
467 | */ | |
468 | ||
469 | static int s3c24xx_i2c_set_master(struct s3c24xx_i2c *i2c) | |
470 | { | |
471 | unsigned long iicstat; | |
472 | int timeout = 400; | |
473 | ||
474 | while (timeout-- > 0) { | |
475 | iicstat = readl(i2c->regs + S3C2410_IICSTAT); | |
3d0911bf | 476 | |
1da177e4 LT |
477 | if (!(iicstat & S3C2410_IICSTAT_BUSBUSY)) |
478 | return 0; | |
479 | ||
480 | msleep(1); | |
481 | } | |
482 | ||
1da177e4 LT |
483 | return -ETIMEDOUT; |
484 | } | |
485 | ||
486 | /* s3c24xx_i2c_doxfer | |
487 | * | |
488 | * this starts an i2c transfer | |
489 | */ | |
490 | ||
3d0911bf BD |
491 | static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c, |
492 | struct i2c_msg *msgs, int num) | |
1da177e4 | 493 | { |
1bc2962e MB |
494 | unsigned long iicstat, timeout; |
495 | int spins = 20; | |
1da177e4 LT |
496 | int ret; |
497 | ||
be44f01e | 498 | if (i2c->suspended) |
61c7cff8 BD |
499 | return -EIO; |
500 | ||
1da177e4 LT |
501 | ret = s3c24xx_i2c_set_master(i2c); |
502 | if (ret != 0) { | |
503 | dev_err(i2c->dev, "cannot get bus (error %d)\n", ret); | |
504 | ret = -EAGAIN; | |
505 | goto out; | |
506 | } | |
507 | ||
508 | spin_lock_irq(&i2c->lock); | |
509 | ||
510 | i2c->msg = msgs; | |
511 | i2c->msg_num = num; | |
512 | i2c->msg_ptr = 0; | |
513 | i2c->msg_idx = 0; | |
514 | i2c->state = STATE_START; | |
515 | ||
516 | s3c24xx_i2c_enable_irq(i2c); | |
517 | s3c24xx_i2c_message_start(i2c, msgs); | |
518 | spin_unlock_irq(&i2c->lock); | |
3d0911bf | 519 | |
1da177e4 LT |
520 | timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5); |
521 | ||
522 | ret = i2c->msg_idx; | |
523 | ||
3d0911bf | 524 | /* having these next two as dev_err() makes life very |
1da177e4 LT |
525 | * noisy when doing an i2cdetect */ |
526 | ||
527 | if (timeout == 0) | |
528 | dev_dbg(i2c->dev, "timeout\n"); | |
529 | else if (ret != num) | |
530 | dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret); | |
531 | ||
532 | /* ensure the stop has been through the bus */ | |
533 | ||
1bc2962e MB |
534 | dev_dbg(i2c->dev, "waiting for bus idle\n"); |
535 | ||
536 | /* first, try busy waiting briefly */ | |
537 | do { | |
37de03ea | 538 | cpu_relax(); |
1bc2962e MB |
539 | iicstat = readl(i2c->regs + S3C2410_IICSTAT); |
540 | } while ((iicstat & S3C2410_IICSTAT_START) && --spins); | |
541 | ||
542 | /* if that timed out sleep */ | |
543 | if (!spins) { | |
544 | msleep(1); | |
545 | iicstat = readl(i2c->regs + S3C2410_IICSTAT); | |
546 | } | |
547 | ||
548 | if (iicstat & S3C2410_IICSTAT_START) | |
549 | dev_warn(i2c->dev, "timeout waiting for bus idle\n"); | |
1da177e4 LT |
550 | |
551 | out: | |
552 | return ret; | |
553 | } | |
554 | ||
555 | /* s3c24xx_i2c_xfer | |
556 | * | |
557 | * first port of call from the i2c bus code when an message needs | |
44bbe87e | 558 | * transferring across the i2c bus. |
1da177e4 LT |
559 | */ |
560 | ||
561 | static int s3c24xx_i2c_xfer(struct i2c_adapter *adap, | |
562 | struct i2c_msg *msgs, int num) | |
563 | { | |
564 | struct s3c24xx_i2c *i2c = (struct s3c24xx_i2c *)adap->algo_data; | |
565 | int retry; | |
566 | int ret; | |
567 | ||
c62c3ca5 | 568 | pm_runtime_get_sync(&adap->dev); |
d2360b8e APR |
569 | clk_enable(i2c->clk); |
570 | ||
1da177e4 LT |
571 | for (retry = 0; retry < adap->retries; retry++) { |
572 | ||
573 | ret = s3c24xx_i2c_doxfer(i2c, msgs, num); | |
574 | ||
d2360b8e APR |
575 | if (ret != -EAGAIN) { |
576 | clk_disable(i2c->clk); | |
c62c3ca5 | 577 | pm_runtime_put_sync(&adap->dev); |
1da177e4 | 578 | return ret; |
d2360b8e | 579 | } |
1da177e4 LT |
580 | |
581 | dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry); | |
582 | ||
583 | udelay(100); | |
584 | } | |
585 | ||
d2360b8e | 586 | clk_disable(i2c->clk); |
c62c3ca5 | 587 | pm_runtime_put_sync(&adap->dev); |
1da177e4 LT |
588 | return -EREMOTEIO; |
589 | } | |
590 | ||
591 | /* declare our i2c functionality */ | |
592 | static u32 s3c24xx_i2c_func(struct i2c_adapter *adap) | |
593 | { | |
594 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING; | |
595 | } | |
596 | ||
597 | /* i2c bus registration info */ | |
598 | ||
8f9082c5 | 599 | static const struct i2c_algorithm s3c24xx_i2c_algorithm = { |
1da177e4 LT |
600 | .master_xfer = s3c24xx_i2c_xfer, |
601 | .functionality = s3c24xx_i2c_func, | |
602 | }; | |
603 | ||
1da177e4 LT |
604 | /* s3c24xx_i2c_calcdivisor |
605 | * | |
606 | * return the divisor settings for a given frequency | |
607 | */ | |
608 | ||
609 | static int s3c24xx_i2c_calcdivisor(unsigned long clkin, unsigned int wanted, | |
610 | unsigned int *div1, unsigned int *divs) | |
611 | { | |
612 | unsigned int calc_divs = clkin / wanted; | |
613 | unsigned int calc_div1; | |
614 | ||
615 | if (calc_divs > (16*16)) | |
616 | calc_div1 = 512; | |
617 | else | |
618 | calc_div1 = 16; | |
619 | ||
620 | calc_divs += calc_div1-1; | |
621 | calc_divs /= calc_div1; | |
622 | ||
623 | if (calc_divs == 0) | |
624 | calc_divs = 1; | |
625 | if (calc_divs > 17) | |
626 | calc_divs = 17; | |
627 | ||
628 | *divs = calc_divs; | |
629 | *div1 = calc_div1; | |
630 | ||
631 | return clkin / (calc_divs * calc_div1); | |
632 | } | |
633 | ||
61c7cff8 | 634 | /* s3c24xx_i2c_clockrate |
1da177e4 LT |
635 | * |
636 | * work out a divisor for the user requested frequency setting, | |
637 | * either by the requested frequency, or scanning the acceptable | |
638 | * range of frequencies until something is found | |
639 | */ | |
640 | ||
61c7cff8 | 641 | static int s3c24xx_i2c_clockrate(struct s3c24xx_i2c *i2c, unsigned int *got) |
1da177e4 | 642 | { |
4fd81eb2 | 643 | struct s3c2410_platform_i2c *pdata = i2c->pdata; |
1da177e4 | 644 | unsigned long clkin = clk_get_rate(i2c->clk); |
1da177e4 | 645 | unsigned int divs, div1; |
c564e6ae | 646 | unsigned long target_frequency; |
61c7cff8 | 647 | u32 iiccon; |
1da177e4 | 648 | int freq; |
1da177e4 | 649 | |
61c7cff8 | 650 | i2c->clkrate = clkin; |
1da177e4 | 651 | clkin /= 1000; /* clkin now in KHz */ |
3d0911bf | 652 | |
c564e6ae | 653 | dev_dbg(i2c->dev, "pdata desired frequency %lu\n", pdata->frequency); |
1da177e4 | 654 | |
c564e6ae | 655 | target_frequency = pdata->frequency ? pdata->frequency : 100000; |
1da177e4 | 656 | |
c564e6ae | 657 | target_frequency /= 1000; /* Target frequency now in KHz */ |
1da177e4 | 658 | |
c564e6ae | 659 | freq = s3c24xx_i2c_calcdivisor(clkin, target_frequency, &div1, &divs); |
1da177e4 | 660 | |
c564e6ae DS |
661 | if (freq > target_frequency) { |
662 | dev_err(i2c->dev, | |
663 | "Unable to achieve desired frequency %luKHz." \ | |
664 | " Lowest achievable %dKHz\n", target_frequency, freq); | |
665 | return -EINVAL; | |
1da177e4 LT |
666 | } |
667 | ||
1da177e4 | 668 | *got = freq; |
61c7cff8 BD |
669 | |
670 | iiccon = readl(i2c->regs + S3C2410_IICCON); | |
671 | iiccon &= ~(S3C2410_IICCON_SCALEMASK | S3C2410_IICCON_TXDIV_512); | |
672 | iiccon |= (divs-1); | |
673 | ||
674 | if (div1 == 512) | |
675 | iiccon |= S3C2410_IICCON_TXDIV_512; | |
676 | ||
677 | writel(iiccon, i2c->regs + S3C2410_IICCON); | |
678 | ||
a192f715 BD |
679 | if (s3c24xx_i2c_is2440(i2c)) { |
680 | unsigned long sda_delay; | |
681 | ||
682 | if (pdata->sda_delay) { | |
7031307a MH |
683 | sda_delay = clkin * pdata->sda_delay; |
684 | sda_delay = DIV_ROUND_UP(sda_delay, 1000000); | |
a192f715 BD |
685 | sda_delay = DIV_ROUND_UP(sda_delay, 5); |
686 | if (sda_delay > 3) | |
687 | sda_delay = 3; | |
688 | sda_delay |= S3C2410_IICLC_FILTER_ON; | |
689 | } else | |
690 | sda_delay = 0; | |
691 | ||
692 | dev_dbg(i2c->dev, "IICLC=%08lx\n", sda_delay); | |
693 | writel(sda_delay, i2c->regs + S3C2440_IICLC); | |
694 | } | |
695 | ||
61c7cff8 BD |
696 | return 0; |
697 | } | |
698 | ||
699 | #ifdef CONFIG_CPU_FREQ | |
700 | ||
701 | #define freq_to_i2c(_n) container_of(_n, struct s3c24xx_i2c, freq_transition) | |
702 | ||
703 | static int s3c24xx_i2c_cpufreq_transition(struct notifier_block *nb, | |
704 | unsigned long val, void *data) | |
705 | { | |
706 | struct s3c24xx_i2c *i2c = freq_to_i2c(nb); | |
707 | unsigned long flags; | |
708 | unsigned int got; | |
709 | int delta_f; | |
710 | int ret; | |
711 | ||
712 | delta_f = clk_get_rate(i2c->clk) - i2c->clkrate; | |
713 | ||
714 | /* if we're post-change and the input clock has slowed down | |
715 | * or at pre-change and the clock is about to speed up, then | |
716 | * adjust our clock rate. <0 is slow, >0 speedup. | |
717 | */ | |
718 | ||
719 | if ((val == CPUFREQ_POSTCHANGE && delta_f < 0) || | |
720 | (val == CPUFREQ_PRECHANGE && delta_f > 0)) { | |
721 | spin_lock_irqsave(&i2c->lock, flags); | |
722 | ret = s3c24xx_i2c_clockrate(i2c, &got); | |
723 | spin_unlock_irqrestore(&i2c->lock, flags); | |
724 | ||
725 | if (ret < 0) | |
726 | dev_err(i2c->dev, "cannot find frequency\n"); | |
727 | else | |
728 | dev_info(i2c->dev, "setting freq %d\n", got); | |
729 | } | |
730 | ||
1da177e4 LT |
731 | return 0; |
732 | } | |
733 | ||
61c7cff8 BD |
734 | static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c) |
735 | { | |
736 | i2c->freq_transition.notifier_call = s3c24xx_i2c_cpufreq_transition; | |
737 | ||
738 | return cpufreq_register_notifier(&i2c->freq_transition, | |
739 | CPUFREQ_TRANSITION_NOTIFIER); | |
740 | } | |
741 | ||
742 | static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c) | |
743 | { | |
744 | cpufreq_unregister_notifier(&i2c->freq_transition, | |
745 | CPUFREQ_TRANSITION_NOTIFIER); | |
746 | } | |
747 | ||
748 | #else | |
749 | static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c) | |
750 | { | |
1da177e4 LT |
751 | return 0; |
752 | } | |
753 | ||
61c7cff8 BD |
754 | static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c) |
755 | { | |
756 | } | |
757 | #endif | |
758 | ||
5a5f5080 TA |
759 | #ifdef CONFIG_OF |
760 | static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c *i2c) | |
761 | { | |
762 | int idx, gpio, ret; | |
763 | ||
764 | for (idx = 0; idx < 2; idx++) { | |
765 | gpio = of_get_gpio(i2c->dev->of_node, idx); | |
766 | if (!gpio_is_valid(gpio)) { | |
767 | dev_err(i2c->dev, "invalid gpio[%d]: %d\n", idx, gpio); | |
768 | goto free_gpio; | |
769 | } | |
770 | ||
771 | ret = gpio_request(gpio, "i2c-bus"); | |
772 | if (ret) { | |
773 | dev_err(i2c->dev, "gpio [%d] request failed\n", gpio); | |
774 | goto free_gpio; | |
775 | } | |
776 | } | |
777 | return 0; | |
778 | ||
779 | free_gpio: | |
780 | while (--idx >= 0) | |
781 | gpio_free(i2c->gpios[idx]); | |
782 | return -EINVAL; | |
783 | } | |
784 | ||
785 | static void s3c24xx_i2c_dt_gpio_free(struct s3c24xx_i2c *i2c) | |
786 | { | |
787 | unsigned int idx; | |
788 | for (idx = 0; idx < 2; idx++) | |
789 | gpio_free(i2c->gpios[idx]); | |
790 | } | |
791 | #else | |
792 | static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c *i2c) | |
793 | { | |
8ebe661d | 794 | return 0; |
5a5f5080 TA |
795 | } |
796 | ||
797 | static void s3c24xx_i2c_dt_gpio_free(struct s3c24xx_i2c *i2c) | |
798 | { | |
799 | } | |
800 | #endif | |
801 | ||
1da177e4 LT |
802 | /* s3c24xx_i2c_init |
803 | * | |
3d0911bf | 804 | * initialise the controller, set the IO lines and frequency |
1da177e4 LT |
805 | */ |
806 | ||
807 | static int s3c24xx_i2c_init(struct s3c24xx_i2c *i2c) | |
808 | { | |
809 | unsigned long iicon = S3C2410_IICCON_IRQEN | S3C2410_IICCON_ACKEN; | |
810 | struct s3c2410_platform_i2c *pdata; | |
811 | unsigned int freq; | |
812 | ||
813 | /* get the plafrom data */ | |
814 | ||
4fd81eb2 | 815 | pdata = i2c->pdata; |
1da177e4 LT |
816 | |
817 | /* inititalise the gpio */ | |
818 | ||
8be310a6 BD |
819 | if (pdata->cfg_gpio) |
820 | pdata->cfg_gpio(to_platform_device(i2c->dev)); | |
5a5f5080 TA |
821 | else |
822 | if (s3c24xx_i2c_parse_dt_gpio(i2c)) | |
823 | return -EINVAL; | |
1da177e4 LT |
824 | |
825 | /* write slave address */ | |
3d0911bf | 826 | |
1da177e4 LT |
827 | writeb(pdata->slave_addr, i2c->regs + S3C2410_IICADD); |
828 | ||
829 | dev_info(i2c->dev, "slave address 0x%02x\n", pdata->slave_addr); | |
830 | ||
61c7cff8 BD |
831 | writel(iicon, i2c->regs + S3C2410_IICCON); |
832 | ||
1da177e4 LT |
833 | /* we need to work out the divisors for the clock... */ |
834 | ||
61c7cff8 BD |
835 | if (s3c24xx_i2c_clockrate(i2c, &freq) != 0) { |
836 | writel(0, i2c->regs + S3C2410_IICCON); | |
1da177e4 LT |
837 | dev_err(i2c->dev, "cannot meet bus frequency required\n"); |
838 | return -EINVAL; | |
839 | } | |
840 | ||
841 | /* todo - check that the i2c lines aren't being dragged anywhere */ | |
842 | ||
843 | dev_info(i2c->dev, "bus frequency set to %d KHz\n", freq); | |
844 | dev_dbg(i2c->dev, "S3C2410_IICCON=0x%02lx\n", iicon); | |
1da177e4 | 845 | |
1da177e4 LT |
846 | return 0; |
847 | } | |
848 | ||
5a5f5080 TA |
849 | #ifdef CONFIG_OF |
850 | /* s3c24xx_i2c_parse_dt | |
851 | * | |
852 | * Parse the device tree node and retreive the platform data. | |
853 | */ | |
854 | ||
855 | static void | |
856 | s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c) | |
857 | { | |
858 | struct s3c2410_platform_i2c *pdata = i2c->pdata; | |
859 | ||
860 | if (!np) | |
861 | return; | |
862 | ||
863 | pdata->bus_num = -1; /* i2c bus number is dynamically assigned */ | |
864 | of_property_read_u32(np, "samsung,i2c-sda-delay", &pdata->sda_delay); | |
865 | of_property_read_u32(np, "samsung,i2c-slave-addr", &pdata->slave_addr); | |
866 | of_property_read_u32(np, "samsung,i2c-max-bus-freq", | |
867 | (u32 *)&pdata->frequency); | |
868 | } | |
869 | #else | |
870 | static void | |
871 | s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c) | |
872 | { | |
873 | return; | |
874 | } | |
875 | #endif | |
876 | ||
1da177e4 LT |
877 | /* s3c24xx_i2c_probe |
878 | * | |
879 | * called by the bus driver when a suitable device is found | |
880 | */ | |
881 | ||
3ae5eaec | 882 | static int s3c24xx_i2c_probe(struct platform_device *pdev) |
1da177e4 | 883 | { |
692acbd3 | 884 | struct s3c24xx_i2c *i2c; |
4fd81eb2 | 885 | struct s3c2410_platform_i2c *pdata = NULL; |
1da177e4 LT |
886 | struct resource *res; |
887 | int ret; | |
888 | ||
5a5f5080 TA |
889 | if (!pdev->dev.of_node) { |
890 | pdata = pdev->dev.platform_data; | |
891 | if (!pdata) { | |
892 | dev_err(&pdev->dev, "no platform data\n"); | |
893 | return -EINVAL; | |
894 | } | |
6a039cab | 895 | } |
399dee23 | 896 | |
4ea1557f | 897 | i2c = devm_kzalloc(&pdev->dev, sizeof(struct s3c24xx_i2c), GFP_KERNEL); |
692acbd3 BD |
898 | if (!i2c) { |
899 | dev_err(&pdev->dev, "no memory for state\n"); | |
900 | return -ENOMEM; | |
901 | } | |
902 | ||
4fd81eb2 TA |
903 | i2c->pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); |
904 | if (!i2c->pdata) { | |
905 | ret = -ENOMEM; | |
906 | goto err_noclk; | |
907 | } | |
908 | ||
909 | if (pdata) | |
910 | memcpy(i2c->pdata, pdata, sizeof(*pdata)); | |
5a5f5080 TA |
911 | else |
912 | s3c24xx_i2c_parse_dt(pdev->dev.of_node, i2c); | |
4fd81eb2 | 913 | |
692acbd3 BD |
914 | strlcpy(i2c->adap.name, "s3c2410-i2c", sizeof(i2c->adap.name)); |
915 | i2c->adap.owner = THIS_MODULE; | |
916 | i2c->adap.algo = &s3c24xx_i2c_algorithm; | |
917 | i2c->adap.retries = 2; | |
918 | i2c->adap.class = I2C_CLASS_HWMON | I2C_CLASS_SPD; | |
919 | i2c->tx_setup = 50; | |
920 | ||
921 | spin_lock_init(&i2c->lock); | |
922 | init_waitqueue_head(&i2c->wait); | |
399dee23 | 923 | |
1da177e4 LT |
924 | /* find the clock and enable it */ |
925 | ||
3ae5eaec RK |
926 | i2c->dev = &pdev->dev; |
927 | i2c->clk = clk_get(&pdev->dev, "i2c"); | |
1da177e4 | 928 | if (IS_ERR(i2c->clk)) { |
3ae5eaec | 929 | dev_err(&pdev->dev, "cannot get clock\n"); |
1da177e4 | 930 | ret = -ENOENT; |
5b68790c | 931 | goto err_noclk; |
1da177e4 LT |
932 | } |
933 | ||
3ae5eaec | 934 | dev_dbg(&pdev->dev, "clock source %p\n", i2c->clk); |
1da177e4 | 935 | |
1da177e4 LT |
936 | clk_enable(i2c->clk); |
937 | ||
938 | /* map the registers */ | |
939 | ||
940 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
941 | if (res == NULL) { | |
3ae5eaec | 942 | dev_err(&pdev->dev, "cannot find IO resource\n"); |
1da177e4 | 943 | ret = -ENOENT; |
5b68790c | 944 | goto err_clk; |
1da177e4 LT |
945 | } |
946 | ||
933a2aec | 947 | i2c->ioarea = request_mem_region(res->start, resource_size(res), |
1da177e4 LT |
948 | pdev->name); |
949 | ||
950 | if (i2c->ioarea == NULL) { | |
3ae5eaec | 951 | dev_err(&pdev->dev, "cannot request IO\n"); |
1da177e4 | 952 | ret = -ENXIO; |
5b68790c | 953 | goto err_clk; |
1da177e4 LT |
954 | } |
955 | ||
933a2aec | 956 | i2c->regs = ioremap(res->start, resource_size(res)); |
1da177e4 LT |
957 | |
958 | if (i2c->regs == NULL) { | |
3ae5eaec | 959 | dev_err(&pdev->dev, "cannot map IO\n"); |
1da177e4 | 960 | ret = -ENXIO; |
5b68790c | 961 | goto err_ioarea; |
1da177e4 LT |
962 | } |
963 | ||
3d0911bf BD |
964 | dev_dbg(&pdev->dev, "registers %p (%p, %p)\n", |
965 | i2c->regs, i2c->ioarea, res); | |
1da177e4 LT |
966 | |
967 | /* setup info block for the i2c core */ | |
968 | ||
969 | i2c->adap.algo_data = i2c; | |
3ae5eaec | 970 | i2c->adap.dev.parent = &pdev->dev; |
1da177e4 LT |
971 | |
972 | /* initialise the i2c controller */ | |
973 | ||
974 | ret = s3c24xx_i2c_init(i2c); | |
975 | if (ret != 0) | |
5b68790c | 976 | goto err_iomap; |
1da177e4 LT |
977 | |
978 | /* find the IRQ for this unit (note, this relies on the init call to | |
3d0911bf | 979 | * ensure no current IRQs pending |
1da177e4 LT |
980 | */ |
981 | ||
e0d1ec97 BD |
982 | i2c->irq = ret = platform_get_irq(pdev, 0); |
983 | if (ret <= 0) { | |
3ae5eaec | 984 | dev_err(&pdev->dev, "cannot find IRQ\n"); |
5b68790c | 985 | goto err_iomap; |
1da177e4 LT |
986 | } |
987 | ||
4311051c | 988 | ret = request_irq(i2c->irq, s3c24xx_i2c_irq, 0, |
e0d1ec97 | 989 | dev_name(&pdev->dev), i2c); |
1da177e4 LT |
990 | |
991 | if (ret != 0) { | |
e0d1ec97 | 992 | dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq); |
5b68790c | 993 | goto err_iomap; |
1da177e4 LT |
994 | } |
995 | ||
61c7cff8 | 996 | ret = s3c24xx_i2c_register_cpufreq(i2c); |
1da177e4 | 997 | if (ret < 0) { |
61c7cff8 | 998 | dev_err(&pdev->dev, "failed to register cpufreq notifier\n"); |
5b68790c | 999 | goto err_irq; |
1da177e4 LT |
1000 | } |
1001 | ||
399dee23 BD |
1002 | /* Note, previous versions of the driver used i2c_add_adapter() |
1003 | * to add the bus at any number. We now pass the bus number via | |
1004 | * the platform data, so if unset it will now default to always | |
1005 | * being bus 0. | |
1006 | */ | |
1007 | ||
4fd81eb2 | 1008 | i2c->adap.nr = i2c->pdata->bus_num; |
5a5f5080 | 1009 | i2c->adap.dev.of_node = pdev->dev.of_node; |
399dee23 BD |
1010 | |
1011 | ret = i2c_add_numbered_adapter(&i2c->adap); | |
1da177e4 | 1012 | if (ret < 0) { |
3ae5eaec | 1013 | dev_err(&pdev->dev, "failed to add bus to i2c core\n"); |
61c7cff8 | 1014 | goto err_cpufreq; |
1da177e4 LT |
1015 | } |
1016 | ||
5a5f5080 | 1017 | of_i2c_register_devices(&i2c->adap); |
3ae5eaec | 1018 | platform_set_drvdata(pdev, i2c); |
1da177e4 | 1019 | |
c62c3ca5 MB |
1020 | pm_runtime_enable(&pdev->dev); |
1021 | pm_runtime_enable(&i2c->adap.dev); | |
1022 | ||
22e965c2 | 1023 | dev_info(&pdev->dev, "%s: S3C I2C adapter\n", dev_name(&i2c->adap.dev)); |
d2360b8e | 1024 | clk_disable(i2c->clk); |
5b68790c | 1025 | return 0; |
1da177e4 | 1026 | |
61c7cff8 BD |
1027 | err_cpufreq: |
1028 | s3c24xx_i2c_deregister_cpufreq(i2c); | |
1029 | ||
5b68790c | 1030 | err_irq: |
e0d1ec97 | 1031 | free_irq(i2c->irq, i2c); |
5b68790c BD |
1032 | |
1033 | err_iomap: | |
1034 | iounmap(i2c->regs); | |
1035 | ||
1036 | err_ioarea: | |
1037 | release_resource(i2c->ioarea); | |
1038 | kfree(i2c->ioarea); | |
1039 | ||
1040 | err_clk: | |
1041 | clk_disable(i2c->clk); | |
1042 | clk_put(i2c->clk); | |
1da177e4 | 1043 | |
5b68790c | 1044 | err_noclk: |
1da177e4 LT |
1045 | return ret; |
1046 | } | |
1047 | ||
1048 | /* s3c24xx_i2c_remove | |
1049 | * | |
1050 | * called when device is removed from the bus | |
1051 | */ | |
1052 | ||
3ae5eaec | 1053 | static int s3c24xx_i2c_remove(struct platform_device *pdev) |
1da177e4 | 1054 | { |
3ae5eaec | 1055 | struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev); |
5b68790c | 1056 | |
c62c3ca5 MB |
1057 | pm_runtime_disable(&i2c->adap.dev); |
1058 | pm_runtime_disable(&pdev->dev); | |
1059 | ||
61c7cff8 BD |
1060 | s3c24xx_i2c_deregister_cpufreq(i2c); |
1061 | ||
5b68790c | 1062 | i2c_del_adapter(&i2c->adap); |
e0d1ec97 | 1063 | free_irq(i2c->irq, i2c); |
5b68790c BD |
1064 | |
1065 | clk_disable(i2c->clk); | |
1066 | clk_put(i2c->clk); | |
1067 | ||
1068 | iounmap(i2c->regs); | |
1069 | ||
1070 | release_resource(i2c->ioarea); | |
5a5f5080 | 1071 | s3c24xx_i2c_dt_gpio_free(i2c); |
5b68790c | 1072 | kfree(i2c->ioarea); |
1da177e4 LT |
1073 | |
1074 | return 0; | |
1075 | } | |
1076 | ||
1077 | #ifdef CONFIG_PM | |
6a6c6189 | 1078 | static int s3c24xx_i2c_suspend_noirq(struct device *dev) |
be44f01e | 1079 | { |
6a6c6189 MD |
1080 | struct platform_device *pdev = to_platform_device(dev); |
1081 | struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev); | |
1082 | ||
be44f01e | 1083 | i2c->suspended = 1; |
6a6c6189 | 1084 | |
be44f01e BD |
1085 | return 0; |
1086 | } | |
1087 | ||
6a6c6189 | 1088 | static int s3c24xx_i2c_resume(struct device *dev) |
1da177e4 | 1089 | { |
6a6c6189 MD |
1090 | struct platform_device *pdev = to_platform_device(dev); |
1091 | struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev); | |
9480e307 | 1092 | |
be44f01e | 1093 | i2c->suspended = 0; |
d2360b8e | 1094 | clk_enable(i2c->clk); |
be44f01e | 1095 | s3c24xx_i2c_init(i2c); |
d2360b8e | 1096 | clk_disable(i2c->clk); |
1da177e4 LT |
1097 | |
1098 | return 0; | |
1099 | } | |
1100 | ||
47145210 | 1101 | static const struct dev_pm_ops s3c24xx_i2c_dev_pm_ops = { |
6a6c6189 MD |
1102 | .suspend_noirq = s3c24xx_i2c_suspend_noirq, |
1103 | .resume = s3c24xx_i2c_resume, | |
1104 | }; | |
1105 | ||
1106 | #define S3C24XX_DEV_PM_OPS (&s3c24xx_i2c_dev_pm_ops) | |
1da177e4 | 1107 | #else |
6a6c6189 | 1108 | #define S3C24XX_DEV_PM_OPS NULL |
1da177e4 LT |
1109 | #endif |
1110 | ||
1111 | /* device driver for platform bus bits */ | |
1112 | ||
7d85ccd8 BD |
1113 | static struct platform_device_id s3c24xx_driver_ids[] = { |
1114 | { | |
1115 | .name = "s3c2410-i2c", | |
1116 | .driver_data = TYPE_S3C2410, | |
1117 | }, { | |
1118 | .name = "s3c2440-i2c", | |
1119 | .driver_data = TYPE_S3C2440, | |
1120 | }, { }, | |
1da177e4 | 1121 | }; |
7d85ccd8 | 1122 | MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids); |
1da177e4 | 1123 | |
5a5f5080 TA |
1124 | #ifdef CONFIG_OF |
1125 | static const struct of_device_id s3c24xx_i2c_match[] = { | |
1126 | { .compatible = "samsung,s3c2410-i2c" }, | |
1127 | { .compatible = "samsung,s3c2440-i2c" }, | |
1128 | {}, | |
1129 | }; | |
1130 | MODULE_DEVICE_TABLE(of, s3c24xx_i2c_match); | |
1131 | #else | |
1132 | #define s3c24xx_i2c_match NULL | |
1133 | #endif | |
1134 | ||
7d85ccd8 | 1135 | static struct platform_driver s3c24xx_i2c_driver = { |
1da177e4 LT |
1136 | .probe = s3c24xx_i2c_probe, |
1137 | .remove = s3c24xx_i2c_remove, | |
7d85ccd8 | 1138 | .id_table = s3c24xx_driver_ids, |
3ae5eaec RK |
1139 | .driver = { |
1140 | .owner = THIS_MODULE, | |
7d85ccd8 | 1141 | .name = "s3c-i2c", |
6a6c6189 | 1142 | .pm = S3C24XX_DEV_PM_OPS, |
5a5f5080 | 1143 | .of_match_table = s3c24xx_i2c_match, |
3ae5eaec | 1144 | }, |
1da177e4 LT |
1145 | }; |
1146 | ||
1147 | static int __init i2c_adap_s3c_init(void) | |
1148 | { | |
7d85ccd8 | 1149 | return platform_driver_register(&s3c24xx_i2c_driver); |
1da177e4 | 1150 | } |
18dc83a6 | 1151 | subsys_initcall(i2c_adap_s3c_init); |
1da177e4 LT |
1152 | |
1153 | static void __exit i2c_adap_s3c_exit(void) | |
1154 | { | |
7d85ccd8 | 1155 | platform_driver_unregister(&s3c24xx_i2c_driver); |
1da177e4 | 1156 | } |
1da177e4 LT |
1157 | module_exit(i2c_adap_s3c_exit); |
1158 | ||
1159 | MODULE_DESCRIPTION("S3C24XX I2C Bus driver"); | |
1160 | MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>"); | |
1161 | MODULE_LICENSE("GPL"); |