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1da177e4 LT |
1 | /* linux/drivers/i2c/busses/i2c-s3c2410.c |
2 | * | |
c564e6ae | 3 | * Copyright (C) 2004,2005,2009 Simtec Electronics |
1da177e4 LT |
4 | * Ben Dooks <ben@simtec.co.uk> |
5 | * | |
6 | * S3C2410 I2C Controller | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | #include <linux/kernel.h> | |
24 | #include <linux/module.h> | |
25 | ||
26 | #include <linux/i2c.h> | |
1da177e4 LT |
27 | #include <linux/init.h> |
28 | #include <linux/time.h> | |
29 | #include <linux/interrupt.h> | |
1da177e4 LT |
30 | #include <linux/delay.h> |
31 | #include <linux/errno.h> | |
32 | #include <linux/err.h> | |
d052d1be | 33 | #include <linux/platform_device.h> |
c62c3ca5 | 34 | #include <linux/pm_runtime.h> |
f8ce2547 | 35 | #include <linux/clk.h> |
61c7cff8 | 36 | #include <linux/cpufreq.h> |
5a0e3ad6 | 37 | #include <linux/slab.h> |
21782180 | 38 | #include <linux/io.h> |
5a5f5080 | 39 | #include <linux/of_gpio.h> |
2693ac69 | 40 | #include <linux/pinctrl/consumer.h> |
1da177e4 | 41 | |
1da177e4 | 42 | #include <asm/irq.h> |
1da177e4 | 43 | |
436d42c6 | 44 | #include <linux/platform_data/i2c-s3c2410.h> |
1da177e4 | 45 | |
e636602a HS |
46 | /* see s3c2410x user guide, v1.1, section 9 (p447) for more info */ |
47 | ||
7a6674da HS |
48 | #define S3C2410_IICCON 0x00 |
49 | #define S3C2410_IICSTAT 0x04 | |
50 | #define S3C2410_IICADD 0x08 | |
51 | #define S3C2410_IICDS 0x0C | |
52 | #define S3C2440_IICLC 0x10 | |
e636602a | 53 | |
7a6674da HS |
54 | #define S3C2410_IICCON_ACKEN (1 << 7) |
55 | #define S3C2410_IICCON_TXDIV_16 (0 << 6) | |
56 | #define S3C2410_IICCON_TXDIV_512 (1 << 6) | |
57 | #define S3C2410_IICCON_IRQEN (1 << 5) | |
58 | #define S3C2410_IICCON_IRQPEND (1 << 4) | |
59 | #define S3C2410_IICCON_SCALE(x) ((x) & 0xf) | |
e636602a HS |
60 | #define S3C2410_IICCON_SCALEMASK (0xf) |
61 | ||
7a6674da HS |
62 | #define S3C2410_IICSTAT_MASTER_RX (2 << 6) |
63 | #define S3C2410_IICSTAT_MASTER_TX (3 << 6) | |
64 | #define S3C2410_IICSTAT_SLAVE_RX (0 << 6) | |
65 | #define S3C2410_IICSTAT_SLAVE_TX (1 << 6) | |
66 | #define S3C2410_IICSTAT_MODEMASK (3 << 6) | |
e636602a | 67 | |
7a6674da HS |
68 | #define S3C2410_IICSTAT_START (1 << 5) |
69 | #define S3C2410_IICSTAT_BUSBUSY (1 << 5) | |
70 | #define S3C2410_IICSTAT_TXRXEN (1 << 4) | |
71 | #define S3C2410_IICSTAT_ARBITR (1 << 3) | |
72 | #define S3C2410_IICSTAT_ASSLAVE (1 << 2) | |
73 | #define S3C2410_IICSTAT_ADDR0 (1 << 1) | |
74 | #define S3C2410_IICSTAT_LASTBIT (1 << 0) | |
e636602a HS |
75 | |
76 | #define S3C2410_IICLC_SDA_DELAY0 (0 << 0) | |
77 | #define S3C2410_IICLC_SDA_DELAY5 (1 << 0) | |
78 | #define S3C2410_IICLC_SDA_DELAY10 (2 << 0) | |
79 | #define S3C2410_IICLC_SDA_DELAY15 (3 << 0) | |
80 | #define S3C2410_IICLC_SDA_DELAY_MASK (3 << 0) | |
81 | ||
7a6674da | 82 | #define S3C2410_IICLC_FILTER_ON (1 << 2) |
e636602a | 83 | |
27452498 KL |
84 | /* Treat S3C2410 as baseline hardware, anything else is supported via quirks */ |
85 | #define QUIRK_S3C2440 (1 << 0) | |
ec39ef83 KL |
86 | #define QUIRK_HDMIPHY (1 << 1) |
87 | #define QUIRK_NO_GPIO (1 << 2) | |
1da177e4 | 88 | |
fe724bf9 DK |
89 | /* Max time to wait for bus to become idle after a xfer (in us) */ |
90 | #define S3C2410_IDLE_TIMEOUT 5000 | |
91 | ||
27452498 | 92 | /* i2c controller state */ |
1da177e4 LT |
93 | enum s3c24xx_i2c_state { |
94 | STATE_IDLE, | |
95 | STATE_START, | |
96 | STATE_READ, | |
97 | STATE_WRITE, | |
98 | STATE_STOP | |
99 | }; | |
100 | ||
101 | struct s3c24xx_i2c { | |
1da177e4 | 102 | wait_queue_head_t wait; |
27452498 | 103 | unsigned int quirks; |
be44f01e | 104 | unsigned int suspended:1; |
1da177e4 LT |
105 | |
106 | struct i2c_msg *msg; | |
107 | unsigned int msg_num; | |
108 | unsigned int msg_idx; | |
109 | unsigned int msg_ptr; | |
110 | ||
e00a8cdf | 111 | unsigned int tx_setup; |
e0d1ec97 | 112 | unsigned int irq; |
e00a8cdf | 113 | |
1da177e4 | 114 | enum s3c24xx_i2c_state state; |
61c7cff8 | 115 | unsigned long clkrate; |
1da177e4 LT |
116 | |
117 | void __iomem *regs; | |
118 | struct clk *clk; | |
119 | struct device *dev; | |
1da177e4 | 120 | struct i2c_adapter adap; |
61c7cff8 | 121 | |
4fd81eb2 | 122 | struct s3c2410_platform_i2c *pdata; |
5a5f5080 | 123 | int gpios[2]; |
2693ac69 | 124 | struct pinctrl *pctrl; |
61c7cff8 BD |
125 | #ifdef CONFIG_CPU_FREQ |
126 | struct notifier_block freq_transition; | |
127 | #endif | |
1da177e4 LT |
128 | }; |
129 | ||
27452498 KL |
130 | static struct platform_device_id s3c24xx_driver_ids[] = { |
131 | { | |
132 | .name = "s3c2410-i2c", | |
133 | .driver_data = 0, | |
134 | }, { | |
135 | .name = "s3c2440-i2c", | |
136 | .driver_data = QUIRK_S3C2440, | |
ec39ef83 KL |
137 | }, { |
138 | .name = "s3c2440-hdmiphy-i2c", | |
139 | .driver_data = QUIRK_S3C2440 | QUIRK_HDMIPHY | QUIRK_NO_GPIO, | |
27452498 KL |
140 | }, { }, |
141 | }; | |
142 | MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids); | |
143 | ||
144 | #ifdef CONFIG_OF | |
145 | static const struct of_device_id s3c24xx_i2c_match[] = { | |
146 | { .compatible = "samsung,s3c2410-i2c", .data = (void *)0 }, | |
147 | { .compatible = "samsung,s3c2440-i2c", .data = (void *)QUIRK_S3C2440 }, | |
ec39ef83 KL |
148 | { .compatible = "samsung,s3c2440-hdmiphy-i2c", |
149 | .data = (void *)(QUIRK_S3C2440 | QUIRK_HDMIPHY | QUIRK_NO_GPIO) }, | |
faf93ff6 GM |
150 | { .compatible = "samsung,exynos5440-i2c", |
151 | .data = (void *)(QUIRK_S3C2440 | QUIRK_NO_GPIO) }, | |
27452498 KL |
152 | {}, |
153 | }; | |
154 | MODULE_DEVICE_TABLE(of, s3c24xx_i2c_match); | |
155 | #endif | |
1da177e4 | 156 | |
27452498 | 157 | /* s3c24xx_get_device_quirks |
1da177e4 | 158 | * |
27452498 | 159 | * Get controller type either from device tree or platform device variant. |
1da177e4 LT |
160 | */ |
161 | ||
27452498 | 162 | static inline unsigned int s3c24xx_get_device_quirks(struct platform_device *pdev) |
1da177e4 | 163 | { |
27452498 KL |
164 | if (pdev->dev.of_node) { |
165 | const struct of_device_id *match; | |
b900ba4c | 166 | match = of_match_node(s3c24xx_i2c_match, pdev->dev.of_node); |
27452498 KL |
167 | return (unsigned int)match->data; |
168 | } | |
5a5f5080 | 169 | |
27452498 | 170 | return platform_get_device_id(pdev)->driver_data; |
1da177e4 LT |
171 | } |
172 | ||
1da177e4 LT |
173 | /* s3c24xx_i2c_master_complete |
174 | * | |
175 | * complete the message and wake up the caller, using the given return code, | |
176 | * or zero to mean ok. | |
177 | */ | |
178 | ||
179 | static inline void s3c24xx_i2c_master_complete(struct s3c24xx_i2c *i2c, int ret) | |
180 | { | |
181 | dev_dbg(i2c->dev, "master_complete %d\n", ret); | |
182 | ||
183 | i2c->msg_ptr = 0; | |
184 | i2c->msg = NULL; | |
3d0911bf | 185 | i2c->msg_idx++; |
1da177e4 LT |
186 | i2c->msg_num = 0; |
187 | if (ret) | |
188 | i2c->msg_idx = ret; | |
189 | ||
190 | wake_up(&i2c->wait); | |
191 | } | |
192 | ||
193 | static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c) | |
194 | { | |
195 | unsigned long tmp; | |
3d0911bf | 196 | |
1da177e4 LT |
197 | tmp = readl(i2c->regs + S3C2410_IICCON); |
198 | writel(tmp & ~S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON); | |
1da177e4 LT |
199 | } |
200 | ||
201 | static inline void s3c24xx_i2c_enable_ack(struct s3c24xx_i2c *i2c) | |
202 | { | |
203 | unsigned long tmp; | |
3d0911bf | 204 | |
1da177e4 LT |
205 | tmp = readl(i2c->regs + S3C2410_IICCON); |
206 | writel(tmp | S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON); | |
1da177e4 LT |
207 | } |
208 | ||
209 | /* irq enable/disable functions */ | |
210 | ||
211 | static inline void s3c24xx_i2c_disable_irq(struct s3c24xx_i2c *i2c) | |
212 | { | |
213 | unsigned long tmp; | |
3d0911bf | 214 | |
1da177e4 LT |
215 | tmp = readl(i2c->regs + S3C2410_IICCON); |
216 | writel(tmp & ~S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON); | |
217 | } | |
218 | ||
219 | static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c *i2c) | |
220 | { | |
221 | unsigned long tmp; | |
3d0911bf | 222 | |
1da177e4 LT |
223 | tmp = readl(i2c->regs + S3C2410_IICCON); |
224 | writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON); | |
225 | } | |
226 | ||
227 | ||
228 | /* s3c24xx_i2c_message_start | |
229 | * | |
3d0911bf | 230 | * put the start of a message onto the bus |
1da177e4 LT |
231 | */ |
232 | ||
3d0911bf | 233 | static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c, |
1da177e4 LT |
234 | struct i2c_msg *msg) |
235 | { | |
236 | unsigned int addr = (msg->addr & 0x7f) << 1; | |
237 | unsigned long stat; | |
238 | unsigned long iiccon; | |
239 | ||
240 | stat = 0; | |
241 | stat |= S3C2410_IICSTAT_TXRXEN; | |
242 | ||
243 | if (msg->flags & I2C_M_RD) { | |
244 | stat |= S3C2410_IICSTAT_MASTER_RX; | |
245 | addr |= 1; | |
246 | } else | |
247 | stat |= S3C2410_IICSTAT_MASTER_TX; | |
248 | ||
249 | if (msg->flags & I2C_M_REV_DIR_ADDR) | |
250 | addr ^= 1; | |
251 | ||
48fc7f7e | 252 | /* todo - check for whether ack wanted or not */ |
1da177e4 LT |
253 | s3c24xx_i2c_enable_ack(i2c); |
254 | ||
255 | iiccon = readl(i2c->regs + S3C2410_IICCON); | |
256 | writel(stat, i2c->regs + S3C2410_IICSTAT); | |
3d0911bf | 257 | |
1da177e4 LT |
258 | dev_dbg(i2c->dev, "START: %08lx to IICSTAT, %02x to DS\n", stat, addr); |
259 | writeb(addr, i2c->regs + S3C2410_IICDS); | |
3d0911bf | 260 | |
e00a8cdf BD |
261 | /* delay here to ensure the data byte has gotten onto the bus |
262 | * before the transaction is started */ | |
263 | ||
264 | ndelay(i2c->tx_setup); | |
265 | ||
1da177e4 LT |
266 | dev_dbg(i2c->dev, "iiccon, %08lx\n", iiccon); |
267 | writel(iiccon, i2c->regs + S3C2410_IICCON); | |
3d0911bf BD |
268 | |
269 | stat |= S3C2410_IICSTAT_START; | |
1da177e4 LT |
270 | writel(stat, i2c->regs + S3C2410_IICSTAT); |
271 | } | |
272 | ||
273 | static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c *i2c, int ret) | |
274 | { | |
275 | unsigned long iicstat = readl(i2c->regs + S3C2410_IICSTAT); | |
276 | ||
277 | dev_dbg(i2c->dev, "STOP\n"); | |
278 | ||
0da2e776 DK |
279 | /* |
280 | * The datasheet says that the STOP sequence should be: | |
281 | * 1) I2CSTAT.5 = 0 - Clear BUSY (or 'generate STOP') | |
282 | * 2) I2CCON.4 = 0 - Clear IRQPEND | |
283 | * 3) Wait until the stop condition takes effect. | |
284 | * 4*) I2CSTAT.4 = 0 - Clear TXRXEN | |
285 | * | |
286 | * Where, step "4*" is only for buses with the "HDMIPHY" quirk. | |
287 | * | |
288 | * However, after much experimentation, it appears that: | |
289 | * a) normal buses automatically clear BUSY and transition from | |
290 | * Master->Slave when they complete generating a STOP condition. | |
291 | * Therefore, step (3) can be done in doxfer() by polling I2CCON.4 | |
292 | * after starting the STOP generation here. | |
293 | * b) HDMIPHY bus does neither, so there is no way to do step 3. | |
294 | * There is no indication when this bus has finished generating | |
295 | * STOP. | |
296 | * | |
297 | * In fact, we have found that as soon as the IRQPEND bit is cleared in | |
298 | * step 2, the HDMIPHY bus generates the STOP condition, and then | |
299 | * immediately starts transferring another data byte, even though the | |
300 | * bus is supposedly stopped. This is presumably because the bus is | |
301 | * still in "Master" mode, and its BUSY bit is still set. | |
302 | * | |
303 | * To avoid these extra post-STOP transactions on HDMI phy devices, we | |
304 | * just disable Serial Output on the bus (I2CSTAT.4 = 0) directly, | |
305 | * instead of first generating a proper STOP condition. This should | |
306 | * float SDA & SCK terminating the transfer. Subsequent transfers | |
307 | * start with a proper START condition, and proceed normally. | |
308 | * | |
309 | * The HDMIPHY bus is an internal bus that always has exactly two | |
310 | * devices, the host as Master and the HDMIPHY device as the slave. | |
311 | * Skipping the STOP condition has been tested on this bus and works. | |
312 | */ | |
313 | if (i2c->quirks & QUIRK_HDMIPHY) { | |
314 | /* Stop driving the I2C pins */ | |
315 | iicstat &= ~S3C2410_IICSTAT_TXRXEN; | |
316 | } else { | |
317 | /* stop the transfer */ | |
318 | iicstat &= ~S3C2410_IICSTAT_START; | |
319 | } | |
1da177e4 | 320 | writel(iicstat, i2c->regs + S3C2410_IICSTAT); |
3d0911bf | 321 | |
1da177e4 | 322 | i2c->state = STATE_STOP; |
3d0911bf | 323 | |
1da177e4 LT |
324 | s3c24xx_i2c_master_complete(i2c, ret); |
325 | s3c24xx_i2c_disable_irq(i2c); | |
326 | } | |
327 | ||
328 | /* helper functions to determine the current state in the set of | |
329 | * messages we are sending */ | |
330 | ||
331 | /* is_lastmsg() | |
332 | * | |
3d0911bf | 333 | * returns TRUE if the current message is the last in the set |
1da177e4 LT |
334 | */ |
335 | ||
336 | static inline int is_lastmsg(struct s3c24xx_i2c *i2c) | |
337 | { | |
338 | return i2c->msg_idx >= (i2c->msg_num - 1); | |
339 | } | |
340 | ||
341 | /* is_msglast | |
342 | * | |
343 | * returns TRUE if we this is the last byte in the current message | |
344 | */ | |
345 | ||
346 | static inline int is_msglast(struct s3c24xx_i2c *i2c) | |
347 | { | |
85747311 JY |
348 | /* msg->len is always 1 for the first byte of smbus block read. |
349 | * Actual length will be read from slave. More bytes will be | |
350 | * read according to the length then. */ | |
351 | if (i2c->msg->flags & I2C_M_RECV_LEN && i2c->msg->len == 1) | |
352 | return 0; | |
353 | ||
1da177e4 LT |
354 | return i2c->msg_ptr == i2c->msg->len-1; |
355 | } | |
356 | ||
357 | /* is_msgend | |
358 | * | |
359 | * returns TRUE if we reached the end of the current message | |
360 | */ | |
361 | ||
362 | static inline int is_msgend(struct s3c24xx_i2c *i2c) | |
363 | { | |
364 | return i2c->msg_ptr >= i2c->msg->len; | |
365 | } | |
366 | ||
19820510 | 367 | /* i2c_s3c_irq_nextbyte |
1da177e4 LT |
368 | * |
369 | * process an interrupt and work out what to do | |
370 | */ | |
371 | ||
19820510 | 372 | static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat) |
1da177e4 LT |
373 | { |
374 | unsigned long tmp; | |
375 | unsigned char byte; | |
376 | int ret = 0; | |
377 | ||
378 | switch (i2c->state) { | |
379 | ||
380 | case STATE_IDLE: | |
08882d20 | 381 | dev_err(i2c->dev, "%s: called in STATE_IDLE\n", __func__); |
1da177e4 | 382 | goto out; |
1da177e4 LT |
383 | |
384 | case STATE_STOP: | |
08882d20 | 385 | dev_err(i2c->dev, "%s: called in STATE_STOP\n", __func__); |
3d0911bf | 386 | s3c24xx_i2c_disable_irq(i2c); |
1da177e4 LT |
387 | goto out_ack; |
388 | ||
389 | case STATE_START: | |
390 | /* last thing we did was send a start condition on the | |
391 | * bus, or started a new i2c message | |
392 | */ | |
3d0911bf | 393 | |
63f5c289 | 394 | if (iicstat & S3C2410_IICSTAT_LASTBIT && |
1da177e4 LT |
395 | !(i2c->msg->flags & I2C_M_IGNORE_NAK)) { |
396 | /* ack was not received... */ | |
397 | ||
398 | dev_dbg(i2c->dev, "ack was not received\n"); | |
63f5c289 | 399 | s3c24xx_i2c_stop(i2c, -ENXIO); |
1da177e4 LT |
400 | goto out_ack; |
401 | } | |
402 | ||
403 | if (i2c->msg->flags & I2C_M_RD) | |
404 | i2c->state = STATE_READ; | |
405 | else | |
406 | i2c->state = STATE_WRITE; | |
407 | ||
408 | /* terminate the transfer if there is nothing to do | |
63f5c289 | 409 | * as this is used by the i2c probe to find devices. */ |
1da177e4 LT |
410 | |
411 | if (is_lastmsg(i2c) && i2c->msg->len == 0) { | |
412 | s3c24xx_i2c_stop(i2c, 0); | |
413 | goto out_ack; | |
414 | } | |
415 | ||
416 | if (i2c->state == STATE_READ) | |
417 | goto prepare_read; | |
418 | ||
3d0911bf | 419 | /* fall through to the write state, as we will need to |
1da177e4 LT |
420 | * send a byte as well */ |
421 | ||
422 | case STATE_WRITE: | |
423 | /* we are writing data to the device... check for the | |
424 | * end of the message, and if so, work out what to do | |
425 | */ | |
426 | ||
2709781b BD |
427 | if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) { |
428 | if (iicstat & S3C2410_IICSTAT_LASTBIT) { | |
429 | dev_dbg(i2c->dev, "WRITE: No Ack\n"); | |
430 | ||
431 | s3c24xx_i2c_stop(i2c, -ECONNREFUSED); | |
432 | goto out_ack; | |
433 | } | |
434 | } | |
435 | ||
3d0911bf | 436 | retry_write: |
2709781b | 437 | |
1da177e4 LT |
438 | if (!is_msgend(i2c)) { |
439 | byte = i2c->msg->buf[i2c->msg_ptr++]; | |
440 | writeb(byte, i2c->regs + S3C2410_IICDS); | |
e00a8cdf BD |
441 | |
442 | /* delay after writing the byte to allow the | |
443 | * data setup time on the bus, as writing the | |
444 | * data to the register causes the first bit | |
445 | * to appear on SDA, and SCL will change as | |
446 | * soon as the interrupt is acknowledged */ | |
447 | ||
448 | ndelay(i2c->tx_setup); | |
449 | ||
1da177e4 LT |
450 | } else if (!is_lastmsg(i2c)) { |
451 | /* we need to go to the next i2c message */ | |
452 | ||
453 | dev_dbg(i2c->dev, "WRITE: Next Message\n"); | |
454 | ||
455 | i2c->msg_ptr = 0; | |
3d0911bf | 456 | i2c->msg_idx++; |
1da177e4 | 457 | i2c->msg++; |
3d0911bf | 458 | |
1da177e4 LT |
459 | /* check to see if we need to do another message */ |
460 | if (i2c->msg->flags & I2C_M_NOSTART) { | |
461 | ||
462 | if (i2c->msg->flags & I2C_M_RD) { | |
463 | /* cannot do this, the controller | |
464 | * forces us to send a new START | |
465 | * when we change direction */ | |
466 | ||
467 | s3c24xx_i2c_stop(i2c, -EINVAL); | |
468 | } | |
469 | ||
470 | goto retry_write; | |
471 | } else { | |
1da177e4 LT |
472 | /* send the new start */ |
473 | s3c24xx_i2c_message_start(i2c, i2c->msg); | |
474 | i2c->state = STATE_START; | |
475 | } | |
476 | ||
477 | } else { | |
478 | /* send stop */ | |
479 | ||
480 | s3c24xx_i2c_stop(i2c, 0); | |
481 | } | |
482 | break; | |
483 | ||
484 | case STATE_READ: | |
3d0911bf | 485 | /* we have a byte of data in the data register, do |
48fc7f7e | 486 | * something with it, and then work out whether we are |
1da177e4 LT |
487 | * going to do any more read/write |
488 | */ | |
489 | ||
1da177e4 LT |
490 | byte = readb(i2c->regs + S3C2410_IICDS); |
491 | i2c->msg->buf[i2c->msg_ptr++] = byte; | |
492 | ||
85747311 JY |
493 | /* Add actual length to read for smbus block read */ |
494 | if (i2c->msg->flags & I2C_M_RECV_LEN && i2c->msg->len == 1) | |
495 | i2c->msg->len += byte; | |
3d0911bf | 496 | prepare_read: |
1da177e4 LT |
497 | if (is_msglast(i2c)) { |
498 | /* last byte of buffer */ | |
499 | ||
500 | if (is_lastmsg(i2c)) | |
501 | s3c24xx_i2c_disable_ack(i2c); | |
3d0911bf | 502 | |
1da177e4 LT |
503 | } else if (is_msgend(i2c)) { |
504 | /* ok, we've read the entire buffer, see if there | |
505 | * is anything else we need to do */ | |
506 | ||
507 | if (is_lastmsg(i2c)) { | |
508 | /* last message, send stop and complete */ | |
509 | dev_dbg(i2c->dev, "READ: Send Stop\n"); | |
510 | ||
511 | s3c24xx_i2c_stop(i2c, 0); | |
512 | } else { | |
513 | /* go to the next transfer */ | |
514 | dev_dbg(i2c->dev, "READ: Next Transfer\n"); | |
515 | ||
516 | i2c->msg_ptr = 0; | |
517 | i2c->msg_idx++; | |
518 | i2c->msg++; | |
519 | } | |
520 | } | |
521 | ||
522 | break; | |
523 | } | |
524 | ||
525 | /* acknowlegde the IRQ and get back on with the work */ | |
526 | ||
527 | out_ack: | |
3d0911bf | 528 | tmp = readl(i2c->regs + S3C2410_IICCON); |
1da177e4 LT |
529 | tmp &= ~S3C2410_IICCON_IRQPEND; |
530 | writel(tmp, i2c->regs + S3C2410_IICCON); | |
531 | out: | |
532 | return ret; | |
533 | } | |
534 | ||
535 | /* s3c24xx_i2c_irq | |
536 | * | |
537 | * top level IRQ servicing routine | |
538 | */ | |
539 | ||
7d12e780 | 540 | static irqreturn_t s3c24xx_i2c_irq(int irqno, void *dev_id) |
1da177e4 LT |
541 | { |
542 | struct s3c24xx_i2c *i2c = dev_id; | |
543 | unsigned long status; | |
544 | unsigned long tmp; | |
545 | ||
546 | status = readl(i2c->regs + S3C2410_IICSTAT); | |
547 | ||
548 | if (status & S3C2410_IICSTAT_ARBITR) { | |
3d0911bf | 549 | /* deal with arbitration loss */ |
1da177e4 LT |
550 | dev_err(i2c->dev, "deal with arbitration loss\n"); |
551 | } | |
552 | ||
553 | if (i2c->state == STATE_IDLE) { | |
554 | dev_dbg(i2c->dev, "IRQ: error i2c->state == IDLE\n"); | |
555 | ||
3d0911bf | 556 | tmp = readl(i2c->regs + S3C2410_IICCON); |
1da177e4 LT |
557 | tmp &= ~S3C2410_IICCON_IRQPEND; |
558 | writel(tmp, i2c->regs + S3C2410_IICCON); | |
559 | goto out; | |
560 | } | |
3d0911bf | 561 | |
1da177e4 LT |
562 | /* pretty much this leaves us with the fact that we've |
563 | * transmitted or received whatever byte we last sent */ | |
564 | ||
19820510 | 565 | i2c_s3c_irq_nextbyte(i2c, status); |
1da177e4 LT |
566 | |
567 | out: | |
568 | return IRQ_HANDLED; | |
569 | } | |
570 | ||
571 | ||
572 | /* s3c24xx_i2c_set_master | |
573 | * | |
574 | * get the i2c bus for a master transaction | |
575 | */ | |
576 | ||
577 | static int s3c24xx_i2c_set_master(struct s3c24xx_i2c *i2c) | |
578 | { | |
579 | unsigned long iicstat; | |
580 | int timeout = 400; | |
581 | ||
582 | while (timeout-- > 0) { | |
583 | iicstat = readl(i2c->regs + S3C2410_IICSTAT); | |
3d0911bf | 584 | |
1da177e4 LT |
585 | if (!(iicstat & S3C2410_IICSTAT_BUSBUSY)) |
586 | return 0; | |
587 | ||
588 | msleep(1); | |
589 | } | |
590 | ||
1da177e4 LT |
591 | return -ETIMEDOUT; |
592 | } | |
ec39ef83 | 593 | |
fe724bf9 DK |
594 | /* s3c24xx_i2c_wait_idle |
595 | * | |
596 | * wait for the i2c bus to become idle. | |
597 | */ | |
598 | ||
599 | static void s3c24xx_i2c_wait_idle(struct s3c24xx_i2c *i2c) | |
600 | { | |
601 | unsigned long iicstat; | |
602 | ktime_t start, now; | |
603 | unsigned long delay; | |
31f313d9 | 604 | int spins; |
fe724bf9 DK |
605 | |
606 | /* ensure the stop has been through the bus */ | |
607 | ||
608 | dev_dbg(i2c->dev, "waiting for bus idle\n"); | |
609 | ||
610 | start = now = ktime_get(); | |
611 | ||
612 | /* | |
613 | * Most of the time, the bus is already idle within a few usec of the | |
614 | * end of a transaction. However, really slow i2c devices can stretch | |
615 | * the clock, delaying STOP generation. | |
616 | * | |
31f313d9 MB |
617 | * On slower SoCs this typically happens within a very small number of |
618 | * instructions so busy wait briefly to avoid scheduling overhead. | |
fe724bf9 | 619 | */ |
31f313d9 | 620 | spins = 3; |
fe724bf9 | 621 | iicstat = readl(i2c->regs + S3C2410_IICSTAT); |
31f313d9 MB |
622 | while ((iicstat & S3C2410_IICSTAT_START) && --spins) { |
623 | cpu_relax(); | |
624 | iicstat = readl(i2c->regs + S3C2410_IICSTAT); | |
ec39ef83 KL |
625 | } |
626 | ||
31f313d9 MB |
627 | /* |
628 | * If we do get an appreciable delay as a compromise between idle | |
629 | * detection latency for the normal, fast case, and system load in the | |
630 | * slow device case, use an exponential back off in the polling loop, | |
631 | * up to 1/10th of the total timeout, then continue to poll at a | |
632 | * constant rate up to the timeout. | |
633 | */ | |
fe724bf9 DK |
634 | delay = 1; |
635 | while ((iicstat & S3C2410_IICSTAT_START) && | |
636 | ktime_us_delta(now, start) < S3C2410_IDLE_TIMEOUT) { | |
637 | usleep_range(delay, 2 * delay); | |
638 | if (delay < S3C2410_IDLE_TIMEOUT / 10) | |
639 | delay <<= 1; | |
640 | now = ktime_get(); | |
641 | iicstat = readl(i2c->regs + S3C2410_IICSTAT); | |
642 | } | |
643 | ||
644 | if (iicstat & S3C2410_IICSTAT_START) | |
645 | dev_warn(i2c->dev, "timeout waiting for bus idle\n"); | |
1da177e4 LT |
646 | } |
647 | ||
648 | /* s3c24xx_i2c_doxfer | |
649 | * | |
650 | * this starts an i2c transfer | |
651 | */ | |
652 | ||
3d0911bf BD |
653 | static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c, |
654 | struct i2c_msg *msgs, int num) | |
1da177e4 | 655 | { |
fe724bf9 | 656 | unsigned long timeout; |
1da177e4 LT |
657 | int ret; |
658 | ||
be44f01e | 659 | if (i2c->suspended) |
61c7cff8 BD |
660 | return -EIO; |
661 | ||
1da177e4 LT |
662 | ret = s3c24xx_i2c_set_master(i2c); |
663 | if (ret != 0) { | |
664 | dev_err(i2c->dev, "cannot get bus (error %d)\n", ret); | |
665 | ret = -EAGAIN; | |
666 | goto out; | |
667 | } | |
668 | ||
1da177e4 LT |
669 | i2c->msg = msgs; |
670 | i2c->msg_num = num; | |
671 | i2c->msg_ptr = 0; | |
672 | i2c->msg_idx = 0; | |
673 | i2c->state = STATE_START; | |
674 | ||
675 | s3c24xx_i2c_enable_irq(i2c); | |
676 | s3c24xx_i2c_message_start(i2c, msgs); | |
3d0911bf | 677 | |
1da177e4 LT |
678 | timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5); |
679 | ||
680 | ret = i2c->msg_idx; | |
681 | ||
3d0911bf | 682 | /* having these next two as dev_err() makes life very |
1da177e4 LT |
683 | * noisy when doing an i2cdetect */ |
684 | ||
685 | if (timeout == 0) | |
686 | dev_dbg(i2c->dev, "timeout\n"); | |
687 | else if (ret != num) | |
688 | dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret); | |
689 | ||
0da2e776 DK |
690 | /* For QUIRK_HDMIPHY, bus is already disabled */ |
691 | if (i2c->quirks & QUIRK_HDMIPHY) | |
692 | goto out; | |
1bc2962e | 693 | |
fe724bf9 | 694 | s3c24xx_i2c_wait_idle(i2c); |
1da177e4 LT |
695 | |
696 | out: | |
697 | return ret; | |
698 | } | |
699 | ||
700 | /* s3c24xx_i2c_xfer | |
701 | * | |
702 | * first port of call from the i2c bus code when an message needs | |
44bbe87e | 703 | * transferring across the i2c bus. |
1da177e4 LT |
704 | */ |
705 | ||
706 | static int s3c24xx_i2c_xfer(struct i2c_adapter *adap, | |
707 | struct i2c_msg *msgs, int num) | |
708 | { | |
709 | struct s3c24xx_i2c *i2c = (struct s3c24xx_i2c *)adap->algo_data; | |
710 | int retry; | |
711 | int ret; | |
712 | ||
c62c3ca5 | 713 | pm_runtime_get_sync(&adap->dev); |
d3b64c59 | 714 | clk_prepare_enable(i2c->clk); |
d2360b8e | 715 | |
1da177e4 LT |
716 | for (retry = 0; retry < adap->retries; retry++) { |
717 | ||
718 | ret = s3c24xx_i2c_doxfer(i2c, msgs, num); | |
719 | ||
d2360b8e | 720 | if (ret != -EAGAIN) { |
d3b64c59 | 721 | clk_disable_unprepare(i2c->clk); |
a86ae9ff | 722 | pm_runtime_put(&adap->dev); |
1da177e4 | 723 | return ret; |
d2360b8e | 724 | } |
1da177e4 LT |
725 | |
726 | dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry); | |
727 | ||
728 | udelay(100); | |
729 | } | |
730 | ||
d3b64c59 | 731 | clk_disable_unprepare(i2c->clk); |
a86ae9ff | 732 | pm_runtime_put(&adap->dev); |
1da177e4 LT |
733 | return -EREMOTEIO; |
734 | } | |
735 | ||
736 | /* declare our i2c functionality */ | |
737 | static u32 s3c24xx_i2c_func(struct i2c_adapter *adap) | |
738 | { | |
14674e70 MB |
739 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_NOSTART | |
740 | I2C_FUNC_PROTOCOL_MANGLING; | |
1da177e4 LT |
741 | } |
742 | ||
743 | /* i2c bus registration info */ | |
744 | ||
8f9082c5 | 745 | static const struct i2c_algorithm s3c24xx_i2c_algorithm = { |
1da177e4 LT |
746 | .master_xfer = s3c24xx_i2c_xfer, |
747 | .functionality = s3c24xx_i2c_func, | |
748 | }; | |
749 | ||
1da177e4 LT |
750 | /* s3c24xx_i2c_calcdivisor |
751 | * | |
752 | * return the divisor settings for a given frequency | |
753 | */ | |
754 | ||
755 | static int s3c24xx_i2c_calcdivisor(unsigned long clkin, unsigned int wanted, | |
756 | unsigned int *div1, unsigned int *divs) | |
757 | { | |
758 | unsigned int calc_divs = clkin / wanted; | |
759 | unsigned int calc_div1; | |
760 | ||
761 | if (calc_divs > (16*16)) | |
762 | calc_div1 = 512; | |
763 | else | |
764 | calc_div1 = 16; | |
765 | ||
766 | calc_divs += calc_div1-1; | |
767 | calc_divs /= calc_div1; | |
768 | ||
769 | if (calc_divs == 0) | |
770 | calc_divs = 1; | |
771 | if (calc_divs > 17) | |
772 | calc_divs = 17; | |
773 | ||
774 | *divs = calc_divs; | |
775 | *div1 = calc_div1; | |
776 | ||
777 | return clkin / (calc_divs * calc_div1); | |
778 | } | |
779 | ||
61c7cff8 | 780 | /* s3c24xx_i2c_clockrate |
1da177e4 LT |
781 | * |
782 | * work out a divisor for the user requested frequency setting, | |
783 | * either by the requested frequency, or scanning the acceptable | |
784 | * range of frequencies until something is found | |
785 | */ | |
786 | ||
61c7cff8 | 787 | static int s3c24xx_i2c_clockrate(struct s3c24xx_i2c *i2c, unsigned int *got) |
1da177e4 | 788 | { |
4fd81eb2 | 789 | struct s3c2410_platform_i2c *pdata = i2c->pdata; |
1da177e4 | 790 | unsigned long clkin = clk_get_rate(i2c->clk); |
1da177e4 | 791 | unsigned int divs, div1; |
c564e6ae | 792 | unsigned long target_frequency; |
61c7cff8 | 793 | u32 iiccon; |
1da177e4 | 794 | int freq; |
1da177e4 | 795 | |
61c7cff8 | 796 | i2c->clkrate = clkin; |
1da177e4 | 797 | clkin /= 1000; /* clkin now in KHz */ |
3d0911bf | 798 | |
c564e6ae | 799 | dev_dbg(i2c->dev, "pdata desired frequency %lu\n", pdata->frequency); |
1da177e4 | 800 | |
c564e6ae | 801 | target_frequency = pdata->frequency ? pdata->frequency : 100000; |
1da177e4 | 802 | |
c564e6ae | 803 | target_frequency /= 1000; /* Target frequency now in KHz */ |
1da177e4 | 804 | |
c564e6ae | 805 | freq = s3c24xx_i2c_calcdivisor(clkin, target_frequency, &div1, &divs); |
1da177e4 | 806 | |
c564e6ae DS |
807 | if (freq > target_frequency) { |
808 | dev_err(i2c->dev, | |
809 | "Unable to achieve desired frequency %luKHz." \ | |
810 | " Lowest achievable %dKHz\n", target_frequency, freq); | |
811 | return -EINVAL; | |
1da177e4 LT |
812 | } |
813 | ||
1da177e4 | 814 | *got = freq; |
61c7cff8 BD |
815 | |
816 | iiccon = readl(i2c->regs + S3C2410_IICCON); | |
817 | iiccon &= ~(S3C2410_IICCON_SCALEMASK | S3C2410_IICCON_TXDIV_512); | |
818 | iiccon |= (divs-1); | |
819 | ||
820 | if (div1 == 512) | |
821 | iiccon |= S3C2410_IICCON_TXDIV_512; | |
822 | ||
823 | writel(iiccon, i2c->regs + S3C2410_IICCON); | |
824 | ||
27452498 | 825 | if (i2c->quirks & QUIRK_S3C2440) { |
a192f715 BD |
826 | unsigned long sda_delay; |
827 | ||
828 | if (pdata->sda_delay) { | |
7031307a MH |
829 | sda_delay = clkin * pdata->sda_delay; |
830 | sda_delay = DIV_ROUND_UP(sda_delay, 1000000); | |
a192f715 BD |
831 | sda_delay = DIV_ROUND_UP(sda_delay, 5); |
832 | if (sda_delay > 3) | |
833 | sda_delay = 3; | |
834 | sda_delay |= S3C2410_IICLC_FILTER_ON; | |
835 | } else | |
836 | sda_delay = 0; | |
837 | ||
838 | dev_dbg(i2c->dev, "IICLC=%08lx\n", sda_delay); | |
839 | writel(sda_delay, i2c->regs + S3C2440_IICLC); | |
840 | } | |
841 | ||
61c7cff8 BD |
842 | return 0; |
843 | } | |
844 | ||
845 | #ifdef CONFIG_CPU_FREQ | |
846 | ||
847 | #define freq_to_i2c(_n) container_of(_n, struct s3c24xx_i2c, freq_transition) | |
848 | ||
849 | static int s3c24xx_i2c_cpufreq_transition(struct notifier_block *nb, | |
850 | unsigned long val, void *data) | |
851 | { | |
852 | struct s3c24xx_i2c *i2c = freq_to_i2c(nb); | |
61c7cff8 BD |
853 | unsigned int got; |
854 | int delta_f; | |
855 | int ret; | |
856 | ||
857 | delta_f = clk_get_rate(i2c->clk) - i2c->clkrate; | |
858 | ||
859 | /* if we're post-change and the input clock has slowed down | |
860 | * or at pre-change and the clock is about to speed up, then | |
861 | * adjust our clock rate. <0 is slow, >0 speedup. | |
862 | */ | |
863 | ||
864 | if ((val == CPUFREQ_POSTCHANGE && delta_f < 0) || | |
865 | (val == CPUFREQ_PRECHANGE && delta_f > 0)) { | |
9bcd04bf | 866 | i2c_lock_adapter(&i2c->adap); |
61c7cff8 | 867 | ret = s3c24xx_i2c_clockrate(i2c, &got); |
9bcd04bf | 868 | i2c_unlock_adapter(&i2c->adap); |
61c7cff8 BD |
869 | |
870 | if (ret < 0) | |
871 | dev_err(i2c->dev, "cannot find frequency\n"); | |
872 | else | |
873 | dev_info(i2c->dev, "setting freq %d\n", got); | |
874 | } | |
875 | ||
1da177e4 LT |
876 | return 0; |
877 | } | |
878 | ||
61c7cff8 BD |
879 | static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c) |
880 | { | |
881 | i2c->freq_transition.notifier_call = s3c24xx_i2c_cpufreq_transition; | |
882 | ||
883 | return cpufreq_register_notifier(&i2c->freq_transition, | |
884 | CPUFREQ_TRANSITION_NOTIFIER); | |
885 | } | |
886 | ||
887 | static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c) | |
888 | { | |
889 | cpufreq_unregister_notifier(&i2c->freq_transition, | |
890 | CPUFREQ_TRANSITION_NOTIFIER); | |
891 | } | |
892 | ||
893 | #else | |
894 | static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c) | |
895 | { | |
1da177e4 LT |
896 | return 0; |
897 | } | |
898 | ||
61c7cff8 BD |
899 | static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c) |
900 | { | |
901 | } | |
902 | #endif | |
903 | ||
5a5f5080 TA |
904 | #ifdef CONFIG_OF |
905 | static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c *i2c) | |
906 | { | |
907 | int idx, gpio, ret; | |
908 | ||
ec39ef83 KL |
909 | if (i2c->quirks & QUIRK_NO_GPIO) |
910 | return 0; | |
911 | ||
5a5f5080 TA |
912 | for (idx = 0; idx < 2; idx++) { |
913 | gpio = of_get_gpio(i2c->dev->of_node, idx); | |
914 | if (!gpio_is_valid(gpio)) { | |
915 | dev_err(i2c->dev, "invalid gpio[%d]: %d\n", idx, gpio); | |
916 | goto free_gpio; | |
917 | } | |
963f2076 | 918 | i2c->gpios[idx] = gpio; |
5a5f5080 TA |
919 | |
920 | ret = gpio_request(gpio, "i2c-bus"); | |
921 | if (ret) { | |
922 | dev_err(i2c->dev, "gpio [%d] request failed\n", gpio); | |
923 | goto free_gpio; | |
924 | } | |
925 | } | |
926 | return 0; | |
927 | ||
928 | free_gpio: | |
929 | while (--idx >= 0) | |
930 | gpio_free(i2c->gpios[idx]); | |
931 | return -EINVAL; | |
932 | } | |
933 | ||
934 | static void s3c24xx_i2c_dt_gpio_free(struct s3c24xx_i2c *i2c) | |
935 | { | |
936 | unsigned int idx; | |
ec39ef83 KL |
937 | |
938 | if (i2c->quirks & QUIRK_NO_GPIO) | |
939 | return; | |
940 | ||
5a5f5080 TA |
941 | for (idx = 0; idx < 2; idx++) |
942 | gpio_free(i2c->gpios[idx]); | |
943 | } | |
944 | #else | |
945 | static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c *i2c) | |
946 | { | |
8ebe661d | 947 | return 0; |
5a5f5080 TA |
948 | } |
949 | ||
950 | static void s3c24xx_i2c_dt_gpio_free(struct s3c24xx_i2c *i2c) | |
951 | { | |
952 | } | |
953 | #endif | |
954 | ||
1da177e4 LT |
955 | /* s3c24xx_i2c_init |
956 | * | |
3d0911bf | 957 | * initialise the controller, set the IO lines and frequency |
1da177e4 LT |
958 | */ |
959 | ||
960 | static int s3c24xx_i2c_init(struct s3c24xx_i2c *i2c) | |
961 | { | |
962 | unsigned long iicon = S3C2410_IICCON_IRQEN | S3C2410_IICCON_ACKEN; | |
963 | struct s3c2410_platform_i2c *pdata; | |
964 | unsigned int freq; | |
965 | ||
966 | /* get the plafrom data */ | |
967 | ||
4fd81eb2 | 968 | pdata = i2c->pdata; |
1da177e4 | 969 | |
1da177e4 | 970 | /* write slave address */ |
3d0911bf | 971 | |
1da177e4 LT |
972 | writeb(pdata->slave_addr, i2c->regs + S3C2410_IICADD); |
973 | ||
974 | dev_info(i2c->dev, "slave address 0x%02x\n", pdata->slave_addr); | |
975 | ||
61c7cff8 BD |
976 | writel(iicon, i2c->regs + S3C2410_IICCON); |
977 | ||
1da177e4 LT |
978 | /* we need to work out the divisors for the clock... */ |
979 | ||
61c7cff8 BD |
980 | if (s3c24xx_i2c_clockrate(i2c, &freq) != 0) { |
981 | writel(0, i2c->regs + S3C2410_IICCON); | |
1da177e4 LT |
982 | dev_err(i2c->dev, "cannot meet bus frequency required\n"); |
983 | return -EINVAL; | |
984 | } | |
985 | ||
986 | /* todo - check that the i2c lines aren't being dragged anywhere */ | |
987 | ||
988 | dev_info(i2c->dev, "bus frequency set to %d KHz\n", freq); | |
989 | dev_dbg(i2c->dev, "S3C2410_IICCON=0x%02lx\n", iicon); | |
1da177e4 | 990 | |
1da177e4 LT |
991 | return 0; |
992 | } | |
993 | ||
5a5f5080 TA |
994 | #ifdef CONFIG_OF |
995 | /* s3c24xx_i2c_parse_dt | |
996 | * | |
997 | * Parse the device tree node and retreive the platform data. | |
998 | */ | |
999 | ||
1000 | static void | |
1001 | s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c) | |
1002 | { | |
1003 | struct s3c2410_platform_i2c *pdata = i2c->pdata; | |
1004 | ||
1005 | if (!np) | |
1006 | return; | |
1007 | ||
1008 | pdata->bus_num = -1; /* i2c bus number is dynamically assigned */ | |
1009 | of_property_read_u32(np, "samsung,i2c-sda-delay", &pdata->sda_delay); | |
1010 | of_property_read_u32(np, "samsung,i2c-slave-addr", &pdata->slave_addr); | |
1011 | of_property_read_u32(np, "samsung,i2c-max-bus-freq", | |
1012 | (u32 *)&pdata->frequency); | |
1013 | } | |
1014 | #else | |
1015 | static void | |
1016 | s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c) | |
1017 | { | |
1018 | return; | |
1019 | } | |
1020 | #endif | |
1021 | ||
1da177e4 LT |
1022 | /* s3c24xx_i2c_probe |
1023 | * | |
1024 | * called by the bus driver when a suitable device is found | |
1025 | */ | |
1026 | ||
3ae5eaec | 1027 | static int s3c24xx_i2c_probe(struct platform_device *pdev) |
1da177e4 | 1028 | { |
692acbd3 | 1029 | struct s3c24xx_i2c *i2c; |
4fd81eb2 | 1030 | struct s3c2410_platform_i2c *pdata = NULL; |
1da177e4 LT |
1031 | struct resource *res; |
1032 | int ret; | |
1033 | ||
5a5f5080 | 1034 | if (!pdev->dev.of_node) { |
6d4028c6 | 1035 | pdata = dev_get_platdata(&pdev->dev); |
5a5f5080 TA |
1036 | if (!pdata) { |
1037 | dev_err(&pdev->dev, "no platform data\n"); | |
1038 | return -EINVAL; | |
1039 | } | |
6a039cab | 1040 | } |
399dee23 | 1041 | |
4ea1557f | 1042 | i2c = devm_kzalloc(&pdev->dev, sizeof(struct s3c24xx_i2c), GFP_KERNEL); |
692acbd3 BD |
1043 | if (!i2c) { |
1044 | dev_err(&pdev->dev, "no memory for state\n"); | |
1045 | return -ENOMEM; | |
1046 | } | |
1047 | ||
4fd81eb2 TA |
1048 | i2c->pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); |
1049 | if (!i2c->pdata) { | |
669da30d TB |
1050 | dev_err(&pdev->dev, "no memory for platform data\n"); |
1051 | return -ENOMEM; | |
4fd81eb2 TA |
1052 | } |
1053 | ||
27452498 | 1054 | i2c->quirks = s3c24xx_get_device_quirks(pdev); |
4fd81eb2 TA |
1055 | if (pdata) |
1056 | memcpy(i2c->pdata, pdata, sizeof(*pdata)); | |
5a5f5080 TA |
1057 | else |
1058 | s3c24xx_i2c_parse_dt(pdev->dev.of_node, i2c); | |
4fd81eb2 | 1059 | |
692acbd3 BD |
1060 | strlcpy(i2c->adap.name, "s3c2410-i2c", sizeof(i2c->adap.name)); |
1061 | i2c->adap.owner = THIS_MODULE; | |
1062 | i2c->adap.algo = &s3c24xx_i2c_algorithm; | |
1063 | i2c->adap.retries = 2; | |
1064 | i2c->adap.class = I2C_CLASS_HWMON | I2C_CLASS_SPD; | |
1065 | i2c->tx_setup = 50; | |
1066 | ||
692acbd3 | 1067 | init_waitqueue_head(&i2c->wait); |
399dee23 | 1068 | |
1da177e4 LT |
1069 | /* find the clock and enable it */ |
1070 | ||
3ae5eaec | 1071 | i2c->dev = &pdev->dev; |
2b255b94 | 1072 | i2c->clk = devm_clk_get(&pdev->dev, "i2c"); |
1da177e4 | 1073 | if (IS_ERR(i2c->clk)) { |
3ae5eaec | 1074 | dev_err(&pdev->dev, "cannot get clock\n"); |
669da30d | 1075 | return -ENOENT; |
1da177e4 LT |
1076 | } |
1077 | ||
3ae5eaec | 1078 | dev_dbg(&pdev->dev, "clock source %p\n", i2c->clk); |
1da177e4 | 1079 | |
1da177e4 LT |
1080 | |
1081 | /* map the registers */ | |
1082 | ||
1083 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
84dbf809 | 1084 | i2c->regs = devm_ioremap_resource(&pdev->dev, res); |
1da177e4 | 1085 | |
52caa59e LT |
1086 | if (IS_ERR(i2c->regs)) |
1087 | return PTR_ERR(i2c->regs); | |
1da177e4 | 1088 | |
a72ad456 MB |
1089 | dev_dbg(&pdev->dev, "registers %p (%p)\n", |
1090 | i2c->regs, res); | |
1da177e4 LT |
1091 | |
1092 | /* setup info block for the i2c core */ | |
1093 | ||
1094 | i2c->adap.algo_data = i2c; | |
3ae5eaec | 1095 | i2c->adap.dev.parent = &pdev->dev; |
1da177e4 | 1096 | |
2693ac69 TF |
1097 | i2c->pctrl = devm_pinctrl_get_select_default(i2c->dev); |
1098 | ||
658122fe AK |
1099 | /* inititalise the i2c gpio lines */ |
1100 | ||
1101 | if (i2c->pdata->cfg_gpio) { | |
1102 | i2c->pdata->cfg_gpio(to_platform_device(i2c->dev)); | |
1103 | } else if (IS_ERR(i2c->pctrl) && s3c24xx_i2c_parse_dt_gpio(i2c)) { | |
d16933b3 | 1104 | return -EINVAL; |
658122fe AK |
1105 | } |
1106 | ||
1da177e4 LT |
1107 | /* initialise the i2c controller */ |
1108 | ||
d16933b3 | 1109 | clk_prepare_enable(i2c->clk); |
1da177e4 | 1110 | ret = s3c24xx_i2c_init(i2c); |
d16933b3 TB |
1111 | clk_disable_unprepare(i2c->clk); |
1112 | if (ret != 0) { | |
1113 | dev_err(&pdev->dev, "I2C controller init failed\n"); | |
1114 | return ret; | |
1115 | } | |
1da177e4 | 1116 | /* find the IRQ for this unit (note, this relies on the init call to |
3d0911bf | 1117 | * ensure no current IRQs pending |
1da177e4 LT |
1118 | */ |
1119 | ||
e0d1ec97 BD |
1120 | i2c->irq = ret = platform_get_irq(pdev, 0); |
1121 | if (ret <= 0) { | |
3ae5eaec | 1122 | dev_err(&pdev->dev, "cannot find IRQ\n"); |
d16933b3 | 1123 | return ret; |
1da177e4 LT |
1124 | } |
1125 | ||
2b255b94 TB |
1126 | ret = devm_request_irq(&pdev->dev, i2c->irq, s3c24xx_i2c_irq, 0, |
1127 | dev_name(&pdev->dev), i2c); | |
1da177e4 LT |
1128 | |
1129 | if (ret != 0) { | |
e0d1ec97 | 1130 | dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq); |
d16933b3 | 1131 | return ret; |
1da177e4 LT |
1132 | } |
1133 | ||
61c7cff8 | 1134 | ret = s3c24xx_i2c_register_cpufreq(i2c); |
1da177e4 | 1135 | if (ret < 0) { |
61c7cff8 | 1136 | dev_err(&pdev->dev, "failed to register cpufreq notifier\n"); |
d16933b3 | 1137 | return ret; |
1da177e4 LT |
1138 | } |
1139 | ||
399dee23 BD |
1140 | /* Note, previous versions of the driver used i2c_add_adapter() |
1141 | * to add the bus at any number. We now pass the bus number via | |
1142 | * the platform data, so if unset it will now default to always | |
1143 | * being bus 0. | |
1144 | */ | |
1145 | ||
4fd81eb2 | 1146 | i2c->adap.nr = i2c->pdata->bus_num; |
5a5f5080 | 1147 | i2c->adap.dev.of_node = pdev->dev.of_node; |
399dee23 BD |
1148 | |
1149 | ret = i2c_add_numbered_adapter(&i2c->adap); | |
1da177e4 | 1150 | if (ret < 0) { |
3ae5eaec | 1151 | dev_err(&pdev->dev, "failed to add bus to i2c core\n"); |
dc6fea44 TB |
1152 | s3c24xx_i2c_deregister_cpufreq(i2c); |
1153 | return ret; | |
1da177e4 LT |
1154 | } |
1155 | ||
3ae5eaec | 1156 | platform_set_drvdata(pdev, i2c); |
1da177e4 | 1157 | |
c62c3ca5 MB |
1158 | pm_runtime_enable(&pdev->dev); |
1159 | pm_runtime_enable(&i2c->adap.dev); | |
1160 | ||
22e965c2 | 1161 | dev_info(&pdev->dev, "%s: S3C I2C adapter\n", dev_name(&i2c->adap.dev)); |
5b68790c | 1162 | return 0; |
1da177e4 LT |
1163 | } |
1164 | ||
1165 | /* s3c24xx_i2c_remove | |
1166 | * | |
1167 | * called when device is removed from the bus | |
1168 | */ | |
1169 | ||
3ae5eaec | 1170 | static int s3c24xx_i2c_remove(struct platform_device *pdev) |
1da177e4 | 1171 | { |
3ae5eaec | 1172 | struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev); |
5b68790c | 1173 | |
c62c3ca5 MB |
1174 | pm_runtime_disable(&i2c->adap.dev); |
1175 | pm_runtime_disable(&pdev->dev); | |
1176 | ||
61c7cff8 BD |
1177 | s3c24xx_i2c_deregister_cpufreq(i2c); |
1178 | ||
5b68790c | 1179 | i2c_del_adapter(&i2c->adap); |
5b68790c | 1180 | |
2693ac69 TF |
1181 | if (pdev->dev.of_node && IS_ERR(i2c->pctrl)) |
1182 | s3c24xx_i2c_dt_gpio_free(i2c); | |
1da177e4 LT |
1183 | |
1184 | return 0; | |
1185 | } | |
1186 | ||
2935e0e0 | 1187 | #ifdef CONFIG_PM_SLEEP |
6a6c6189 | 1188 | static int s3c24xx_i2c_suspend_noirq(struct device *dev) |
be44f01e | 1189 | { |
6a6c6189 MD |
1190 | struct platform_device *pdev = to_platform_device(dev); |
1191 | struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev); | |
1192 | ||
be44f01e | 1193 | i2c->suspended = 1; |
6a6c6189 | 1194 | |
be44f01e BD |
1195 | return 0; |
1196 | } | |
1197 | ||
6a6c6189 | 1198 | static int s3c24xx_i2c_resume(struct device *dev) |
1da177e4 | 1199 | { |
6a6c6189 MD |
1200 | struct platform_device *pdev = to_platform_device(dev); |
1201 | struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev); | |
9480e307 | 1202 | |
be44f01e | 1203 | i2c->suspended = 0; |
d3b64c59 | 1204 | clk_prepare_enable(i2c->clk); |
be44f01e | 1205 | s3c24xx_i2c_init(i2c); |
d3b64c59 | 1206 | clk_disable_unprepare(i2c->clk); |
1da177e4 LT |
1207 | |
1208 | return 0; | |
1209 | } | |
2935e0e0 | 1210 | #endif |
1da177e4 | 1211 | |
2935e0e0 | 1212 | #ifdef CONFIG_PM |
47145210 | 1213 | static const struct dev_pm_ops s3c24xx_i2c_dev_pm_ops = { |
2935e0e0 | 1214 | #ifdef CONFIG_PM_SLEEP |
6a6c6189 MD |
1215 | .suspend_noirq = s3c24xx_i2c_suspend_noirq, |
1216 | .resume = s3c24xx_i2c_resume, | |
2935e0e0 | 1217 | #endif |
6a6c6189 MD |
1218 | }; |
1219 | ||
1220 | #define S3C24XX_DEV_PM_OPS (&s3c24xx_i2c_dev_pm_ops) | |
1da177e4 | 1221 | #else |
6a6c6189 | 1222 | #define S3C24XX_DEV_PM_OPS NULL |
1da177e4 LT |
1223 | #endif |
1224 | ||
1225 | /* device driver for platform bus bits */ | |
1226 | ||
7d85ccd8 | 1227 | static struct platform_driver s3c24xx_i2c_driver = { |
1da177e4 LT |
1228 | .probe = s3c24xx_i2c_probe, |
1229 | .remove = s3c24xx_i2c_remove, | |
7d85ccd8 | 1230 | .id_table = s3c24xx_driver_ids, |
3ae5eaec RK |
1231 | .driver = { |
1232 | .owner = THIS_MODULE, | |
7d85ccd8 | 1233 | .name = "s3c-i2c", |
6a6c6189 | 1234 | .pm = S3C24XX_DEV_PM_OPS, |
9df7eadf | 1235 | .of_match_table = of_match_ptr(s3c24xx_i2c_match), |
3ae5eaec | 1236 | }, |
1da177e4 LT |
1237 | }; |
1238 | ||
1239 | static int __init i2c_adap_s3c_init(void) | |
1240 | { | |
7d85ccd8 | 1241 | return platform_driver_register(&s3c24xx_i2c_driver); |
1da177e4 | 1242 | } |
18dc83a6 | 1243 | subsys_initcall(i2c_adap_s3c_init); |
1da177e4 LT |
1244 | |
1245 | static void __exit i2c_adap_s3c_exit(void) | |
1246 | { | |
7d85ccd8 | 1247 | platform_driver_unregister(&s3c24xx_i2c_driver); |
1da177e4 | 1248 | } |
1da177e4 LT |
1249 | module_exit(i2c_adap_s3c_exit); |
1250 | ||
1251 | MODULE_DESCRIPTION("S3C24XX I2C Bus driver"); | |
1252 | MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>"); | |
1253 | MODULE_LICENSE("GPL"); |