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Merge branch 'i2c/for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa...
[deliverable/linux.git] / drivers / i2c / busses / i2c-sh_mobile.c
CommitLineData
da672773
MD		 1/*
2 * SuperH Mobile I2C Controller
3 *
4 * Copyright (C) 2008 Magnus Damm
5 *
6 * Portions of the code based on out-of-tree driver i2c-sh7343.c
7 * Copyright (c) 2006 Carlos Munoz <carlos@kenati.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23#include <linux/kernel.h>
24#include <linux/module.h>
25#include <linux/init.h>
26#include <linux/delay.h>
27#include <linux/platform_device.h>
28#include <linux/interrupt.h>
29#include <linux/i2c.h>
30#include <linux/err.h>
f1a3b994 31#include <linux/pm_runtime.h>
da672773
MD		 32#include <linux/clk.h>
33#include <linux/io.h>
5a0e3ad6 34#include <linux/slab.h>
67240dfc 35#include <linux/of_device.h>
81f81153 36#include <linux/i2c/i2c-sh_mobile.h>
da672773 37
4eb00c9f
MD		 38/* Transmit operation: */
39/* */
40/* 0 byte transmit */
e7890297 41/* BUS: S A8 ACK P(*) */
4eb00c9f
MD		 42/* IRQ: DTE WAIT */
43/* ICIC: */
44/* ICCR: 0x94 0x90 */
45/* ICDR: A8 */
46/* */
47/* 1 byte transmit */
e7890297 48/* BUS: S A8 ACK D8(1) ACK P(*) */
4eb00c9f
MD		 49/* IRQ: DTE WAIT WAIT */
50/* ICIC: -DTE */
51/* ICCR: 0x94 0x90 */
52/* ICDR: A8 D8(1) */
53/* */
54/* 2 byte transmit */
e7890297 55/* BUS: S A8 ACK D8(1) ACK D8(2) ACK P(*) */
4eb00c9f
MD		 56/* IRQ: DTE WAIT WAIT WAIT */
57/* ICIC: -DTE */
58/* ICCR: 0x94 0x90 */
59/* ICDR: A8 D8(1) D8(2) */
60/* */
61/* 3 bytes or more, +---------+ gets repeated */
62/* */
63/* */
64/* Receive operation: */
65/* */
66/* 0 byte receive - not supported since slave may hold SDA low */
67/* */
68/* 1 byte receive [TX] | [RX] */
e7890297 69/* BUS: S A8 ACK | D8(1) ACK P(*) */
4eb00c9f
MD		 70/* IRQ: DTE WAIT | WAIT DTE */
71/* ICIC: -DTE | +DTE */
72/* ICCR: 0x94 0x81 | 0xc0 */
73/* ICDR: A8 | D8(1) */
74/* */
75/* 2 byte receive [TX]| [RX] */
e7890297 76/* BUS: S A8 ACK | D8(1) ACK D8(2) ACK P(*) */
4eb00c9f
MD		 77/* IRQ: DTE WAIT | WAIT WAIT DTE */
78/* ICIC: -DTE | +DTE */
79/* ICCR: 0x94 0x81 | 0xc0 */
80/* ICDR: A8 | D8(1) D8(2) */
81/* */
e7890297 82/* 3 byte receive [TX] | [RX] (*) */
4eb00c9f
MD		 83/* BUS: S A8 ACK | D8(1) ACK D8(2) ACK D8(3) ACK P */
84/* IRQ: DTE WAIT | WAIT WAIT WAIT DTE */
85/* ICIC: -DTE | +DTE */
86/* ICCR: 0x94 0x81 | 0xc0 */
87/* ICDR: A8 | D8(1) D8(2) D8(3) */
88/* */
89/* 4 bytes or more, this part is repeated +---------+ */
90/* */
91/* */
92/* Interrupt order and BUSY flag */
93/* ___ _ */
94/* SDA ___\___XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXAAAAAAAAA___/ */
95/* SCL \_/1\_/2\_/3\_/4\_/5\_/6\_/7\_/8\___/9\_____/ */
96/* */
e7890297 97/* S D7 D6 D5 D4 D3 D2 D1 D0 P(*) */
4eb00c9f
MD		 98/* ___ */
99/* WAIT IRQ ________________________________/ \___________ */
100/* TACK IRQ ____________________________________/ \_______ */
101/* DTE IRQ __________________________________________/ \_ */
102/* AL IRQ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX */
103/* _______________________________________________ */
104/* BUSY __/ \_ */
105/* */
e7890297
GL		 106/* (*) The STOP condition is only sent by the master at the end of the last */
107/* I2C message or if the I2C_M_STOP flag is set. Similarly, the BUSY bit is */
108/* only cleared after the STOP condition, so, between messages we have to */
109/* poll for the DTE bit. */
110/* */
4eb00c9f 111
da672773
MD		 112enum sh_mobile_i2c_op {
113 OP_START = 0,
4eb00c9f
MD		 114 OP_TX_FIRST,
115 OP_TX,
da672773
MD		 116 OP_TX_STOP,
117 OP_TX_TO_RX,
4eb00c9f 118 OP_RX,
da672773 119 OP_RX_STOP,
4eb00c9f 120 OP_RX_STOP_DATA,
da672773
MD		 121};
122
123struct sh_mobile_i2c_data {
124 struct device *dev;
125 void __iomem *reg;
126 struct i2c_adapter adap;
81f81153 127 unsigned long bus_speed;
ebd5ac16 128 unsigned int clks_per_count;
da672773 129 struct clk *clk;
962b6032 130 u_int8_t icic;
962b6032 131 u_int8_t flags;
23a61291
SK		 132 u_int16_t iccl;
133 u_int16_t icch;
da672773
MD		 134
135 spinlock_t lock;
136 wait_queue_head_t wait;
137 struct i2c_msg *msg;
138 int pos;
139 int sr;
e7890297 140 bool send_stop;
da672773
MD		 141};
142
67240dfc
WS		 143struct sh_mobile_dt_config {
144 int clks_per_count;
145};
146
962b6032
MD		 147#define IIC_FLAG_HAS_ICIC67 (1 << 0)
148
23a61291
SK		 149#define STANDARD_MODE 100000
150#define FAST_MODE 400000
da672773
MD		 151
152/* Register offsets */
12a55f2d
MD		 153#define ICDR 0x00
154#define ICCR 0x04
155#define ICSR 0x08
156#define ICIC 0x0c
157#define ICCL 0x10
158#define ICCH 0x14
da672773
MD		 159
160/* Register bits */
161#define ICCR_ICE 0x80
162#define ICCR_RACK 0x40
163#define ICCR_TRS 0x10
164#define ICCR_BBSY 0x04
165#define ICCR_SCP 0x01
166
167#define ICSR_SCLM 0x80
168#define ICSR_SDAM 0x40
169#define SW_DONE 0x20
170#define ICSR_BUSY 0x10
171#define ICSR_AL 0x08
172#define ICSR_TACK 0x04
173#define ICSR_WAIT 0x02
174#define ICSR_DTE 0x01
175
962b6032
MD		 176#define ICIC_ICCLB8 0x80
177#define ICIC_ICCHB8 0x40
da672773
MD		 178#define ICIC_ALE 0x08
179#define ICIC_TACKE 0x04
180#define ICIC_WAITE 0x02
181#define ICIC_DTEE 0x01
182
12a55f2d
MD		 183static void iic_wr(struct sh_mobile_i2c_data *pd, int offs, unsigned char data)
184{
962b6032
MD		 185 if (offs == ICIC)
186 data |= pd->icic;
187
12a55f2d
MD		 188 iowrite8(data, pd->reg + offs);
189}
190
191static unsigned char iic_rd(struct sh_mobile_i2c_data *pd, int offs)
192{
193 return ioread8(pd->reg + offs);
194}
195
196static void iic_set_clr(struct sh_mobile_i2c_data *pd, int offs,
197 unsigned char set, unsigned char clr)
198{
199 iic_wr(pd, offs, (iic_rd(pd, offs) | set) & ~clr);
200}
201
ed4121e1 202static u32 sh_mobile_i2c_iccl(unsigned long count_khz, u32 tLOW, u32 tf)
23a61291
SK		 203{
204 /*
205 * Conditional expression:
206 * ICCL >= COUNT_CLK * (tLOW + tf)
207 *
208 * SH-Mobile IIC hardware starts counting the LOW period of
209 * the SCL signal (tLOW) as soon as it pulls the SCL line.
210 * In order to meet the tLOW timing spec, we need to take into
211 * account the fall time of SCL signal (tf). Default tf value
212 * should be 0.3 us, for safety.
213 */
ed4121e1 214 return (((count_khz * (tLOW + tf)) + 5000) / 10000);
23a61291
SK		 215}
216
ed4121e1 217static u32 sh_mobile_i2c_icch(unsigned long count_khz, u32 tHIGH, u32 tf)
23a61291
SK		 218{
219 /*
220 * Conditional expression:
221 * ICCH >= COUNT_CLK * (tHIGH + tf)
222 *
223 * SH-Mobile IIC hardware is aware of SCL transition period 'tr',
224 * and can ignore it. SH-Mobile IIC controller starts counting
225 * the HIGH period of the SCL signal (tHIGH) after the SCL input
226 * voltage increases at VIH.
227 *
228 * Afterward it turned out calculating ICCH using only tHIGH spec
229 * will result in violation of the tHD;STA timing spec. We need
230 * to take into account the fall time of SDA signal (tf) at START
231 * condition, in order to meet both tHIGH and tHD;STA specs.
232 */
ed4121e1 233 return (((count_khz * (tHIGH + tf)) + 5000) / 10000);
23a61291
SK		 234}
235
6ed7053c 236static int sh_mobile_i2c_init(struct sh_mobile_i2c_data *pd)
da672773 237{
23a61291
SK		 238 unsigned long i2c_clk_khz;
239 u32 tHIGH, tLOW, tf;
7663ebef 240 uint16_t max_val;
a5616bd0 241
a5616bd0 242 /* Get clock rate after clock is enabled */
f887605d 243 clk_prepare_enable(pd->clk);
23a61291 244 i2c_clk_khz = clk_get_rate(pd->clk) / 1000;
6ed7053c 245 clk_disable_unprepare(pd->clk);
ebd5ac16 246 i2c_clk_khz /= pd->clks_per_count;
23a61291
SK		 247
248 if (pd->bus_speed == STANDARD_MODE) {
249 tLOW = 47; /* tLOW = 4.7 us */
250 tHIGH = 40; /* tHD;STA = tHIGH = 4.0 us */
251 tf = 3; /* tf = 0.3 us */
23a61291
SK		 252 } else if (pd->bus_speed == FAST_MODE) {
253 tLOW = 13; /* tLOW = 1.3 us */
254 tHIGH = 6; /* tHD;STA = tHIGH = 0.6 us */
255 tf = 3; /* tf = 0.3 us */
23a61291
SK		 256 } else {
257 dev_err(pd->dev, "unrecognized bus speed %lu Hz\n",
258 pd->bus_speed);
6ed7053c 259 return -EINVAL;
962b6032
MD		 260 }
261
ed4121e1 262 pd->iccl = sh_mobile_i2c_iccl(i2c_clk_khz, tLOW, tf);
7663ebef
WS		 263 pd->icch = sh_mobile_i2c_icch(i2c_clk_khz, tHIGH, tf);
264
265 max_val = pd->flags & IIC_FLAG_HAS_ICIC67 ? 0x1ff : 0xff;
266 if (pd->iccl > max_val || pd->icch > max_val) {
267 dev_err(pd->dev, "timing values out of range: L/H=0x%x/0x%x\n",
268 pd->iccl, pd->icch);
269 return -EINVAL;
270 }
271
23a61291 272 /* one more bit of ICCL in ICIC */
7663ebef 273 if (pd->iccl & 0x100)
23a61291 274 pd->icic |= ICIC_ICCLB8;
a5616bd0 275 else
23a61291 276 pd->icic &= ~ICIC_ICCLB8;
a5616bd0 277
962b6032 278 /* one more bit of ICCH in ICIC */
7663ebef 279 if (pd->icch & 0x100)
23a61291
SK		 280 pd->icic |= ICIC_ICCHB8;
281 else
282 pd->icic &= ~ICIC_ICCHB8;
962b6032 283
6ed7053c 284 return 0;
7b0e6292
SK		 285}
286
287static void activate_ch(struct sh_mobile_i2c_data *pd)
288{
289 /* Wake up device and enable clock */
290 pm_runtime_get_sync(pd->dev);
f887605d 291 clk_prepare_enable(pd->clk);
7b0e6292 292
da672773 293 /* Enable channel and configure rx ack */
12a55f2d 294 iic_set_clr(pd, ICCR, ICCR_ICE, 0);
da672773
MD		 295
296 /* Mask all interrupts */
12a55f2d 297 iic_wr(pd, ICIC, 0);
da672773
MD		 298
299 /* Set the clock */
23a61291
SK		 300 iic_wr(pd, ICCL, pd->iccl & 0xff);
301 iic_wr(pd, ICCH, pd->icch & 0xff);
da672773
MD		 302}
303
304static void deactivate_ch(struct sh_mobile_i2c_data *pd)
305{
306 /* Clear/disable interrupts */
12a55f2d
MD		 307 iic_wr(pd, ICSR, 0);
308 iic_wr(pd, ICIC, 0);
da672773
MD		 309
310 /* Disable channel */
12a55f2d 311 iic_set_clr(pd, ICCR, 0, ICCR_ICE);
da672773 312
f1a3b994 313 /* Disable clock and mark device as idle */
f887605d 314 clk_disable_unprepare(pd->clk);
f1a3b994 315 pm_runtime_put_sync(pd->dev);
da672773
MD		 316}
317
318static unsigned char i2c_op(struct sh_mobile_i2c_data *pd,
319 enum sh_mobile_i2c_op op, unsigned char data)
320{
321 unsigned char ret = 0;
322 unsigned long flags;
323
324 dev_dbg(pd->dev, "op %d, data in 0x%02x\n", op, data);
325
326 spin_lock_irqsave(&pd->lock, flags);
327
328 switch (op) {
4eb00c9f 329 case OP_START: /* issue start and trigger DTE interrupt */
a78f6a41 330 iic_wr(pd, ICCR, ICCR_ICE | ICCR_TRS | ICCR_BBSY);
da672773 331 break;
4eb00c9f 332 case OP_TX_FIRST: /* disable DTE interrupt and write data */
12a55f2d
MD		 333 iic_wr(pd, ICIC, ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
334 iic_wr(pd, ICDR, data);
da672773 335 break;
4eb00c9f 336 case OP_TX: /* write data */
12a55f2d 337 iic_wr(pd, ICDR, data);
da672773 338 break;
4eb00c9f 339 case OP_TX_STOP: /* write data and issue a stop afterwards */
12a55f2d 340 iic_wr(pd, ICDR, data);
a78f6a41
WS		 341 iic_wr(pd, ICCR, pd->send_stop ? ICCR_ICE | ICCR_TRS
342 : ICCR_ICE | ICCR_TRS | ICCR_BBSY);
4eb00c9f
MD		 343 break;
344 case OP_TX_TO_RX: /* select read mode */
a78f6a41 345 iic_wr(pd, ICCR, ICCR_ICE | ICCR_SCP);
da672773 346 break;
4eb00c9f 347 case OP_RX: /* just read data */
12a55f2d 348 ret = iic_rd(pd, ICDR);
da672773 349 break;
4eb00c9f 350 case OP_RX_STOP: /* enable DTE interrupt, issue stop */
12a55f2d
MD		 351 iic_wr(pd, ICIC,
352 ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
a78f6a41 353 iic_wr(pd, ICCR, ICCR_ICE | ICCR_RACK);
4eb00c9f
MD		 354 break;
355 case OP_RX_STOP_DATA: /* enable DTE interrupt, read data, issue stop */
12a55f2d
MD		 356 iic_wr(pd, ICIC,
357 ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
358 ret = iic_rd(pd, ICDR);
a78f6a41 359 iic_wr(pd, ICCR, ICCR_ICE | ICCR_RACK);
da672773
MD		 360 break;
361 }
362
363 spin_unlock_irqrestore(&pd->lock, flags);
364
365 dev_dbg(pd->dev, "op %d, data out 0x%02x\n", op, ret);
366 return ret;
367}
368
05cf9368 369static bool sh_mobile_i2c_is_first_byte(struct sh_mobile_i2c_data *pd)
4eb00c9f 370{
05cf9368 371 return pd->pos == -1;
4eb00c9f
MD		 372}
373
05cf9368 374static bool sh_mobile_i2c_is_last_byte(struct sh_mobile_i2c_data *pd)
4eb00c9f 375{
05cf9368 376 return pd->pos == pd->msg->len - 1;
4eb00c9f
MD		 377}
378
379static void sh_mobile_i2c_get_data(struct sh_mobile_i2c_data *pd,
380 unsigned char *buf)
381{
382 switch (pd->pos) {
383 case -1:
384 *buf = (pd->msg->addr & 0x7f) << 1;
385 *buf |= (pd->msg->flags & I2C_M_RD) ? 1 : 0;
386 break;
387 default:
388 *buf = pd->msg->buf[pd->pos];
389 }
390}
391
392static int sh_mobile_i2c_isr_tx(struct sh_mobile_i2c_data *pd)
393{
394 unsigned char data;
395
396 if (pd->pos == pd->msg->len)
397 return 1;
398
399 sh_mobile_i2c_get_data(pd, &data);
400
401 if (sh_mobile_i2c_is_last_byte(pd))
402 i2c_op(pd, OP_TX_STOP, data);
403 else if (sh_mobile_i2c_is_first_byte(pd))
404 i2c_op(pd, OP_TX_FIRST, data);
405 else
406 i2c_op(pd, OP_TX, data);
407
408 pd->pos++;
409 return 0;
410}
411
412static int sh_mobile_i2c_isr_rx(struct sh_mobile_i2c_data *pd)
413{
414 unsigned char data;
415 int real_pos;
416
417 do {
418 if (pd->pos <= -1) {
419 sh_mobile_i2c_get_data(pd, &data);
420
421 if (sh_mobile_i2c_is_first_byte(pd))
422 i2c_op(pd, OP_TX_FIRST, data);
423 else
424 i2c_op(pd, OP_TX, data);
425 break;
426 }
427
428 if (pd->pos == 0) {
429 i2c_op(pd, OP_TX_TO_RX, 0);
430 break;
431 }
432
433 real_pos = pd->pos - 2;
434
435 if (pd->pos == pd->msg->len) {
436 if (real_pos < 0) {
437 i2c_op(pd, OP_RX_STOP, 0);
438 break;
439 }
440 data = i2c_op(pd, OP_RX_STOP_DATA, 0);
441 } else
442 data = i2c_op(pd, OP_RX, 0);
443
bff4056c
MD		 444 if (real_pos >= 0)
445 pd->msg->buf[real_pos] = data;
4eb00c9f
MD		 446 } while (0);
447
448 pd->pos++;
449 return pd->pos == (pd->msg->len + 2);
450}
451
da672773
MD		 452static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id)
453{
454 struct platform_device *dev = dev_id;
455 struct sh_mobile_i2c_data *pd = platform_get_drvdata(dev);
4eb00c9f
MD		 456 unsigned char sr;
457 int wakeup;
da672773 458
12a55f2d 459 sr = iic_rd(pd, ICSR);
4eb00c9f 460 pd->sr |= sr; /* remember state */
da672773
MD		 461
462 dev_dbg(pd->dev, "i2c_isr 0x%02x 0x%02x %s %d %d!\n", sr, pd->sr,
4eb00c9f
MD		 463 (pd->msg->flags & I2C_M_RD) ? "read" : "write",
464 pd->pos, pd->msg->len);
da672773
MD		 465
466 if (sr & (ICSR_AL | ICSR_TACK)) {
4eb00c9f 467 /* don't interrupt transaction - continue to issue stop */
12a55f2d 468 iic_wr(pd, ICSR, sr & ~(ICSR_AL | ICSR_TACK));
4eb00c9f
MD		 469 wakeup = 0;
470 } else if (pd->msg->flags & I2C_M_RD)
471 wakeup = sh_mobile_i2c_isr_rx(pd);
472 else
473 wakeup = sh_mobile_i2c_isr_tx(pd);
da672773 474
4eb00c9f 475 if (sr & ICSR_WAIT) /* TODO: add delay here to support slow acks */
12a55f2d 476 iic_wr(pd, ICSR, sr & ~ICSR_WAIT);
da672773 477
da672773
MD		 478 if (wakeup) {
479 pd->sr |= SW_DONE;
480 wake_up(&pd->wait);
481 }
482
29fb08c3
SK		 483 /* defeat write posting to avoid spurious WAIT interrupts */
484 iic_rd(pd, ICSR);
485
da672773
MD		 486 return IRQ_HANDLED;
487}
488
e7890297
GL		 489static int start_ch(struct sh_mobile_i2c_data *pd, struct i2c_msg *usr_msg,
490 bool do_init)
da672773 491{
4eb00c9f
MD		 492 if (usr_msg->len == 0 && (usr_msg->flags & I2C_M_RD)) {
493 dev_err(pd->dev, "Unsupported zero length i2c read\n");
5a72b25e 494 return -EOPNOTSUPP;
4eb00c9f
MD		 495 }
496
e7890297
GL		 497 if (do_init) {
498 /* Initialize channel registers */
499 iic_set_clr(pd, ICCR, 0, ICCR_ICE);
da672773 500
e7890297
GL		 501 /* Enable channel and configure rx ack */
502 iic_set_clr(pd, ICCR, ICCR_ICE, 0);
da672773 503
e7890297
GL		 504 /* Set the clock */
505 iic_wr(pd, ICCL, pd->iccl & 0xff);
506 iic_wr(pd, ICCH, pd->icch & 0xff);
507 }
da672773
MD		 508
509 pd->msg = usr_msg;
510 pd->pos = -1;
511 pd->sr = 0;
512
4eb00c9f 513 /* Enable all interrupts to begin with */
12a55f2d 514 iic_wr(pd, ICIC, ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
da672773
MD		 515 return 0;
516}
517
e7890297
GL		 518static int poll_dte(struct sh_mobile_i2c_data *pd)
519{
520 int i;
521
522 for (i = 1000; i; i--) {
523 u_int8_t val = iic_rd(pd, ICSR);
524
525 if (val & ICSR_DTE)
526 break;
527
528 if (val & ICSR_TACK)
5a72b25e 529 return -ENXIO;
e7890297
GL		 530
531 udelay(10);
532 }
533
5a72b25e 534 return i ? 0 : -ETIMEDOUT;
e7890297
GL		 535}
536
4b382318
GL		 537static int poll_busy(struct sh_mobile_i2c_data *pd)
538{
539 int i;
540
541 for (i = 1000; i; i--) {
542 u_int8_t val = iic_rd(pd, ICSR);
543
544 dev_dbg(pd->dev, "val 0x%02x pd->sr 0x%02x\n", val, pd->sr);
545
546 /* the interrupt handler may wake us up before the
547 * transfer is finished, so poll the hardware
548 * until we're done.
549 */
550 if (!(val & ICSR_BUSY)) {
551 /* handle missing acknowledge and arbitration lost */
5a72b25e
WS		 552 val |= pd->sr;
553 if (val & ICSR_TACK)
554 return -ENXIO;
555 if (val & ICSR_AL)
556 return -EAGAIN;
4b382318
GL		 557 break;
558 }
559
560 udelay(10);
561 }
562
5a72b25e 563 return i ? 0 : -ETIMEDOUT;
4b382318
GL		 564}
565
da672773
MD		 566static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter,
567 struct i2c_msg *msgs,
568 int num)
569{
570 struct sh_mobile_i2c_data *pd = i2c_get_adapdata(adapter);
571 struct i2c_msg *msg;
572 int err = 0;
4b382318 573 int i, k;
da672773
MD		 574
575 activate_ch(pd);
576
577 /* Process all messages */
578 for (i = 0; i < num; i++) {
e7890297 579 bool do_start = pd->send_stop || !i;
da672773 580 msg = &msgs[i];
e7890297 581 pd->send_stop = i == num - 1 || msg->flags & I2C_M_STOP;
da672773 582
e7890297 583 err = start_ch(pd, msg, do_start);
da672773
MD		 584 if (err)
585 break;
586
e7890297
GL		 587 if (do_start)
588 i2c_op(pd, OP_START, 0);
da672773
MD		 589
590 /* The interrupt handler takes care of the rest... */
591 k = wait_event_timeout(pd->wait,
592 pd->sr & (ICSR_TACK | SW_DONE),
593 5 * HZ);
5687265b 594 if (!k) {
da672773 595 dev_err(pd->dev, "Transfer request timed out\n");
5687265b
GL		 596 err = -ETIMEDOUT;
597 break;
598 }
da672773 599
e7890297
GL		 600 if (pd->send_stop)
601 err = poll_busy(pd);
602 else
603 err = poll_dte(pd);
4b382318 604 if (err < 0)
da672773 605 break;
da672773
MD		 606 }
607
608 deactivate_ch(pd);
609
610 if (!err)
611 err = num;
612 return err;
613}
614
615static u32 sh_mobile_i2c_func(struct i2c_adapter *adapter)
616{
e7890297 617 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
da672773
MD		 618}
619
620static struct i2c_algorithm sh_mobile_i2c_algorithm = {
621 .functionality = sh_mobile_i2c_func,
622 .master_xfer = sh_mobile_i2c_xfer,
623};
624
67240dfc
WS		 625static const struct sh_mobile_dt_config default_dt_config = {
626 .clks_per_count = 1,
627};
628
629static const struct sh_mobile_dt_config rcar_gen2_dt_config = {
630 .clks_per_count = 2,
631};
632
633static const struct of_device_id sh_mobile_i2c_dt_ids[] = {
634 { .compatible = "renesas,rmobile-iic", .data = &default_dt_config },
635 { .compatible = "renesas,iic-r8a7790", .data = &rcar_gen2_dt_config },
636 { .compatible = "renesas,iic-r8a7791", .data = &rcar_gen2_dt_config },
90104d06
WS		 637 { .compatible = "renesas,iic-r8a7792", .data = &rcar_gen2_dt_config },
638 { .compatible = "renesas,iic-r8a7793", .data = &rcar_gen2_dt_config },
639 { .compatible = "renesas,iic-r8a7794", .data = &rcar_gen2_dt_config },
67240dfc
WS		 640 {},
641};
642MODULE_DEVICE_TABLE(of, sh_mobile_i2c_dt_ids);
643
7fe8a999 644static int sh_mobile_i2c_hook_irqs(struct platform_device *dev)
da672773
MD		 645{
646 struct resource *res;
7fe8a999
WS		 647 resource_size_t n;
648 int k = 0, ret;
da672773
MD		 649
650 while ((res = platform_get_resource(dev, IORESOURCE_IRQ, k))) {
7fe8a999
WS		 651 for (n = res->start; n <= res->end; n++) {
652 ret = devm_request_irq(&dev->dev, n, sh_mobile_i2c_isr,
653 0, dev_name(&dev->dev), dev);
654 if (ret) {
655 dev_err(&dev->dev, "cannot request IRQ %pa\n", &n);
656 return ret;
82b20d8b 657 }
da672773
MD		 658 }
659 k++;
660 }
661
7fe8a999 662 return k > 0 ? 0 : -ENOENT;
da672773
MD		 663}
664
665static int sh_mobile_i2c_probe(struct platform_device *dev)
666{
6d4028c6 667 struct i2c_sh_mobile_platform_data *pdata = dev_get_platdata(&dev->dev);
da672773
MD		 668 struct sh_mobile_i2c_data *pd;
669 struct i2c_adapter *adap;
670 struct resource *res;
da672773 671 int ret;
88c289ec 672 u32 bus_speed;
da672773 673
4fd31c2e
WS		 674 pd = devm_kzalloc(&dev->dev, sizeof(struct sh_mobile_i2c_data), GFP_KERNEL);
675 if (!pd)
da672773 676 return -ENOMEM;
da672773 677
4fd31c2e 678 pd->clk = devm_clk_get(&dev->dev, NULL);
da672773 679 if (IS_ERR(pd->clk)) {
1082d5d2 680 dev_err(&dev->dev, "cannot get clock\n");
4fd31c2e 681 return PTR_ERR(pd->clk);
da672773
MD		 682 }
683
7fe8a999
WS		 684 ret = sh_mobile_i2c_hook_irqs(dev);
685 if (ret)
4fd31c2e 686 return ret;
da672773
MD		 687
688 pd->dev = &dev->dev;
689 platform_set_drvdata(dev, pd);
690
691 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
da672773 692
4fd31c2e 693 pd->reg = devm_ioremap_resource(&dev->dev, res);
7fe8a999
WS		 694 if (IS_ERR(pd->reg))
695 return PTR_ERR(pd->reg);
da672773 696
23a61291 697 /* Use platform data bus speed or STANDARD_MODE */
88c289ec
WS		 698 ret = of_property_read_u32(dev->dev.of_node, "clock-frequency", &bus_speed);
699 pd->bus_speed = ret ? STANDARD_MODE : bus_speed;
700
ebd5ac16 701 pd->clks_per_count = 1;
67240dfc
WS		 702
703 if (dev->dev.of_node) {
704 const struct of_device_id *match;
705
706 match = of_match_device(sh_mobile_i2c_dt_ids, &dev->dev);
707 if (match) {
708 const struct sh_mobile_dt_config *config;
709
710 config = match->data;
711 pd->clks_per_count = config->clks_per_count;
712 }
713 } else {
714 if (pdata && pdata->bus_speed)
715 pd->bus_speed = pdata->bus_speed;
716 if (pdata && pdata->clks_per_count)
717 pd->clks_per_count = pdata->clks_per_count;
718 }
81f81153 719
962b6032
MD		 720 /* The IIC blocks on SH-Mobile ARM processors
721 * come with two new bits in ICIC.
722 */
4fd31c2e 723 if (resource_size(res) > 0x17)
962b6032
MD		 724 pd->flags |= IIC_FLAG_HAS_ICIC67;
725
6ed7053c
WS		 726 ret = sh_mobile_i2c_init(pd);
727 if (ret)
728 return ret;
7b0e6292 729
f1a3b994
MD		 730 /* Enable Runtime PM for this device.
731 *
732 * Also tell the Runtime PM core to ignore children
733 * for this device since it is valid for us to suspend
734 * this I2C master driver even though the slave devices
735 * on the I2C bus may not be suspended.
736 *
737 * The state of the I2C hardware bus is unaffected by
738 * the Runtime PM state.
739 */
740 pm_suspend_ignore_children(&dev->dev, true);
741 pm_runtime_enable(&dev->dev);
742
da672773
MD		 743 /* setup the private data */
744 adap = &pd->adap;
745 i2c_set_adapdata(adap, pd);
746
747 adap->owner = THIS_MODULE;
748 adap->algo = &sh_mobile_i2c_algorithm;
749 adap->dev.parent = &dev->dev;
750 adap->retries = 5;
751 adap->nr = dev->id;
ad337074 752 adap->dev.of_node = dev->dev.of_node;
da672773
MD		 753
754 strlcpy(adap->name, dev->name, sizeof(adap->name));
755
a5616bd0
MD		 756 spin_lock_init(&pd->lock);
757 init_waitqueue_head(&pd->wait);
da672773
MD		 758
759 ret = i2c_add_numbered_adapter(adap);
760 if (ret < 0) {
761 dev_err(&dev->dev, "cannot add numbered adapter\n");
7fe8a999 762 return ret;
da672773
MD		 763 }
764
23a61291 765 dev_info(&dev->dev,
7663ebef 766 "I2C adapter %d with bus speed %lu Hz (L/H=0x%x/0x%x)\n",
23a61291 767 adap->nr, pd->bus_speed, pd->iccl, pd->icch);
ad337074 768
da672773 769 return 0;
da672773
MD		 770}
771
772static int sh_mobile_i2c_remove(struct platform_device *dev)
773{
774 struct sh_mobile_i2c_data *pd = platform_get_drvdata(dev);
775
776 i2c_del_adapter(&pd->adap);
f1a3b994 777 pm_runtime_disable(&dev->dev);
da672773
MD		 778 return 0;
779}
780
f1a3b994
MD		 781static int sh_mobile_i2c_runtime_nop(struct device *dev)
782{
783 /* Runtime PM callback shared between ->runtime_suspend()
784 * and ->runtime_resume(). Simply returns success.
785 *
786 * This driver re-initializes all registers after
787 * pm_runtime_get_sync() anyway so there is no need
788 * to save and restore registers here.
789 */
790 return 0;
791}
792
47145210 793static const struct dev_pm_ops sh_mobile_i2c_dev_pm_ops = {
f1a3b994
MD		 794 .runtime_suspend = sh_mobile_i2c_runtime_nop,
795 .runtime_resume = sh_mobile_i2c_runtime_nop,
796};
797
da672773
MD		 798static struct platform_driver sh_mobile_i2c_driver = {
799 .driver = {
800 .name = "i2c-sh_mobile",
801 .owner = THIS_MODULE,
f1a3b994 802 .pm = &sh_mobile_i2c_dev_pm_ops,
ad337074 803 .of_match_table = sh_mobile_i2c_dt_ids,
da672773
MD		 804 },
805 .probe = sh_mobile_i2c_probe,
806 .remove = sh_mobile_i2c_remove,
807};
808
809static int __init sh_mobile_i2c_adap_init(void)
810{
811 return platform_driver_register(&sh_mobile_i2c_driver);
812}
813
814static void __exit sh_mobile_i2c_adap_exit(void)
815{
816 platform_driver_unregister(&sh_mobile_i2c_driver);
817}
818
ccb3bc16 819subsys_initcall(sh_mobile_i2c_adap_init);
da672773
MD		 820module_exit(sh_mobile_i2c_adap_exit);
821
822MODULE_DESCRIPTION("SuperH Mobile I2C Bus Controller driver");
823MODULE_AUTHOR("Magnus Damm");
824MODULE_LICENSE("GPL v2");
7ef0c12a 825MODULE_ALIAS("platform:i2c-sh_mobile");
Linux kernel - Deliverables
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