Commit | Line | Data |
---|---|---|
da672773 MD |
1 | /* |
2 | * SuperH Mobile I2C Controller | |
3 | * | |
4 | * Copyright (C) 2008 Magnus Damm | |
5 | * | |
6 | * Portions of the code based on out-of-tree driver i2c-sh7343.c | |
7 | * Copyright (c) 2006 Carlos Munoz <carlos@kenati.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | #include <linux/kernel.h> | |
24 | #include <linux/module.h> | |
25 | #include <linux/init.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/platform_device.h> | |
28 | #include <linux/interrupt.h> | |
29 | #include <linux/i2c.h> | |
30 | #include <linux/err.h> | |
f1a3b994 | 31 | #include <linux/pm_runtime.h> |
da672773 MD |
32 | #include <linux/clk.h> |
33 | #include <linux/io.h> | |
5a0e3ad6 | 34 | #include <linux/slab.h> |
81f81153 | 35 | #include <linux/i2c/i2c-sh_mobile.h> |
da672773 | 36 | |
4eb00c9f MD |
37 | /* Transmit operation: */ |
38 | /* */ | |
39 | /* 0 byte transmit */ | |
e7890297 | 40 | /* BUS: S A8 ACK P(*) */ |
4eb00c9f MD |
41 | /* IRQ: DTE WAIT */ |
42 | /* ICIC: */ | |
43 | /* ICCR: 0x94 0x90 */ | |
44 | /* ICDR: A8 */ | |
45 | /* */ | |
46 | /* 1 byte transmit */ | |
e7890297 | 47 | /* BUS: S A8 ACK D8(1) ACK P(*) */ |
4eb00c9f MD |
48 | /* IRQ: DTE WAIT WAIT */ |
49 | /* ICIC: -DTE */ | |
50 | /* ICCR: 0x94 0x90 */ | |
51 | /* ICDR: A8 D8(1) */ | |
52 | /* */ | |
53 | /* 2 byte transmit */ | |
e7890297 | 54 | /* BUS: S A8 ACK D8(1) ACK D8(2) ACK P(*) */ |
4eb00c9f MD |
55 | /* IRQ: DTE WAIT WAIT WAIT */ |
56 | /* ICIC: -DTE */ | |
57 | /* ICCR: 0x94 0x90 */ | |
58 | /* ICDR: A8 D8(1) D8(2) */ | |
59 | /* */ | |
60 | /* 3 bytes or more, +---------+ gets repeated */ | |
61 | /* */ | |
62 | /* */ | |
63 | /* Receive operation: */ | |
64 | /* */ | |
65 | /* 0 byte receive - not supported since slave may hold SDA low */ | |
66 | /* */ | |
67 | /* 1 byte receive [TX] | [RX] */ | |
e7890297 | 68 | /* BUS: S A8 ACK | D8(1) ACK P(*) */ |
4eb00c9f MD |
69 | /* IRQ: DTE WAIT | WAIT DTE */ |
70 | /* ICIC: -DTE | +DTE */ | |
71 | /* ICCR: 0x94 0x81 | 0xc0 */ | |
72 | /* ICDR: A8 | D8(1) */ | |
73 | /* */ | |
74 | /* 2 byte receive [TX]| [RX] */ | |
e7890297 | 75 | /* BUS: S A8 ACK | D8(1) ACK D8(2) ACK P(*) */ |
4eb00c9f MD |
76 | /* IRQ: DTE WAIT | WAIT WAIT DTE */ |
77 | /* ICIC: -DTE | +DTE */ | |
78 | /* ICCR: 0x94 0x81 | 0xc0 */ | |
79 | /* ICDR: A8 | D8(1) D8(2) */ | |
80 | /* */ | |
e7890297 | 81 | /* 3 byte receive [TX] | [RX] (*) */ |
4eb00c9f MD |
82 | /* BUS: S A8 ACK | D8(1) ACK D8(2) ACK D8(3) ACK P */ |
83 | /* IRQ: DTE WAIT | WAIT WAIT WAIT DTE */ | |
84 | /* ICIC: -DTE | +DTE */ | |
85 | /* ICCR: 0x94 0x81 | 0xc0 */ | |
86 | /* ICDR: A8 | D8(1) D8(2) D8(3) */ | |
87 | /* */ | |
88 | /* 4 bytes or more, this part is repeated +---------+ */ | |
89 | /* */ | |
90 | /* */ | |
91 | /* Interrupt order and BUSY flag */ | |
92 | /* ___ _ */ | |
93 | /* SDA ___\___XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXAAAAAAAAA___/ */ | |
94 | /* SCL \_/1\_/2\_/3\_/4\_/5\_/6\_/7\_/8\___/9\_____/ */ | |
95 | /* */ | |
e7890297 | 96 | /* S D7 D6 D5 D4 D3 D2 D1 D0 P(*) */ |
4eb00c9f MD |
97 | /* ___ */ |
98 | /* WAIT IRQ ________________________________/ \___________ */ | |
99 | /* TACK IRQ ____________________________________/ \_______ */ | |
100 | /* DTE IRQ __________________________________________/ \_ */ | |
101 | /* AL IRQ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX */ | |
102 | /* _______________________________________________ */ | |
103 | /* BUSY __/ \_ */ | |
104 | /* */ | |
e7890297 GL |
105 | /* (*) The STOP condition is only sent by the master at the end of the last */ |
106 | /* I2C message or if the I2C_M_STOP flag is set. Similarly, the BUSY bit is */ | |
107 | /* only cleared after the STOP condition, so, between messages we have to */ | |
108 | /* poll for the DTE bit. */ | |
109 | /* */ | |
4eb00c9f | 110 | |
da672773 MD |
111 | enum sh_mobile_i2c_op { |
112 | OP_START = 0, | |
4eb00c9f MD |
113 | OP_TX_FIRST, |
114 | OP_TX, | |
da672773 MD |
115 | OP_TX_STOP, |
116 | OP_TX_TO_RX, | |
4eb00c9f | 117 | OP_RX, |
da672773 | 118 | OP_RX_STOP, |
4eb00c9f | 119 | OP_RX_STOP_DATA, |
da672773 MD |
120 | }; |
121 | ||
122 | struct sh_mobile_i2c_data { | |
123 | struct device *dev; | |
124 | void __iomem *reg; | |
125 | struct i2c_adapter adap; | |
81f81153 | 126 | unsigned long bus_speed; |
ebd5ac16 | 127 | unsigned int clks_per_count; |
da672773 | 128 | struct clk *clk; |
962b6032 | 129 | u_int8_t icic; |
962b6032 | 130 | u_int8_t flags; |
23a61291 SK |
131 | u_int16_t iccl; |
132 | u_int16_t icch; | |
da672773 MD |
133 | |
134 | spinlock_t lock; | |
135 | wait_queue_head_t wait; | |
136 | struct i2c_msg *msg; | |
137 | int pos; | |
138 | int sr; | |
e7890297 | 139 | bool send_stop; |
da672773 MD |
140 | }; |
141 | ||
962b6032 MD |
142 | #define IIC_FLAG_HAS_ICIC67 (1 << 0) |
143 | ||
23a61291 SK |
144 | #define STANDARD_MODE 100000 |
145 | #define FAST_MODE 400000 | |
da672773 MD |
146 | |
147 | /* Register offsets */ | |
12a55f2d MD |
148 | #define ICDR 0x00 |
149 | #define ICCR 0x04 | |
150 | #define ICSR 0x08 | |
151 | #define ICIC 0x0c | |
152 | #define ICCL 0x10 | |
153 | #define ICCH 0x14 | |
da672773 MD |
154 | |
155 | /* Register bits */ | |
156 | #define ICCR_ICE 0x80 | |
157 | #define ICCR_RACK 0x40 | |
158 | #define ICCR_TRS 0x10 | |
159 | #define ICCR_BBSY 0x04 | |
160 | #define ICCR_SCP 0x01 | |
161 | ||
162 | #define ICSR_SCLM 0x80 | |
163 | #define ICSR_SDAM 0x40 | |
164 | #define SW_DONE 0x20 | |
165 | #define ICSR_BUSY 0x10 | |
166 | #define ICSR_AL 0x08 | |
167 | #define ICSR_TACK 0x04 | |
168 | #define ICSR_WAIT 0x02 | |
169 | #define ICSR_DTE 0x01 | |
170 | ||
962b6032 MD |
171 | #define ICIC_ICCLB8 0x80 |
172 | #define ICIC_ICCHB8 0x40 | |
da672773 MD |
173 | #define ICIC_ALE 0x08 |
174 | #define ICIC_TACKE 0x04 | |
175 | #define ICIC_WAITE 0x02 | |
176 | #define ICIC_DTEE 0x01 | |
177 | ||
12a55f2d MD |
178 | static void iic_wr(struct sh_mobile_i2c_data *pd, int offs, unsigned char data) |
179 | { | |
962b6032 MD |
180 | if (offs == ICIC) |
181 | data |= pd->icic; | |
182 | ||
12a55f2d MD |
183 | iowrite8(data, pd->reg + offs); |
184 | } | |
185 | ||
186 | static unsigned char iic_rd(struct sh_mobile_i2c_data *pd, int offs) | |
187 | { | |
188 | return ioread8(pd->reg + offs); | |
189 | } | |
190 | ||
191 | static void iic_set_clr(struct sh_mobile_i2c_data *pd, int offs, | |
192 | unsigned char set, unsigned char clr) | |
193 | { | |
194 | iic_wr(pd, offs, (iic_rd(pd, offs) | set) & ~clr); | |
195 | } | |
196 | ||
ed4121e1 | 197 | static u32 sh_mobile_i2c_iccl(unsigned long count_khz, u32 tLOW, u32 tf) |
23a61291 SK |
198 | { |
199 | /* | |
200 | * Conditional expression: | |
201 | * ICCL >= COUNT_CLK * (tLOW + tf) | |
202 | * | |
203 | * SH-Mobile IIC hardware starts counting the LOW period of | |
204 | * the SCL signal (tLOW) as soon as it pulls the SCL line. | |
205 | * In order to meet the tLOW timing spec, we need to take into | |
206 | * account the fall time of SCL signal (tf). Default tf value | |
207 | * should be 0.3 us, for safety. | |
208 | */ | |
ed4121e1 | 209 | return (((count_khz * (tLOW + tf)) + 5000) / 10000); |
23a61291 SK |
210 | } |
211 | ||
ed4121e1 | 212 | static u32 sh_mobile_i2c_icch(unsigned long count_khz, u32 tHIGH, u32 tf) |
23a61291 SK |
213 | { |
214 | /* | |
215 | * Conditional expression: | |
216 | * ICCH >= COUNT_CLK * (tHIGH + tf) | |
217 | * | |
218 | * SH-Mobile IIC hardware is aware of SCL transition period 'tr', | |
219 | * and can ignore it. SH-Mobile IIC controller starts counting | |
220 | * the HIGH period of the SCL signal (tHIGH) after the SCL input | |
221 | * voltage increases at VIH. | |
222 | * | |
223 | * Afterward it turned out calculating ICCH using only tHIGH spec | |
224 | * will result in violation of the tHD;STA timing spec. We need | |
225 | * to take into account the fall time of SDA signal (tf) at START | |
226 | * condition, in order to meet both tHIGH and tHD;STA specs. | |
227 | */ | |
ed4121e1 | 228 | return (((count_khz * (tHIGH + tf)) + 5000) / 10000); |
23a61291 SK |
229 | } |
230 | ||
7b0e6292 | 231 | static void sh_mobile_i2c_init(struct sh_mobile_i2c_data *pd) |
da672773 | 232 | { |
23a61291 SK |
233 | unsigned long i2c_clk_khz; |
234 | u32 tHIGH, tLOW, tf; | |
a5616bd0 | 235 | |
a5616bd0 | 236 | /* Get clock rate after clock is enabled */ |
f887605d | 237 | clk_prepare_enable(pd->clk); |
23a61291 | 238 | i2c_clk_khz = clk_get_rate(pd->clk) / 1000; |
ebd5ac16 | 239 | i2c_clk_khz /= pd->clks_per_count; |
23a61291 SK |
240 | |
241 | if (pd->bus_speed == STANDARD_MODE) { | |
242 | tLOW = 47; /* tLOW = 4.7 us */ | |
243 | tHIGH = 40; /* tHD;STA = tHIGH = 4.0 us */ | |
244 | tf = 3; /* tf = 0.3 us */ | |
23a61291 SK |
245 | } else if (pd->bus_speed == FAST_MODE) { |
246 | tLOW = 13; /* tLOW = 1.3 us */ | |
247 | tHIGH = 6; /* tHD;STA = tHIGH = 0.6 us */ | |
248 | tf = 3; /* tf = 0.3 us */ | |
23a61291 SK |
249 | } else { |
250 | dev_err(pd->dev, "unrecognized bus speed %lu Hz\n", | |
251 | pd->bus_speed); | |
252 | goto out; | |
962b6032 MD |
253 | } |
254 | ||
ed4121e1 | 255 | pd->iccl = sh_mobile_i2c_iccl(i2c_clk_khz, tLOW, tf); |
23a61291 SK |
256 | /* one more bit of ICCL in ICIC */ |
257 | if ((pd->iccl > 0xff) && (pd->flags & IIC_FLAG_HAS_ICIC67)) | |
258 | pd->icic |= ICIC_ICCLB8; | |
a5616bd0 | 259 | else |
23a61291 | 260 | pd->icic &= ~ICIC_ICCLB8; |
a5616bd0 | 261 | |
ed4121e1 | 262 | pd->icch = sh_mobile_i2c_icch(i2c_clk_khz, tHIGH, tf); |
962b6032 | 263 | /* one more bit of ICCH in ICIC */ |
23a61291 SK |
264 | if ((pd->icch > 0xff) && (pd->flags & IIC_FLAG_HAS_ICIC67)) |
265 | pd->icic |= ICIC_ICCHB8; | |
266 | else | |
267 | pd->icic &= ~ICIC_ICCHB8; | |
962b6032 | 268 | |
23a61291 | 269 | out: |
f887605d | 270 | clk_disable_unprepare(pd->clk); |
7b0e6292 SK |
271 | } |
272 | ||
273 | static void activate_ch(struct sh_mobile_i2c_data *pd) | |
274 | { | |
275 | /* Wake up device and enable clock */ | |
276 | pm_runtime_get_sync(pd->dev); | |
f887605d | 277 | clk_prepare_enable(pd->clk); |
7b0e6292 | 278 | |
da672773 | 279 | /* Enable channel and configure rx ack */ |
12a55f2d | 280 | iic_set_clr(pd, ICCR, ICCR_ICE, 0); |
da672773 MD |
281 | |
282 | /* Mask all interrupts */ | |
12a55f2d | 283 | iic_wr(pd, ICIC, 0); |
da672773 MD |
284 | |
285 | /* Set the clock */ | |
23a61291 SK |
286 | iic_wr(pd, ICCL, pd->iccl & 0xff); |
287 | iic_wr(pd, ICCH, pd->icch & 0xff); | |
da672773 MD |
288 | } |
289 | ||
290 | static void deactivate_ch(struct sh_mobile_i2c_data *pd) | |
291 | { | |
292 | /* Clear/disable interrupts */ | |
12a55f2d MD |
293 | iic_wr(pd, ICSR, 0); |
294 | iic_wr(pd, ICIC, 0); | |
da672773 MD |
295 | |
296 | /* Disable channel */ | |
12a55f2d | 297 | iic_set_clr(pd, ICCR, 0, ICCR_ICE); |
da672773 | 298 | |
f1a3b994 | 299 | /* Disable clock and mark device as idle */ |
f887605d | 300 | clk_disable_unprepare(pd->clk); |
f1a3b994 | 301 | pm_runtime_put_sync(pd->dev); |
da672773 MD |
302 | } |
303 | ||
304 | static unsigned char i2c_op(struct sh_mobile_i2c_data *pd, | |
305 | enum sh_mobile_i2c_op op, unsigned char data) | |
306 | { | |
307 | unsigned char ret = 0; | |
308 | unsigned long flags; | |
309 | ||
310 | dev_dbg(pd->dev, "op %d, data in 0x%02x\n", op, data); | |
311 | ||
312 | spin_lock_irqsave(&pd->lock, flags); | |
313 | ||
314 | switch (op) { | |
4eb00c9f | 315 | case OP_START: /* issue start and trigger DTE interrupt */ |
a78f6a41 | 316 | iic_wr(pd, ICCR, ICCR_ICE | ICCR_TRS | ICCR_BBSY); |
da672773 | 317 | break; |
4eb00c9f | 318 | case OP_TX_FIRST: /* disable DTE interrupt and write data */ |
12a55f2d MD |
319 | iic_wr(pd, ICIC, ICIC_WAITE | ICIC_ALE | ICIC_TACKE); |
320 | iic_wr(pd, ICDR, data); | |
da672773 | 321 | break; |
4eb00c9f | 322 | case OP_TX: /* write data */ |
12a55f2d | 323 | iic_wr(pd, ICDR, data); |
da672773 | 324 | break; |
4eb00c9f | 325 | case OP_TX_STOP: /* write data and issue a stop afterwards */ |
12a55f2d | 326 | iic_wr(pd, ICDR, data); |
a78f6a41 WS |
327 | iic_wr(pd, ICCR, pd->send_stop ? ICCR_ICE | ICCR_TRS |
328 | : ICCR_ICE | ICCR_TRS | ICCR_BBSY); | |
4eb00c9f MD |
329 | break; |
330 | case OP_TX_TO_RX: /* select read mode */ | |
a78f6a41 | 331 | iic_wr(pd, ICCR, ICCR_ICE | ICCR_SCP); |
da672773 | 332 | break; |
4eb00c9f | 333 | case OP_RX: /* just read data */ |
12a55f2d | 334 | ret = iic_rd(pd, ICDR); |
da672773 | 335 | break; |
4eb00c9f | 336 | case OP_RX_STOP: /* enable DTE interrupt, issue stop */ |
12a55f2d MD |
337 | iic_wr(pd, ICIC, |
338 | ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE); | |
a78f6a41 | 339 | iic_wr(pd, ICCR, ICCR_ICE | ICCR_RACK); |
4eb00c9f MD |
340 | break; |
341 | case OP_RX_STOP_DATA: /* enable DTE interrupt, read data, issue stop */ | |
12a55f2d MD |
342 | iic_wr(pd, ICIC, |
343 | ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE); | |
344 | ret = iic_rd(pd, ICDR); | |
a78f6a41 | 345 | iic_wr(pd, ICCR, ICCR_ICE | ICCR_RACK); |
da672773 MD |
346 | break; |
347 | } | |
348 | ||
349 | spin_unlock_irqrestore(&pd->lock, flags); | |
350 | ||
351 | dev_dbg(pd->dev, "op %d, data out 0x%02x\n", op, ret); | |
352 | return ret; | |
353 | } | |
354 | ||
05cf9368 | 355 | static bool sh_mobile_i2c_is_first_byte(struct sh_mobile_i2c_data *pd) |
4eb00c9f | 356 | { |
05cf9368 | 357 | return pd->pos == -1; |
4eb00c9f MD |
358 | } |
359 | ||
05cf9368 | 360 | static bool sh_mobile_i2c_is_last_byte(struct sh_mobile_i2c_data *pd) |
4eb00c9f | 361 | { |
05cf9368 | 362 | return pd->pos == pd->msg->len - 1; |
4eb00c9f MD |
363 | } |
364 | ||
365 | static void sh_mobile_i2c_get_data(struct sh_mobile_i2c_data *pd, | |
366 | unsigned char *buf) | |
367 | { | |
368 | switch (pd->pos) { | |
369 | case -1: | |
370 | *buf = (pd->msg->addr & 0x7f) << 1; | |
371 | *buf |= (pd->msg->flags & I2C_M_RD) ? 1 : 0; | |
372 | break; | |
373 | default: | |
374 | *buf = pd->msg->buf[pd->pos]; | |
375 | } | |
376 | } | |
377 | ||
378 | static int sh_mobile_i2c_isr_tx(struct sh_mobile_i2c_data *pd) | |
379 | { | |
380 | unsigned char data; | |
381 | ||
382 | if (pd->pos == pd->msg->len) | |
383 | return 1; | |
384 | ||
385 | sh_mobile_i2c_get_data(pd, &data); | |
386 | ||
387 | if (sh_mobile_i2c_is_last_byte(pd)) | |
388 | i2c_op(pd, OP_TX_STOP, data); | |
389 | else if (sh_mobile_i2c_is_first_byte(pd)) | |
390 | i2c_op(pd, OP_TX_FIRST, data); | |
391 | else | |
392 | i2c_op(pd, OP_TX, data); | |
393 | ||
394 | pd->pos++; | |
395 | return 0; | |
396 | } | |
397 | ||
398 | static int sh_mobile_i2c_isr_rx(struct sh_mobile_i2c_data *pd) | |
399 | { | |
400 | unsigned char data; | |
401 | int real_pos; | |
402 | ||
403 | do { | |
404 | if (pd->pos <= -1) { | |
405 | sh_mobile_i2c_get_data(pd, &data); | |
406 | ||
407 | if (sh_mobile_i2c_is_first_byte(pd)) | |
408 | i2c_op(pd, OP_TX_FIRST, data); | |
409 | else | |
410 | i2c_op(pd, OP_TX, data); | |
411 | break; | |
412 | } | |
413 | ||
414 | if (pd->pos == 0) { | |
415 | i2c_op(pd, OP_TX_TO_RX, 0); | |
416 | break; | |
417 | } | |
418 | ||
419 | real_pos = pd->pos - 2; | |
420 | ||
421 | if (pd->pos == pd->msg->len) { | |
422 | if (real_pos < 0) { | |
423 | i2c_op(pd, OP_RX_STOP, 0); | |
424 | break; | |
425 | } | |
426 | data = i2c_op(pd, OP_RX_STOP_DATA, 0); | |
427 | } else | |
428 | data = i2c_op(pd, OP_RX, 0); | |
429 | ||
bff4056c MD |
430 | if (real_pos >= 0) |
431 | pd->msg->buf[real_pos] = data; | |
4eb00c9f MD |
432 | } while (0); |
433 | ||
434 | pd->pos++; | |
435 | return pd->pos == (pd->msg->len + 2); | |
436 | } | |
437 | ||
da672773 MD |
438 | static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id) |
439 | { | |
440 | struct platform_device *dev = dev_id; | |
441 | struct sh_mobile_i2c_data *pd = platform_get_drvdata(dev); | |
4eb00c9f MD |
442 | unsigned char sr; |
443 | int wakeup; | |
da672773 | 444 | |
12a55f2d | 445 | sr = iic_rd(pd, ICSR); |
4eb00c9f | 446 | pd->sr |= sr; /* remember state */ |
da672773 MD |
447 | |
448 | dev_dbg(pd->dev, "i2c_isr 0x%02x 0x%02x %s %d %d!\n", sr, pd->sr, | |
4eb00c9f MD |
449 | (pd->msg->flags & I2C_M_RD) ? "read" : "write", |
450 | pd->pos, pd->msg->len); | |
da672773 MD |
451 | |
452 | if (sr & (ICSR_AL | ICSR_TACK)) { | |
4eb00c9f | 453 | /* don't interrupt transaction - continue to issue stop */ |
12a55f2d | 454 | iic_wr(pd, ICSR, sr & ~(ICSR_AL | ICSR_TACK)); |
4eb00c9f MD |
455 | wakeup = 0; |
456 | } else if (pd->msg->flags & I2C_M_RD) | |
457 | wakeup = sh_mobile_i2c_isr_rx(pd); | |
458 | else | |
459 | wakeup = sh_mobile_i2c_isr_tx(pd); | |
da672773 | 460 | |
4eb00c9f | 461 | if (sr & ICSR_WAIT) /* TODO: add delay here to support slow acks */ |
12a55f2d | 462 | iic_wr(pd, ICSR, sr & ~ICSR_WAIT); |
da672773 | 463 | |
da672773 MD |
464 | if (wakeup) { |
465 | pd->sr |= SW_DONE; | |
466 | wake_up(&pd->wait); | |
467 | } | |
468 | ||
29fb08c3 SK |
469 | /* defeat write posting to avoid spurious WAIT interrupts */ |
470 | iic_rd(pd, ICSR); | |
471 | ||
da672773 MD |
472 | return IRQ_HANDLED; |
473 | } | |
474 | ||
e7890297 GL |
475 | static int start_ch(struct sh_mobile_i2c_data *pd, struct i2c_msg *usr_msg, |
476 | bool do_init) | |
da672773 | 477 | { |
4eb00c9f MD |
478 | if (usr_msg->len == 0 && (usr_msg->flags & I2C_M_RD)) { |
479 | dev_err(pd->dev, "Unsupported zero length i2c read\n"); | |
5a72b25e | 480 | return -EOPNOTSUPP; |
4eb00c9f MD |
481 | } |
482 | ||
e7890297 GL |
483 | if (do_init) { |
484 | /* Initialize channel registers */ | |
485 | iic_set_clr(pd, ICCR, 0, ICCR_ICE); | |
da672773 | 486 | |
e7890297 GL |
487 | /* Enable channel and configure rx ack */ |
488 | iic_set_clr(pd, ICCR, ICCR_ICE, 0); | |
da672773 | 489 | |
e7890297 GL |
490 | /* Set the clock */ |
491 | iic_wr(pd, ICCL, pd->iccl & 0xff); | |
492 | iic_wr(pd, ICCH, pd->icch & 0xff); | |
493 | } | |
da672773 MD |
494 | |
495 | pd->msg = usr_msg; | |
496 | pd->pos = -1; | |
497 | pd->sr = 0; | |
498 | ||
4eb00c9f | 499 | /* Enable all interrupts to begin with */ |
12a55f2d | 500 | iic_wr(pd, ICIC, ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE); |
da672773 MD |
501 | return 0; |
502 | } | |
503 | ||
e7890297 GL |
504 | static int poll_dte(struct sh_mobile_i2c_data *pd) |
505 | { | |
506 | int i; | |
507 | ||
508 | for (i = 1000; i; i--) { | |
509 | u_int8_t val = iic_rd(pd, ICSR); | |
510 | ||
511 | if (val & ICSR_DTE) | |
512 | break; | |
513 | ||
514 | if (val & ICSR_TACK) | |
5a72b25e | 515 | return -ENXIO; |
e7890297 GL |
516 | |
517 | udelay(10); | |
518 | } | |
519 | ||
5a72b25e | 520 | return i ? 0 : -ETIMEDOUT; |
e7890297 GL |
521 | } |
522 | ||
4b382318 GL |
523 | static int poll_busy(struct sh_mobile_i2c_data *pd) |
524 | { | |
525 | int i; | |
526 | ||
527 | for (i = 1000; i; i--) { | |
528 | u_int8_t val = iic_rd(pd, ICSR); | |
529 | ||
530 | dev_dbg(pd->dev, "val 0x%02x pd->sr 0x%02x\n", val, pd->sr); | |
531 | ||
532 | /* the interrupt handler may wake us up before the | |
533 | * transfer is finished, so poll the hardware | |
534 | * until we're done. | |
535 | */ | |
536 | if (!(val & ICSR_BUSY)) { | |
537 | /* handle missing acknowledge and arbitration lost */ | |
5a72b25e WS |
538 | val |= pd->sr; |
539 | if (val & ICSR_TACK) | |
540 | return -ENXIO; | |
541 | if (val & ICSR_AL) | |
542 | return -EAGAIN; | |
4b382318 GL |
543 | break; |
544 | } | |
545 | ||
546 | udelay(10); | |
547 | } | |
548 | ||
5a72b25e | 549 | return i ? 0 : -ETIMEDOUT; |
4b382318 GL |
550 | } |
551 | ||
da672773 MD |
552 | static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter, |
553 | struct i2c_msg *msgs, | |
554 | int num) | |
555 | { | |
556 | struct sh_mobile_i2c_data *pd = i2c_get_adapdata(adapter); | |
557 | struct i2c_msg *msg; | |
558 | int err = 0; | |
4b382318 | 559 | int i, k; |
da672773 MD |
560 | |
561 | activate_ch(pd); | |
562 | ||
563 | /* Process all messages */ | |
564 | for (i = 0; i < num; i++) { | |
e7890297 | 565 | bool do_start = pd->send_stop || !i; |
da672773 | 566 | msg = &msgs[i]; |
e7890297 | 567 | pd->send_stop = i == num - 1 || msg->flags & I2C_M_STOP; |
da672773 | 568 | |
e7890297 | 569 | err = start_ch(pd, msg, do_start); |
da672773 MD |
570 | if (err) |
571 | break; | |
572 | ||
e7890297 GL |
573 | if (do_start) |
574 | i2c_op(pd, OP_START, 0); | |
da672773 MD |
575 | |
576 | /* The interrupt handler takes care of the rest... */ | |
577 | k = wait_event_timeout(pd->wait, | |
578 | pd->sr & (ICSR_TACK | SW_DONE), | |
579 | 5 * HZ); | |
5687265b | 580 | if (!k) { |
da672773 | 581 | dev_err(pd->dev, "Transfer request timed out\n"); |
5687265b GL |
582 | err = -ETIMEDOUT; |
583 | break; | |
584 | } | |
da672773 | 585 | |
e7890297 GL |
586 | if (pd->send_stop) |
587 | err = poll_busy(pd); | |
588 | else | |
589 | err = poll_dte(pd); | |
4b382318 | 590 | if (err < 0) |
da672773 | 591 | break; |
da672773 MD |
592 | } |
593 | ||
594 | deactivate_ch(pd); | |
595 | ||
596 | if (!err) | |
597 | err = num; | |
598 | return err; | |
599 | } | |
600 | ||
601 | static u32 sh_mobile_i2c_func(struct i2c_adapter *adapter) | |
602 | { | |
e7890297 | 603 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING; |
da672773 MD |
604 | } |
605 | ||
606 | static struct i2c_algorithm sh_mobile_i2c_algorithm = { | |
607 | .functionality = sh_mobile_i2c_func, | |
608 | .master_xfer = sh_mobile_i2c_xfer, | |
609 | }; | |
610 | ||
7fe8a999 | 611 | static int sh_mobile_i2c_hook_irqs(struct platform_device *dev) |
da672773 MD |
612 | { |
613 | struct resource *res; | |
7fe8a999 WS |
614 | resource_size_t n; |
615 | int k = 0, ret; | |
da672773 MD |
616 | |
617 | while ((res = platform_get_resource(dev, IORESOURCE_IRQ, k))) { | |
7fe8a999 WS |
618 | for (n = res->start; n <= res->end; n++) { |
619 | ret = devm_request_irq(&dev->dev, n, sh_mobile_i2c_isr, | |
620 | 0, dev_name(&dev->dev), dev); | |
621 | if (ret) { | |
622 | dev_err(&dev->dev, "cannot request IRQ %pa\n", &n); | |
623 | return ret; | |
82b20d8b | 624 | } |
da672773 MD |
625 | } |
626 | k++; | |
627 | } | |
628 | ||
7fe8a999 | 629 | return k > 0 ? 0 : -ENOENT; |
da672773 MD |
630 | } |
631 | ||
632 | static int sh_mobile_i2c_probe(struct platform_device *dev) | |
633 | { | |
6d4028c6 | 634 | struct i2c_sh_mobile_platform_data *pdata = dev_get_platdata(&dev->dev); |
da672773 MD |
635 | struct sh_mobile_i2c_data *pd; |
636 | struct i2c_adapter *adap; | |
637 | struct resource *res; | |
da672773 | 638 | int ret; |
88c289ec | 639 | u32 bus_speed; |
da672773 | 640 | |
4fd31c2e WS |
641 | pd = devm_kzalloc(&dev->dev, sizeof(struct sh_mobile_i2c_data), GFP_KERNEL); |
642 | if (!pd) | |
da672773 | 643 | return -ENOMEM; |
da672773 | 644 | |
4fd31c2e | 645 | pd->clk = devm_clk_get(&dev->dev, NULL); |
da672773 | 646 | if (IS_ERR(pd->clk)) { |
1082d5d2 | 647 | dev_err(&dev->dev, "cannot get clock\n"); |
4fd31c2e | 648 | return PTR_ERR(pd->clk); |
da672773 MD |
649 | } |
650 | ||
7fe8a999 WS |
651 | ret = sh_mobile_i2c_hook_irqs(dev); |
652 | if (ret) | |
4fd31c2e | 653 | return ret; |
da672773 MD |
654 | |
655 | pd->dev = &dev->dev; | |
656 | platform_set_drvdata(dev, pd); | |
657 | ||
658 | res = platform_get_resource(dev, IORESOURCE_MEM, 0); | |
da672773 | 659 | |
4fd31c2e | 660 | pd->reg = devm_ioremap_resource(&dev->dev, res); |
7fe8a999 WS |
661 | if (IS_ERR(pd->reg)) |
662 | return PTR_ERR(pd->reg); | |
da672773 | 663 | |
23a61291 | 664 | /* Use platform data bus speed or STANDARD_MODE */ |
88c289ec WS |
665 | ret = of_property_read_u32(dev->dev.of_node, "clock-frequency", &bus_speed); |
666 | pd->bus_speed = ret ? STANDARD_MODE : bus_speed; | |
667 | ||
81f81153 MD |
668 | if (pdata && pdata->bus_speed) |
669 | pd->bus_speed = pdata->bus_speed; | |
ebd5ac16 SK |
670 | pd->clks_per_count = 1; |
671 | if (pdata && pdata->clks_per_count) | |
672 | pd->clks_per_count = pdata->clks_per_count; | |
81f81153 | 673 | |
962b6032 MD |
674 | /* The IIC blocks on SH-Mobile ARM processors |
675 | * come with two new bits in ICIC. | |
676 | */ | |
4fd31c2e | 677 | if (resource_size(res) > 0x17) |
962b6032 MD |
678 | pd->flags |= IIC_FLAG_HAS_ICIC67; |
679 | ||
7b0e6292 SK |
680 | sh_mobile_i2c_init(pd); |
681 | ||
f1a3b994 MD |
682 | /* Enable Runtime PM for this device. |
683 | * | |
684 | * Also tell the Runtime PM core to ignore children | |
685 | * for this device since it is valid for us to suspend | |
686 | * this I2C master driver even though the slave devices | |
687 | * on the I2C bus may not be suspended. | |
688 | * | |
689 | * The state of the I2C hardware bus is unaffected by | |
690 | * the Runtime PM state. | |
691 | */ | |
692 | pm_suspend_ignore_children(&dev->dev, true); | |
693 | pm_runtime_enable(&dev->dev); | |
694 | ||
da672773 MD |
695 | /* setup the private data */ |
696 | adap = &pd->adap; | |
697 | i2c_set_adapdata(adap, pd); | |
698 | ||
699 | adap->owner = THIS_MODULE; | |
700 | adap->algo = &sh_mobile_i2c_algorithm; | |
701 | adap->dev.parent = &dev->dev; | |
702 | adap->retries = 5; | |
703 | adap->nr = dev->id; | |
ad337074 | 704 | adap->dev.of_node = dev->dev.of_node; |
da672773 MD |
705 | |
706 | strlcpy(adap->name, dev->name, sizeof(adap->name)); | |
707 | ||
a5616bd0 MD |
708 | spin_lock_init(&pd->lock); |
709 | init_waitqueue_head(&pd->wait); | |
da672773 MD |
710 | |
711 | ret = i2c_add_numbered_adapter(adap); | |
712 | if (ret < 0) { | |
713 | dev_err(&dev->dev, "cannot add numbered adapter\n"); | |
7fe8a999 | 714 | return ret; |
da672773 MD |
715 | } |
716 | ||
23a61291 SK |
717 | dev_info(&dev->dev, |
718 | "I2C adapter %d with bus speed %lu Hz (L/H=%x/%x)\n", | |
719 | adap->nr, pd->bus_speed, pd->iccl, pd->icch); | |
ad337074 | 720 | |
da672773 | 721 | return 0; |
da672773 MD |
722 | } |
723 | ||
724 | static int sh_mobile_i2c_remove(struct platform_device *dev) | |
725 | { | |
726 | struct sh_mobile_i2c_data *pd = platform_get_drvdata(dev); | |
727 | ||
728 | i2c_del_adapter(&pd->adap); | |
f1a3b994 | 729 | pm_runtime_disable(&dev->dev); |
da672773 MD |
730 | return 0; |
731 | } | |
732 | ||
f1a3b994 MD |
733 | static int sh_mobile_i2c_runtime_nop(struct device *dev) |
734 | { | |
735 | /* Runtime PM callback shared between ->runtime_suspend() | |
736 | * and ->runtime_resume(). Simply returns success. | |
737 | * | |
738 | * This driver re-initializes all registers after | |
739 | * pm_runtime_get_sync() anyway so there is no need | |
740 | * to save and restore registers here. | |
741 | */ | |
742 | return 0; | |
743 | } | |
744 | ||
47145210 | 745 | static const struct dev_pm_ops sh_mobile_i2c_dev_pm_ops = { |
f1a3b994 MD |
746 | .runtime_suspend = sh_mobile_i2c_runtime_nop, |
747 | .runtime_resume = sh_mobile_i2c_runtime_nop, | |
748 | }; | |
749 | ||
0b255e92 | 750 | static const struct of_device_id sh_mobile_i2c_dt_ids[] = { |
ad337074 MD |
751 | { .compatible = "renesas,rmobile-iic", }, |
752 | {}, | |
753 | }; | |
754 | MODULE_DEVICE_TABLE(of, sh_mobile_i2c_dt_ids); | |
755 | ||
da672773 MD |
756 | static struct platform_driver sh_mobile_i2c_driver = { |
757 | .driver = { | |
758 | .name = "i2c-sh_mobile", | |
759 | .owner = THIS_MODULE, | |
f1a3b994 | 760 | .pm = &sh_mobile_i2c_dev_pm_ops, |
ad337074 | 761 | .of_match_table = sh_mobile_i2c_dt_ids, |
da672773 MD |
762 | }, |
763 | .probe = sh_mobile_i2c_probe, | |
764 | .remove = sh_mobile_i2c_remove, | |
765 | }; | |
766 | ||
767 | static int __init sh_mobile_i2c_adap_init(void) | |
768 | { | |
769 | return platform_driver_register(&sh_mobile_i2c_driver); | |
770 | } | |
771 | ||
772 | static void __exit sh_mobile_i2c_adap_exit(void) | |
773 | { | |
774 | platform_driver_unregister(&sh_mobile_i2c_driver); | |
775 | } | |
776 | ||
ccb3bc16 | 777 | subsys_initcall(sh_mobile_i2c_adap_init); |
da672773 MD |
778 | module_exit(sh_mobile_i2c_adap_exit); |
779 | ||
780 | MODULE_DESCRIPTION("SuperH Mobile I2C Bus Controller driver"); | |
781 | MODULE_AUTHOR("Magnus Damm"); | |
782 | MODULE_LICENSE("GPL v2"); | |
7ef0c12a | 783 | MODULE_ALIAS("platform:i2c-sh_mobile"); |