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db811ca0 CC |
1 | /* |
2 | * drivers/i2c/busses/i2c-tegra.c | |
3 | * | |
4 | * Copyright (C) 2010 Google, Inc. | |
5 | * Author: Colin Cross <ccross@android.com> | |
6 | * | |
7 | * This software is licensed under the terms of the GNU General Public | |
8 | * License version 2, as published by the Free Software Foundation, and | |
9 | * may be copied, distributed, and modified under those terms. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | */ | |
17 | ||
18 | #include <linux/kernel.h> | |
19 | #include <linux/init.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/clk.h> | |
22 | #include <linux/err.h> | |
23 | #include <linux/i2c.h> | |
24 | #include <linux/io.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/slab.h> | |
6ad068ed | 28 | #include <linux/of_device.h> |
93cf5d75 | 29 | #include <linux/module.h> |
dda9d6a8 | 30 | #include <linux/reset.h> |
db811ca0 CC |
31 | |
32 | #include <asm/unaligned.h> | |
33 | ||
db811ca0 CC |
34 | #define TEGRA_I2C_TIMEOUT (msecs_to_jiffies(1000)) |
35 | #define BYTES_PER_FIFO_WORD 4 | |
36 | ||
37 | #define I2C_CNFG 0x000 | |
40abcf77 | 38 | #define I2C_CNFG_DEBOUNCE_CNT_SHIFT 12 |
db811ca0 CC |
39 | #define I2C_CNFG_PACKET_MODE_EN (1<<10) |
40 | #define I2C_CNFG_NEW_MASTER_FSM (1<<11) | |
cb63c62d | 41 | #define I2C_STATUS 0x01C |
db811ca0 | 42 | #define I2C_SL_CNFG 0x020 |
5afa9d35 | 43 | #define I2C_SL_CNFG_NACK (1<<1) |
db811ca0 CC |
44 | #define I2C_SL_CNFG_NEWSL (1<<2) |
45 | #define I2C_SL_ADDR1 0x02c | |
5afa9d35 | 46 | #define I2C_SL_ADDR2 0x030 |
db811ca0 CC |
47 | #define I2C_TX_FIFO 0x050 |
48 | #define I2C_RX_FIFO 0x054 | |
49 | #define I2C_PACKET_TRANSFER_STATUS 0x058 | |
50 | #define I2C_FIFO_CONTROL 0x05c | |
51 | #define I2C_FIFO_CONTROL_TX_FLUSH (1<<1) | |
52 | #define I2C_FIFO_CONTROL_RX_FLUSH (1<<0) | |
53 | #define I2C_FIFO_CONTROL_TX_TRIG_SHIFT 5 | |
54 | #define I2C_FIFO_CONTROL_RX_TRIG_SHIFT 2 | |
55 | #define I2C_FIFO_STATUS 0x060 | |
56 | #define I2C_FIFO_STATUS_TX_MASK 0xF0 | |
57 | #define I2C_FIFO_STATUS_TX_SHIFT 4 | |
58 | #define I2C_FIFO_STATUS_RX_MASK 0x0F | |
59 | #define I2C_FIFO_STATUS_RX_SHIFT 0 | |
60 | #define I2C_INT_MASK 0x064 | |
61 | #define I2C_INT_STATUS 0x068 | |
62 | #define I2C_INT_PACKET_XFER_COMPLETE (1<<7) | |
63 | #define I2C_INT_ALL_PACKETS_XFER_COMPLETE (1<<6) | |
64 | #define I2C_INT_TX_FIFO_OVERFLOW (1<<5) | |
65 | #define I2C_INT_RX_FIFO_UNDERFLOW (1<<4) | |
66 | #define I2C_INT_NO_ACK (1<<3) | |
67 | #define I2C_INT_ARBITRATION_LOST (1<<2) | |
68 | #define I2C_INT_TX_FIFO_DATA_REQ (1<<1) | |
69 | #define I2C_INT_RX_FIFO_DATA_REQ (1<<0) | |
70 | #define I2C_CLK_DIVISOR 0x06c | |
2a2897ba LD |
71 | #define I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT 16 |
72 | #define I2C_CLK_MULTIPLIER_STD_FAST_MODE 8 | |
db811ca0 CC |
73 | |
74 | #define DVC_CTRL_REG1 0x000 | |
75 | #define DVC_CTRL_REG1_INTR_EN (1<<10) | |
76 | #define DVC_CTRL_REG2 0x004 | |
77 | #define DVC_CTRL_REG3 0x008 | |
78 | #define DVC_CTRL_REG3_SW_PROG (1<<26) | |
79 | #define DVC_CTRL_REG3_I2C_DONE_INTR_EN (1<<30) | |
80 | #define DVC_STATUS 0x00c | |
81 | #define DVC_STATUS_I2C_DONE_INTR (1<<30) | |
82 | ||
83 | #define I2C_ERR_NONE 0x00 | |
84 | #define I2C_ERR_NO_ACK 0x01 | |
85 | #define I2C_ERR_ARBITRATION_LOST 0x02 | |
cb63c62d | 86 | #define I2C_ERR_UNKNOWN_INTERRUPT 0x04 |
db811ca0 CC |
87 | |
88 | #define PACKET_HEADER0_HEADER_SIZE_SHIFT 28 | |
89 | #define PACKET_HEADER0_PACKET_ID_SHIFT 16 | |
90 | #define PACKET_HEADER0_CONT_ID_SHIFT 12 | |
91 | #define PACKET_HEADER0_PROTOCOL_I2C (1<<4) | |
92 | ||
93 | #define I2C_HEADER_HIGHSPEED_MODE (1<<22) | |
94 | #define I2C_HEADER_CONT_ON_NAK (1<<21) | |
95 | #define I2C_HEADER_SEND_START_BYTE (1<<20) | |
96 | #define I2C_HEADER_READ (1<<19) | |
97 | #define I2C_HEADER_10BIT_ADDR (1<<18) | |
98 | #define I2C_HEADER_IE_ENABLE (1<<17) | |
99 | #define I2C_HEADER_REPEAT_START (1<<16) | |
c8f5af2f | 100 | #define I2C_HEADER_CONTINUE_XFER (1<<15) |
db811ca0 CC |
101 | #define I2C_HEADER_MASTER_ADDR_SHIFT 12 |
102 | #define I2C_HEADER_SLAVE_ADDR_SHIFT 1 | |
c8f5af2f LD |
103 | /* |
104 | * msg_end_type: The bus control which need to be send at end of transfer. | |
105 | * @MSG_END_STOP: Send stop pulse at end of transfer. | |
106 | * @MSG_END_REPEAT_START: Send repeat start at end of transfer. | |
107 | * @MSG_END_CONTINUE: The following on message is coming and so do not send | |
108 | * stop or repeat start. | |
109 | */ | |
110 | enum msg_end_type { | |
111 | MSG_END_STOP, | |
112 | MSG_END_REPEAT_START, | |
113 | MSG_END_CONTINUE, | |
114 | }; | |
db811ca0 | 115 | |
6ad068ed LD |
116 | /** |
117 | * struct tegra_i2c_hw_feature : Different HW support on Tegra | |
118 | * @has_continue_xfer_support: Continue transfer supports. | |
2a2897ba LD |
119 | * @has_per_pkt_xfer_complete_irq: Has enable/disable capability for transfer |
120 | * complete interrupt per packet basis. | |
121 | * @has_single_clk_source: The i2c controller has single clock source. Tegra30 | |
122 | * and earlier Socs has two clock sources i.e. div-clk and | |
123 | * fast-clk. | |
124 | * @clk_divisor_hs_mode: Clock divisor in HS mode. | |
125 | * @clk_divisor_std_fast_mode: Clock divisor in standard/fast mode. It is | |
126 | * applicable if there is no fast clock source i.e. single clock | |
127 | * source. | |
6ad068ed LD |
128 | */ |
129 | ||
130 | struct tegra_i2c_hw_feature { | |
131 | bool has_continue_xfer_support; | |
2a2897ba LD |
132 | bool has_per_pkt_xfer_complete_irq; |
133 | bool has_single_clk_source; | |
134 | int clk_divisor_hs_mode; | |
135 | int clk_divisor_std_fast_mode; | |
6ad068ed LD |
136 | }; |
137 | ||
db811ca0 CC |
138 | /** |
139 | * struct tegra_i2c_dev - per device i2c context | |
140 | * @dev: device reference for power management | |
6ad068ed | 141 | * @hw: Tegra i2c hw feature. |
db811ca0 | 142 | * @adapter: core i2c layer adapter information |
14e92bd4 LD |
143 | * @div_clk: clock reference for div clock of i2c controller. |
144 | * @fast_clk: clock reference for fast clock of i2c controller. | |
db811ca0 CC |
145 | * @base: ioremapped registers cookie |
146 | * @cont_id: i2c controller id, used for for packet header | |
147 | * @irq: irq number of transfer complete interrupt | |
148 | * @is_dvc: identifies the DVC i2c controller, has a different register layout | |
149 | * @msg_complete: transfer completion notifier | |
150 | * @msg_err: error code for completed message | |
151 | * @msg_buf: pointer to current message data | |
152 | * @msg_buf_remaining: size of unsent data in the message buffer | |
153 | * @msg_read: identifies read transfers | |
154 | * @bus_clk_rate: current i2c bus clock rate | |
155 | * @is_suspended: prevents i2c controller accesses after suspend is called | |
156 | */ | |
157 | struct tegra_i2c_dev { | |
158 | struct device *dev; | |
6ad068ed | 159 | const struct tegra_i2c_hw_feature *hw; |
db811ca0 | 160 | struct i2c_adapter adapter; |
14e92bd4 LD |
161 | struct clk *div_clk; |
162 | struct clk *fast_clk; | |
dda9d6a8 | 163 | struct reset_control *rst; |
db811ca0 CC |
164 | void __iomem *base; |
165 | int cont_id; | |
166 | int irq; | |
cb63c62d | 167 | bool irq_disabled; |
db811ca0 CC |
168 | int is_dvc; |
169 | struct completion msg_complete; | |
170 | int msg_err; | |
171 | u8 *msg_buf; | |
172 | size_t msg_buf_remaining; | |
173 | int msg_read; | |
49a64ac5 | 174 | u32 bus_clk_rate; |
db811ca0 CC |
175 | bool is_suspended; |
176 | }; | |
177 | ||
178 | static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned long reg) | |
179 | { | |
180 | writel(val, i2c_dev->base + reg); | |
181 | } | |
182 | ||
183 | static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg) | |
184 | { | |
185 | return readl(i2c_dev->base + reg); | |
186 | } | |
187 | ||
188 | /* | |
189 | * i2c_writel and i2c_readl will offset the register if necessary to talk | |
190 | * to the I2C block inside the DVC block | |
191 | */ | |
192 | static unsigned long tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev, | |
193 | unsigned long reg) | |
194 | { | |
195 | if (i2c_dev->is_dvc) | |
196 | reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40; | |
197 | return reg; | |
198 | } | |
199 | ||
200 | static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val, | |
201 | unsigned long reg) | |
202 | { | |
203 | writel(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); | |
ec7aaca2 LD |
204 | |
205 | /* Read back register to make sure that register writes completed */ | |
206 | if (reg != I2C_TX_FIFO) | |
207 | readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); | |
db811ca0 CC |
208 | } |
209 | ||
210 | static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg) | |
211 | { | |
212 | return readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); | |
213 | } | |
214 | ||
215 | static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data, | |
216 | unsigned long reg, int len) | |
217 | { | |
218 | writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); | |
219 | } | |
220 | ||
221 | static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data, | |
222 | unsigned long reg, int len) | |
223 | { | |
224 | readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); | |
225 | } | |
226 | ||
227 | static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask) | |
228 | { | |
229 | u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK); | |
230 | int_mask &= ~mask; | |
231 | i2c_writel(i2c_dev, int_mask, I2C_INT_MASK); | |
232 | } | |
233 | ||
234 | static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask) | |
235 | { | |
236 | u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK); | |
237 | int_mask |= mask; | |
238 | i2c_writel(i2c_dev, int_mask, I2C_INT_MASK); | |
239 | } | |
240 | ||
241 | static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev) | |
242 | { | |
243 | unsigned long timeout = jiffies + HZ; | |
244 | u32 val = i2c_readl(i2c_dev, I2C_FIFO_CONTROL); | |
245 | val |= I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH; | |
246 | i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL); | |
247 | ||
248 | while (i2c_readl(i2c_dev, I2C_FIFO_CONTROL) & | |
249 | (I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH)) { | |
250 | if (time_after(jiffies, timeout)) { | |
251 | dev_warn(i2c_dev->dev, "timeout waiting for fifo flush\n"); | |
252 | return -ETIMEDOUT; | |
253 | } | |
254 | msleep(1); | |
255 | } | |
256 | return 0; | |
257 | } | |
258 | ||
259 | static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev) | |
260 | { | |
261 | u32 val; | |
262 | int rx_fifo_avail; | |
263 | u8 *buf = i2c_dev->msg_buf; | |
264 | size_t buf_remaining = i2c_dev->msg_buf_remaining; | |
265 | int words_to_transfer; | |
266 | ||
267 | val = i2c_readl(i2c_dev, I2C_FIFO_STATUS); | |
268 | rx_fifo_avail = (val & I2C_FIFO_STATUS_RX_MASK) >> | |
269 | I2C_FIFO_STATUS_RX_SHIFT; | |
270 | ||
271 | /* Rounds down to not include partial word at the end of buf */ | |
272 | words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD; | |
273 | if (words_to_transfer > rx_fifo_avail) | |
274 | words_to_transfer = rx_fifo_avail; | |
275 | ||
276 | i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer); | |
277 | ||
278 | buf += words_to_transfer * BYTES_PER_FIFO_WORD; | |
279 | buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD; | |
280 | rx_fifo_avail -= words_to_transfer; | |
281 | ||
282 | /* | |
283 | * If there is a partial word at the end of buf, handle it manually to | |
284 | * prevent overwriting past the end of buf | |
285 | */ | |
286 | if (rx_fifo_avail > 0 && buf_remaining > 0) { | |
287 | BUG_ON(buf_remaining > 3); | |
288 | val = i2c_readl(i2c_dev, I2C_RX_FIFO); | |
8c340f60 | 289 | val = cpu_to_le32(val); |
db811ca0 CC |
290 | memcpy(buf, &val, buf_remaining); |
291 | buf_remaining = 0; | |
292 | rx_fifo_avail--; | |
293 | } | |
294 | ||
295 | BUG_ON(rx_fifo_avail > 0 && buf_remaining > 0); | |
296 | i2c_dev->msg_buf_remaining = buf_remaining; | |
297 | i2c_dev->msg_buf = buf; | |
298 | return 0; | |
299 | } | |
300 | ||
301 | static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev) | |
302 | { | |
303 | u32 val; | |
304 | int tx_fifo_avail; | |
305 | u8 *buf = i2c_dev->msg_buf; | |
306 | size_t buf_remaining = i2c_dev->msg_buf_remaining; | |
307 | int words_to_transfer; | |
308 | ||
309 | val = i2c_readl(i2c_dev, I2C_FIFO_STATUS); | |
310 | tx_fifo_avail = (val & I2C_FIFO_STATUS_TX_MASK) >> | |
311 | I2C_FIFO_STATUS_TX_SHIFT; | |
312 | ||
313 | /* Rounds down to not include partial word at the end of buf */ | |
314 | words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD; | |
db811ca0 | 315 | |
96219c3a DA |
316 | /* It's very common to have < 4 bytes, so optimize that case. */ |
317 | if (words_to_transfer) { | |
318 | if (words_to_transfer > tx_fifo_avail) | |
319 | words_to_transfer = tx_fifo_avail; | |
320 | ||
321 | /* | |
322 | * Update state before writing to FIFO. If this casues us | |
323 | * to finish writing all bytes (AKA buf_remaining goes to 0) we | |
324 | * have a potential for an interrupt (PACKET_XFER_COMPLETE is | |
325 | * not maskable). We need to make sure that the isr sees | |
326 | * buf_remaining as 0 and doesn't call us back re-entrantly. | |
327 | */ | |
328 | buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD; | |
329 | tx_fifo_avail -= words_to_transfer; | |
330 | i2c_dev->msg_buf_remaining = buf_remaining; | |
331 | i2c_dev->msg_buf = buf + | |
332 | words_to_transfer * BYTES_PER_FIFO_WORD; | |
333 | barrier(); | |
334 | ||
335 | i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer); | |
336 | ||
337 | buf += words_to_transfer * BYTES_PER_FIFO_WORD; | |
338 | } | |
db811ca0 CC |
339 | |
340 | /* | |
341 | * If there is a partial word at the end of buf, handle it manually to | |
342 | * prevent reading past the end of buf, which could cross a page | |
343 | * boundary and fault. | |
344 | */ | |
345 | if (tx_fifo_avail > 0 && buf_remaining > 0) { | |
346 | BUG_ON(buf_remaining > 3); | |
347 | memcpy(&val, buf, buf_remaining); | |
8c340f60 | 348 | val = le32_to_cpu(val); |
96219c3a DA |
349 | |
350 | /* Again update before writing to FIFO to make sure isr sees. */ | |
351 | i2c_dev->msg_buf_remaining = 0; | |
352 | i2c_dev->msg_buf = NULL; | |
353 | barrier(); | |
354 | ||
db811ca0 | 355 | i2c_writel(i2c_dev, val, I2C_TX_FIFO); |
db811ca0 CC |
356 | } |
357 | ||
db811ca0 CC |
358 | return 0; |
359 | } | |
360 | ||
361 | /* | |
362 | * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller) | |
363 | * block. This block is identical to the rest of the I2C blocks, except that | |
364 | * it only supports master mode, it has registers moved around, and it needs | |
365 | * some extra init to get it into I2C mode. The register moves are handled | |
366 | * by i2c_readl and i2c_writel | |
367 | */ | |
368 | static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev) | |
369 | { | |
370 | u32 val = 0; | |
371 | val = dvc_readl(i2c_dev, DVC_CTRL_REG3); | |
372 | val |= DVC_CTRL_REG3_SW_PROG; | |
373 | val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN; | |
374 | dvc_writel(i2c_dev, val, DVC_CTRL_REG3); | |
375 | ||
376 | val = dvc_readl(i2c_dev, DVC_CTRL_REG1); | |
377 | val |= DVC_CTRL_REG1_INTR_EN; | |
378 | dvc_writel(i2c_dev, val, DVC_CTRL_REG1); | |
379 | } | |
380 | ||
fd301cc4 LD |
381 | static inline int tegra_i2c_clock_enable(struct tegra_i2c_dev *i2c_dev) |
382 | { | |
383 | int ret; | |
2a2897ba | 384 | if (!i2c_dev->hw->has_single_clk_source) { |
c9a9ef41 | 385 | ret = clk_enable(i2c_dev->fast_clk); |
2a2897ba LD |
386 | if (ret < 0) { |
387 | dev_err(i2c_dev->dev, | |
388 | "Enabling fast clk failed, err %d\n", ret); | |
389 | return ret; | |
390 | } | |
fd301cc4 | 391 | } |
c9a9ef41 | 392 | ret = clk_enable(i2c_dev->div_clk); |
fd301cc4 LD |
393 | if (ret < 0) { |
394 | dev_err(i2c_dev->dev, | |
395 | "Enabling div clk failed, err %d\n", ret); | |
c9a9ef41 | 396 | clk_disable(i2c_dev->fast_clk); |
fd301cc4 LD |
397 | } |
398 | return ret; | |
399 | } | |
400 | ||
401 | static inline void tegra_i2c_clock_disable(struct tegra_i2c_dev *i2c_dev) | |
402 | { | |
c9a9ef41 | 403 | clk_disable(i2c_dev->div_clk); |
2a2897ba | 404 | if (!i2c_dev->hw->has_single_clk_source) |
c9a9ef41 | 405 | clk_disable(i2c_dev->fast_clk); |
fd301cc4 LD |
406 | } |
407 | ||
db811ca0 CC |
408 | static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev) |
409 | { | |
410 | u32 val; | |
411 | int err = 0; | |
2a2897ba | 412 | u32 clk_divisor; |
db811ca0 | 413 | |
132c803f LD |
414 | err = tegra_i2c_clock_enable(i2c_dev); |
415 | if (err < 0) { | |
416 | dev_err(i2c_dev->dev, "Clock enable failed %d\n", err); | |
417 | return err; | |
418 | } | |
db811ca0 | 419 | |
dda9d6a8 | 420 | reset_control_assert(i2c_dev->rst); |
db811ca0 | 421 | udelay(2); |
dda9d6a8 | 422 | reset_control_deassert(i2c_dev->rst); |
db811ca0 CC |
423 | |
424 | if (i2c_dev->is_dvc) | |
425 | tegra_dvc_init(i2c_dev); | |
426 | ||
40abcf77 JC |
427 | val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN | |
428 | (0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT); | |
db811ca0 CC |
429 | i2c_writel(i2c_dev, val, I2C_CNFG); |
430 | i2c_writel(i2c_dev, 0, I2C_INT_MASK); | |
2a2897ba | 431 | |
2a2897ba LD |
432 | /* Make sure clock divisor programmed correctly */ |
433 | clk_divisor = i2c_dev->hw->clk_divisor_hs_mode; | |
434 | clk_divisor |= i2c_dev->hw->clk_divisor_std_fast_mode << | |
435 | I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT; | |
436 | i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR); | |
db811ca0 | 437 | |
65a1a0ac KW |
438 | if (!i2c_dev->is_dvc) { |
439 | u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG); | |
5afa9d35 SW |
440 | sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL; |
441 | i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG); | |
442 | i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1); | |
443 | i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2); | |
444 | ||
65a1a0ac KW |
445 | } |
446 | ||
db811ca0 CC |
447 | val = 7 << I2C_FIFO_CONTROL_TX_TRIG_SHIFT | |
448 | 0 << I2C_FIFO_CONTROL_RX_TRIG_SHIFT; | |
449 | i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL); | |
450 | ||
451 | if (tegra_i2c_flush_fifos(i2c_dev)) | |
452 | err = -ETIMEDOUT; | |
453 | ||
fd301cc4 | 454 | tegra_i2c_clock_disable(i2c_dev); |
cb63c62d TP |
455 | |
456 | if (i2c_dev->irq_disabled) { | |
457 | i2c_dev->irq_disabled = 0; | |
458 | enable_irq(i2c_dev->irq); | |
459 | } | |
460 | ||
db811ca0 CC |
461 | return err; |
462 | } | |
463 | ||
464 | static irqreturn_t tegra_i2c_isr(int irq, void *dev_id) | |
465 | { | |
466 | u32 status; | |
467 | const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST; | |
468 | struct tegra_i2c_dev *i2c_dev = dev_id; | |
469 | ||
470 | status = i2c_readl(i2c_dev, I2C_INT_STATUS); | |
471 | ||
472 | if (status == 0) { | |
cb63c62d TP |
473 | dev_warn(i2c_dev->dev, "irq status 0 %08x %08x %08x\n", |
474 | i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS), | |
475 | i2c_readl(i2c_dev, I2C_STATUS), | |
476 | i2c_readl(i2c_dev, I2C_CNFG)); | |
477 | i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT; | |
478 | ||
479 | if (!i2c_dev->irq_disabled) { | |
480 | disable_irq_nosync(i2c_dev->irq); | |
481 | i2c_dev->irq_disabled = 1; | |
482 | } | |
cb63c62d | 483 | goto err; |
db811ca0 CC |
484 | } |
485 | ||
486 | if (unlikely(status & status_err)) { | |
487 | if (status & I2C_INT_NO_ACK) | |
488 | i2c_dev->msg_err |= I2C_ERR_NO_ACK; | |
489 | if (status & I2C_INT_ARBITRATION_LOST) | |
490 | i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST; | |
db811ca0 CC |
491 | goto err; |
492 | } | |
493 | ||
494 | if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) { | |
495 | if (i2c_dev->msg_buf_remaining) | |
496 | tegra_i2c_empty_rx_fifo(i2c_dev); | |
497 | else | |
498 | BUG(); | |
499 | } | |
500 | ||
501 | if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) { | |
502 | if (i2c_dev->msg_buf_remaining) | |
503 | tegra_i2c_fill_tx_fifo(i2c_dev); | |
504 | else | |
505 | tegra_i2c_mask_irq(i2c_dev, I2C_INT_TX_FIFO_DATA_REQ); | |
506 | } | |
507 | ||
c889e91d LD |
508 | i2c_writel(i2c_dev, status, I2C_INT_STATUS); |
509 | if (i2c_dev->is_dvc) | |
510 | dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS); | |
511 | ||
96219c3a DA |
512 | if (status & I2C_INT_PACKET_XFER_COMPLETE) { |
513 | BUG_ON(i2c_dev->msg_buf_remaining); | |
db811ca0 | 514 | complete(&i2c_dev->msg_complete); |
96219c3a | 515 | } |
db811ca0 CC |
516 | return IRQ_HANDLED; |
517 | err: | |
25985edc | 518 | /* An error occurred, mask all interrupts */ |
db811ca0 CC |
519 | tegra_i2c_mask_irq(i2c_dev, I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST | |
520 | I2C_INT_PACKET_XFER_COMPLETE | I2C_INT_TX_FIFO_DATA_REQ | | |
521 | I2C_INT_RX_FIFO_DATA_REQ); | |
522 | i2c_writel(i2c_dev, status, I2C_INT_STATUS); | |
cb63c62d TP |
523 | if (i2c_dev->is_dvc) |
524 | dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS); | |
c889e91d LD |
525 | |
526 | complete(&i2c_dev->msg_complete); | |
db811ca0 CC |
527 | return IRQ_HANDLED; |
528 | } | |
529 | ||
530 | static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev, | |
c8f5af2f | 531 | struct i2c_msg *msg, enum msg_end_type end_state) |
db811ca0 CC |
532 | { |
533 | u32 packet_header; | |
534 | u32 int_mask; | |
6973a39c | 535 | unsigned long time_left; |
db811ca0 CC |
536 | |
537 | tegra_i2c_flush_fifos(i2c_dev); | |
db811ca0 CC |
538 | |
539 | if (msg->len == 0) | |
540 | return -EINVAL; | |
541 | ||
542 | i2c_dev->msg_buf = msg->buf; | |
543 | i2c_dev->msg_buf_remaining = msg->len; | |
544 | i2c_dev->msg_err = I2C_ERR_NONE; | |
545 | i2c_dev->msg_read = (msg->flags & I2C_M_RD); | |
16735d02 | 546 | reinit_completion(&i2c_dev->msg_complete); |
db811ca0 CC |
547 | |
548 | packet_header = (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) | | |
549 | PACKET_HEADER0_PROTOCOL_I2C | | |
550 | (i2c_dev->cont_id << PACKET_HEADER0_CONT_ID_SHIFT) | | |
551 | (1 << PACKET_HEADER0_PACKET_ID_SHIFT); | |
552 | i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); | |
553 | ||
554 | packet_header = msg->len - 1; | |
555 | i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); | |
556 | ||
353f56b5 | 557 | packet_header = I2C_HEADER_IE_ENABLE; |
c8f5af2f LD |
558 | if (end_state == MSG_END_CONTINUE) |
559 | packet_header |= I2C_HEADER_CONTINUE_XFER; | |
560 | else if (end_state == MSG_END_REPEAT_START) | |
2078cf3b | 561 | packet_header |= I2C_HEADER_REPEAT_START; |
353f56b5 LD |
562 | if (msg->flags & I2C_M_TEN) { |
563 | packet_header |= msg->addr; | |
db811ca0 | 564 | packet_header |= I2C_HEADER_10BIT_ADDR; |
353f56b5 LD |
565 | } else { |
566 | packet_header |= msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT; | |
567 | } | |
db811ca0 CC |
568 | if (msg->flags & I2C_M_IGNORE_NAK) |
569 | packet_header |= I2C_HEADER_CONT_ON_NAK; | |
db811ca0 CC |
570 | if (msg->flags & I2C_M_RD) |
571 | packet_header |= I2C_HEADER_READ; | |
572 | i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); | |
573 | ||
574 | if (!(msg->flags & I2C_M_RD)) | |
575 | tegra_i2c_fill_tx_fifo(i2c_dev); | |
576 | ||
577 | int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST; | |
2a2897ba LD |
578 | if (i2c_dev->hw->has_per_pkt_xfer_complete_irq) |
579 | int_mask |= I2C_INT_PACKET_XFER_COMPLETE; | |
db811ca0 CC |
580 | if (msg->flags & I2C_M_RD) |
581 | int_mask |= I2C_INT_RX_FIFO_DATA_REQ; | |
582 | else if (i2c_dev->msg_buf_remaining) | |
583 | int_mask |= I2C_INT_TX_FIFO_DATA_REQ; | |
584 | tegra_i2c_unmask_irq(i2c_dev, int_mask); | |
585 | dev_dbg(i2c_dev->dev, "unmasked irq: %02x\n", | |
586 | i2c_readl(i2c_dev, I2C_INT_MASK)); | |
587 | ||
6973a39c NMG |
588 | time_left = wait_for_completion_timeout(&i2c_dev->msg_complete, |
589 | TEGRA_I2C_TIMEOUT); | |
db811ca0 CC |
590 | tegra_i2c_mask_irq(i2c_dev, int_mask); |
591 | ||
6973a39c | 592 | if (time_left == 0) { |
db811ca0 CC |
593 | dev_err(i2c_dev->dev, "i2c transfer timed out\n"); |
594 | ||
595 | tegra_i2c_init(i2c_dev); | |
596 | return -ETIMEDOUT; | |
597 | } | |
598 | ||
6973a39c NMG |
599 | dev_dbg(i2c_dev->dev, "transfer complete: %lu %d %d\n", |
600 | time_left, completion_done(&i2c_dev->msg_complete), | |
601 | i2c_dev->msg_err); | |
db811ca0 CC |
602 | |
603 | if (likely(i2c_dev->msg_err == I2C_ERR_NONE)) | |
604 | return 0; | |
605 | ||
f70893d0 AC |
606 | /* |
607 | * NACK interrupt is generated before the I2C controller generates the | |
608 | * STOP condition on the bus. So wait for 2 clock periods before resetting | |
609 | * the controller so that STOP condition has been delivered properly. | |
610 | */ | |
611 | if (i2c_dev->msg_err == I2C_ERR_NO_ACK) | |
612 | udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->bus_clk_rate)); | |
613 | ||
db811ca0 CC |
614 | tegra_i2c_init(i2c_dev); |
615 | if (i2c_dev->msg_err == I2C_ERR_NO_ACK) { | |
616 | if (msg->flags & I2C_M_IGNORE_NAK) | |
617 | return 0; | |
618 | return -EREMOTEIO; | |
619 | } | |
620 | ||
621 | return -EIO; | |
622 | } | |
623 | ||
624 | static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], | |
625 | int num) | |
626 | { | |
627 | struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap); | |
628 | int i; | |
629 | int ret = 0; | |
630 | ||
631 | if (i2c_dev->is_suspended) | |
632 | return -EBUSY; | |
633 | ||
132c803f LD |
634 | ret = tegra_i2c_clock_enable(i2c_dev); |
635 | if (ret < 0) { | |
636 | dev_err(i2c_dev->dev, "Clock enable failed %d\n", ret); | |
637 | return ret; | |
638 | } | |
639 | ||
db811ca0 | 640 | for (i = 0; i < num; i++) { |
c8f5af2f LD |
641 | enum msg_end_type end_type = MSG_END_STOP; |
642 | if (i < (num - 1)) { | |
643 | if (msgs[i + 1].flags & I2C_M_NOSTART) | |
644 | end_type = MSG_END_CONTINUE; | |
645 | else | |
646 | end_type = MSG_END_REPEAT_START; | |
647 | } | |
648 | ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], end_type); | |
db811ca0 CC |
649 | if (ret) |
650 | break; | |
651 | } | |
fd301cc4 | 652 | tegra_i2c_clock_disable(i2c_dev); |
db811ca0 CC |
653 | return ret ?: i; |
654 | } | |
655 | ||
656 | static u32 tegra_i2c_func(struct i2c_adapter *adap) | |
657 | { | |
6ad068ed LD |
658 | struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap); |
659 | u32 ret = I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR | | |
660 | I2C_FUNC_PROTOCOL_MANGLING; | |
661 | ||
662 | if (i2c_dev->hw->has_continue_xfer_support) | |
663 | ret |= I2C_FUNC_NOSTART; | |
664 | return ret; | |
db811ca0 CC |
665 | } |
666 | ||
667 | static const struct i2c_algorithm tegra_i2c_algo = { | |
668 | .master_xfer = tegra_i2c_xfer, | |
669 | .functionality = tegra_i2c_func, | |
670 | }; | |
671 | ||
6ad068ed LD |
672 | static const struct tegra_i2c_hw_feature tegra20_i2c_hw = { |
673 | .has_continue_xfer_support = false, | |
2a2897ba LD |
674 | .has_per_pkt_xfer_complete_irq = false, |
675 | .has_single_clk_source = false, | |
676 | .clk_divisor_hs_mode = 3, | |
677 | .clk_divisor_std_fast_mode = 0, | |
6ad068ed LD |
678 | }; |
679 | ||
680 | static const struct tegra_i2c_hw_feature tegra30_i2c_hw = { | |
681 | .has_continue_xfer_support = true, | |
2a2897ba LD |
682 | .has_per_pkt_xfer_complete_irq = false, |
683 | .has_single_clk_source = false, | |
684 | .clk_divisor_hs_mode = 3, | |
685 | .clk_divisor_std_fast_mode = 0, | |
686 | }; | |
687 | ||
688 | static const struct tegra_i2c_hw_feature tegra114_i2c_hw = { | |
689 | .has_continue_xfer_support = true, | |
690 | .has_per_pkt_xfer_complete_irq = true, | |
691 | .has_single_clk_source = true, | |
692 | .clk_divisor_hs_mode = 1, | |
693 | .clk_divisor_std_fast_mode = 0x19, | |
6ad068ed LD |
694 | }; |
695 | ||
6ad068ed | 696 | /* Match table for of_platform binding */ |
0b255e92 | 697 | static const struct of_device_id tegra_i2c_of_match[] = { |
2a2897ba | 698 | { .compatible = "nvidia,tegra114-i2c", .data = &tegra114_i2c_hw, }, |
6ad068ed LD |
699 | { .compatible = "nvidia,tegra30-i2c", .data = &tegra30_i2c_hw, }, |
700 | { .compatible = "nvidia,tegra20-i2c", .data = &tegra20_i2c_hw, }, | |
701 | { .compatible = "nvidia,tegra20-i2c-dvc", .data = &tegra20_i2c_hw, }, | |
702 | {}, | |
703 | }; | |
704 | MODULE_DEVICE_TABLE(of, tegra_i2c_of_match); | |
6ad068ed | 705 | |
0b255e92 | 706 | static int tegra_i2c_probe(struct platform_device *pdev) |
db811ca0 CC |
707 | { |
708 | struct tegra_i2c_dev *i2c_dev; | |
db811ca0 | 709 | struct resource *res; |
14e92bd4 LD |
710 | struct clk *div_clk; |
711 | struct clk *fast_clk; | |
f533c61e | 712 | void __iomem *base; |
db811ca0 CC |
713 | int irq; |
714 | int ret = 0; | |
c9a9ef41 | 715 | int clk_multiplier = I2C_CLK_MULTIPLIER_STD_FAST_MODE; |
db811ca0 CC |
716 | |
717 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
84dbf809 TR |
718 | base = devm_ioremap_resource(&pdev->dev, res); |
719 | if (IS_ERR(base)) | |
720 | return PTR_ERR(base); | |
db811ca0 CC |
721 | |
722 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
723 | if (!res) { | |
724 | dev_err(&pdev->dev, "no irq resource\n"); | |
9cbb6b2b | 725 | return -EINVAL; |
db811ca0 CC |
726 | } |
727 | irq = res->start; | |
728 | ||
14e92bd4 LD |
729 | div_clk = devm_clk_get(&pdev->dev, "div-clk"); |
730 | if (IS_ERR(div_clk)) { | |
db811ca0 | 731 | dev_err(&pdev->dev, "missing controller clock"); |
14e92bd4 | 732 | return PTR_ERR(div_clk); |
db811ca0 CC |
733 | } |
734 | ||
9cbb6b2b | 735 | i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL); |
46797a2a | 736 | if (!i2c_dev) |
9cbb6b2b | 737 | return -ENOMEM; |
db811ca0 CC |
738 | |
739 | i2c_dev->base = base; | |
14e92bd4 | 740 | i2c_dev->div_clk = div_clk; |
db811ca0 CC |
741 | i2c_dev->adapter.algo = &tegra_i2c_algo; |
742 | i2c_dev->irq = irq; | |
743 | i2c_dev->cont_id = pdev->id; | |
744 | i2c_dev->dev = &pdev->dev; | |
5c470f39 | 745 | |
dda9d6a8 SW |
746 | i2c_dev->rst = devm_reset_control_get(&pdev->dev, "i2c"); |
747 | if (IS_ERR(i2c_dev->rst)) { | |
748 | dev_err(&pdev->dev, "missing controller reset"); | |
749 | return PTR_ERR(i2c_dev->rst); | |
750 | } | |
751 | ||
49a64ac5 SW |
752 | ret = of_property_read_u32(i2c_dev->dev->of_node, "clock-frequency", |
753 | &i2c_dev->bus_clk_rate); | |
754 | if (ret) | |
755 | i2c_dev->bus_clk_rate = 100000; /* default clock rate */ | |
db811ca0 | 756 | |
6ad068ed LD |
757 | i2c_dev->hw = &tegra20_i2c_hw; |
758 | ||
759 | if (pdev->dev.of_node) { | |
760 | const struct of_device_id *match; | |
49a64ac5 | 761 | match = of_match_device(tegra_i2c_of_match, &pdev->dev); |
6ad068ed | 762 | i2c_dev->hw = match->data; |
68fb6695 SW |
763 | i2c_dev->is_dvc = of_device_is_compatible(pdev->dev.of_node, |
764 | "nvidia,tegra20-i2c-dvc"); | |
6ad068ed | 765 | } else if (pdev->id == 3) { |
db811ca0 | 766 | i2c_dev->is_dvc = 1; |
6ad068ed | 767 | } |
db811ca0 CC |
768 | init_completion(&i2c_dev->msg_complete); |
769 | ||
2a2897ba LD |
770 | if (!i2c_dev->hw->has_single_clk_source) { |
771 | fast_clk = devm_clk_get(&pdev->dev, "fast-clk"); | |
772 | if (IS_ERR(fast_clk)) { | |
773 | dev_err(&pdev->dev, "missing fast clock"); | |
774 | return PTR_ERR(fast_clk); | |
775 | } | |
776 | i2c_dev->fast_clk = fast_clk; | |
777 | } | |
778 | ||
db811ca0 CC |
779 | platform_set_drvdata(pdev, i2c_dev); |
780 | ||
c9a9ef41 MP |
781 | if (!i2c_dev->hw->has_single_clk_source) { |
782 | ret = clk_prepare(i2c_dev->fast_clk); | |
783 | if (ret < 0) { | |
784 | dev_err(i2c_dev->dev, "Clock prepare failed %d\n", ret); | |
785 | return ret; | |
786 | } | |
787 | } | |
788 | ||
789 | clk_multiplier *= (i2c_dev->hw->clk_divisor_std_fast_mode + 1); | |
790 | ret = clk_set_rate(i2c_dev->div_clk, | |
791 | i2c_dev->bus_clk_rate * clk_multiplier); | |
792 | if (ret) { | |
793 | dev_err(i2c_dev->dev, "Clock rate change failed %d\n", ret); | |
794 | goto unprepare_fast_clk; | |
795 | } | |
796 | ||
797 | ret = clk_prepare(i2c_dev->div_clk); | |
798 | if (ret < 0) { | |
799 | dev_err(i2c_dev->dev, "Clock prepare failed %d\n", ret); | |
800 | goto unprepare_fast_clk; | |
801 | } | |
802 | ||
db811ca0 CC |
803 | ret = tegra_i2c_init(i2c_dev); |
804 | if (ret) { | |
805 | dev_err(&pdev->dev, "Failed to initialize i2c controller"); | |
c9a9ef41 | 806 | goto unprepare_div_clk; |
db811ca0 CC |
807 | } |
808 | ||
9cbb6b2b | 809 | ret = devm_request_irq(&pdev->dev, i2c_dev->irq, |
91b370a0 | 810 | tegra_i2c_isr, 0, dev_name(&pdev->dev), i2c_dev); |
db811ca0 CC |
811 | if (ret) { |
812 | dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq); | |
c9a9ef41 | 813 | goto unprepare_div_clk; |
db811ca0 CC |
814 | } |
815 | ||
db811ca0 CC |
816 | i2c_set_adapdata(&i2c_dev->adapter, i2c_dev); |
817 | i2c_dev->adapter.owner = THIS_MODULE; | |
6025189a | 818 | i2c_dev->adapter.class = I2C_CLASS_DEPRECATED; |
db811ca0 CC |
819 | strlcpy(i2c_dev->adapter.name, "Tegra I2C adapter", |
820 | sizeof(i2c_dev->adapter.name)); | |
821 | i2c_dev->adapter.algo = &tegra_i2c_algo; | |
822 | i2c_dev->adapter.dev.parent = &pdev->dev; | |
823 | i2c_dev->adapter.nr = pdev->id; | |
5c470f39 | 824 | i2c_dev->adapter.dev.of_node = pdev->dev.of_node; |
db811ca0 CC |
825 | |
826 | ret = i2c_add_numbered_adapter(&i2c_dev->adapter); | |
827 | if (ret) { | |
828 | dev_err(&pdev->dev, "Failed to add I2C adapter\n"); | |
c9a9ef41 | 829 | goto unprepare_div_clk; |
db811ca0 CC |
830 | } |
831 | ||
832 | return 0; | |
c9a9ef41 MP |
833 | |
834 | unprepare_div_clk: | |
835 | clk_unprepare(i2c_dev->div_clk); | |
836 | ||
837 | unprepare_fast_clk: | |
838 | if (!i2c_dev->hw->has_single_clk_source) | |
839 | clk_unprepare(i2c_dev->fast_clk); | |
840 | ||
841 | return ret; | |
db811ca0 CC |
842 | } |
843 | ||
0b255e92 | 844 | static int tegra_i2c_remove(struct platform_device *pdev) |
db811ca0 CC |
845 | { |
846 | struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev); | |
847 | i2c_del_adapter(&i2c_dev->adapter); | |
c9a9ef41 MP |
848 | |
849 | clk_unprepare(i2c_dev->div_clk); | |
850 | if (!i2c_dev->hw->has_single_clk_source) | |
851 | clk_unprepare(i2c_dev->fast_clk); | |
852 | ||
db811ca0 CC |
853 | return 0; |
854 | } | |
855 | ||
371e67c9 | 856 | #ifdef CONFIG_PM_SLEEP |
5db20c49 | 857 | static int tegra_i2c_suspend(struct device *dev) |
db811ca0 | 858 | { |
6a7b3c3c | 859 | struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev); |
db811ca0 CC |
860 | |
861 | i2c_lock_adapter(&i2c_dev->adapter); | |
862 | i2c_dev->is_suspended = true; | |
863 | i2c_unlock_adapter(&i2c_dev->adapter); | |
864 | ||
865 | return 0; | |
866 | } | |
867 | ||
5db20c49 | 868 | static int tegra_i2c_resume(struct device *dev) |
db811ca0 | 869 | { |
6a7b3c3c | 870 | struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev); |
db811ca0 CC |
871 | int ret; |
872 | ||
873 | i2c_lock_adapter(&i2c_dev->adapter); | |
874 | ||
875 | ret = tegra_i2c_init(i2c_dev); | |
876 | ||
877 | if (ret) { | |
878 | i2c_unlock_adapter(&i2c_dev->adapter); | |
879 | return ret; | |
880 | } | |
881 | ||
882 | i2c_dev->is_suspended = false; | |
883 | ||
884 | i2c_unlock_adapter(&i2c_dev->adapter); | |
885 | ||
886 | return 0; | |
887 | } | |
6a7b3c3c | 888 | |
5db20c49 | 889 | static SIMPLE_DEV_PM_OPS(tegra_i2c_pm, tegra_i2c_suspend, tegra_i2c_resume); |
6a7b3c3c RW |
890 | #define TEGRA_I2C_PM (&tegra_i2c_pm) |
891 | #else | |
892 | #define TEGRA_I2C_PM NULL | |
db811ca0 CC |
893 | #endif |
894 | ||
895 | static struct platform_driver tegra_i2c_driver = { | |
896 | .probe = tegra_i2c_probe, | |
0b255e92 | 897 | .remove = tegra_i2c_remove, |
db811ca0 CC |
898 | .driver = { |
899 | .name = "tegra-i2c", | |
49a64ac5 | 900 | .of_match_table = tegra_i2c_of_match, |
6a7b3c3c | 901 | .pm = TEGRA_I2C_PM, |
db811ca0 CC |
902 | }, |
903 | }; | |
904 | ||
905 | static int __init tegra_i2c_init_driver(void) | |
906 | { | |
907 | return platform_driver_register(&tegra_i2c_driver); | |
908 | } | |
909 | ||
910 | static void __exit tegra_i2c_exit_driver(void) | |
911 | { | |
912 | platform_driver_unregister(&tegra_i2c_driver); | |
913 | } | |
914 | ||
915 | subsys_initcall(tegra_i2c_init_driver); | |
916 | module_exit(tegra_i2c_exit_driver); | |
917 | ||
918 | MODULE_DESCRIPTION("nVidia Tegra2 I2C Bus Controller driver"); | |
919 | MODULE_AUTHOR("Colin Cross"); | |
920 | MODULE_LICENSE("GPL v2"); |