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1 | /* |
2 | * i2c-xiic.c | |
3 | * Copyright (c) 2002-2007 Xilinx Inc. | |
4 | * Copyright (c) 2009-2010 Intel Corporation | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
18 | * | |
19 | * | |
20 | * This code was implemented by Mocean Laboratories AB when porting linux | |
21 | * to the automotive development board Russellville. The copyright holder | |
22 | * as seen in the header is Intel corporation. | |
23 | * Mocean Laboratories forked off the GNU/Linux platform work into a | |
25985edc | 24 | * separate company called Pelagicore AB, which committed the code to the |
e1d5b659 RR |
25 | * kernel. |
26 | */ | |
27 | ||
28 | /* Supports: | |
29 | * Xilinx IIC | |
30 | */ | |
31 | #include <linux/kernel.h> | |
32 | #include <linux/module.h> | |
33 | #include <linux/init.h> | |
34 | #include <linux/errno.h> | |
02ca6c40 | 35 | #include <linux/delay.h> |
e1d5b659 RR |
36 | #include <linux/platform_device.h> |
37 | #include <linux/i2c.h> | |
38 | #include <linux/interrupt.h> | |
39 | #include <linux/wait.h> | |
40 | #include <linux/i2c-xiic.h> | |
41 | #include <linux/io.h> | |
5a0e3ad6 | 42 | #include <linux/slab.h> |
e1d5b659 RR |
43 | |
44 | #define DRIVER_NAME "xiic-i2c" | |
45 | ||
46 | enum xilinx_i2c_state { | |
47 | STATE_DONE, | |
48 | STATE_ERROR, | |
49 | STATE_START | |
50 | }; | |
51 | ||
52 | /** | |
53 | * struct xiic_i2c - Internal representation of the XIIC I2C bus | |
54 | * @base: Memory base of the HW registers | |
55 | * @wait: Wait queue for callers | |
56 | * @adap: Kernel adapter representation | |
57 | * @tx_msg: Messages from above to be sent | |
58 | * @lock: Mutual exclusion | |
59 | * @tx_pos: Current pos in TX message | |
60 | * @nmsgs: Number of messages in tx_msg | |
61 | * @state: See STATE_ | |
62 | * @rx_msg: Current RX message | |
63 | * @rx_pos: Position within current RX message | |
64 | */ | |
65 | struct xiic_i2c { | |
66 | void __iomem *base; | |
67 | wait_queue_head_t wait; | |
68 | struct i2c_adapter adap; | |
69 | struct i2c_msg *tx_msg; | |
70 | spinlock_t lock; | |
71 | unsigned int tx_pos; | |
72 | unsigned int nmsgs; | |
73 | enum xilinx_i2c_state state; | |
74 | struct i2c_msg *rx_msg; | |
75 | int rx_pos; | |
76 | }; | |
77 | ||
78 | ||
79 | #define XIIC_MSB_OFFSET 0 | |
80 | #define XIIC_REG_OFFSET (0x100+XIIC_MSB_OFFSET) | |
81 | ||
82 | /* | |
83 | * Register offsets in bytes from RegisterBase. Three is added to the | |
84 | * base offset to access LSB (IBM style) of the word | |
85 | */ | |
86 | #define XIIC_CR_REG_OFFSET (0x00+XIIC_REG_OFFSET) /* Control Register */ | |
87 | #define XIIC_SR_REG_OFFSET (0x04+XIIC_REG_OFFSET) /* Status Register */ | |
88 | #define XIIC_DTR_REG_OFFSET (0x08+XIIC_REG_OFFSET) /* Data Tx Register */ | |
89 | #define XIIC_DRR_REG_OFFSET (0x0C+XIIC_REG_OFFSET) /* Data Rx Register */ | |
90 | #define XIIC_ADR_REG_OFFSET (0x10+XIIC_REG_OFFSET) /* Address Register */ | |
91 | #define XIIC_TFO_REG_OFFSET (0x14+XIIC_REG_OFFSET) /* Tx FIFO Occupancy */ | |
92 | #define XIIC_RFO_REG_OFFSET (0x18+XIIC_REG_OFFSET) /* Rx FIFO Occupancy */ | |
93 | #define XIIC_TBA_REG_OFFSET (0x1C+XIIC_REG_OFFSET) /* 10 Bit Address reg */ | |
94 | #define XIIC_RFD_REG_OFFSET (0x20+XIIC_REG_OFFSET) /* Rx FIFO Depth reg */ | |
95 | #define XIIC_GPO_REG_OFFSET (0x24+XIIC_REG_OFFSET) /* Output Register */ | |
96 | ||
97 | /* Control Register masks */ | |
98 | #define XIIC_CR_ENABLE_DEVICE_MASK 0x01 /* Device enable = 1 */ | |
99 | #define XIIC_CR_TX_FIFO_RESET_MASK 0x02 /* Transmit FIFO reset=1 */ | |
100 | #define XIIC_CR_MSMS_MASK 0x04 /* Master starts Txing=1 */ | |
101 | #define XIIC_CR_DIR_IS_TX_MASK 0x08 /* Dir of tx. Txing=1 */ | |
102 | #define XIIC_CR_NO_ACK_MASK 0x10 /* Tx Ack. NO ack = 1 */ | |
103 | #define XIIC_CR_REPEATED_START_MASK 0x20 /* Repeated start = 1 */ | |
104 | #define XIIC_CR_GENERAL_CALL_MASK 0x40 /* Gen Call enabled = 1 */ | |
105 | ||
106 | /* Status Register masks */ | |
107 | #define XIIC_SR_GEN_CALL_MASK 0x01 /* 1=a mstr issued a GC */ | |
108 | #define XIIC_SR_ADDR_AS_SLAVE_MASK 0x02 /* 1=when addr as slave */ | |
109 | #define XIIC_SR_BUS_BUSY_MASK 0x04 /* 1 = bus is busy */ | |
110 | #define XIIC_SR_MSTR_RDING_SLAVE_MASK 0x08 /* 1=Dir: mstr <-- slave */ | |
111 | #define XIIC_SR_TX_FIFO_FULL_MASK 0x10 /* 1 = Tx FIFO full */ | |
112 | #define XIIC_SR_RX_FIFO_FULL_MASK 0x20 /* 1 = Rx FIFO full */ | |
113 | #define XIIC_SR_RX_FIFO_EMPTY_MASK 0x40 /* 1 = Rx FIFO empty */ | |
114 | #define XIIC_SR_TX_FIFO_EMPTY_MASK 0x80 /* 1 = Tx FIFO empty */ | |
115 | ||
116 | /* Interrupt Status Register masks Interrupt occurs when... */ | |
117 | #define XIIC_INTR_ARB_LOST_MASK 0x01 /* 1 = arbitration lost */ | |
118 | #define XIIC_INTR_TX_ERROR_MASK 0x02 /* 1=Tx error/msg complete */ | |
119 | #define XIIC_INTR_TX_EMPTY_MASK 0x04 /* 1 = Tx FIFO/reg empty */ | |
120 | #define XIIC_INTR_RX_FULL_MASK 0x08 /* 1=Rx FIFO/reg=OCY level */ | |
121 | #define XIIC_INTR_BNB_MASK 0x10 /* 1 = Bus not busy */ | |
122 | #define XIIC_INTR_AAS_MASK 0x20 /* 1 = when addr as slave */ | |
123 | #define XIIC_INTR_NAAS_MASK 0x40 /* 1 = not addr as slave */ | |
124 | #define XIIC_INTR_TX_HALF_MASK 0x80 /* 1 = TX FIFO half empty */ | |
125 | ||
126 | /* The following constants specify the depth of the FIFOs */ | |
127 | #define IIC_RX_FIFO_DEPTH 16 /* Rx fifo capacity */ | |
128 | #define IIC_TX_FIFO_DEPTH 16 /* Tx fifo capacity */ | |
129 | ||
130 | /* The following constants specify groups of interrupts that are typically | |
131 | * enabled or disables at the same time | |
132 | */ | |
133 | #define XIIC_TX_INTERRUPTS \ | |
134 | (XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK) | |
135 | ||
136 | #define XIIC_TX_RX_INTERRUPTS (XIIC_INTR_RX_FULL_MASK | XIIC_TX_INTERRUPTS) | |
137 | ||
138 | /* The following constants are used with the following macros to specify the | |
139 | * operation, a read or write operation. | |
140 | */ | |
141 | #define XIIC_READ_OPERATION 1 | |
142 | #define XIIC_WRITE_OPERATION 0 | |
143 | ||
144 | /* | |
145 | * Tx Fifo upper bit masks. | |
146 | */ | |
147 | #define XIIC_TX_DYN_START_MASK 0x0100 /* 1 = Set dynamic start */ | |
148 | #define XIIC_TX_DYN_STOP_MASK 0x0200 /* 1 = Set dynamic stop */ | |
149 | ||
150 | /* | |
151 | * The following constants define the register offsets for the Interrupt | |
152 | * registers. There are some holes in the memory map for reserved addresses | |
153 | * to allow other registers to be added and still match the memory map of the | |
154 | * interrupt controller registers | |
155 | */ | |
156 | #define XIIC_DGIER_OFFSET 0x1C /* Device Global Interrupt Enable Register */ | |
157 | #define XIIC_IISR_OFFSET 0x20 /* Interrupt Status Register */ | |
158 | #define XIIC_IIER_OFFSET 0x28 /* Interrupt Enable Register */ | |
159 | #define XIIC_RESETR_OFFSET 0x40 /* Reset Register */ | |
160 | ||
161 | #define XIIC_RESET_MASK 0xAUL | |
162 | ||
163 | /* | |
164 | * The following constant is used for the device global interrupt enable | |
165 | * register, to enable all interrupts for the device, this is the only bit | |
166 | * in the register | |
167 | */ | |
168 | #define XIIC_GINTR_ENABLE_MASK 0x80000000UL | |
169 | ||
170 | #define xiic_tx_space(i2c) ((i2c)->tx_msg->len - (i2c)->tx_pos) | |
171 | #define xiic_rx_space(i2c) ((i2c)->rx_msg->len - (i2c)->rx_pos) | |
172 | ||
173 | static void xiic_start_xfer(struct xiic_i2c *i2c); | |
174 | static void __xiic_start_xfer(struct xiic_i2c *i2c); | |
175 | ||
176 | static inline void xiic_setreg8(struct xiic_i2c *i2c, int reg, u8 value) | |
177 | { | |
178 | iowrite8(value, i2c->base + reg); | |
179 | } | |
180 | ||
181 | static inline u8 xiic_getreg8(struct xiic_i2c *i2c, int reg) | |
182 | { | |
183 | return ioread8(i2c->base + reg); | |
184 | } | |
185 | ||
186 | static inline void xiic_setreg16(struct xiic_i2c *i2c, int reg, u16 value) | |
187 | { | |
188 | iowrite16(value, i2c->base + reg); | |
189 | } | |
190 | ||
191 | static inline void xiic_setreg32(struct xiic_i2c *i2c, int reg, int value) | |
192 | { | |
193 | iowrite32(value, i2c->base + reg); | |
194 | } | |
195 | ||
196 | static inline int xiic_getreg32(struct xiic_i2c *i2c, int reg) | |
197 | { | |
198 | return ioread32(i2c->base + reg); | |
199 | } | |
200 | ||
201 | static inline void xiic_irq_dis(struct xiic_i2c *i2c, u32 mask) | |
202 | { | |
203 | u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); | |
204 | xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier & ~mask); | |
205 | } | |
206 | ||
207 | static inline void xiic_irq_en(struct xiic_i2c *i2c, u32 mask) | |
208 | { | |
209 | u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); | |
210 | xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier | mask); | |
211 | } | |
212 | ||
213 | static inline void xiic_irq_clr(struct xiic_i2c *i2c, u32 mask) | |
214 | { | |
215 | u32 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET); | |
216 | xiic_setreg32(i2c, XIIC_IISR_OFFSET, isr & mask); | |
217 | } | |
218 | ||
219 | static inline void xiic_irq_clr_en(struct xiic_i2c *i2c, u32 mask) | |
220 | { | |
221 | xiic_irq_clr(i2c, mask); | |
222 | xiic_irq_en(i2c, mask); | |
223 | } | |
224 | ||
225 | static void xiic_clear_rx_fifo(struct xiic_i2c *i2c) | |
226 | { | |
227 | u8 sr; | |
228 | for (sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET); | |
229 | !(sr & XIIC_SR_RX_FIFO_EMPTY_MASK); | |
230 | sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET)) | |
231 | xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET); | |
232 | } | |
233 | ||
234 | static void xiic_reinit(struct xiic_i2c *i2c) | |
235 | { | |
236 | xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK); | |
237 | ||
238 | /* Set receive Fifo depth to maximum (zero based). */ | |
239 | xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, IIC_RX_FIFO_DEPTH - 1); | |
240 | ||
241 | /* Reset Tx Fifo. */ | |
242 | xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK); | |
243 | ||
244 | /* Enable IIC Device, remove Tx Fifo reset & disable general call. */ | |
245 | xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_ENABLE_DEVICE_MASK); | |
246 | ||
247 | /* make sure RX fifo is empty */ | |
248 | xiic_clear_rx_fifo(i2c); | |
249 | ||
250 | /* Enable interrupts */ | |
251 | xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK); | |
252 | ||
253 | xiic_irq_clr_en(i2c, XIIC_INTR_AAS_MASK | XIIC_INTR_ARB_LOST_MASK); | |
254 | } | |
255 | ||
256 | static void xiic_deinit(struct xiic_i2c *i2c) | |
257 | { | |
258 | u8 cr; | |
259 | ||
260 | xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK); | |
261 | ||
262 | /* Disable IIC Device. */ | |
263 | cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); | |
264 | xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & ~XIIC_CR_ENABLE_DEVICE_MASK); | |
265 | } | |
266 | ||
267 | static void xiic_read_rx(struct xiic_i2c *i2c) | |
268 | { | |
269 | u8 bytes_in_fifo; | |
270 | int i; | |
271 | ||
272 | bytes_in_fifo = xiic_getreg8(i2c, XIIC_RFO_REG_OFFSET) + 1; | |
273 | ||
274 | dev_dbg(i2c->adap.dev.parent, "%s entry, bytes in fifo: %d, msg: %d" | |
275 | ", SR: 0x%x, CR: 0x%x\n", | |
276 | __func__, bytes_in_fifo, xiic_rx_space(i2c), | |
277 | xiic_getreg8(i2c, XIIC_SR_REG_OFFSET), | |
278 | xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); | |
279 | ||
280 | if (bytes_in_fifo > xiic_rx_space(i2c)) | |
281 | bytes_in_fifo = xiic_rx_space(i2c); | |
282 | ||
283 | for (i = 0; i < bytes_in_fifo; i++) | |
284 | i2c->rx_msg->buf[i2c->rx_pos++] = | |
285 | xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET); | |
286 | ||
287 | xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, | |
288 | (xiic_rx_space(i2c) > IIC_RX_FIFO_DEPTH) ? | |
289 | IIC_RX_FIFO_DEPTH - 1 : xiic_rx_space(i2c) - 1); | |
290 | } | |
291 | ||
292 | static int xiic_tx_fifo_space(struct xiic_i2c *i2c) | |
293 | { | |
294 | /* return the actual space left in the FIFO */ | |
295 | return IIC_TX_FIFO_DEPTH - xiic_getreg8(i2c, XIIC_TFO_REG_OFFSET) - 1; | |
296 | } | |
297 | ||
298 | static void xiic_fill_tx_fifo(struct xiic_i2c *i2c) | |
299 | { | |
300 | u8 fifo_space = xiic_tx_fifo_space(i2c); | |
301 | int len = xiic_tx_space(i2c); | |
302 | ||
303 | len = (len > fifo_space) ? fifo_space : len; | |
304 | ||
305 | dev_dbg(i2c->adap.dev.parent, "%s entry, len: %d, fifo space: %d\n", | |
306 | __func__, len, fifo_space); | |
307 | ||
308 | while (len--) { | |
309 | u16 data = i2c->tx_msg->buf[i2c->tx_pos++]; | |
310 | if ((xiic_tx_space(i2c) == 0) && (i2c->nmsgs == 1)) { | |
311 | /* last message in transfer -> STOP */ | |
312 | data |= XIIC_TX_DYN_STOP_MASK; | |
313 | dev_dbg(i2c->adap.dev.parent, "%s TX STOP\n", __func__); | |
314 | ||
315 | xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data); | |
316 | } else | |
317 | xiic_setreg8(i2c, XIIC_DTR_REG_OFFSET, data); | |
318 | } | |
319 | } | |
320 | ||
321 | static void xiic_wakeup(struct xiic_i2c *i2c, int code) | |
322 | { | |
323 | i2c->tx_msg = NULL; | |
324 | i2c->rx_msg = NULL; | |
325 | i2c->nmsgs = 0; | |
326 | i2c->state = code; | |
327 | wake_up(&i2c->wait); | |
328 | } | |
329 | ||
330 | static void xiic_process(struct xiic_i2c *i2c) | |
331 | { | |
332 | u32 pend, isr, ier; | |
333 | u32 clr = 0; | |
334 | ||
335 | /* Get the interrupt Status from the IPIF. There is no clearing of | |
336 | * interrupts in the IPIF. Interrupts must be cleared at the source. | |
337 | * To find which interrupts are pending; AND interrupts pending with | |
338 | * interrupts masked. | |
339 | */ | |
340 | isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET); | |
341 | ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); | |
342 | pend = isr & ier; | |
343 | ||
344 | dev_dbg(i2c->adap.dev.parent, "%s entry, IER: 0x%x, ISR: 0x%x, " | |
345 | "pend: 0x%x, SR: 0x%x, msg: %p, nmsgs: %d\n", | |
346 | __func__, ier, isr, pend, xiic_getreg8(i2c, XIIC_SR_REG_OFFSET), | |
347 | i2c->tx_msg, i2c->nmsgs); | |
348 | ||
349 | /* Do not processes a devices interrupts if the device has no | |
350 | * interrupts pending | |
351 | */ | |
352 | if (!pend) | |
353 | return; | |
354 | ||
355 | /* Service requesting interrupt */ | |
356 | if ((pend & XIIC_INTR_ARB_LOST_MASK) || | |
357 | ((pend & XIIC_INTR_TX_ERROR_MASK) && | |
358 | !(pend & XIIC_INTR_RX_FULL_MASK))) { | |
359 | /* bus arbritration lost, or... | |
360 | * Transmit error _OR_ RX completed | |
361 | * if this happens when RX_FULL is not set | |
362 | * this is probably a TX error | |
363 | */ | |
364 | ||
365 | dev_dbg(i2c->adap.dev.parent, "%s error\n", __func__); | |
366 | ||
367 | /* dynamic mode seem to suffer from problems if we just flushes | |
368 | * fifos and the next message is a TX with len 0 (only addr) | |
369 | * reset the IP instead of just flush fifos | |
370 | */ | |
371 | xiic_reinit(i2c); | |
372 | ||
373 | if (i2c->tx_msg) | |
374 | xiic_wakeup(i2c, STATE_ERROR); | |
375 | ||
376 | } else if (pend & XIIC_INTR_RX_FULL_MASK) { | |
377 | /* Receive register/FIFO is full */ | |
378 | ||
379 | clr = XIIC_INTR_RX_FULL_MASK; | |
380 | if (!i2c->rx_msg) { | |
381 | dev_dbg(i2c->adap.dev.parent, | |
382 | "%s unexpexted RX IRQ\n", __func__); | |
383 | xiic_clear_rx_fifo(i2c); | |
384 | goto out; | |
385 | } | |
386 | ||
387 | xiic_read_rx(i2c); | |
388 | if (xiic_rx_space(i2c) == 0) { | |
389 | /* this is the last part of the message */ | |
390 | i2c->rx_msg = NULL; | |
391 | ||
392 | /* also clear TX error if there (RX complete) */ | |
393 | clr |= (isr & XIIC_INTR_TX_ERROR_MASK); | |
394 | ||
395 | dev_dbg(i2c->adap.dev.parent, | |
396 | "%s end of message, nmsgs: %d\n", | |
397 | __func__, i2c->nmsgs); | |
398 | ||
399 | /* send next message if this wasn't the last, | |
400 | * otherwise the transfer will be finialise when | |
401 | * receiving the bus not busy interrupt | |
402 | */ | |
403 | if (i2c->nmsgs > 1) { | |
404 | i2c->nmsgs--; | |
405 | i2c->tx_msg++; | |
406 | dev_dbg(i2c->adap.dev.parent, | |
407 | "%s will start next...\n", __func__); | |
408 | ||
409 | __xiic_start_xfer(i2c); | |
410 | } | |
411 | } | |
412 | } else if (pend & XIIC_INTR_BNB_MASK) { | |
413 | /* IIC bus has transitioned to not busy */ | |
414 | clr = XIIC_INTR_BNB_MASK; | |
415 | ||
416 | /* The bus is not busy, disable BusNotBusy interrupt */ | |
417 | xiic_irq_dis(i2c, XIIC_INTR_BNB_MASK); | |
418 | ||
419 | if (!i2c->tx_msg) | |
420 | goto out; | |
421 | ||
422 | if ((i2c->nmsgs == 1) && !i2c->rx_msg && | |
423 | xiic_tx_space(i2c) == 0) | |
424 | xiic_wakeup(i2c, STATE_DONE); | |
425 | else | |
426 | xiic_wakeup(i2c, STATE_ERROR); | |
427 | ||
428 | } else if (pend & (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)) { |