[deliverable/linux.git] / drivers / i2c / busses / scx200_acb.c

/*
    Copyright (c) 2001,2002 Christer Weinigel <wingel@nano-system.com>

    National Semiconductor SCx200 ACCESS.bus support

    Based on i2c-keywest.c which is:
        Copyright (c) 2001 Benjamin Herrenschmidt <benh@kernel.crashing.org>
        Copyright (c) 2000 Philip Edelbrock <phil@stimpy.netroedge.com>

    This program is free software; you can redistribute it and/or
    modify it under the terms of the GNU General Public License as
    published by the Free Software Foundation; either version 2 of the
    License, or (at your option) any later version.

    This program is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
    General Public License for more details.

    You should have received a copy of the GNU General Public License
    along with this program; if not, write to the Free Software
    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/

#include <linux/module.h>
#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/i2c.h>
#include <linux/smp_lock.h>
#include <linux/pci.h>
#include <linux/delay.h>
#include <asm/io.h>

#include <linux/scx200.h>

#define NAME "scx200_acb"

MODULE_AUTHOR("Christer Weinigel <wingel@nano-system.com>");
MODULE_DESCRIPTION("NatSemi SCx200 ACCESS.bus Driver");
MODULE_LICENSE("GPL");

#define MAX_DEVICES 4
static int base[MAX_DEVICES] = { 0x820, 0x840 };
module_param_array(base, int, NULL, 0);
MODULE_PARM_DESC(base, "Base addresses for the ACCESS.bus controllers");

/* The hardware supports interrupt driven mode too, but I haven't
   implemented that. */
#define POLLED_MODE 1
#define POLL_TIMEOUT (HZ)

enum scx200_acb_state {
	state_idle,
	state_address,
	state_command,
	state_repeat_start,
	state_quick,
	state_read,
	state_write,
};

static const char *scx200_acb_state_name[] = {
	"idle",
	"address",
	"command",
	"repeat_start",
	"quick",
	"read",
	"write",
};

/* Physical interface */
struct scx200_acb_iface {
	struct scx200_acb_iface *next;
	struct i2c_adapter adapter;
	unsigned base;
	struct semaphore sem;

	/* State machine data */
	enum scx200_acb_state state;
	int result;
	u8 address_byte;
	u8 command;
	u8 *ptr;
	char needs_reset;
	unsigned len;
};

/* Register Definitions */
#define ACBSDA		(iface->base + 0)
#define ACBST		(iface->base + 1)
#define    ACBST_SDAST		0x40 /* SDA Status */
#define    ACBST_BER		0x20
#define    ACBST_NEGACK		0x10 /* Negative Acknowledge */
#define    ACBST_STASTR		0x08 /* Stall After Start */
#define    ACBST_MASTER		0x02
#define ACBCST		(iface->base + 2)
#define    ACBCST_BB		0x02
#define ACBCTL1		(iface->base + 3)
#define    ACBCTL1_STASTRE	0x80
#define    ACBCTL1_NMINTE	0x40
#define    ACBCTL1_ACK		0x10
#define    ACBCTL1_STOP		0x02
#define    ACBCTL1_START	0x01
#define ACBADDR		(iface->base + 4)
#define ACBCTL2		(iface->base + 5)
#define    ACBCTL2_ENABLE	0x01

/************************************************************************/

static void scx200_acb_machine(struct scx200_acb_iface *iface, u8 status)
{
	const char *errmsg;

	dev_dbg(&iface->adapter.dev, "state %s, status = 0x%02x\n",
		scx200_acb_state_name[iface->state], status);

	if (status & ACBST_BER) {
		errmsg = "bus error";
		goto error;
	}
	if (!(status & ACBST_MASTER)) {
		errmsg = "not master";
		goto error;
	}
	if (status & ACBST_NEGACK) {
		dev_dbg(&iface->adapter.dev, "negative ack in state %s\n",
			scx200_acb_state_name[iface->state]);

		iface->state = state_idle;
		iface->result = -ENXIO;

		outb(inb(ACBCTL1) | ACBCTL1_STOP, ACBCTL1);
		outb(ACBST_STASTR | ACBST_NEGACK, ACBST);
		return;
	}

	switch (iface->state) {
	case state_idle:
		dev_warn(&iface->adapter.dev, "interrupt in idle state\n");
		break;

	case state_address:
		/* Do a pointer write first */
		outb(iface->address_byte & ~1, ACBSDA);

		iface->state = state_command;
		break;

	case state_command:
		outb(iface->command, ACBSDA);

		if (iface->address_byte & 1)
			iface->state = state_repeat_start;
		else
			iface->state = state_write;
		break;

	case state_repeat_start:
		outb(inb(ACBCTL1) | ACBCTL1_START, ACBCTL1);
		/* fallthrough */

	case state_quick:
		if (iface->address_byte & 1) {
			if (iface->len == 1)
				outb(inb(ACBCTL1) | ACBCTL1_ACK, ACBCTL1);
			else
				outb(inb(ACBCTL1) & ~ACBCTL1_ACK, ACBCTL1);
			outb(iface->address_byte, ACBSDA);

			iface->state = state_read;
		} else {
			outb(iface->address_byte, ACBSDA);

			iface->state = state_write;
		}
		break;

	case state_read:
		/* Set ACK if receiving the last byte */
		if (iface->len == 1)
			outb(inb(ACBCTL1) | ACBCTL1_ACK, ACBCTL1);
		else
			outb(inb(ACBCTL1) & ~ACBCTL1_ACK, ACBCTL1);

		*iface->ptr++ = inb(ACBSDA);
		--iface->len;

		if (iface->len == 0) {
			iface->result = 0;
			iface->state = state_idle;
			outb(inb(ACBCTL1) | ACBCTL1_STOP, ACBCTL1);
		}

		break;

	case state_write:
		if (iface->len == 0) {
			iface->result = 0;
			iface->state = state_idle;
			outb(inb(ACBCTL1) | ACBCTL1_STOP, ACBCTL1);
			break;
		}

		outb(*iface->ptr++, ACBSDA);
		--iface->len;

		break;
	}

	return;

 error:
	dev_err(&iface->adapter.dev, "%s in state %s\n", errmsg,
		scx200_acb_state_name[iface->state]);

	iface->state = state_idle;
	iface->result = -EIO;
	iface->needs_reset = 1;
}

#ifdef POLLED_MODE
static void scx200_acb_poll(struct scx200_acb_iface *iface)
{
	u8 status;
	unsigned long timeout;

	timeout = jiffies + POLL_TIMEOUT;
	while (time_before(jiffies, timeout)) {
		status = inb(ACBST);
		if ((status & (ACBST_SDAST|ACBST_BER|ACBST_NEGACK)) != 0) {
			scx200_acb_machine(iface, status);
			return;
		}
		msleep(10);
	}

	dev_err(&iface->adapter.dev, "timeout in state %s\n",
		scx200_acb_state_name[iface->state]);

	iface->state = state_idle;
	iface->result = -EIO;
	iface->needs_reset = 1;
}
#endif /* POLLED_MODE */

static void scx200_acb_reset(struct scx200_acb_iface *iface)
{
	/* Disable the ACCESS.bus device and Configure the SCL
	   frequency: 16 clock cycles */
	outb(0x70, ACBCTL2);
	/* Polling mode */
	outb(0, ACBCTL1);
	/* Disable slave address */
	outb(0, ACBADDR);
	/* Enable the ACCESS.bus device */
	outb(inb(ACBCTL2) | ACBCTL2_ENABLE, ACBCTL2);
	/* Free STALL after START */
	outb(inb(ACBCTL1) & ~(ACBCTL1_STASTRE | ACBCTL1_NMINTE), ACBCTL1);
	/* Send a STOP */
	outb(inb(ACBCTL1) | ACBCTL1_STOP, ACBCTL1);
	/* Clear BER, NEGACK and STASTR bits */
	outb(ACBST_BER | ACBST_NEGACK | ACBST_STASTR, ACBST);
	/* Clear BB bit */
	outb(inb(ACBCST) | ACBCST_BB, ACBCST);
}

static s32 scx200_acb_smbus_xfer(struct i2c_adapter *adapter,
				 u16 address, unsigned short flags,
				 char rw, u8 command, int size,
				 union i2c_smbus_data *data)
{
	struct scx200_acb_iface *iface = i2c_get_adapdata(adapter);
	int len;
	u8 *buffer;
	u16 cur_word;
	int rc;

	switch (size) {
	case I2C_SMBUS_QUICK:
		len = 0;
		buffer = NULL;
		break;

	case I2C_SMBUS_BYTE:
		len = 1;
		buffer = rw ? &data->byte : &command;
		break;

	case I2C_SMBUS_BYTE_DATA:
		len = 1;
		buffer = &data->byte;
		break;

	case I2C_SMBUS_WORD_DATA:
		len = 2;
		cur_word = cpu_to_le16(data->word);
		buffer = (u8 *)&cur_word;
		break;

	case I2C_SMBUS_BLOCK_DATA:
		len = data->block[0];
		buffer = &data->block[1];
		break;

	default:
		return -EINVAL;
	}

	dev_dbg(&adapter->dev,
		"size=%d, address=0x%x, command=0x%x, len=%d, read=%d\n",
		size, address, command, len, rw);

	if (!len && rw == I2C_SMBUS_READ) {
		dev_dbg(&adapter->dev, "zero length read\n");
		return -EINVAL;
	}

	down(&iface->sem);

	iface->address_byte = (address << 1) | rw;
	iface->command = command;
	iface->ptr = buffer;
	iface->len = len;
	iface->result = -EINVAL;
	iface->needs_reset = 0;

	outb(inb(ACBCTL1) | ACBCTL1_START, ACBCTL1);

	if (size == I2C_SMBUS_QUICK || size == I2C_SMBUS_BYTE)
		iface->state = state_quick;
	else
		iface->state = state_address;

#ifdef POLLED_MODE
	while (iface->state != state_idle)
		scx200_acb_poll(iface);
#else /* POLLED_MODE */
#error Interrupt driven mode not implemented
#endif /* POLLED_MODE */	

	if (iface->needs_reset)
		scx200_acb_reset(iface);

	rc = iface->result;

	up(&iface->sem);

	if (rc == 0 && size == I2C_SMBUS_WORD_DATA && rw == I2C_SMBUS_READ)
		data->word = le16_to_cpu(cur_word);

#ifdef DEBUG
	dev_dbg(&adapter->dev, "transfer done, result: %d", rc);
	if (buffer) {
		int i;
		printk(" data:");
		for (i = 0; i < len; ++i)
			printk(" %02x", buffer[i]);
	}
	printk("\n");
#endif

	return rc;
}

static u32 scx200_acb_func(struct i2c_adapter *adapter)
{
	return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
	       I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
	       I2C_FUNC_SMBUS_BLOCK_DATA;
}

/* For now, we only handle combined mode (smbus) */
static struct i2c_algorithm scx200_acb_algorithm = {
	.smbus_xfer	= scx200_acb_smbus_xfer,
	.functionality	= scx200_acb_func,
};

static struct scx200_acb_iface *scx200_acb_list;
static DECLARE_MUTEX(scx200_acb_list_mutex);

static int scx200_acb_probe(struct scx200_acb_iface *iface)
{
	u8 val;

	/* Disable the ACCESS.bus device and Configure the SCL
	   frequency: 16 clock cycles */
	outb(0x70, ACBCTL2);

	if (inb(ACBCTL2) != 0x70) {
		pr_debug(NAME ": ACBCTL2 readback failed\n");
		return -ENXIO;
	}

	outb(inb(ACBCTL1) | ACBCTL1_NMINTE, ACBCTL1);

	val = inb(ACBCTL1);
	if (val) {
		pr_debug(NAME ": disabled, but ACBCTL1=0x%02x\n",
			val);
		return -ENXIO;
	}

	outb(inb(ACBCTL2) | ACBCTL2_ENABLE, ACBCTL2);

	outb(inb(ACBCTL1) | ACBCTL1_NMINTE, ACBCTL1);

	val = inb(ACBCTL1);
	if ((val & ACBCTL1_NMINTE) != ACBCTL1_NMINTE) {
		pr_debug(NAME ": enabled, but NMINTE won't be set, "
			 "ACBCTL1=0x%02x\n", val);
		return -ENXIO;
	}

	return 0;
}

static int  __init scx200_acb_create(int base, int index)
{
	struct scx200_acb_iface *iface;
	struct i2c_adapter *adapter;
	int rc;
	char description[64];

	iface = kzalloc(sizeof(*iface), GFP_KERNEL);
	if (!iface) {
		printk(KERN_ERR NAME ": can't allocate memory\n");
		rc = -ENOMEM;
		goto errout;
	}

	adapter = &iface->adapter;
	i2c_set_adapdata(adapter, iface);
	snprintf(adapter->name, I2C_NAME_SIZE, "SCx200 ACB%d", index);
	adapter->owner = THIS_MODULE;
	adapter->id = I2C_HW_SMBUS_SCX200;
	adapter->algo = &scx200_acb_algorithm;
	adapter->class = I2C_CLASS_HWMON;

	init_MUTEX(&iface->sem);

	snprintf(description, sizeof(description),
		 "NatSemi SCx200 ACCESS.bus [%s]", adapter->name);
	if (request_region(base, 8, description) == 0) {
		printk(KERN_ERR NAME ": can't allocate io 0x%x-0x%x\n",
			base, base + 8-1);
		rc = -EBUSY;
		goto errout_free;
	}
	iface->base = base;

	rc = scx200_acb_probe(iface);
	if (rc) {
		printk(KERN_WARNING NAME ": probe failed\n");
		goto errout_release;
	}

	scx200_acb_reset(iface);

	if (i2c_add_adapter(adapter) < 0) {
		printk(KERN_ERR NAME ": failed to register\n");
		rc = -ENODEV;
		goto errout_release;
	}

	down(&scx200_acb_list_mutex);
	iface->next = scx200_acb_list;
	scx200_acb_list = iface;
	up(&scx200_acb_list_mutex);

	return 0;

 errout_release:
	release_region(iface->base, 8);
 errout_free:
	kfree(iface);
 errout:
	return rc;
}

static struct pci_device_id scx200[] = {
	{ PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_SCx200_BRIDGE) },
	{ PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_SC1100_BRIDGE) },
	{ },
};

static int __init scx200_acb_init(void)
{
	int i;
	int rc;

	pr_debug(NAME ": NatSemi SCx200 ACCESS.bus Driver\n");

	/* Verify that this really is a SCx200 processor */
	if (pci_dev_present(scx200) == 0)
		return -ENODEV;

	rc = -ENXIO;
	for (i = 0; i < MAX_DEVICES; ++i) {
		if (base[i] > 0)
			rc = scx200_acb_create(base[i], i);
	}
	if (scx200_acb_list)
		return 0;
	return rc;
}

static void __exit scx200_acb_cleanup(void)
{
	struct scx200_acb_iface *iface;

	down(&scx200_acb_list_mutex);
	while ((iface = scx200_acb_list) != NULL) {
		scx200_acb_list = iface->next;
		up(&scx200_acb_list_mutex);

		i2c_del_adapter(&iface->adapter);
		release_region(iface->base, 8);
		kfree(iface);
		down(&scx200_acb_list_mutex);
	}
	up(&scx200_acb_list_mutex);
}

module_init(scx200_acb_init);
module_exit(scx200_acb_cleanup);
Commit	Line	Data
99c3adb4	1	/*
1da177e4 LT	2	Copyright (c) 2001,2002 Christer Weinigel <wingel@nano-system.com>
	3
	4	National Semiconductor SCx200 ACCESS.bus support
99c3adb4	5
1da177e4 LT	6	Based on i2c-keywest.c which is:
	7	Copyright (c) 2001 Benjamin Herrenschmidt <benh@kernel.crashing.org>
	8	Copyright (c) 2000 Philip Edelbrock <phil@stimpy.netroedge.com>
99c3adb4	9
1da177e4 LT	10	This program is free software; you can redistribute it and/or
	11	modify it under the terms of the GNU General Public License as
	12	published by the Free Software Foundation; either version 2 of the
	13	License, or (at your option) any later version.
99c3adb4	14
1da177e4 LT	15	This program is distributed in the hope that it will be useful,
	16	but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	18	General Public License for more details.
99c3adb4	19
1da177e4 LT	20	You should have received a copy of the GNU General Public License
	21	along with this program; if not, write to the Free Software
	22	Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
1da177e4 LT	23	*/
1da177e4 LT	24
1da177e4 LT	25	#include <linux/module.h>
	26	#include <linux/errno.h>
	27	#include <linux/kernel.h>
	28	#include <linux/init.h>
	29	#include <linux/i2c.h>
	30	#include <linux/smp_lock.h>
	31	#include <linux/pci.h>
	32	#include <linux/delay.h>
	33	#include <asm/io.h>
	34
	35	#include <linux/scx200.h>
	36
	37	#define NAME "scx200_acb"
	38
	39	MODULE_AUTHOR("Christer Weinigel <wingel@nano-system.com>");
	40	MODULE_DESCRIPTION("NatSemi SCx200 ACCESS.bus Driver");
	41	MODULE_LICENSE("GPL");
	42
	43	#define MAX_DEVICES 4
	44	static int base[MAX_DEVICES] = { 0x820, 0x840 };
	45	module_param_array(base, int, NULL, 0);
	46	MODULE_PARM_DESC(base, "Base addresses for the ACCESS.bus controllers");
	47
1da177e4 LT	48	/* The hardware supports interrupt driven mode too, but I haven't
	49	implemented that. */
	50	#define POLLED_MODE 1
	51	#define POLL_TIMEOUT (HZ)
	52
	53	enum scx200_acb_state {
	54	state_idle,
	55	state_address,
	56	state_command,
	57	state_repeat_start,
	58	state_quick,
	59	state_read,
	60	state_write,
	61	};
	62
	63	static const char *scx200_acb_state_name[] = {
	64	"idle",
	65	"address",
	66	"command",
	67	"repeat_start",
	68	"quick",
	69	"read",
	70	"write",
	71	};
	72
	73	/* Physical interface */
99c3adb4	74	struct scx200_acb_iface {
1da177e4 LT	75	struct scx200_acb_iface *next;
	76	struct i2c_adapter adapter;
	77	unsigned base;
	78	struct semaphore sem;
	79
	80	/* State machine data */
	81	enum scx200_acb_state state;
	82	int result;
	83	u8 address_byte;
	84	u8 command;
	85	u8 *ptr;
	86	char needs_reset;
	87	unsigned len;
	88	};
	89
	90	/* Register Definitions */
	91	#define ACBSDA (iface->base + 0)
	92	#define ACBST (iface->base + 1)
	93	#define ACBST_SDAST 0x40 /* SDA Status */
99c3adb4	94	#define ACBST_BER 0x20
1da177e4 LT	95	#define ACBST_NEGACK 0x10 /* Negative Acknowledge */
	96	#define ACBST_STASTR 0x08 /* Stall After Start */
	97	#define ACBST_MASTER 0x02
	98	#define ACBCST (iface->base + 2)
	99	#define ACBCST_BB 0x02
	100	#define ACBCTL1 (iface->base + 3)
	101	#define ACBCTL1_STASTRE 0x80
	102	#define ACBCTL1_NMINTE 0x40
99c3adb4 BG	103	#define ACBCTL1_ACK 0x10
	104	#define ACBCTL1_STOP 0x02
	105	#define ACBCTL1_START 0x01
1da177e4 LT	106	#define ACBADDR (iface->base + 4)
	107	#define ACBCTL2 (iface->base + 5)
	108	#define ACBCTL2_ENABLE 0x01
	109
	110	/************************************************************************/
	111
	112	static void scx200_acb_machine(struct scx200_acb_iface *iface, u8 status)
	113	{
	114	const char *errmsg;
	115
ef4d9275 BG	116	dev_dbg(&iface->adapter.dev, "state %s, status = 0x%02x\n",
ef4d9275 BG	117	scx200_acb_state_name[iface->state], status);
1da177e4 LT	118
	119	if (status & ACBST_BER) {
	120	errmsg = "bus error";
	121	goto error;
	122	}
	123	if (!(status & ACBST_MASTER)) {
	124	errmsg = "not master";
	125	goto error;
	126	}
9b7b6d3b BG	127	if (status & ACBST_NEGACK) {
	128	dev_dbg(&iface->adapter.dev, "negative ack in state %s\n",
	129	scx200_acb_state_name[iface->state]);
	130
	131	iface->state = state_idle;
	132	iface->result = -ENXIO;
	133
	134	outb(inb(ACBCTL1) \| ACBCTL1_STOP, ACBCTL1);
	135	outb(ACBST_STASTR \| ACBST_NEGACK, ACBST);
	136	return;
	137	}
1da177e4 LT	138
	139	switch (iface->state) {
	140	case state_idle:
	141	dev_warn(&iface->adapter.dev, "interrupt in idle state\n");
	142	break;
	143
	144	case state_address:
	145	/* Do a pointer write first */
	146	outb(iface->address_byte & ~1, ACBSDA);
	147
	148	iface->state = state_command;
	149	break;
	150
	151	case state_command:
	152	outb(iface->command, ACBSDA);
	153
	154	if (iface->address_byte & 1)
	155	iface->state = state_repeat_start;
	156	else
	157	iface->state = state_write;
	158	break;
	159
	160	case state_repeat_start:
	161	outb(inb(ACBCTL1) \| ACBCTL1_START, ACBCTL1);
	162	/* fallthrough */
99c3adb4	163
1da177e4 LT	164	case state_quick:
1da177e4 LT	165	if (iface->address_byte & 1) {
99c3adb4	166	if (iface->len == 1)
1da177e4 LT	167	outb(inb(ACBCTL1) \| ACBCTL1_ACK, ACBCTL1);
	168	else
	169	outb(inb(ACBCTL1) & ~ACBCTL1_ACK, ACBCTL1);
	170	outb(iface->address_byte, ACBSDA);
	171
	172	iface->state = state_read;
	173	} else {
	174	outb(iface->address_byte, ACBSDA);
	175
	176	iface->state = state_write;
	177	}
	178	break;
	179
	180	case state_read:
	181	/* Set ACK if receiving the last byte */
	182	if (iface->len == 1)
	183	outb(inb(ACBCTL1) \| ACBCTL1_ACK, ACBCTL1);
	184	else
	185	outb(inb(ACBCTL1) & ~ACBCTL1_ACK, ACBCTL1);
	186
	187	*iface->ptr++ = inb(ACBSDA);
	188	--iface->len;
	189
	190	if (iface->len == 0) {
	191	iface->result = 0;
	192	iface->state = state_idle;
	193	outb(inb(ACBCTL1) \| ACBCTL1_STOP, ACBCTL1);
	194	}
	195
	196	break;
	197
	198	case state_write:
	199	if (iface->len == 0) {
	200	iface->result = 0;
	201	iface->state = state_idle;
	202	outb(inb(ACBCTL1) \| ACBCTL1_STOP, ACBCTL1);
	203	break;
	204	}
99c3adb4	205
1da177e4 LT	206	outb(*iface->ptr++, ACBSDA);
1da177e4 LT	207	--iface->len;
99c3adb4	208
1da177e4 LT	209	break;
	210	}
	211
	212	return;
	213
1da177e4 LT	214	error:
	215	dev_err(&iface->adapter.dev, "%s in state %s\n", errmsg,
	216	scx200_acb_state_name[iface->state]);
	217
	218	iface->state = state_idle;
	219	iface->result = -EIO;
	220	iface->needs_reset = 1;
	221	}
	222
1da177e4 LT	223	#ifdef POLLED_MODE
	224	static void scx200_acb_poll(struct scx200_acb_iface *iface)
	225	{
9b7b6d3b	226	u8 status;
1da177e4 LT	227	unsigned long timeout;
	228
	229	timeout = jiffies + POLL_TIMEOUT;
	230	while (time_before(jiffies, timeout)) {
	231	status = inb(ACBST);
	232	if ((status & (ACBST_SDAST\|ACBST_BER\|ACBST_NEGACK)) != 0) {
	233	scx200_acb_machine(iface, status);
	234	return;
	235	}
	236	msleep(10);
	237	}
	238
9b7b6d3b BG	239	dev_err(&iface->adapter.dev, "timeout in state %s\n",
	240	scx200_acb_state_name[iface->state]);
	241
	242	iface->state = state_idle;
	243	iface->result = -EIO;
	244	iface->needs_reset = 1;
1da177e4 LT	245	}
	246	#endif /* POLLED_MODE */
	247
	248	static void scx200_acb_reset(struct scx200_acb_iface *iface)
	249	{
	250	/* Disable the ACCESS.bus device and Configure the SCL
99c3adb4	251	frequency: 16 clock cycles */
1da177e4 LT	252	outb(0x70, ACBCTL2);
	253	/* Polling mode */
	254	outb(0, ACBCTL1);
	255	/* Disable slave address */
	256	outb(0, ACBADDR);
	257	/* Enable the ACCESS.bus device */
	258	outb(inb(ACBCTL2) \| ACBCTL2_ENABLE, ACBCTL2);
	259	/* Free STALL after START */
	260	outb(inb(ACBCTL1) & ~(ACBCTL1_STASTRE \| ACBCTL1_NMINTE), ACBCTL1);
	261	/* Send a STOP */
	262	outb(inb(ACBCTL1) \| ACBCTL1_STOP, ACBCTL1);
	263	/* Clear BER, NEGACK and STASTR bits */
	264	outb(ACBST_BER \| ACBST_NEGACK \| ACBST_STASTR, ACBST);
	265	/* Clear BB bit */
	266	outb(inb(ACBCST) \| ACBCST_BB, ACBCST);
	267	}
	268
	269	static s32 scx200_acb_smbus_xfer(struct i2c_adapter *adapter,
99c3adb4 BG	270	u16 address, unsigned short flags,
	271	char rw, u8 command, int size,
	272	union i2c_smbus_data *data)
1da177e4 LT	273	{
	274	struct scx200_acb_iface *iface = i2c_get_adapdata(adapter);
	275	int len;
	276	u8 *buffer;
	277	u16 cur_word;
	278	int rc;
	279
	280	switch (size) {
	281	case I2C_SMBUS_QUICK:
99c3adb4 BG	282	len = 0;
	283	buffer = NULL;
	284	break;
	285
1da177e4	286	case I2C_SMBUS_BYTE:
9b7b6d3b BG	287	len = 1;
9b7b6d3b BG	288	buffer = rw ? &data->byte : &command;
99c3adb4 BG	289	break;
99c3adb4 BG	290
1da177e4	291	case I2C_SMBUS_BYTE_DATA:
99c3adb4 BG	292	len = 1;
	293	buffer = &data->byte;
	294	break;
	295
1da177e4 LT	296	case I2C_SMBUS_WORD_DATA:
1da177e4 LT	297	len = 2;
99c3adb4 BG	298	cur_word = cpu_to_le16(data->word);
99c3adb4 BG	299	buffer = (u8 *)&cur_word;
1da177e4	300	break;
99c3adb4	301
1da177e4	302	case I2C_SMBUS_BLOCK_DATA:
99c3adb4 BG	303	len = data->block[0];
99c3adb4 BG	304	buffer = &data->block[1];
1da177e4	305	break;
99c3adb4	306
1da177e4	307	default:
99c3adb4	308	return -EINVAL;
1da177e4 LT	309	}
1da177e4 LT	310
ef4d9275 BG	311	dev_dbg(&adapter->dev,
	312	"size=%d, address=0x%x, command=0x%x, len=%d, read=%d\n",
	313	size, address, command, len, rw);
1da177e4 LT	314
1da177e4 LT	315	if (!len && rw == I2C_SMBUS_READ) {
ef4d9275	316	dev_dbg(&adapter->dev, "zero length read\n");
1da177e4 LT	317	return -EINVAL;
	318	}
	319
1da177e4 LT	320	down(&iface->sem);
1da177e4 LT	321
9b7b6d3b	322	iface->address_byte = (address << 1) \| rw;
1da177e4 LT	323	iface->command = command;
	324	iface->ptr = buffer;
	325	iface->len = len;
	326	iface->result = -EINVAL;
	327	iface->needs_reset = 0;
	328
	329	outb(inb(ACBCTL1) \| ACBCTL1_START, ACBCTL1);
	330
	331	if (size == I2C_SMBUS_QUICK \|\| size == I2C_SMBUS_BYTE)
	332	iface->state = state_quick;
	333	else
	334	iface->state = state_address;
	335
	336	#ifdef POLLED_MODE
	337	while (iface->state != state_idle)
	338	scx200_acb_poll(iface);
	339	#else /* POLLED_MODE */
	340	#error Interrupt driven mode not implemented
	341	#endif /* POLLED_MODE */
	342
	343	if (iface->needs_reset)
	344	scx200_acb_reset(iface);
	345
	346	rc = iface->result;
	347
	348	up(&iface->sem);
	349
	350	if (rc == 0 && size == I2C_SMBUS_WORD_DATA && rw == I2C_SMBUS_READ)
99c3adb4	351	data->word = le16_to_cpu(cur_word);
1da177e4 LT	352
1da177e4 LT	353	#ifdef DEBUG
ef4d9275	354	dev_dbg(&adapter->dev, "transfer done, result: %d", rc);
1da177e4 LT	355	if (buffer) {
	356	int i;
	357	printk(" data:");
	358	for (i = 0; i < len; ++i)
	359	printk(" %02x", buffer[i]);
	360	}
	361	printk("\n");
	362	#endif
	363
	364	return rc;
	365	}
	366
	367	static u32 scx200_acb_func(struct i2c_adapter *adapter)
	368	{
	369	return I2C_FUNC_SMBUS_QUICK \| I2C_FUNC_SMBUS_BYTE \|
	370	I2C_FUNC_SMBUS_BYTE_DATA \| I2C_FUNC_SMBUS_WORD_DATA \|
	371	I2C_FUNC_SMBUS_BLOCK_DATA;
	372	}
	373
	374	/* For now, we only handle combined mode (smbus) */
	375	static struct i2c_algorithm scx200_acb_algorithm = {
1da177e4 LT	376	.smbus_xfer = scx200_acb_smbus_xfer,
	377	.functionality = scx200_acb_func,
	378	};
	379
	380	static struct scx200_acb_iface *scx200_acb_list;
8a05940d	381	static DECLARE_MUTEX(scx200_acb_list_mutex);
1da177e4 LT	382
	383	static int scx200_acb_probe(struct scx200_acb_iface *iface)
	384	{
	385	u8 val;
	386
	387	/* Disable the ACCESS.bus device and Configure the SCL
99c3adb4	388	frequency: 16 clock cycles */
1da177e4 LT	389	outb(0x70, ACBCTL2);
	390
	391	if (inb(ACBCTL2) != 0x70) {
ef4d9275	392	pr_debug(NAME ": ACBCTL2 readback failed\n");
1da177e4 LT	393	return -ENXIO;
	394	}
	395
	396	outb(inb(ACBCTL1) \| ACBCTL1_NMINTE, ACBCTL1);
	397
	398	val = inb(ACBCTL1);
	399	if (val) {
ef4d9275 BG	400	pr_debug(NAME ": disabled, but ACBCTL1=0x%02x\n",
ef4d9275 BG	401	val);
1da177e4 LT	402	return -ENXIO;
	403	}
	404
	405	outb(inb(ACBCTL2) \| ACBCTL2_ENABLE, ACBCTL2);
	406
	407	outb(inb(ACBCTL1) \| ACBCTL1_NMINTE, ACBCTL1);
	408
	409	val = inb(ACBCTL1);
	410	if ((val & ACBCTL1_NMINTE) != ACBCTL1_NMINTE) {
ef4d9275 BG	411	pr_debug(NAME ": enabled, but NMINTE won't be set, "
ef4d9275 BG	412	"ACBCTL1=0x%02x\n", val);
1da177e4 LT	413	return -ENXIO;
	414	}
	415
	416	return 0;
	417	}
	418
	419	static int __init scx200_acb_create(int base, int index)
	420	{
	421	struct scx200_acb_iface *iface;
	422	struct i2c_adapter *adapter;
9b7b6d3b	423	int rc;
1da177e4 LT	424	char description[64];
1da177e4 LT	425
5263ebb5	426	iface = kzalloc(sizeof(*iface), GFP_KERNEL);
1da177e4 LT	427	if (!iface) {
	428	printk(KERN_ERR NAME ": can't allocate memory\n");
	429	rc = -ENOMEM;
	430	goto errout;
	431	}
	432
1da177e4 LT	433	adapter = &iface->adapter;
	434	i2c_set_adapdata(adapter, iface);
	435	snprintf(adapter->name, I2C_NAME_SIZE, "SCx200 ACB%d", index);
	436	adapter->owner = THIS_MODULE;
1684a984	437	adapter->id = I2C_HW_SMBUS_SCX200;
1da177e4 LT	438	adapter->algo = &scx200_acb_algorithm;
	439	adapter->class = I2C_CLASS_HWMON;
	440
	441	init_MUTEX(&iface->sem);
	442
99c3adb4 BG	443	snprintf(description, sizeof(description),
99c3adb4 BG	444	"NatSemi SCx200 ACCESS.bus [%s]", adapter->name);
1da177e4	445	if (request_region(base, 8, description) == 0) {
ef4d9275	446	printk(KERN_ERR NAME ": can't allocate io 0x%x-0x%x\n",
1da177e4 LT	447	base, base + 8-1);
1da177e4 LT	448	rc = -EBUSY;
9b7b6d3b	449	goto errout_free;
1da177e4 LT	450	}
	451	iface->base = base;
	452
	453	rc = scx200_acb_probe(iface);
	454	if (rc) {
ef4d9275	455	printk(KERN_WARNING NAME ": probe failed\n");
9b7b6d3b	456	goto errout_release;
1da177e4 LT	457	}
	458
	459	scx200_acb_reset(iface);
	460
	461	if (i2c_add_adapter(adapter) < 0) {
ef4d9275	462	printk(KERN_ERR NAME ": failed to register\n");
1da177e4	463	rc = -ENODEV;
9b7b6d3b	464	goto errout_release;
1da177e4 LT	465	}
1da177e4 LT	466
8a05940d	467	down(&scx200_acb_list_mutex);
1da177e4 LT	468	iface->next = scx200_acb_list;
1da177e4 LT	469	scx200_acb_list = iface;
8a05940d	470	up(&scx200_acb_list_mutex);
1da177e4 LT	471
	472	return 0;
	473
9b7b6d3b BG	474	errout_release:
	475	release_region(iface->base, 8);
	476	errout_free:
	477	kfree(iface);
1da177e4	478	errout:
1da177e4 LT	479	return rc;
	480	}
	481
	482	static struct pci_device_id scx200[] = {
	483	{ PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_SCx200_BRIDGE) },
	484	{ PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_SC1100_BRIDGE) },
	485	{ },
	486	};
	487
	488	static int __init scx200_acb_init(void)
	489	{
	490	int i;
	491	int rc;
	492
	493	pr_debug(NAME ": NatSemi SCx200 ACCESS.bus Driver\n");
	494
	495	/* Verify that this really is a SCx200 processor */
	496	if (pci_dev_present(scx200) == 0)
	497	return -ENODEV;
	498
	499	rc = -ENXIO;
	500	for (i = 0; i < MAX_DEVICES; ++i) {
	501	if (base[i] > 0)
	502	rc = scx200_acb_create(base[i], i);
	503	}
	504	if (scx200_acb_list)
	505	return 0;
	506	return rc;
	507	}
	508
	509	static void __exit scx200_acb_cleanup(void)
	510	{
	511	struct scx200_acb_iface *iface;
99c3adb4	512
8a05940d	513	down(&scx200_acb_list_mutex);
1da177e4 LT	514	while ((iface = scx200_acb_list) != NULL) {
1da177e4 LT	515	scx200_acb_list = iface->next;
8a05940d	516	up(&scx200_acb_list_mutex);
1da177e4 LT	517
	518	i2c_del_adapter(&iface->adapter);
	519	release_region(iface->base, 8);
	520	kfree(iface);
8a05940d	521	down(&scx200_acb_list_mutex);
1da177e4	522	}
8a05940d	523	up(&scx200_acb_list_mutex);
1da177e4 LT	524	}
	525
	526	module_init(scx200_acb_init);
	527	module_exit(scx200_acb_cleanup);