Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Copyright (c) 1996-2004 Russell King. |
3 | * | |
4 | * Please note that this platform does not support 32-bit IDE IO. | |
5 | */ | |
6 | ||
1da177e4 LT |
7 | #include <linux/string.h> |
8 | #include <linux/module.h> | |
9 | #include <linux/ioport.h> | |
10 | #include <linux/slab.h> | |
11 | #include <linux/blkdev.h> | |
12 | #include <linux/errno.h> | |
13 | #include <linux/hdreg.h> | |
14 | #include <linux/ide.h> | |
15 | #include <linux/dma-mapping.h> | |
16 | #include <linux/device.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/scatterlist.h> | |
ba5b55d0 | 19 | #include <linux/io.h> |
1da177e4 LT |
20 | |
21 | #include <asm/dma.h> | |
22 | #include <asm/ecard.h> | |
1da177e4 LT |
23 | |
24 | #define ICS_IDENT_OFFSET 0x2280 | |
25 | ||
26 | #define ICS_ARCIN_V5_INTRSTAT 0x0000 | |
27 | #define ICS_ARCIN_V5_INTROFFSET 0x0004 | |
28 | #define ICS_ARCIN_V5_IDEOFFSET 0x2800 | |
29 | #define ICS_ARCIN_V5_IDEALTOFFSET 0x2b80 | |
30 | #define ICS_ARCIN_V5_IDESTEPPING 6 | |
31 | ||
32 | #define ICS_ARCIN_V6_IDEOFFSET_1 0x2000 | |
33 | #define ICS_ARCIN_V6_INTROFFSET_1 0x2200 | |
34 | #define ICS_ARCIN_V6_INTRSTAT_1 0x2290 | |
35 | #define ICS_ARCIN_V6_IDEALTOFFSET_1 0x2380 | |
36 | #define ICS_ARCIN_V6_IDEOFFSET_2 0x3000 | |
37 | #define ICS_ARCIN_V6_INTROFFSET_2 0x3200 | |
38 | #define ICS_ARCIN_V6_INTRSTAT_2 0x3290 | |
39 | #define ICS_ARCIN_V6_IDEALTOFFSET_2 0x3380 | |
40 | #define ICS_ARCIN_V6_IDESTEPPING 6 | |
41 | ||
42 | struct cardinfo { | |
43 | unsigned int dataoffset; | |
44 | unsigned int ctrloffset; | |
45 | unsigned int stepping; | |
46 | }; | |
47 | ||
48 | static struct cardinfo icside_cardinfo_v5 = { | |
49 | .dataoffset = ICS_ARCIN_V5_IDEOFFSET, | |
50 | .ctrloffset = ICS_ARCIN_V5_IDEALTOFFSET, | |
51 | .stepping = ICS_ARCIN_V5_IDESTEPPING, | |
52 | }; | |
53 | ||
54 | static struct cardinfo icside_cardinfo_v6_1 = { | |
55 | .dataoffset = ICS_ARCIN_V6_IDEOFFSET_1, | |
56 | .ctrloffset = ICS_ARCIN_V6_IDEALTOFFSET_1, | |
57 | .stepping = ICS_ARCIN_V6_IDESTEPPING, | |
58 | }; | |
59 | ||
60 | static struct cardinfo icside_cardinfo_v6_2 = { | |
61 | .dataoffset = ICS_ARCIN_V6_IDEOFFSET_2, | |
62 | .ctrloffset = ICS_ARCIN_V6_IDEALTOFFSET_2, | |
63 | .stepping = ICS_ARCIN_V6_IDESTEPPING, | |
64 | }; | |
65 | ||
66 | struct icside_state { | |
67 | unsigned int channel; | |
68 | unsigned int enabled; | |
69 | void __iomem *irq_port; | |
70 | void __iomem *ioc_base; | |
26839f09 | 71 | unsigned int sel; |
1da177e4 | 72 | unsigned int type; |
1da177e4 LT |
73 | ide_hwif_t *hwif[2]; |
74 | }; | |
75 | ||
76 | #define ICS_TYPE_A3IN 0 | |
77 | #define ICS_TYPE_A3USER 1 | |
78 | #define ICS_TYPE_V6 3 | |
79 | #define ICS_TYPE_V5 15 | |
80 | #define ICS_TYPE_NOTYPE ((unsigned int)-1) | |
81 | ||
82 | /* ---------------- Version 5 PCB Support Functions --------------------- */ | |
83 | /* Prototype: icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr) | |
84 | * Purpose : enable interrupts from card | |
85 | */ | |
86 | static void icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr) | |
87 | { | |
88 | struct icside_state *state = ec->irq_data; | |
89 | ||
90 | writeb(0, state->irq_port + ICS_ARCIN_V5_INTROFFSET); | |
91 | } | |
92 | ||
93 | /* Prototype: icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr) | |
94 | * Purpose : disable interrupts from card | |
95 | */ | |
96 | static void icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr) | |
97 | { | |
98 | struct icside_state *state = ec->irq_data; | |
99 | ||
100 | readb(state->irq_port + ICS_ARCIN_V5_INTROFFSET); | |
101 | } | |
102 | ||
103 | static const expansioncard_ops_t icside_ops_arcin_v5 = { | |
104 | .irqenable = icside_irqenable_arcin_v5, | |
105 | .irqdisable = icside_irqdisable_arcin_v5, | |
106 | }; | |
107 | ||
108 | ||
109 | /* ---------------- Version 6 PCB Support Functions --------------------- */ | |
110 | /* Prototype: icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr) | |
111 | * Purpose : enable interrupts from card | |
112 | */ | |
113 | static void icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr) | |
114 | { | |
115 | struct icside_state *state = ec->irq_data; | |
116 | void __iomem *base = state->irq_port; | |
117 | ||
118 | state->enabled = 1; | |
119 | ||
120 | switch (state->channel) { | |
121 | case 0: | |
122 | writeb(0, base + ICS_ARCIN_V6_INTROFFSET_1); | |
123 | readb(base + ICS_ARCIN_V6_INTROFFSET_2); | |
124 | break; | |
125 | case 1: | |
126 | writeb(0, base + ICS_ARCIN_V6_INTROFFSET_2); | |
127 | readb(base + ICS_ARCIN_V6_INTROFFSET_1); | |
128 | break; | |
129 | } | |
130 | } | |
131 | ||
132 | /* Prototype: icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr) | |
133 | * Purpose : disable interrupts from card | |
134 | */ | |
135 | static void icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr) | |
136 | { | |
137 | struct icside_state *state = ec->irq_data; | |
138 | ||
139 | state->enabled = 0; | |
140 | ||
141 | readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1); | |
142 | readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2); | |
143 | } | |
144 | ||
145 | /* Prototype: icside_irqprobe(struct expansion_card *ec) | |
146 | * Purpose : detect an active interrupt from card | |
147 | */ | |
148 | static int icside_irqpending_arcin_v6(struct expansion_card *ec) | |
149 | { | |
150 | struct icside_state *state = ec->irq_data; | |
151 | ||
152 | return readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_1) & 1 || | |
153 | readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_2) & 1; | |
154 | } | |
155 | ||
156 | static const expansioncard_ops_t icside_ops_arcin_v6 = { | |
157 | .irqenable = icside_irqenable_arcin_v6, | |
158 | .irqdisable = icside_irqdisable_arcin_v6, | |
159 | .irqpending = icside_irqpending_arcin_v6, | |
160 | }; | |
161 | ||
162 | /* | |
163 | * Handle routing of interrupts. This is called before | |
164 | * we write the command to the drive. | |
165 | */ | |
166 | static void icside_maskproc(ide_drive_t *drive, int mask) | |
167 | { | |
168 | ide_hwif_t *hwif = HWIF(drive); | |
26839f09 BZ |
169 | struct expansion_card *ec = ECARD_DEV(hwif->dev); |
170 | struct icside_state *state = ecard_get_drvdata(ec); | |
1da177e4 LT |
171 | unsigned long flags; |
172 | ||
173 | local_irq_save(flags); | |
174 | ||
175 | state->channel = hwif->channel; | |
176 | ||
177 | if (state->enabled && !mask) { | |
178 | switch (hwif->channel) { | |
179 | case 0: | |
180 | writeb(0, state->irq_port + ICS_ARCIN_V6_INTROFFSET_1); | |
181 | readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2); | |
182 | break; | |
183 | case 1: | |
184 | writeb(0, state->irq_port + ICS_ARCIN_V6_INTROFFSET_2); | |
185 | readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1); | |
186 | break; | |
187 | } | |
188 | } else { | |
189 | readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2); | |
190 | readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1); | |
191 | } | |
192 | ||
193 | local_irq_restore(flags); | |
194 | } | |
195 | ||
ac95beed BZ |
196 | static const struct ide_port_ops icside_v6_no_dma_port_ops = { |
197 | .maskproc = icside_maskproc, | |
198 | }; | |
199 | ||
1da177e4 | 200 | #ifdef CONFIG_BLK_DEV_IDEDMA_ICS |
1da177e4 LT |
201 | /* |
202 | * SG-DMA support. | |
203 | * | |
204 | * Similar to the BM-DMA, but we use the RiscPCs IOMD DMA controllers. | |
205 | * There is only one DMA controller per card, which means that only | |
206 | * one drive can be accessed at one time. NOTE! We do not enforce that | |
207 | * here, but we rely on the main IDE driver spotting that both | |
208 | * interfaces use the same IRQ, which should guarantee this. | |
209 | */ | |
210 | ||
1da177e4 LT |
211 | /* |
212 | * Configure the IOMD to give the appropriate timings for the transfer | |
213 | * mode being requested. We take the advice of the ATA standards, and | |
214 | * calculate the cycle time based on the transfer mode, and the EIDE | |
215 | * MW DMA specs that the drive provides in the IDENTIFY command. | |
216 | * | |
217 | * We have the following IOMD DMA modes to choose from: | |
218 | * | |
219 | * Type Active Recovery Cycle | |
220 | * A 250 (250) 312 (550) 562 (800) | |
221 | * B 187 250 437 | |
222 | * C 125 (125) 125 (375) 250 (500) | |
223 | * D 62 125 187 | |
224 | * | |
225 | * (figures in brackets are actual measured timings) | |
226 | * | |
227 | * However, we also need to take care of the read/write active and | |
228 | * recovery timings: | |
229 | * | |
230 | * Read Write | |
231 | * Mode Active -- Recovery -- Cycle IOMD type | |
232 | * MW0 215 50 215 480 A | |
233 | * MW1 80 50 50 150 C | |
234 | * MW2 70 25 25 120 C | |
235 | */ | |
88b2b32b | 236 | static void icside_set_dma_mode(ide_drive_t *drive, const u8 xfer_mode) |
1da177e4 | 237 | { |
f44ae58a | 238 | int cycle_time, use_dma_info = 0; |
1da177e4 | 239 | |
1da177e4 LT |
240 | switch (xfer_mode) { |
241 | case XFER_MW_DMA_2: | |
242 | cycle_time = 250; | |
243 | use_dma_info = 1; | |
244 | break; | |
245 | ||
246 | case XFER_MW_DMA_1: | |
247 | cycle_time = 250; | |
248 | use_dma_info = 1; | |
249 | break; | |
250 | ||
251 | case XFER_MW_DMA_0: | |
252 | cycle_time = 480; | |
253 | break; | |
254 | ||
255 | case XFER_SW_DMA_2: | |
256 | case XFER_SW_DMA_1: | |
257 | case XFER_SW_DMA_0: | |
258 | cycle_time = 480; | |
259 | break; | |
260 | } | |
261 | ||
262 | /* | |
263 | * If we're going to be doing MW_DMA_1 or MW_DMA_2, we should | |
264 | * take care to note the values in the ID... | |
265 | */ | |
266 | if (use_dma_info && drive->id->eide_dma_time > cycle_time) | |
267 | cycle_time = drive->id->eide_dma_time; | |
268 | ||
269 | drive->drive_data = cycle_time; | |
270 | ||
1da177e4 LT |
271 | printk("%s: %s selected (peak %dMB/s)\n", drive->name, |
272 | ide_xfer_verbose(xfer_mode), 2000 / drive->drive_data); | |
1da177e4 LT |
273 | } |
274 | ||
ac95beed BZ |
275 | static const struct ide_port_ops icside_v6_port_ops = { |
276 | .set_dma_mode = icside_set_dma_mode, | |
277 | .maskproc = icside_maskproc, | |
278 | }; | |
279 | ||
15ce926a | 280 | static void icside_dma_host_set(ide_drive_t *drive, int on) |
1da177e4 | 281 | { |
1da177e4 LT |
282 | } |
283 | ||
1da177e4 LT |
284 | static int icside_dma_end(ide_drive_t *drive) |
285 | { | |
286 | ide_hwif_t *hwif = HWIF(drive); | |
f8341c1c | 287 | struct expansion_card *ec = ECARD_DEV(hwif->dev); |
1da177e4 LT |
288 | |
289 | drive->waiting_for_dma = 0; | |
290 | ||
f8341c1c | 291 | disable_dma(ec->dma); |
1da177e4 LT |
292 | |
293 | /* Teardown mappings after DMA has completed. */ | |
062f9f02 | 294 | ide_destroy_dmatable(drive); |
1da177e4 | 295 | |
f8341c1c | 296 | return get_dma_residue(ec->dma) != 0; |
1da177e4 LT |
297 | } |
298 | ||
299 | static void icside_dma_start(ide_drive_t *drive) | |
300 | { | |
301 | ide_hwif_t *hwif = HWIF(drive); | |
f8341c1c | 302 | struct expansion_card *ec = ECARD_DEV(hwif->dev); |
1da177e4 LT |
303 | |
304 | /* We can not enable DMA on both channels simultaneously. */ | |
f8341c1c BZ |
305 | BUG_ON(dma_channel_active(ec->dma)); |
306 | enable_dma(ec->dma); | |
1da177e4 LT |
307 | } |
308 | ||
309 | static int icside_dma_setup(ide_drive_t *drive) | |
310 | { | |
311 | ide_hwif_t *hwif = HWIF(drive); | |
f8341c1c | 312 | struct expansion_card *ec = ECARD_DEV(hwif->dev); |
26839f09 | 313 | struct icside_state *state = ecard_get_drvdata(ec); |
1da177e4 LT |
314 | struct request *rq = hwif->hwgroup->rq; |
315 | unsigned int dma_mode; | |
316 | ||
317 | if (rq_data_dir(rq)) | |
318 | dma_mode = DMA_MODE_WRITE; | |
319 | else | |
320 | dma_mode = DMA_MODE_READ; | |
321 | ||
322 | /* | |
323 | * We can not enable DMA on both channels. | |
324 | */ | |
f8341c1c | 325 | BUG_ON(dma_channel_active(ec->dma)); |
1da177e4 | 326 | |
062f9f02 | 327 | hwif->sg_nents = ide_build_sglist(drive, rq); |
1da177e4 LT |
328 | |
329 | /* | |
330 | * Ensure that we have the right interrupt routed. | |
331 | */ | |
332 | icside_maskproc(drive, 0); | |
333 | ||
334 | /* | |
335 | * Route the DMA signals to the correct interface. | |
336 | */ | |
26839f09 | 337 | writeb(state->sel | hwif->channel, state->ioc_base); |
1da177e4 LT |
338 | |
339 | /* | |
340 | * Select the correct timing for this drive. | |
341 | */ | |
f8341c1c | 342 | set_dma_speed(ec->dma, drive->drive_data); |
1da177e4 LT |
343 | |
344 | /* | |
345 | * Tell the DMA engine about the SG table and | |
346 | * data direction. | |
347 | */ | |
f8341c1c BZ |
348 | set_dma_sg(ec->dma, hwif->sg_table, hwif->sg_nents); |
349 | set_dma_mode(ec->dma, dma_mode); | |
1da177e4 LT |
350 | |
351 | drive->waiting_for_dma = 1; | |
352 | ||
353 | return 0; | |
354 | } | |
355 | ||
356 | static void icside_dma_exec_cmd(ide_drive_t *drive, u8 cmd) | |
357 | { | |
358 | /* issue cmd to drive */ | |
359 | ide_execute_command(drive, cmd, ide_dma_intr, 2 * WAIT_CMD, NULL); | |
360 | } | |
361 | ||
362 | static int icside_dma_test_irq(ide_drive_t *drive) | |
363 | { | |
364 | ide_hwif_t *hwif = HWIF(drive); | |
26839f09 BZ |
365 | struct expansion_card *ec = ECARD_DEV(hwif->dev); |
366 | struct icside_state *state = ecard_get_drvdata(ec); | |
1da177e4 LT |
367 | |
368 | return readb(state->irq_port + | |
369 | (hwif->channel ? | |
370 | ICS_ARCIN_V6_INTRSTAT_2 : | |
371 | ICS_ARCIN_V6_INTRSTAT_1)) & 1; | |
372 | } | |
373 | ||
c283f5db | 374 | static void icside_dma_timeout(ide_drive_t *drive) |
1da177e4 LT |
375 | { |
376 | printk(KERN_ERR "%s: DMA timeout occurred: ", drive->name); | |
377 | ||
378 | if (icside_dma_test_irq(drive)) | |
c283f5db | 379 | return; |
1da177e4 | 380 | |
c47137a9 | 381 | ide_dump_status(drive, "DMA timeout", ide_read_status(drive)); |
1da177e4 | 382 | |
c283f5db | 383 | icside_dma_end(drive); |
1da177e4 LT |
384 | } |
385 | ||
841d2a9b | 386 | static void icside_dma_lost_irq(ide_drive_t *drive) |
1da177e4 LT |
387 | { |
388 | printk(KERN_ERR "%s: IRQ lost\n", drive->name); | |
1da177e4 LT |
389 | } |
390 | ||
91432f48 | 391 | static int icside_dma_init(ide_hwif_t *hwif, const struct ide_port_info *d) |
1da177e4 | 392 | { |
1da177e4 LT |
393 | hwif->dmatable_cpu = NULL; |
394 | hwif->dmatable_dma = 0; | |
1da177e4 | 395 | |
91432f48 | 396 | return 0; |
1da177e4 | 397 | } |
5e37bdc0 | 398 | |
f37afdac | 399 | static const struct ide_dma_ops icside_v6_dma_ops = { |
5e37bdc0 BZ |
400 | .dma_host_set = icside_dma_host_set, |
401 | .dma_setup = icside_dma_setup, | |
402 | .dma_exec_cmd = icside_dma_exec_cmd, | |
403 | .dma_start = icside_dma_start, | |
404 | .dma_end = icside_dma_end, | |
405 | .dma_test_irq = icside_dma_test_irq, | |
406 | .dma_timeout = icside_dma_timeout, | |
407 | .dma_lost_irq = icside_dma_lost_irq, | |
408 | }; | |
409 | #else | |
410 | #define icside_v6_dma_ops NULL | |
1da177e4 LT |
411 | #endif |
412 | ||
91432f48 BZ |
413 | static int icside_dma_off_init(ide_hwif_t *hwif, const struct ide_port_info *d) |
414 | { | |
415 | return -EOPNOTSUPP; | |
416 | } | |
417 | ||
b25afdf1 BZ |
418 | static void icside_setup_ports(hw_regs_t *hw, void __iomem *base, |
419 | struct cardinfo *info, struct expansion_card *ec) | |
1da177e4 LT |
420 | { |
421 | unsigned long port = (unsigned long)base + info->dataoffset; | |
1da177e4 | 422 | |
b25afdf1 BZ |
423 | hw->io_ports.data_addr = port; |
424 | hw->io_ports.error_addr = port + (1 << info->stepping); | |
425 | hw->io_ports.nsect_addr = port + (2 << info->stepping); | |
426 | hw->io_ports.lbal_addr = port + (3 << info->stepping); | |
427 | hw->io_ports.lbam_addr = port + (4 << info->stepping); | |
428 | hw->io_ports.lbah_addr = port + (5 << info->stepping); | |
429 | hw->io_ports.device_addr = port + (6 << info->stepping); | |
430 | hw->io_ports.status_addr = port + (7 << info->stepping); | |
431 | hw->io_ports.ctl_addr = (unsigned long)base + info->ctrloffset; | |
432 | ||
433 | hw->irq = ec->irq; | |
434 | hw->dev = &ec->dev; | |
435 | hw->chipset = ide_acorn; | |
1da177e4 LT |
436 | } |
437 | ||
438 | static int __init | |
439 | icside_register_v5(struct icside_state *state, struct expansion_card *ec) | |
440 | { | |
441 | ide_hwif_t *hwif; | |
442 | void __iomem *base; | |
8447d9d5 | 443 | u8 idx[4] = { 0xff, 0xff, 0xff, 0xff }; |
b25afdf1 | 444 | hw_regs_t hw; |
1da177e4 | 445 | |
10bdaaa0 | 446 | base = ecardm_iomap(ec, ECARD_RES_MEMC, 0, 0); |
1da177e4 LT |
447 | if (!base) |
448 | return -ENOMEM; | |
449 | ||
450 | state->irq_port = base; | |
451 | ||
452 | ec->irqaddr = base + ICS_ARCIN_V5_INTRSTAT; | |
453 | ec->irqmask = 1; | |
c7b87f3d RK |
454 | |
455 | ecard_setirq(ec, &icside_ops_arcin_v5, state); | |
1da177e4 LT |
456 | |
457 | /* | |
458 | * Be on the safe side - disable interrupts | |
459 | */ | |
460 | icside_irqdisable_arcin_v5(ec, 0); | |
461 | ||
b25afdf1 BZ |
462 | icside_setup_ports(&hw, base, &icside_cardinfo_v5, ec); |
463 | ||
464 | hwif = ide_find_port(); | |
10bdaaa0 | 465 | if (!hwif) |
1da177e4 | 466 | return -ENODEV; |
1da177e4 | 467 | |
b25afdf1 BZ |
468 | ide_init_port_hw(hwif, &hw); |
469 | default_hwif_mmiops(hwif); | |
470 | ||
1da177e4 LT |
471 | state->hwif[0] = hwif; |
472 | ||
26839f09 BZ |
473 | ecard_set_drvdata(ec, state); |
474 | ||
8447d9d5 | 475 | idx[0] = hwif->index; |
5cbf79cd | 476 | |
c413b9b9 | 477 | ide_device_add(idx, NULL); |
1da177e4 LT |
478 | |
479 | return 0; | |
480 | } | |
481 | ||
c413b9b9 | 482 | static const struct ide_port_info icside_v6_port_info __initdata = { |
91432f48 | 483 | .init_dma = icside_dma_off_init, |
ac95beed | 484 | .port_ops = &icside_v6_no_dma_port_ops, |
5e37bdc0 | 485 | .dma_ops = &icside_v6_dma_ops, |
c5dd43ec | 486 | .host_flags = IDE_HFLAG_SERIALIZE | IDE_HFLAG_MMIO, |
c413b9b9 BZ |
487 | .mwdma_mask = ATA_MWDMA2, |
488 | .swdma_mask = ATA_SWDMA2, | |
489 | }; | |
490 | ||
1da177e4 LT |
491 | static int __init |
492 | icside_register_v6(struct icside_state *state, struct expansion_card *ec) | |
493 | { | |
494 | ide_hwif_t *hwif, *mate; | |
495 | void __iomem *ioc_base, *easi_base; | |
496 | unsigned int sel = 0; | |
497 | int ret; | |
8447d9d5 | 498 | u8 idx[4] = { 0xff, 0xff, 0xff, 0xff }; |
c413b9b9 | 499 | struct ide_port_info d = icside_v6_port_info; |
b25afdf1 | 500 | hw_regs_t hw[2]; |
1da177e4 | 501 | |
10bdaaa0 | 502 | ioc_base = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0); |
1da177e4 LT |
503 | if (!ioc_base) { |
504 | ret = -ENOMEM; | |
505 | goto out; | |
506 | } | |
507 | ||
508 | easi_base = ioc_base; | |
509 | ||
510 | if (ecard_resource_flags(ec, ECARD_RES_EASI)) { | |
10bdaaa0 | 511 | easi_base = ecardm_iomap(ec, ECARD_RES_EASI, 0, 0); |
1da177e4 LT |
512 | if (!easi_base) { |
513 | ret = -ENOMEM; | |
10bdaaa0 | 514 | goto out; |
1da177e4 LT |
515 | } |
516 | ||
517 | /* | |
518 | * Enable access to the EASI region. | |
519 | */ | |
520 | sel = 1 << 5; | |
521 | } | |
522 | ||
523 | writeb(sel, ioc_base); | |
524 | ||
c7b87f3d | 525 | ecard_setirq(ec, &icside_ops_arcin_v6, state); |
1da177e4 LT |
526 | |
527 | state->irq_port = easi_base; | |
528 | state->ioc_base = ioc_base; | |
26839f09 | 529 | state->sel = sel; |
1da177e4 LT |
530 | |
531 | /* | |
532 | * Be on the safe side - disable interrupts | |
533 | */ | |
534 | icside_irqdisable_arcin_v6(ec, 0); | |
535 | ||
b25afdf1 BZ |
536 | icside_setup_ports(&hw[0], easi_base, &icside_cardinfo_v6_1, ec); |
537 | icside_setup_ports(&hw[1], easi_base, &icside_cardinfo_v6_2, ec); | |
538 | ||
1da177e4 LT |
539 | /* |
540 | * Find and register the interfaces. | |
541 | */ | |
b25afdf1 BZ |
542 | hwif = ide_find_port(); |
543 | if (hwif == NULL) | |
544 | return -ENODEV; | |
1da177e4 | 545 | |
b25afdf1 BZ |
546 | ide_init_port_hw(hwif, &hw[0]); |
547 | default_hwif_mmiops(hwif); | |
548 | ||
549 | mate = ide_find_port(); | |
550 | if (mate == NULL) | |
551 | return -ENODEV; | |
552 | ||
553 | ide_init_port_hw(mate, &hw[1]); | |
554 | default_hwif_mmiops(mate); | |
1da177e4 LT |
555 | |
556 | state->hwif[0] = hwif; | |
557 | state->hwif[1] = mate; | |
558 | ||
26839f09 | 559 | ecard_set_drvdata(ec, state); |
1da177e4 LT |
560 | |
561 | if (ec->dma != NO_DMA && !request_dma(ec->dma, hwif->name)) { | |
91432f48 | 562 | d.init_dma = icside_dma_init; |
9c391bae | 563 | d.port_ops = &icside_v6_port_ops; |
5e37bdc0 | 564 | d.dma_ops = NULL; |
91432f48 | 565 | } |
1da177e4 | 566 | |
8447d9d5 BZ |
567 | idx[0] = hwif->index; |
568 | idx[1] = mate->index; | |
5cbf79cd | 569 | |
c413b9b9 | 570 | ide_device_add(idx, &d); |
1da177e4 LT |
571 | |
572 | return 0; | |
573 | ||
1da177e4 LT |
574 | out: |
575 | return ret; | |
576 | } | |
577 | ||
578 | static int __devinit | |
579 | icside_probe(struct expansion_card *ec, const struct ecard_id *id) | |
580 | { | |
581 | struct icside_state *state; | |
582 | void __iomem *idmem; | |
583 | int ret; | |
584 | ||
585 | ret = ecard_request_resources(ec); | |
586 | if (ret) | |
587 | goto out; | |
588 | ||
cc60d8ba | 589 | state = kzalloc(sizeof(struct icside_state), GFP_KERNEL); |
1da177e4 LT |
590 | if (!state) { |
591 | ret = -ENOMEM; | |
592 | goto release; | |
593 | } | |
594 | ||
1da177e4 | 595 | state->type = ICS_TYPE_NOTYPE; |
1da177e4 | 596 | |
10bdaaa0 | 597 | idmem = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0); |
1da177e4 LT |
598 | if (idmem) { |
599 | unsigned int type; | |
600 | ||
601 | type = readb(idmem + ICS_IDENT_OFFSET) & 1; | |
602 | type |= (readb(idmem + ICS_IDENT_OFFSET + 4) & 1) << 1; | |
603 | type |= (readb(idmem + ICS_IDENT_OFFSET + 8) & 1) << 2; | |
604 | type |= (readb(idmem + ICS_IDENT_OFFSET + 12) & 1) << 3; | |
10bdaaa0 | 605 | ecardm_iounmap(ec, idmem); |
1da177e4 LT |
606 | |
607 | state->type = type; | |
608 | } | |
609 | ||
610 | switch (state->type) { | |
611 | case ICS_TYPE_A3IN: | |
612 | dev_warn(&ec->dev, "A3IN unsupported\n"); | |
613 | ret = -ENODEV; | |
614 | break; | |
615 | ||
616 | case ICS_TYPE_A3USER: | |
617 | dev_warn(&ec->dev, "A3USER unsupported\n"); | |
618 | ret = -ENODEV; | |
619 | break; | |
620 | ||
621 | case ICS_TYPE_V5: | |
622 | ret = icside_register_v5(state, ec); | |
623 | break; | |
624 | ||
625 | case ICS_TYPE_V6: | |
626 | ret = icside_register_v6(state, ec); | |
627 | break; | |
628 | ||
629 | default: | |
630 | dev_warn(&ec->dev, "unknown interface type\n"); | |
631 | ret = -ENODEV; | |
632 | break; | |
633 | } | |
634 | ||
26839f09 | 635 | if (ret == 0) |
1da177e4 | 636 | goto out; |
1da177e4 LT |
637 | |
638 | kfree(state); | |
639 | release: | |
640 | ecard_release_resources(ec); | |
641 | out: | |
642 | return ret; | |
643 | } | |
644 | ||
645 | static void __devexit icside_remove(struct expansion_card *ec) | |
646 | { | |
647 | struct icside_state *state = ecard_get_drvdata(ec); | |
648 | ||
649 | switch (state->type) { | |
650 | case ICS_TYPE_V5: | |
651 | /* FIXME: tell IDE to stop using the interface */ | |
652 | ||
653 | /* Disable interrupts */ | |
654 | icside_irqdisable_arcin_v5(ec, 0); | |
655 | break; | |
656 | ||
657 | case ICS_TYPE_V6: | |
658 | /* FIXME: tell IDE to stop using the interface */ | |
659 | if (ec->dma != NO_DMA) | |
660 | free_dma(ec->dma); | |
661 | ||
662 | /* Disable interrupts */ | |
663 | icside_irqdisable_arcin_v6(ec, 0); | |
664 | ||
665 | /* Reset the ROM pointer/EASI selection */ | |
666 | writeb(0, state->ioc_base); | |
667 | break; | |
668 | } | |
669 | ||
670 | ecard_set_drvdata(ec, NULL); | |
1da177e4 | 671 | |
1da177e4 LT |
672 | kfree(state); |
673 | ecard_release_resources(ec); | |
674 | } | |
675 | ||
676 | static void icside_shutdown(struct expansion_card *ec) | |
677 | { | |
678 | struct icside_state *state = ecard_get_drvdata(ec); | |
679 | unsigned long flags; | |
680 | ||
681 | /* | |
682 | * Disable interrupts from this card. We need to do | |
683 | * this before disabling EASI since we may be accessing | |
684 | * this register via that region. | |
685 | */ | |
686 | local_irq_save(flags); | |
687 | ec->ops->irqdisable(ec, 0); | |
688 | local_irq_restore(flags); | |
689 | ||
690 | /* | |
691 | * Reset the ROM pointer so that we can read the ROM | |
692 | * after a soft reboot. This also disables access to | |
693 | * the IDE taskfile via the EASI region. | |
694 | */ | |
695 | if (state->ioc_base) | |
696 | writeb(0, state->ioc_base); | |
697 | } | |
698 | ||
699 | static const struct ecard_id icside_ids[] = { | |
700 | { MANU_ICS, PROD_ICS_IDE }, | |
701 | { MANU_ICS2, PROD_ICS2_IDE }, | |
702 | { 0xffff, 0xffff } | |
703 | }; | |
704 | ||
705 | static struct ecard_driver icside_driver = { | |
706 | .probe = icside_probe, | |
707 | .remove = __devexit_p(icside_remove), | |
708 | .shutdown = icside_shutdown, | |
709 | .id_table = icside_ids, | |
710 | .drv = { | |
711 | .name = "icside", | |
712 | }, | |
713 | }; | |
714 | ||
715 | static int __init icside_init(void) | |
716 | { | |
717 | return ecard_register_driver(&icside_driver); | |
718 | } | |
719 | ||
720 | MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>"); | |
721 | MODULE_LICENSE("GPL"); | |
722 | MODULE_DESCRIPTION("ICS IDE driver"); | |
723 | ||
724 | module_init(icside_init); |