[deliverable/linux.git] / drivers / ide / arm / icside.c

/*
 * Copyright (c) 1996-2004 Russell King.
 *
 * Please note that this platform does not support 32-bit IDE IO.
 */

#include <linux/string.h>
#include <linux/module.h>
#include <linux/ioport.h>
#include <linux/slab.h>
#include <linux/blkdev.h>
#include <linux/errno.h>
#include <linux/hdreg.h>
#include <linux/ide.h>
#include <linux/dma-mapping.h>
#include <linux/device.h>
#include <linux/init.h>
#include <linux/scatterlist.h>
#include <linux/io.h>

#include <asm/dma.h>
#include <asm/ecard.h>

#define ICS_IDENT_OFFSET		0x2280

#define ICS_ARCIN_V5_INTRSTAT		0x0000
#define ICS_ARCIN_V5_INTROFFSET		0x0004
#define ICS_ARCIN_V5_IDEOFFSET		0x2800
#define ICS_ARCIN_V5_IDEALTOFFSET	0x2b80
#define ICS_ARCIN_V5_IDESTEPPING	6

#define ICS_ARCIN_V6_IDEOFFSET_1	0x2000
#define ICS_ARCIN_V6_INTROFFSET_1	0x2200
#define ICS_ARCIN_V6_INTRSTAT_1		0x2290
#define ICS_ARCIN_V6_IDEALTOFFSET_1	0x2380
#define ICS_ARCIN_V6_IDEOFFSET_2	0x3000
#define ICS_ARCIN_V6_INTROFFSET_2	0x3200
#define ICS_ARCIN_V6_INTRSTAT_2		0x3290
#define ICS_ARCIN_V6_IDEALTOFFSET_2	0x3380
#define ICS_ARCIN_V6_IDESTEPPING	6

struct cardinfo {
	unsigned int dataoffset;
	unsigned int ctrloffset;
	unsigned int stepping;
};

static struct cardinfo icside_cardinfo_v5 = {
	.dataoffset	= ICS_ARCIN_V5_IDEOFFSET,
	.ctrloffset	= ICS_ARCIN_V5_IDEALTOFFSET,
	.stepping	= ICS_ARCIN_V5_IDESTEPPING,
};

static struct cardinfo icside_cardinfo_v6_1 = {
	.dataoffset	= ICS_ARCIN_V6_IDEOFFSET_1,
	.ctrloffset	= ICS_ARCIN_V6_IDEALTOFFSET_1,
	.stepping	= ICS_ARCIN_V6_IDESTEPPING,
};

static struct cardinfo icside_cardinfo_v6_2 = {
	.dataoffset	= ICS_ARCIN_V6_IDEOFFSET_2,
	.ctrloffset	= ICS_ARCIN_V6_IDEALTOFFSET_2,
	.stepping	= ICS_ARCIN_V6_IDESTEPPING,
};

struct icside_state {
	unsigned int channel;
	unsigned int enabled;
	void __iomem *irq_port;
	void __iomem *ioc_base;
	unsigned int type;
	ide_hwif_t *hwif[2];
};

#define ICS_TYPE_A3IN	0
#define ICS_TYPE_A3USER	1
#define ICS_TYPE_V6	3
#define ICS_TYPE_V5	15
#define ICS_TYPE_NOTYPE	((unsigned int)-1)

/* ---------------- Version 5 PCB Support Functions --------------------- */
/* Prototype: icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
 * Purpose  : enable interrupts from card
 */
static void icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
{
	struct icside_state *state = ec->irq_data;

	writeb(0, state->irq_port + ICS_ARCIN_V5_INTROFFSET);
}

/* Prototype: icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
 * Purpose  : disable interrupts from card
 */
static void icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
{
	struct icside_state *state = ec->irq_data;

	readb(state->irq_port + ICS_ARCIN_V5_INTROFFSET);
}

static const expansioncard_ops_t icside_ops_arcin_v5 = {
	.irqenable	= icside_irqenable_arcin_v5,
	.irqdisable	= icside_irqdisable_arcin_v5,
};


/* ---------------- Version 6 PCB Support Functions --------------------- */
/* Prototype: icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
 * Purpose  : enable interrupts from card
 */
static void icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
{
	struct icside_state *state = ec->irq_data;
	void __iomem *base = state->irq_port;

	state->enabled = 1;

	switch (state->channel) {
	case 0:
		writeb(0, base + ICS_ARCIN_V6_INTROFFSET_1);
		readb(base + ICS_ARCIN_V6_INTROFFSET_2);
		break;
	case 1:
		writeb(0, base + ICS_ARCIN_V6_INTROFFSET_2);
		readb(base + ICS_ARCIN_V6_INTROFFSET_1);
		break;
	}
}

/* Prototype: icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
 * Purpose  : disable interrupts from card
 */
static void icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
{
	struct icside_state *state = ec->irq_data;

	state->enabled = 0;

	readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
	readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
}

/* Prototype: icside_irqprobe(struct expansion_card *ec)
 * Purpose  : detect an active interrupt from card
 */
static int icside_irqpending_arcin_v6(struct expansion_card *ec)
{
	struct icside_state *state = ec->irq_data;

	return readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_1) & 1 ||
	       readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_2) & 1;
}

static const expansioncard_ops_t icside_ops_arcin_v6 = {
	.irqenable	= icside_irqenable_arcin_v6,
	.irqdisable	= icside_irqdisable_arcin_v6,
	.irqpending	= icside_irqpending_arcin_v6,
};

/*
 * Handle routing of interrupts.  This is called before
 * we write the command to the drive.
 */
static void icside_maskproc(ide_drive_t *drive, int mask)
{
	ide_hwif_t *hwif = HWIF(drive);
	struct icside_state *state = hwif->hwif_data;
	unsigned long flags;

	local_irq_save(flags);

	state->channel = hwif->channel;

	if (state->enabled && !mask) {
		switch (hwif->channel) {
		case 0:
			writeb(0, state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
			readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
			break;
		case 1:
			writeb(0, state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
			readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
			break;
		}
	} else {
		readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
		readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
	}

	local_irq_restore(flags);
}

static const struct ide_port_ops icside_v6_no_dma_port_ops = {
	.maskproc		= icside_maskproc,
};

#ifdef CONFIG_BLK_DEV_IDEDMA_ICS
/*
 * SG-DMA support.
 *
 * Similar to the BM-DMA, but we use the RiscPCs IOMD DMA controllers.
 * There is only one DMA controller per card, which means that only
 * one drive can be accessed at one time.  NOTE! We do not enforce that
 * here, but we rely on the main IDE driver spotting that both
 * interfaces use the same IRQ, which should guarantee this.
 */

/*
 * Configure the IOMD to give the appropriate timings for the transfer
 * mode being requested.  We take the advice of the ATA standards, and
 * calculate the cycle time based on the transfer mode, and the EIDE
 * MW DMA specs that the drive provides in the IDENTIFY command.
 *
 * We have the following IOMD DMA modes to choose from:
 *
 *	Type	Active		Recovery	Cycle
 *	A	250 (250)	312 (550)	562 (800)
 *	B	187		250		437
 *	C	125 (125)	125 (375)	250 (500)
 *	D	62		125		187
 *
 * (figures in brackets are actual measured timings)
 *
 * However, we also need to take care of the read/write active and
 * recovery timings:
 *
 *			Read	Write
 *  	Mode	Active	-- Recovery --	Cycle	IOMD type
 *	MW0	215	50	215	480	A
 *	MW1	80	50	50	150	C
 *	MW2	70	25	25	120	C
 */
static void icside_set_dma_mode(ide_drive_t *drive, const u8 xfer_mode)
{
	int cycle_time, use_dma_info = 0;

	switch (xfer_mode) {
	case XFER_MW_DMA_2:
		cycle_time = 250;
		use_dma_info = 1;
		break;

	case XFER_MW_DMA_1:
		cycle_time = 250;
		use_dma_info = 1;
		break;

	case XFER_MW_DMA_0:
		cycle_time = 480;
		break;

	case XFER_SW_DMA_2:
	case XFER_SW_DMA_1:
	case XFER_SW_DMA_0:
		cycle_time = 480;
		break;
	}

	/*
	 * If we're going to be doing MW_DMA_1 or MW_DMA_2, we should
	 * take care to note the values in the ID...
	 */
	if (use_dma_info && drive->id->eide_dma_time > cycle_time)
		cycle_time = drive->id->eide_dma_time;

	drive->drive_data = cycle_time;

	printk("%s: %s selected (peak %dMB/s)\n", drive->name,
		ide_xfer_verbose(xfer_mode), 2000 / drive->drive_data);
}

static const struct ide_port_ops icside_v6_port_ops = {
	.set_dma_mode		= icside_set_dma_mode,
	.maskproc		= icside_maskproc,
};

static void icside_dma_host_set(ide_drive_t *drive, int on)
{
}

static int icside_dma_end(ide_drive_t *drive)
{
	ide_hwif_t *hwif = HWIF(drive);
	struct expansion_card *ec = ECARD_DEV(hwif->dev);

	drive->waiting_for_dma = 0;

	disable_dma(ec->dma);

	/* Teardown mappings after DMA has completed. */
	ide_destroy_dmatable(drive);

	return get_dma_residue(ec->dma) != 0;
}

static void icside_dma_start(ide_drive_t *drive)
{
	ide_hwif_t *hwif = HWIF(drive);
	struct expansion_card *ec = ECARD_DEV(hwif->dev);

	/* We can not enable DMA on both channels simultaneously. */
	BUG_ON(dma_channel_active(ec->dma));
	enable_dma(ec->dma);
}

static int icside_dma_setup(ide_drive_t *drive)
{
	ide_hwif_t *hwif = HWIF(drive);
	struct expansion_card *ec = ECARD_DEV(hwif->dev);
	struct request *rq = hwif->hwgroup->rq;
	unsigned int dma_mode;

	if (rq_data_dir(rq))
		dma_mode = DMA_MODE_WRITE;
	else
		dma_mode = DMA_MODE_READ;

	/*
	 * We can not enable DMA on both channels.
	 */
	BUG_ON(dma_channel_active(ec->dma));

	hwif->sg_nents = ide_build_sglist(drive, rq);

	/*
	 * Ensure that we have the right interrupt routed.
	 */
	icside_maskproc(drive, 0);

	/*
	 * Route the DMA signals to the correct interface.
	 */
	writeb(hwif->select_data, hwif->config_data);

	/*
	 * Select the correct timing for this drive.
	 */
	set_dma_speed(ec->dma, drive->drive_data);

	/*
	 * Tell the DMA engine about the SG table and
	 * data direction.
	 */
	set_dma_sg(ec->dma, hwif->sg_table, hwif->sg_nents);
	set_dma_mode(ec->dma, dma_mode);

	drive->waiting_for_dma = 1;

	return 0;
}

static void icside_dma_exec_cmd(ide_drive_t *drive, u8 cmd)
{
	/* issue cmd to drive */
	ide_execute_command(drive, cmd, ide_dma_intr, 2 * WAIT_CMD, NULL);
}

static int icside_dma_test_irq(ide_drive_t *drive)
{
	ide_hwif_t *hwif = HWIF(drive);
	struct icside_state *state = hwif->hwif_data;

	return readb(state->irq_port +
		     (hwif->channel ?
			ICS_ARCIN_V6_INTRSTAT_2 :
			ICS_ARCIN_V6_INTRSTAT_1)) & 1;
}

static void icside_dma_timeout(ide_drive_t *drive)
{
	printk(KERN_ERR "%s: DMA timeout occurred: ", drive->name);

	if (icside_dma_test_irq(drive))
		return;

	ide_dump_status(drive, "DMA timeout", ide_read_status(drive));

	icside_dma_end(drive);
}

static void icside_dma_lost_irq(ide_drive_t *drive)
{
	printk(KERN_ERR "%s: IRQ lost\n", drive->name);
}

static void icside_dma_init(ide_hwif_t *hwif)
{
	hwif->dmatable_cpu	= NULL;
	hwif->dmatable_dma	= 0;

	hwif->dma_host_set	= icside_dma_host_set;
	hwif->dma_setup		= icside_dma_setup;
	hwif->dma_exec_cmd	= icside_dma_exec_cmd;
	hwif->dma_start		= icside_dma_start;
	hwif->ide_dma_end	= icside_dma_end;
	hwif->ide_dma_test_irq	= icside_dma_test_irq;
	hwif->dma_timeout	= icside_dma_timeout;
	hwif->dma_lost_irq	= icside_dma_lost_irq;
}
#else
#define icside_dma_init(hwif)	(0)
#endif

static ide_hwif_t *
icside_setup(void __iomem *base, struct cardinfo *info, struct expansion_card *ec)
{
	unsigned long port = (unsigned long)base + info->dataoffset;
	ide_hwif_t *hwif;

	hwif = ide_find_port();
	if (hwif) {
		int i;

		/*
		 * Ensure we're using MMIO
		 */
		default_hwif_mmiops(hwif);
		hwif->mmio = 1;

		for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) {
			hwif->io_ports[i] = port;
			port += 1 << info->stepping;
		}
		hwif->io_ports[IDE_CONTROL_OFFSET] = (unsigned long)base + info->ctrloffset;
		hwif->irq     = ec->irq;
		hwif->noprobe = 0;
		hwif->chipset = ide_acorn;
		hwif->gendev.parent = &ec->dev;
		hwif->dev = &ec->dev;
	}

	return hwif;
}

static int __init
icside_register_v5(struct icside_state *state, struct expansion_card *ec)
{
	ide_hwif_t *hwif;
	void __iomem *base;
	u8 idx[4] = { 0xff, 0xff, 0xff, 0xff };

	base = ecardm_iomap(ec, ECARD_RES_MEMC, 0, 0);
	if (!base)
		return -ENOMEM;

	state->irq_port = base;

	ec->irqaddr  = base + ICS_ARCIN_V5_INTRSTAT;
	ec->irqmask  = 1;

	ecard_setirq(ec, &icside_ops_arcin_v5, state);

	/*
	 * Be on the safe side - disable interrupts
	 */
	icside_irqdisable_arcin_v5(ec, 0);

	hwif = icside_setup(base, &icside_cardinfo_v5, ec);
	if (!hwif)
		return -ENODEV;

	state->hwif[0] = hwif;

	idx[0] = hwif->index;

	ide_device_add(idx, NULL);

	return 0;
}

static const struct ide_port_info icside_v6_port_info __initdata = {
	.port_ops		= &icside_v6_no_dma_port_ops,
	.host_flags		= IDE_HFLAG_SERIALIZE |
				  IDE_HFLAG_NO_DMA | /* no SFF-style DMA */
				  IDE_HFLAG_NO_AUTOTUNE,
	.mwdma_mask		= ATA_MWDMA2,
	.swdma_mask		= ATA_SWDMA2,
};

static int __init
icside_register_v6(struct icside_state *state, struct expansion_card *ec)
{
	ide_hwif_t *hwif, *mate;
	void __iomem *ioc_base, *easi_base;
	unsigned int sel = 0;
	int ret;
	u8 idx[4] = { 0xff, 0xff, 0xff, 0xff };
	struct ide_port_info d = icside_v6_port_info;

	ioc_base = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);
	if (!ioc_base) {
		ret = -ENOMEM;
		goto out;
	}

	easi_base = ioc_base;

	if (ecard_resource_flags(ec, ECARD_RES_EASI)) {
		easi_base = ecardm_iomap(ec, ECARD_RES_EASI, 0, 0);
		if (!easi_base) {
			ret = -ENOMEM;
			goto out;
		}

		/*
		 * Enable access to the EASI region.
		 */
		sel = 1 << 5;
	}

	writeb(sel, ioc_base);

	ecard_setirq(ec, &icside_ops_arcin_v6, state);

	state->irq_port   = easi_base;
	state->ioc_base   = ioc_base;

	/*
	 * Be on the safe side - disable interrupts
	 */
	icside_irqdisable_arcin_v6(ec, 0);

	/*
	 * Find and register the interfaces.
	 */
	hwif = icside_setup(easi_base, &icside_cardinfo_v6_1, ec);
	mate = icside_setup(easi_base, &icside_cardinfo_v6_2, ec);

	if (!hwif || !mate) {
		ret = -ENODEV;
		goto out;
	}

	state->hwif[0]    = hwif;
	state->hwif[1]    = mate;

	hwif->hwif_data   = state;
	hwif->config_data = (unsigned long)ioc_base;
	hwif->select_data = sel;

	mate->maskproc    = icside_maskproc;
	mate->hwif_data   = state;
	mate->config_data = (unsigned long)ioc_base;
	mate->select_data = sel | 1;

	if (ec->dma != NO_DMA && !request_dma(ec->dma, hwif->name)) {
		icside_dma_init(hwif);
		icside_dma_init(mate);
		d.port_ops = &icside_v6_dma_port_ops;
	} else
		d.mwdma_mask = d.swdma_mask = 0;

	idx[0] = hwif->index;
	idx[1] = mate->index;

	ide_device_add(idx, &d);

	return 0;

 out:
	return ret;
}

static int __devinit
icside_probe(struct expansion_card *ec, const struct ecard_id *id)
{
	struct icside_state *state;
	void __iomem *idmem;
	int ret;

	ret = ecard_request_resources(ec);
	if (ret)
		goto out;

	state = kzalloc(sizeof(struct icside_state), GFP_KERNEL);
	if (!state) {
		ret = -ENOMEM;
		goto release;
	}

	state->type	= ICS_TYPE_NOTYPE;

	idmem = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);
	if (idmem) {
		unsigned int type;

		type = readb(idmem + ICS_IDENT_OFFSET) & 1;
		type |= (readb(idmem + ICS_IDENT_OFFSET + 4) & 1) << 1;
		type |= (readb(idmem + ICS_IDENT_OFFSET + 8) & 1) << 2;
		type |= (readb(idmem + ICS_IDENT_OFFSET + 12) & 1) << 3;
		ecardm_iounmap(ec, idmem);

		state->type = type;
	}

	switch (state->type) {
	case ICS_TYPE_A3IN:
		dev_warn(&ec->dev, "A3IN unsupported\n");
		ret = -ENODEV;
		break;

	case ICS_TYPE_A3USER:
		dev_warn(&ec->dev, "A3USER unsupported\n");
		ret = -ENODEV;
		break;

	case ICS_TYPE_V5:
		ret = icside_register_v5(state, ec);
		break;

	case ICS_TYPE_V6:
		ret = icside_register_v6(state, ec);
		break;

	default:
		dev_warn(&ec->dev, "unknown interface type\n");
		ret = -ENODEV;
		break;
	}

	if (ret == 0) {
		ecard_set_drvdata(ec, state);
		goto out;
	}

	kfree(state);
 release:
	ecard_release_resources(ec);
 out:
	return ret;
}

static void __devexit icside_remove(struct expansion_card *ec)
{
	struct icside_state *state = ecard_get_drvdata(ec);

	switch (state->type) {
	case ICS_TYPE_V5:
		/* FIXME: tell IDE to stop using the interface */

		/* Disable interrupts */
		icside_irqdisable_arcin_v5(ec, 0);
		break;

	case ICS_TYPE_V6:
		/* FIXME: tell IDE to stop using the interface */
		if (ec->dma != NO_DMA)
			free_dma(ec->dma);

		/* Disable interrupts */
		icside_irqdisable_arcin_v6(ec, 0);

		/* Reset the ROM pointer/EASI selection */
		writeb(0, state->ioc_base);
		break;
	}

	ecard_set_drvdata(ec, NULL);

	kfree(state);
	ecard_release_resources(ec);
}

static void icside_shutdown(struct expansion_card *ec)
{
	struct icside_state *state = ecard_get_drvdata(ec);
	unsigned long flags;

	/*
	 * Disable interrupts from this card.  We need to do
	 * this before disabling EASI since we may be accessing
	 * this register via that region.
	 */
	local_irq_save(flags);
	ec->ops->irqdisable(ec, 0);
	local_irq_restore(flags);

	/*
	 * Reset the ROM pointer so that we can read the ROM
	 * after a soft reboot.  This also disables access to
	 * the IDE taskfile via the EASI region.
	 */
	if (state->ioc_base)
		writeb(0, state->ioc_base);
}

static const struct ecard_id icside_ids[] = {
	{ MANU_ICS,  PROD_ICS_IDE  },
	{ MANU_ICS2, PROD_ICS2_IDE },
	{ 0xffff, 0xffff }
};

static struct ecard_driver icside_driver = {
	.probe		= icside_probe,
	.remove		= __devexit_p(icside_remove),
	.shutdown	= icside_shutdown,
	.id_table	= icside_ids,
	.drv = {
		.name	= "icside",
	},
};

static int __init icside_init(void)
{
	return ecard_register_driver(&icside_driver);
}

MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>");
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("ICS IDE driver");

module_init(icside_init);
Commit	Line	Data
1da177e4	1	/*
1da177e4 LT	2	* Copyright (c) 1996-2004 Russell King.
	3	*
	4	* Please note that this platform does not support 32-bit IDE IO.
	5	*/
	6
1da177e4 LT	7	#include <linux/string.h>
	8	#include <linux/module.h>
	9	#include <linux/ioport.h>
	10	#include <linux/slab.h>
	11	#include <linux/blkdev.h>
	12	#include <linux/errno.h>
	13	#include <linux/hdreg.h>
	14	#include <linux/ide.h>
	15	#include <linux/dma-mapping.h>
	16	#include <linux/device.h>
	17	#include <linux/init.h>
	18	#include <linux/scatterlist.h>
ba5b55d0	19	#include <linux/io.h>
1da177e4 LT	20
	21	#include <asm/dma.h>
	22	#include <asm/ecard.h>
1da177e4 LT	23
	24	#define ICS_IDENT_OFFSET 0x2280
	25
	26	#define ICS_ARCIN_V5_INTRSTAT 0x0000
	27	#define ICS_ARCIN_V5_INTROFFSET 0x0004
	28	#define ICS_ARCIN_V5_IDEOFFSET 0x2800
	29	#define ICS_ARCIN_V5_IDEALTOFFSET 0x2b80
	30	#define ICS_ARCIN_V5_IDESTEPPING 6
	31
	32	#define ICS_ARCIN_V6_IDEOFFSET_1 0x2000
	33	#define ICS_ARCIN_V6_INTROFFSET_1 0x2200
	34	#define ICS_ARCIN_V6_INTRSTAT_1 0x2290
	35	#define ICS_ARCIN_V6_IDEALTOFFSET_1 0x2380
	36	#define ICS_ARCIN_V6_IDEOFFSET_2 0x3000
	37	#define ICS_ARCIN_V6_INTROFFSET_2 0x3200
	38	#define ICS_ARCIN_V6_INTRSTAT_2 0x3290
	39	#define ICS_ARCIN_V6_IDEALTOFFSET_2 0x3380
	40	#define ICS_ARCIN_V6_IDESTEPPING 6
	41
	42	struct cardinfo {
	43	unsigned int dataoffset;
	44	unsigned int ctrloffset;
	45	unsigned int stepping;
	46	};
	47
	48	static struct cardinfo icside_cardinfo_v5 = {
	49	.dataoffset = ICS_ARCIN_V5_IDEOFFSET,
	50	.ctrloffset = ICS_ARCIN_V5_IDEALTOFFSET,
	51	.stepping = ICS_ARCIN_V5_IDESTEPPING,
	52	};
	53
	54	static struct cardinfo icside_cardinfo_v6_1 = {
	55	.dataoffset = ICS_ARCIN_V6_IDEOFFSET_1,
	56	.ctrloffset = ICS_ARCIN_V6_IDEALTOFFSET_1,
	57	.stepping = ICS_ARCIN_V6_IDESTEPPING,
	58	};
	59
	60	static struct cardinfo icside_cardinfo_v6_2 = {
	61	.dataoffset = ICS_ARCIN_V6_IDEOFFSET_2,
	62	.ctrloffset = ICS_ARCIN_V6_IDEALTOFFSET_2,
	63	.stepping = ICS_ARCIN_V6_IDESTEPPING,
	64	};
	65
	66	struct icside_state {
	67	unsigned int channel;
	68	unsigned int enabled;
	69	void __iomem *irq_port;
	70	void __iomem *ioc_base;
	71	unsigned int type;
1da177e4 LT	72	ide_hwif_t *hwif[2];
	73	};
	74
	75	#define ICS_TYPE_A3IN 0
	76	#define ICS_TYPE_A3USER 1
	77	#define ICS_TYPE_V6 3
	78	#define ICS_TYPE_V5 15
	79	#define ICS_TYPE_NOTYPE ((unsigned int)-1)
	80
	81	/* ---------------- Version 5 PCB Support Functions --------------------- */
	82	/* Prototype: icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
	83	* Purpose : enable interrupts from card
	84	*/
	85	static void icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
	86	{
	87	struct icside_state *state = ec->irq_data;
	88
	89	writeb(0, state->irq_port + ICS_ARCIN_V5_INTROFFSET);
	90	}
	91
	92	/* Prototype: icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
	93	* Purpose : disable interrupts from card
	94	*/
	95	static void icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
	96	{
	97	struct icside_state *state = ec->irq_data;
	98
	99	readb(state->irq_port + ICS_ARCIN_V5_INTROFFSET);
	100	}
	101
	102	static const expansioncard_ops_t icside_ops_arcin_v5 = {
	103	.irqenable = icside_irqenable_arcin_v5,
	104	.irqdisable = icside_irqdisable_arcin_v5,
	105	};
	106
	107
	108	/* ---------------- Version 6 PCB Support Functions --------------------- */
	109	/* Prototype: icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
	110	* Purpose : enable interrupts from card
	111	*/
	112	static void icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
	113	{
	114	struct icside_state *state = ec->irq_data;
	115	void __iomem *base = state->irq_port;
	116
	117	state->enabled = 1;
	118
	119	switch (state->channel) {
	120	case 0:
	121	writeb(0, base + ICS_ARCIN_V6_INTROFFSET_1);
	122	readb(base + ICS_ARCIN_V6_INTROFFSET_2);
	123	break;
	124	case 1:
	125	writeb(0, base + ICS_ARCIN_V6_INTROFFSET_2);
	126	readb(base + ICS_ARCIN_V6_INTROFFSET_1);
	127	break;
	128	}
	129	}
	130
	131	/* Prototype: icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
	132	* Purpose : disable interrupts from card
	133	*/
	134	static void icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
	135	{
136	struct icside_state *state = ec->irq_data;
137
138	state->enabled = 0;
139
140	readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
141	readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
142	}
143
144	/* Prototype: icside_irqprobe(struct expansion_card *ec)
145	* Purpose : detect an active interrupt from card
146	*/
147	static int icside_irqpending_arcin_v6(struct expansion_card *ec)
148	{
149	struct icside_state *state = ec->irq_data;
150
151	return readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_1) & 1 \|\|
152	readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_2) & 1;
153	}
154
155	static const expansioncard_ops_t icside_ops_arcin_v6 = {
156	.irqenable = icside_irqenable_arcin_v6,
157	.irqdisable = icside_irqdisable_arcin_v6,
158	.irqpending = icside_irqpending_arcin_v6,
159	};
160
161	/*
162	* Handle routing of interrupts. This is called before
163	* we write the command to the drive.
164	*/
165	static void icside_maskproc(ide_drive_t *drive, int mask)
166	{
167	ide_hwif_t *hwif = HWIF(drive);
168	struct icside_state *state = hwif->hwif_data;
169	unsigned long flags;
170
171	local_irq_save(flags);
172
173	state->channel = hwif->channel;
174
175	if (state->enabled && !mask) {
176	switch (hwif->channel) {
177	case 0:
178	writeb(0, state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
179	readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
180	break;
181	case 1:
182	writeb(0, state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
183	readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
184	break;
185	}
186	} else {
187	readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
188	readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
189	}
190
191	local_irq_restore(flags);
192	}
193
ac95beed BZ	194	static const struct ide_port_ops icside_v6_no_dma_port_ops = {
	195	.maskproc = icside_maskproc,
	196	};
	197
1da177e4	198	#ifdef CONFIG_BLK_DEV_IDEDMA_ICS
1da177e4 LT	199	/*
	200	* SG-DMA support.
	201	*
	202	* Similar to the BM-DMA, but we use the RiscPCs IOMD DMA controllers.
	203	* There is only one DMA controller per card, which means that only
	204	* one drive can be accessed at one time. NOTE! We do not enforce that
	205	* here, but we rely on the main IDE driver spotting that both
	206	* interfaces use the same IRQ, which should guarantee this.
	207	*/
	208
1da177e4 LT	209	/*
	210	* Configure the IOMD to give the appropriate timings for the transfer
	211	* mode being requested. We take the advice of the ATA standards, and
	212	* calculate the cycle time based on the transfer mode, and the EIDE
	213	* MW DMA specs that the drive provides in the IDENTIFY command.
	214	*
	215	* We have the following IOMD DMA modes to choose from:
	216	*
	217	* Type Active Recovery Cycle
	218	* A 250 (250) 312 (550) 562 (800)
	219	* B 187 250 437
	220	* C 125 (125) 125 (375) 250 (500)
	221	* D 62 125 187
	222	*
	223	* (figures in brackets are actual measured timings)
	224	*
	225	* However, we also need to take care of the read/write active and
	226	* recovery timings:
	227	*
	228	* Read Write
	229	* Mode Active -- Recovery -- Cycle IOMD type
	230	* MW0 215 50 215 480 A
	231	* MW1 80 50 50 150 C
	232	* MW2 70 25 25 120 C
	233	*/
88b2b32b	234	static void icside_set_dma_mode(ide_drive_t *drive, const u8 xfer_mode)
1da177e4	235	{
f44ae58a	236	int cycle_time, use_dma_info = 0;
1da177e4	237
1da177e4 LT	238	switch (xfer_mode) {
	239	case XFER_MW_DMA_2:
	240	cycle_time = 250;
	241	use_dma_info = 1;
	242	break;
	243
	244	case XFER_MW_DMA_1:
	245	cycle_time = 250;
	246	use_dma_info = 1;
	247	break;
	248
	249	case XFER_MW_DMA_0:
	250	cycle_time = 480;
	251	break;
	252
	253	case XFER_SW_DMA_2:
	254	case XFER_SW_DMA_1:
	255	case XFER_SW_DMA_0:
	256	cycle_time = 480;
	257	break;
	258	}
	259
	260	/*
	261	* If we're going to be doing MW_DMA_1 or MW_DMA_2, we should
	262	* take care to note the values in the ID...
	263	*/
	264	if (use_dma_info && drive->id->eide_dma_time > cycle_time)
	265	cycle_time = drive->id->eide_dma_time;
	266
	267	drive->drive_data = cycle_time;
	268
1da177e4 LT	269	printk("%s: %s selected (peak %dMB/s)\n", drive->name,
1da177e4 LT	270	ide_xfer_verbose(xfer_mode), 2000 / drive->drive_data);
1da177e4 LT	271	}
1da177e4 LT	272
ac95beed BZ	273	static const struct ide_port_ops icside_v6_port_ops = {
	274	.set_dma_mode = icside_set_dma_mode,
	275	.maskproc = icside_maskproc,
	276	};
	277
15ce926a	278	static void icside_dma_host_set(ide_drive_t *drive, int on)
1da177e4	279	{
1da177e4 LT	280	}
1da177e4 LT	281
1da177e4 LT	282	static int icside_dma_end(ide_drive_t *drive)
	283	{
	284	ide_hwif_t *hwif = HWIF(drive);
f8341c1c	285	struct expansion_card *ec = ECARD_DEV(hwif->dev);
1da177e4 LT	286
	287	drive->waiting_for_dma = 0;
	288
f8341c1c	289	disable_dma(ec->dma);
1da177e4 LT	290
1da177e4 LT	291	/* Teardown mappings after DMA has completed. */
062f9f02	292	ide_destroy_dmatable(drive);
1da177e4	293
f8341c1c	294	return get_dma_residue(ec->dma) != 0;
1da177e4 LT	295	}
	296
	297	static void icside_dma_start(ide_drive_t *drive)
	298	{
	299	ide_hwif_t *hwif = HWIF(drive);
f8341c1c	300	struct expansion_card *ec = ECARD_DEV(hwif->dev);
1da177e4 LT	301
1da177e4 LT	302	/* We can not enable DMA on both channels simultaneously. */
f8341c1c BZ	303	BUG_ON(dma_channel_active(ec->dma));
f8341c1c BZ	304	enable_dma(ec->dma);
1da177e4 LT	305	}
	306
	307	static int icside_dma_setup(ide_drive_t *drive)
	308	{
	309	ide_hwif_t *hwif = HWIF(drive);
f8341c1c	310	struct expansion_card *ec = ECARD_DEV(hwif->dev);
1da177e4 LT	311	struct request *rq = hwif->hwgroup->rq;
	312	unsigned int dma_mode;
	313
	314	if (rq_data_dir(rq))
	315	dma_mode = DMA_MODE_WRITE;
	316	else
	317	dma_mode = DMA_MODE_READ;
	318
	319	/*
	320	* We can not enable DMA on both channels.
	321	*/
f8341c1c	322	BUG_ON(dma_channel_active(ec->dma));
1da177e4	323
062f9f02	324	hwif->sg_nents = ide_build_sglist(drive, rq);
1da177e4 LT	325
	326	/*
	327	* Ensure that we have the right interrupt routed.
	328	*/
	329	icside_maskproc(drive, 0);
	330
	331	/*
	332	* Route the DMA signals to the correct interface.
	333	*/
	334	writeb(hwif->select_data, hwif->config_data);
	335
	336	/*
	337	* Select the correct timing for this drive.
	338	*/
f8341c1c	339	set_dma_speed(ec->dma, drive->drive_data);
1da177e4 LT	340
	341	/*
	342	* Tell the DMA engine about the SG table and
	343	* data direction.
	344	*/
f8341c1c BZ	345	set_dma_sg(ec->dma, hwif->sg_table, hwif->sg_nents);
f8341c1c BZ	346	set_dma_mode(ec->dma, dma_mode);
1da177e4 LT	347
	348	drive->waiting_for_dma = 1;
	349
	350	return 0;
	351	}
	352
	353	static void icside_dma_exec_cmd(ide_drive_t *drive, u8 cmd)
	354	{
	355	/* issue cmd to drive */
	356	ide_execute_command(drive, cmd, ide_dma_intr, 2 * WAIT_CMD, NULL);
	357	}
	358
	359	static int icside_dma_test_irq(ide_drive_t *drive)
	360	{
	361	ide_hwif_t *hwif = HWIF(drive);
	362	struct icside_state *state = hwif->hwif_data;
	363
	364	return readb(state->irq_port +
	365	(hwif->channel ?
	366	ICS_ARCIN_V6_INTRSTAT_2 :
	367	ICS_ARCIN_V6_INTRSTAT_1)) & 1;
	368	}
	369
c283f5db	370	static void icside_dma_timeout(ide_drive_t *drive)
1da177e4 LT	371	{
	372	printk(KERN_ERR "%s: DMA timeout occurred: ", drive->name);
	373
	374	if (icside_dma_test_irq(drive))
c283f5db	375	return;
1da177e4	376
c47137a9	377	ide_dump_status(drive, "DMA timeout", ide_read_status(drive));
1da177e4	378
c283f5db	379	icside_dma_end(drive);
1da177e4 LT	380	}
1da177e4 LT	381
841d2a9b	382	static void icside_dma_lost_irq(ide_drive_t *drive)
1da177e4 LT	383	{
1da177e4 LT	384	printk(KERN_ERR "%s: IRQ lost\n", drive->name);
1da177e4 LT	385	}
	386
	387	static void icside_dma_init(ide_hwif_t *hwif)
	388	{
1da177e4 LT	389	hwif->dmatable_cpu = NULL;
1da177e4 LT	390	hwif->dmatable_dma = 0;
1da177e4	391
15ce926a	392	hwif->dma_host_set = icside_dma_host_set;
1da177e4 LT	393	hwif->dma_setup = icside_dma_setup;
	394	hwif->dma_exec_cmd = icside_dma_exec_cmd;
	395	hwif->dma_start = icside_dma_start;
	396	hwif->ide_dma_end = icside_dma_end;
	397	hwif->ide_dma_test_irq = icside_dma_test_irq;
c283f5db	398	hwif->dma_timeout = icside_dma_timeout;
841d2a9b	399	hwif->dma_lost_irq = icside_dma_lost_irq;
1da177e4 LT	400	}
	401	#else
	402	#define icside_dma_init(hwif) (0)
	403	#endif
	404
1da177e4 LT	405	static ide_hwif_t *
	406	icside_setup(void __iomem base, struct cardinfo info, struct expansion_card *ec)
	407	{
	408	unsigned long port = (unsigned long)base + info->dataoffset;
	409	ide_hwif_t *hwif;
	410
59bff5ba	411	hwif = ide_find_port();
1da177e4 LT	412	if (hwif) {
	413	int i;
	414
1da177e4 LT	415	/*
	416	* Ensure we're using MMIO
	417	*/
	418	default_hwif_mmiops(hwif);
2ad1e558	419	hwif->mmio = 1;
1da177e4 LT	420
1da177e4 LT	421	for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) {
1da177e4 LT	422	hwif->io_ports[i] = port;
	423	port += 1 << info->stepping;
	424	}
1da177e4	425	hwif->io_ports[IDE_CONTROL_OFFSET] = (unsigned long)base + info->ctrloffset;
1da177e4 LT	426	hwif->irq = ec->irq;
	427	hwif->noprobe = 0;
	428	hwif->chipset = ide_acorn;
	429	hwif->gendev.parent = &ec->dev;
f8341c1c	430	hwif->dev = &ec->dev;
1da177e4 LT	431	}
	432
	433	return hwif;
	434	}
	435
	436	static int __init
	437	icside_register_v5(struct icside_state state, struct expansion_card ec)
	438	{
	439	ide_hwif_t *hwif;
	440	void __iomem *base;
8447d9d5	441	u8 idx[4] = { 0xff, 0xff, 0xff, 0xff };
1da177e4	442
10bdaaa0	443	base = ecardm_iomap(ec, ECARD_RES_MEMC, 0, 0);
1da177e4 LT	444	if (!base)
	445	return -ENOMEM;
	446
	447	state->irq_port = base;
	448
	449	ec->irqaddr = base + ICS_ARCIN_V5_INTRSTAT;
	450	ec->irqmask = 1;
c7b87f3d RK	451
c7b87f3d RK	452	ecard_setirq(ec, &icside_ops_arcin_v5, state);
1da177e4 LT	453
	454	/*
	455	* Be on the safe side - disable interrupts
	456	*/
	457	icside_irqdisable_arcin_v5(ec, 0);
	458
	459	hwif = icside_setup(base, &icside_cardinfo_v5, ec);
10bdaaa0	460	if (!hwif)
1da177e4	461	return -ENODEV;
1da177e4 LT	462
	463	state->hwif[0] = hwif;
	464
8447d9d5	465	idx[0] = hwif->index;
5cbf79cd	466
c413b9b9	467	ide_device_add(idx, NULL);
1da177e4 LT	468
	469	return 0;
	470	}
	471
c413b9b9	472	static const struct ide_port_info icside_v6_port_info __initdata = {
ac95beed	473	.port_ops = &icside_v6_no_dma_port_ops,
c413b9b9 BZ	474	.host_flags = IDE_HFLAG_SERIALIZE \|
	475	IDE_HFLAG_NO_DMA \| /* no SFF-style DMA */
	476	IDE_HFLAG_NO_AUTOTUNE,
	477	.mwdma_mask = ATA_MWDMA2,
	478	.swdma_mask = ATA_SWDMA2,
	479	};
	480
1da177e4 LT	481	static int __init
	482	icside_register_v6(struct icside_state state, struct expansion_card ec)
	483	{
	484	ide_hwif_t hwif, mate;
	485	void __iomem ioc_base, easi_base;
	486	unsigned int sel = 0;
	487	int ret;
8447d9d5	488	u8 idx[4] = { 0xff, 0xff, 0xff, 0xff };
c413b9b9	489	struct ide_port_info d = icside_v6_port_info;
1da177e4	490
10bdaaa0	491	ioc_base = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);
1da177e4 LT	492	if (!ioc_base) {
	493	ret = -ENOMEM;
	494	goto out;
	495	}
	496
	497	easi_base = ioc_base;
	498
	499	if (ecard_resource_flags(ec, ECARD_RES_EASI)) {
10bdaaa0	500	easi_base = ecardm_iomap(ec, ECARD_RES_EASI, 0, 0);
1da177e4 LT	501	if (!easi_base) {
1da177e4 LT	502	ret = -ENOMEM;
10bdaaa0	503	goto out;
1da177e4 LT	504	}
	505
	506	/*
	507	* Enable access to the EASI region.
	508	*/
	509	sel = 1 << 5;
	510	}
	511
	512	writeb(sel, ioc_base);
	513
c7b87f3d	514	ecard_setirq(ec, &icside_ops_arcin_v6, state);
1da177e4 LT	515
	516	state->irq_port = easi_base;
	517	state->ioc_base = ioc_base;
	518
	519	/*
	520	* Be on the safe side - disable interrupts
	521	*/
	522	icside_irqdisable_arcin_v6(ec, 0);
	523
	524	/*
	525	* Find and register the interfaces.
	526	*/
	527	hwif = icside_setup(easi_base, &icside_cardinfo_v6_1, ec);
	528	mate = icside_setup(easi_base, &icside_cardinfo_v6_2, ec);
	529
	530	if (!hwif \|\| !mate) {
	531	ret = -ENODEV;
10bdaaa0	532	goto out;
1da177e4 LT	533	}
	534
	535	state->hwif[0] = hwif;
	536	state->hwif[1] = mate;
	537
1da177e4	538	hwif->hwif_data = state;
1da177e4 LT	539	hwif->config_data = (unsigned long)ioc_base;
1da177e4 LT	540	hwif->select_data = sel;
1da177e4 LT	541
1da177e4 LT	542	mate->maskproc = icside_maskproc;
1da177e4	543	mate->hwif_data = state;
1da177e4 LT	544	mate->config_data = (unsigned long)ioc_base;
1da177e4 LT	545	mate->select_data = sel \| 1;
1da177e4 LT	546
	547	if (ec->dma != NO_DMA && !request_dma(ec->dma, hwif->name)) {
	548	icside_dma_init(hwif);
	549	icside_dma_init(mate);
ac95beed	550	d.port_ops = &icside_v6_dma_port_ops;
c413b9b9 BZ	551	} else
c413b9b9 BZ	552	d.mwdma_mask = d.swdma_mask = 0;
1da177e4	553
8447d9d5 BZ	554	idx[0] = hwif->index;
8447d9d5 BZ	555	idx[1] = mate->index;
5cbf79cd	556
c413b9b9	557	ide_device_add(idx, &d);
1da177e4 LT	558
	559	return 0;
	560
1da177e4 LT	561	out:
	562	return ret;
	563	}
	564
	565	static int __devinit
	566	icside_probe(struct expansion_card ec, const struct ecard_id id)
	567	{
	568	struct icside_state *state;
	569	void __iomem *idmem;
	570	int ret;
	571
	572	ret = ecard_request_resources(ec);
	573	if (ret)
	574	goto out;
	575
cc60d8ba	576	state = kzalloc(sizeof(struct icside_state), GFP_KERNEL);
1da177e4 LT	577	if (!state) {
	578	ret = -ENOMEM;
	579	goto release;
	580	}
	581
1da177e4	582	state->type = ICS_TYPE_NOTYPE;
1da177e4	583
10bdaaa0	584	idmem = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);
1da177e4 LT	585	if (idmem) {
	586	unsigned int type;
	587
	588	type = readb(idmem + ICS_IDENT_OFFSET) & 1;
	589	type \|= (readb(idmem + ICS_IDENT_OFFSET + 4) & 1) << 1;
	590	type \|= (readb(idmem + ICS_IDENT_OFFSET + 8) & 1) << 2;
	591	type \|= (readb(idmem + ICS_IDENT_OFFSET + 12) & 1) << 3;
10bdaaa0	592	ecardm_iounmap(ec, idmem);
1da177e4 LT	593
	594	state->type = type;
	595	}
	596
	597	switch (state->type) {
	598	case ICS_TYPE_A3IN:
	599	dev_warn(&ec->dev, "A3IN unsupported\n");
	600	ret = -ENODEV;
	601	break;
	602
	603	case ICS_TYPE_A3USER:
	604	dev_warn(&ec->dev, "A3USER unsupported\n");
	605	ret = -ENODEV;
	606	break;
	607
	608	case ICS_TYPE_V5:
	609	ret = icside_register_v5(state, ec);
	610	break;
	611
	612	case ICS_TYPE_V6:
	613	ret = icside_register_v6(state, ec);
	614	break;
	615
	616	default:
	617	dev_warn(&ec->dev, "unknown interface type\n");
	618	ret = -ENODEV;
	619	break;
	620	}
	621
	622	if (ret == 0) {
	623	ecard_set_drvdata(ec, state);
	624	goto out;
	625	}
	626
	627	kfree(state);
	628	release:
	629	ecard_release_resources(ec);
	630	out:
	631	return ret;
	632	}
	633
	634	static void __devexit icside_remove(struct expansion_card *ec)
	635	{
	636	struct icside_state *state = ecard_get_drvdata(ec);
	637
	638	switch (state->type) {
	639	case ICS_TYPE_V5:
	640	/* FIXME: tell IDE to stop using the interface */
	641
	642	/* Disable interrupts */
	643	icside_irqdisable_arcin_v5(ec, 0);
	644	break;
	645
	646	case ICS_TYPE_V6:
	647	/* FIXME: tell IDE to stop using the interface */
	648	if (ec->dma != NO_DMA)
	649	free_dma(ec->dma);
	650
	651	/* Disable interrupts */
	652	icside_irqdisable_arcin_v6(ec, 0);
	653
	654	/* Reset the ROM pointer/EASI selection */
	655	writeb(0, state->ioc_base);
	656	break;
657	}
658
659	ecard_set_drvdata(ec, NULL);
1da177e4	660
1da177e4 LT	661	kfree(state);
	662	ecard_release_resources(ec);
	663	}
	664
	665	static void icside_shutdown(struct expansion_card *ec)
	666	{
	667	struct icside_state *state = ecard_get_drvdata(ec);
	668	unsigned long flags;
	669
	670	/*
	671	* Disable interrupts from this card. We need to do
	672	* this before disabling EASI since we may be accessing
	673	* this register via that region.
	674	*/
	675	local_irq_save(flags);
	676	ec->ops->irqdisable(ec, 0);
	677	local_irq_restore(flags);
	678
	679	/*
	680	* Reset the ROM pointer so that we can read the ROM
	681	* after a soft reboot. This also disables access to
	682	* the IDE taskfile via the EASI region.
	683	*/
	684	if (state->ioc_base)
	685	writeb(0, state->ioc_base);
	686	}
	687
	688	static const struct ecard_id icside_ids[] = {
	689	{ MANU_ICS, PROD_ICS_IDE },
	690	{ MANU_ICS2, PROD_ICS2_IDE },
	691	{ 0xffff, 0xffff }
	692	};
	693
	694	static struct ecard_driver icside_driver = {
	695	.probe = icside_probe,
	696	.remove = __devexit_p(icside_remove),
	697	.shutdown = icside_shutdown,
	698	.id_table = icside_ids,
	699	.drv = {
	700	.name = "icside",
	701	},
	702	};
	703
	704	static int __init icside_init(void)
	705	{
	706	return ecard_register_driver(&icside_driver);
	707	}
	708
	709	MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>");
	710	MODULE_LICENSE("GPL");
	711	MODULE_DESCRIPTION("ICS IDE driver");
	712
	713	module_init(icside_init);