[deliverable/linux.git] / drivers / ide / icside.c

/*
 * Copyright (c) 1996-2004 Russell King.
 *
 * Please note that this platform does not support 32-bit IDE IO.
 */

#include <linux/string.h>
#include <linux/module.h>
#include <linux/ioport.h>
#include <linux/slab.h>
#include <linux/blkdev.h>
#include <linux/errno.h>
#include <linux/ide.h>
#include <linux/dma-mapping.h>
#include <linux/device.h>
#include <linux/init.h>
#include <linux/scatterlist.h>
#include <linux/io.h>

#include <asm/dma.h>
#include <asm/ecard.h>

#define DRV_NAME "icside"

#define ICS_IDENT_OFFSET		0x2280

#define ICS_ARCIN_V5_INTRSTAT		0x0000
#define ICS_ARCIN_V5_INTROFFSET		0x0004
#define ICS_ARCIN_V5_IDEOFFSET		0x2800
#define ICS_ARCIN_V5_IDEALTOFFSET	0x2b80
#define ICS_ARCIN_V5_IDESTEPPING	6

#define ICS_ARCIN_V6_IDEOFFSET_1	0x2000
#define ICS_ARCIN_V6_INTROFFSET_1	0x2200
#define ICS_ARCIN_V6_INTRSTAT_1		0x2290
#define ICS_ARCIN_V6_IDEALTOFFSET_1	0x2380
#define ICS_ARCIN_V6_IDEOFFSET_2	0x3000
#define ICS_ARCIN_V6_INTROFFSET_2	0x3200
#define ICS_ARCIN_V6_INTRSTAT_2		0x3290
#define ICS_ARCIN_V6_IDEALTOFFSET_2	0x3380
#define ICS_ARCIN_V6_IDESTEPPING	6

struct cardinfo {
	unsigned int dataoffset;
	unsigned int ctrloffset;
	unsigned int stepping;
};

static struct cardinfo icside_cardinfo_v5 = {
	.dataoffset	= ICS_ARCIN_V5_IDEOFFSET,
	.ctrloffset	= ICS_ARCIN_V5_IDEALTOFFSET,
	.stepping	= ICS_ARCIN_V5_IDESTEPPING,
};

static struct cardinfo icside_cardinfo_v6_1 = {
	.dataoffset	= ICS_ARCIN_V6_IDEOFFSET_1,
	.ctrloffset	= ICS_ARCIN_V6_IDEALTOFFSET_1,
	.stepping	= ICS_ARCIN_V6_IDESTEPPING,
};

static struct cardinfo icside_cardinfo_v6_2 = {
	.dataoffset	= ICS_ARCIN_V6_IDEOFFSET_2,
	.ctrloffset	= ICS_ARCIN_V6_IDEALTOFFSET_2,
	.stepping	= ICS_ARCIN_V6_IDESTEPPING,
};

struct icside_state {
	void __iomem *irq_port;
	void __iomem *ioc_base;
	unsigned int sel;
	unsigned int type;
	struct ide_host *host;
};

#define ICS_TYPE_A3IN	0
#define ICS_TYPE_A3USER	1
#define ICS_TYPE_V6	3
#define ICS_TYPE_V5	15
#define ICS_TYPE_NOTYPE	((unsigned int)-1)

/* ---------------- Version 5 PCB Support Functions --------------------- */
/* Prototype: icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
 * Purpose  : enable interrupts from card
 */
static void icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
{
	struct icside_state *state = ec->irq_data;

	writeb(0, state->irq_port + ICS_ARCIN_V5_INTROFFSET);
}

/* Prototype: icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
 * Purpose  : disable interrupts from card
 */
static void icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
{
	struct icside_state *state = ec->irq_data;

	readb(state->irq_port + ICS_ARCIN_V5_INTROFFSET);
}

static const expansioncard_ops_t icside_ops_arcin_v5 = {
	.irqenable	= icside_irqenable_arcin_v5,
	.irqdisable	= icside_irqdisable_arcin_v5,
};


/* ---------------- Version 6 PCB Support Functions --------------------- */
/* Prototype: icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
 * Purpose  : enable interrupts from card
 */
static void icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
{
	struct icside_state *state = ec->irq_data;
	void __iomem *base = state->irq_port;

	writeb(0, base + ICS_ARCIN_V6_INTROFFSET_1);
	readb(base + ICS_ARCIN_V6_INTROFFSET_2);

	writeb(0, base + ICS_ARCIN_V6_INTROFFSET_2);
	readb(base + ICS_ARCIN_V6_INTROFFSET_1);
}

/* Prototype: icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
 * Purpose  : disable interrupts from card
 */
static void icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
{
	struct icside_state *state = ec->irq_data;

	readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
	readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
}

/* Prototype: icside_irqprobe(struct expansion_card *ec)
 * Purpose  : detect an active interrupt from card
 */
static int icside_irqpending_arcin_v6(struct expansion_card *ec)
{
	struct icside_state *state = ec->irq_data;

	return readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_1) & 1 ||
	       readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_2) & 1;
}

static const expansioncard_ops_t icside_ops_arcin_v6 = {
	.irqenable	= icside_irqenable_arcin_v6,
	.irqdisable	= icside_irqdisable_arcin_v6,
	.irqpending	= icside_irqpending_arcin_v6,
};

#ifdef CONFIG_BLK_DEV_IDEDMA_ICS
/*
 * SG-DMA support.
 *
 * Similar to the BM-DMA, but we use the RiscPCs IOMD DMA controllers.
 * There is only one DMA controller per card, which means that only
 * one drive can be accessed at one time.  NOTE! We do not enforce that
 * here, but we rely on the main IDE driver spotting that both
 * interfaces use the same IRQ, which should guarantee this.
 */

/*
 * Configure the IOMD to give the appropriate timings for the transfer
 * mode being requested.  We take the advice of the ATA standards, and
 * calculate the cycle time based on the transfer mode, and the EIDE
 * MW DMA specs that the drive provides in the IDENTIFY command.
 *
 * We have the following IOMD DMA modes to choose from:
 *
 *	Type	Active		Recovery	Cycle
 *	A	250 (250)	312 (550)	562 (800)
 *	B	187		250		437
 *	C	125 (125)	125 (375)	250 (500)
 *	D	62		125		187
 *
 * (figures in brackets are actual measured timings)
 *
 * However, we also need to take care of the read/write active and
 * recovery timings:
 *
 *			Read	Write
 *  	Mode	Active	-- Recovery --	Cycle	IOMD type
 *	MW0	215	50	215	480	A
 *	MW1	80	50	50	150	C
 *	MW2	70	25	25	120	C
 */
static void icside_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
{
	unsigned long cycle_time;
	int use_dma_info = 0;
	const u8 xfer_mode = drive->dma_mode;

	switch (xfer_mode) {
	case XFER_MW_DMA_2:
		cycle_time = 250;
		use_dma_info = 1;
		break;

	case XFER_MW_DMA_1:
		cycle_time = 250;
		use_dma_info = 1;
		break;

	case XFER_MW_DMA_0:
		cycle_time = 480;
		break;

	case XFER_SW_DMA_2:
	case XFER_SW_DMA_1:
	case XFER_SW_DMA_0:
		cycle_time = 480;
		break;
	}

	/*
	 * If we're going to be doing MW_DMA_1 or MW_DMA_2, we should
	 * take care to note the values in the ID...
	 */
	if (use_dma_info && drive->id[ATA_ID_EIDE_DMA_TIME] > cycle_time)
		cycle_time = drive->id[ATA_ID_EIDE_DMA_TIME];

	ide_set_drivedata(drive, (void *)cycle_time);

	printk("%s: %s selected (peak %dMB/s)\n", drive->name,
		ide_xfer_verbose(xfer_mode),
		2000 / (unsigned long)ide_get_drivedata(drive));
}

static const struct ide_port_ops icside_v6_port_ops = {
	.set_dma_mode		= icside_set_dma_mode,
};

static void icside_dma_host_set(ide_drive_t *drive, int on)
{
}

static int icside_dma_end(ide_drive_t *drive)
{
	ide_hwif_t *hwif = drive->hwif;
	struct expansion_card *ec = ECARD_DEV(hwif->dev);

	disable_dma(ec->dma);

	return get_dma_residue(ec->dma) != 0;
}

static void icside_dma_start(ide_drive_t *drive)
{
	ide_hwif_t *hwif = drive->hwif;
	struct expansion_card *ec = ECARD_DEV(hwif->dev);

	/* We can not enable DMA on both channels simultaneously. */
	BUG_ON(dma_channel_active(ec->dma));
	enable_dma(ec->dma);
}

static int icside_dma_setup(ide_drive_t *drive, struct ide_cmd *cmd)
{
	ide_hwif_t *hwif = drive->hwif;
	struct expansion_card *ec = ECARD_DEV(hwif->dev);
	struct icside_state *state = ecard_get_drvdata(ec);
	unsigned int dma_mode;

	if (cmd->tf_flags & IDE_TFLAG_WRITE)
		dma_mode = DMA_MODE_WRITE;
	else
		dma_mode = DMA_MODE_READ;

	/*
	 * We can not enable DMA on both channels.
	 */
	BUG_ON(dma_channel_active(ec->dma));

	/*
	 * Route the DMA signals to the correct interface.
	 */
	writeb(state->sel | hwif->channel, state->ioc_base);

	/*
	 * Select the correct timing for this drive.
	 */
	set_dma_speed(ec->dma, (unsigned long)ide_get_drivedata(drive));

	/*
	 * Tell the DMA engine about the SG table and
	 * data direction.
	 */
	set_dma_sg(ec->dma, hwif->sg_table, cmd->sg_nents);
	set_dma_mode(ec->dma, dma_mode);

	return 0;
}

static int icside_dma_test_irq(ide_drive_t *drive)
{
	ide_hwif_t *hwif = drive->hwif;
	struct expansion_card *ec = ECARD_DEV(hwif->dev);
	struct icside_state *state = ecard_get_drvdata(ec);

	return readb(state->irq_port +
		     (hwif->channel ?
			ICS_ARCIN_V6_INTRSTAT_2 :
			ICS_ARCIN_V6_INTRSTAT_1)) & 1;
}

static int icside_dma_init(ide_hwif_t *hwif, const struct ide_port_info *d)
{
	hwif->dmatable_cpu	= NULL;
	hwif->dmatable_dma	= 0;

	return 0;
}

static const struct ide_dma_ops icside_v6_dma_ops = {
	.dma_host_set		= icside_dma_host_set,
	.dma_setup		= icside_dma_setup,
	.dma_start		= icside_dma_start,
	.dma_end		= icside_dma_end,
	.dma_test_irq		= icside_dma_test_irq,
	.dma_lost_irq		= ide_dma_lost_irq,
};
#else
#define icside_v6_dma_ops NULL
#endif

static int icside_dma_off_init(ide_hwif_t *hwif, const struct ide_port_info *d)
{
	return -EOPNOTSUPP;
}

static void icside_setup_ports(struct ide_hw *hw, void __iomem *base,
			       struct cardinfo *info, struct expansion_card *ec)
{
	unsigned long port = (unsigned long)base + info->dataoffset;

	hw->io_ports.data_addr	 = port;
	hw->io_ports.error_addr	 = port + (1 << info->stepping);
	hw->io_ports.nsect_addr	 = port + (2 << info->stepping);
	hw->io_ports.lbal_addr	 = port + (3 << info->stepping);
	hw->io_ports.lbam_addr	 = port + (4 << info->stepping);
	hw->io_ports.lbah_addr	 = port + (5 << info->stepping);
	hw->io_ports.device_addr = port + (6 << info->stepping);
	hw->io_ports.status_addr = port + (7 << info->stepping);
	hw->io_ports.ctl_addr	 = (unsigned long)base + info->ctrloffset;

	hw->irq = ec->irq;
	hw->dev = &ec->dev;
}

static const struct ide_port_info icside_v5_port_info = {
	.host_flags		= IDE_HFLAG_NO_DMA,
	.chipset		= ide_acorn,
};

static int __devinit
icside_register_v5(struct icside_state *state, struct expansion_card *ec)
{
	void __iomem *base;
	struct ide_host *host;
	struct ide_hw hw, *hws[] = { &hw };
	int ret;

	base = ecardm_iomap(ec, ECARD_RES_MEMC, 0, 0);
	if (!base)
		return -ENOMEM;

	state->irq_port = base;

	ec->irqaddr  = base + ICS_ARCIN_V5_INTRSTAT;
	ec->irqmask  = 1;

	ecard_setirq(ec, &icside_ops_arcin_v5, state);

	/*
	 * Be on the safe side - disable interrupts
	 */
	icside_irqdisable_arcin_v5(ec, 0);

	icside_setup_ports(&hw, base, &icside_cardinfo_v5, ec);

	host = ide_host_alloc(&icside_v5_port_info, hws, 1);
	if (host == NULL)
		return -ENODEV;

	state->host = host;

	ecard_set_drvdata(ec, state);

	ret = ide_host_register(host, &icside_v5_port_info, hws);
	if (ret)
		goto err_free;

	return 0;
err_free:
	ide_host_free(host);
	ecard_set_drvdata(ec, NULL);
	return ret;
}

static const struct ide_port_info icside_v6_port_info __initdata = {
	.init_dma		= icside_dma_off_init,
	.dma_ops		= &icside_v6_dma_ops,
	.host_flags		= IDE_HFLAG_SERIALIZE | IDE_HFLAG_MMIO,
	.mwdma_mask		= ATA_MWDMA2,
	.swdma_mask		= ATA_SWDMA2,
	.chipset		= ide_acorn,
};

static int __devinit
icside_register_v6(struct icside_state *state, struct expansion_card *ec)
{
	void __iomem *ioc_base, *easi_base;
	struct ide_host *host;
	unsigned int sel = 0;
	int ret;
	struct ide_hw hw[2], *hws[] = { &hw[0], &hw[1] };
	struct ide_port_info d = icside_v6_port_info;

	ioc_base = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);
	if (!ioc_base) {
		ret = -ENOMEM;
		goto out;
	}

	easi_base = ioc_base;

	if (ecard_resource_flags(ec, ECARD_RES_EASI)) {
		easi_base = ecardm_iomap(ec, ECARD_RES_EASI, 0, 0);
		if (!easi_base) {
			ret = -ENOMEM;
			goto out;
		}

		/*
		 * Enable access to the EASI region.
		 */
		sel = 1 << 5;
	}

	writeb(sel, ioc_base);

	ecard_setirq(ec, &icside_ops_arcin_v6, state);

	state->irq_port   = easi_base;
	state->ioc_base   = ioc_base;
	state->sel	  = sel;

	/*
	 * Be on the safe side - disable interrupts
	 */
	icside_irqdisable_arcin_v6(ec, 0);

	icside_setup_ports(&hw[0], easi_base, &icside_cardinfo_v6_1, ec);
	icside_setup_ports(&hw[1], easi_base, &icside_cardinfo_v6_2, ec);

	host = ide_host_alloc(&d, hws, 2);
	if (host == NULL)
		return -ENODEV;

	state->host = host;

	ecard_set_drvdata(ec, state);

	if (ec->dma != NO_DMA && !request_dma(ec->dma, DRV_NAME)) {
		d.init_dma = icside_dma_init;
		d.port_ops = &icside_v6_port_ops;
		d.dma_ops = NULL;
	}

	ret = ide_host_register(host, &d, hws);
	if (ret)
		goto err_free;

	return 0;
err_free:
	ide_host_free(host);
	if (d.dma_ops)
		free_dma(ec->dma);
	ecard_set_drvdata(ec, NULL);
out:
	return ret;
}

static int __devinit
icside_probe(struct expansion_card *ec, const struct ecard_id *id)
{
	struct icside_state *state;
	void __iomem *idmem;
	int ret;

	ret = ecard_request_resources(ec);
	if (ret)
		goto out;

	state = kzalloc(sizeof(struct icside_state), GFP_KERNEL);
	if (!state) {
		ret = -ENOMEM;
		goto release;
	}

	state->type	= ICS_TYPE_NOTYPE;

	idmem = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);
	if (idmem) {
		unsigned int type;

		type = readb(idmem + ICS_IDENT_OFFSET) & 1;
		type |= (readb(idmem + ICS_IDENT_OFFSET + 4) & 1) << 1;
		type |= (readb(idmem + ICS_IDENT_OFFSET + 8) & 1) << 2;
		type |= (readb(idmem + ICS_IDENT_OFFSET + 12) & 1) << 3;
		ecardm_iounmap(ec, idmem);

		state->type = type;
	}

	switch (state->type) {
	case ICS_TYPE_A3IN:
		dev_warn(&ec->dev, "A3IN unsupported\n");
		ret = -ENODEV;
		break;

	case ICS_TYPE_A3USER:
		dev_warn(&ec->dev, "A3USER unsupported\n");
		ret = -ENODEV;
		break;

	case ICS_TYPE_V5:
		ret = icside_register_v5(state, ec);
		break;

	case ICS_TYPE_V6:
		ret = icside_register_v6(state, ec);
		break;

	default:
		dev_warn(&ec->dev, "unknown interface type\n");
		ret = -ENODEV;
		break;
	}

	if (ret == 0)
		goto out;

	kfree(state);
 release:
	ecard_release_resources(ec);
 out:
	return ret;
}

static void __devexit icside_remove(struct expansion_card *ec)
{
	struct icside_state *state = ecard_get_drvdata(ec);

	switch (state->type) {
	case ICS_TYPE_V5:
		/* FIXME: tell IDE to stop using the interface */

		/* Disable interrupts */
		icside_irqdisable_arcin_v5(ec, 0);
		break;

	case ICS_TYPE_V6:
		/* FIXME: tell IDE to stop using the interface */
		if (ec->dma != NO_DMA)
			free_dma(ec->dma);

		/* Disable interrupts */
		icside_irqdisable_arcin_v6(ec, 0);

		/* Reset the ROM pointer/EASI selection */
		writeb(0, state->ioc_base);
		break;
	}

	ecard_set_drvdata(ec, NULL);

	kfree(state);
	ecard_release_resources(ec);
}

static void icside_shutdown(struct expansion_card *ec)
{
	struct icside_state *state = ecard_get_drvdata(ec);
	unsigned long flags;

	/*
	 * Disable interrupts from this card.  We need to do
	 * this before disabling EASI since we may be accessing
	 * this register via that region.
	 */
	local_irq_save(flags);
	ec->ops->irqdisable(ec, 0);
	local_irq_restore(flags);

	/*
	 * Reset the ROM pointer so that we can read the ROM
	 * after a soft reboot.  This also disables access to
	 * the IDE taskfile via the EASI region.
	 */
	if (state->ioc_base)
		writeb(0, state->ioc_base);
}

static const struct ecard_id icside_ids[] = {
	{ MANU_ICS,  PROD_ICS_IDE  },
	{ MANU_ICS2, PROD_ICS2_IDE },
	{ 0xffff, 0xffff }
};

static struct ecard_driver icside_driver = {
	.probe		= icside_probe,
	.remove		= __devexit_p(icside_remove),
	.shutdown	= icside_shutdown,
	.id_table	= icside_ids,
	.drv = {
		.name	= "icside",
	},
};

static int __init icside_init(void)
{
	return ecard_register_driver(&icside_driver);
}

static void __exit icside_exit(void)
{
	ecard_remove_driver(&icside_driver);
}

MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>");
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("ICS IDE driver");

module_init(icside_init);
module_exit(icside_exit);
Commit	Line	Data
1da177e4	1	/*
1da177e4 LT	2	* Copyright (c) 1996-2004 Russell King.
	3	*
	4	* Please note that this platform does not support 32-bit IDE IO.
	5	*/
	6
1da177e4 LT	7	#include <linux/string.h>
	8	#include <linux/module.h>
	9	#include <linux/ioport.h>
	10	#include <linux/slab.h>
	11	#include <linux/blkdev.h>
	12	#include <linux/errno.h>
1da177e4 LT	13	#include <linux/ide.h>
	14	#include <linux/dma-mapping.h>
	15	#include <linux/device.h>
	16	#include <linux/init.h>
	17	#include <linux/scatterlist.h>
ba5b55d0	18	#include <linux/io.h>
1da177e4 LT	19
	20	#include <asm/dma.h>
	21	#include <asm/ecard.h>
1da177e4	22
67717e22 BZ	23	#define DRV_NAME "icside"
67717e22 BZ	24
1da177e4 LT	25	#define ICS_IDENT_OFFSET 0x2280
	26
	27	#define ICS_ARCIN_V5_INTRSTAT 0x0000
	28	#define ICS_ARCIN_V5_INTROFFSET 0x0004
	29	#define ICS_ARCIN_V5_IDEOFFSET 0x2800
	30	#define ICS_ARCIN_V5_IDEALTOFFSET 0x2b80
	31	#define ICS_ARCIN_V5_IDESTEPPING 6
	32
	33	#define ICS_ARCIN_V6_IDEOFFSET_1 0x2000
	34	#define ICS_ARCIN_V6_INTROFFSET_1 0x2200
	35	#define ICS_ARCIN_V6_INTRSTAT_1 0x2290
	36	#define ICS_ARCIN_V6_IDEALTOFFSET_1 0x2380
	37	#define ICS_ARCIN_V6_IDEOFFSET_2 0x3000
	38	#define ICS_ARCIN_V6_INTROFFSET_2 0x3200
	39	#define ICS_ARCIN_V6_INTRSTAT_2 0x3290
	40	#define ICS_ARCIN_V6_IDEALTOFFSET_2 0x3380
	41	#define ICS_ARCIN_V6_IDESTEPPING 6
	42
	43	struct cardinfo {
	44	unsigned int dataoffset;
	45	unsigned int ctrloffset;
	46	unsigned int stepping;
	47	};
	48
	49	static struct cardinfo icside_cardinfo_v5 = {
	50	.dataoffset = ICS_ARCIN_V5_IDEOFFSET,
	51	.ctrloffset = ICS_ARCIN_V5_IDEALTOFFSET,
	52	.stepping = ICS_ARCIN_V5_IDESTEPPING,
	53	};
	54
	55	static struct cardinfo icside_cardinfo_v6_1 = {
	56	.dataoffset = ICS_ARCIN_V6_IDEOFFSET_1,
	57	.ctrloffset = ICS_ARCIN_V6_IDEALTOFFSET_1,
	58	.stepping = ICS_ARCIN_V6_IDESTEPPING,
	59	};
	60
	61	static struct cardinfo icside_cardinfo_v6_2 = {
	62	.dataoffset = ICS_ARCIN_V6_IDEOFFSET_2,
	63	.ctrloffset = ICS_ARCIN_V6_IDEALTOFFSET_2,
	64	.stepping = ICS_ARCIN_V6_IDESTEPPING,
	65	};
	66
	67	struct icside_state {
1da177e4 LT	68	void __iomem *irq_port;
1da177e4 LT	69	void __iomem *ioc_base;
26839f09	70	unsigned int sel;
1da177e4	71	unsigned int type;
48c3c107	72	struct ide_host *host;
1da177e4 LT	73	};
	74
	75	#define ICS_TYPE_A3IN 0
	76	#define ICS_TYPE_A3USER 1
	77	#define ICS_TYPE_V6 3
	78	#define ICS_TYPE_V5 15
	79	#define ICS_TYPE_NOTYPE ((unsigned int)-1)
	80
	81	/* ---------------- Version 5 PCB Support Functions --------------------- */
	82	/* Prototype: icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
	83	* Purpose : enable interrupts from card
	84	*/
	85	static void icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
	86	{
	87	struct icside_state *state = ec->irq_data;
	88
	89	writeb(0, state->irq_port + ICS_ARCIN_V5_INTROFFSET);
	90	}
	91
	92	/* Prototype: icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
	93	* Purpose : disable interrupts from card
	94	*/
	95	static void icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
	96	{
	97	struct icside_state *state = ec->irq_data;
	98
	99	readb(state->irq_port + ICS_ARCIN_V5_INTROFFSET);
	100	}
	101
	102	static const expansioncard_ops_t icside_ops_arcin_v5 = {
	103	.irqenable = icside_irqenable_arcin_v5,
	104	.irqdisable = icside_irqdisable_arcin_v5,
	105	};
	106
	107
	108	/* ---------------- Version 6 PCB Support Functions --------------------- */
	109	/* Prototype: icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
	110	* Purpose : enable interrupts from card
	111	*/
	112	static void icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
	113	{
	114	struct icside_state *state = ec->irq_data;
	115	void __iomem *base = state->irq_port;
	116
dff8817b BZ	117	writeb(0, base + ICS_ARCIN_V6_INTROFFSET_1);
dff8817b BZ	118	readb(base + ICS_ARCIN_V6_INTROFFSET_2);
1da177e4	119
dff8817b BZ	120	writeb(0, base + ICS_ARCIN_V6_INTROFFSET_2);
dff8817b BZ	121	readb(base + ICS_ARCIN_V6_INTROFFSET_1);
1da177e4 LT	122	}
	123
	124	/* Prototype: icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
	125	* Purpose : disable interrupts from card
	126	*/
	127	static void icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
	128	{
	129	struct icside_state *state = ec->irq_data;
	130
1da177e4 LT	131	readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
	132	readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
	133	}
	134
	135	/* Prototype: icside_irqprobe(struct expansion_card *ec)
	136	* Purpose : detect an active interrupt from card
	137	*/
	138	static int icside_irqpending_arcin_v6(struct expansion_card *ec)
	139	{
	140	struct icside_state *state = ec->irq_data;
	141
	142	return readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_1) & 1 \|\|
	143	readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_2) & 1;
	144	}
	145
	146	static const expansioncard_ops_t icside_ops_arcin_v6 = {
	147	.irqenable = icside_irqenable_arcin_v6,
	148	.irqdisable = icside_irqdisable_arcin_v6,
	149	.irqpending = icside_irqpending_arcin_v6,
	150	};
	151
1da177e4	152	#ifdef CONFIG_BLK_DEV_IDEDMA_ICS
1da177e4 LT	153	/*
	154	* SG-DMA support.
	155	*
	156	* Similar to the BM-DMA, but we use the RiscPCs IOMD DMA controllers.
	157	* There is only one DMA controller per card, which means that only
	158	* one drive can be accessed at one time. NOTE! We do not enforce that
	159	* here, but we rely on the main IDE driver spotting that both
	160	* interfaces use the same IRQ, which should guarantee this.
	161	*/
	162
1da177e4 LT	163	/*
	164	* Configure the IOMD to give the appropriate timings for the transfer
	165	* mode being requested. We take the advice of the ATA standards, and
	166	* calculate the cycle time based on the transfer mode, and the EIDE
	167	* MW DMA specs that the drive provides in the IDENTIFY command.
	168	*
	169	* We have the following IOMD DMA modes to choose from:
	170	*
	171	* Type Active Recovery Cycle
	172	* A 250 (250) 312 (550) 562 (800)
	173	* B 187 250 437
	174	* C 125 (125) 125 (375) 250 (500)
	175	* D 62 125 187
	176	*
	177	* (figures in brackets are actual measured timings)
	178	*
	179	* However, we also need to take care of the read/write active and
	180	* recovery timings:
	181	*
	182	* Read Write
	183	* Mode Active -- Recovery -- Cycle IOMD type
	184	* MW0 215 50 215 480 A
	185	* MW1 80 50 50 150 C
	186	* MW2 70 25 25 120 C
	187	*/
8776168c	188	static void icside_set_dma_mode(ide_hwif_t hwif, ide_drive_t drive)
1da177e4	189	{
5bfb151f JR	190	unsigned long cycle_time;
5bfb151f JR	191	int use_dma_info = 0;
8776168c	192	const u8 xfer_mode = drive->dma_mode;
1da177e4	193
1da177e4 LT	194	switch (xfer_mode) {
	195	case XFER_MW_DMA_2:
	196	cycle_time = 250;
	197	use_dma_info = 1;
	198	break;
	199
	200	case XFER_MW_DMA_1:
	201	cycle_time = 250;
	202	use_dma_info = 1;
	203	break;
	204
	205	case XFER_MW_DMA_0:
	206	cycle_time = 480;
	207	break;
	208
	209	case XFER_SW_DMA_2:
	210	case XFER_SW_DMA_1:
	211	case XFER_SW_DMA_0:
	212	cycle_time = 480;
	213	break;
	214	}
	215
	216	/*
	217	* If we're going to be doing MW_DMA_1 or MW_DMA_2, we should
	218	* take care to note the values in the ID...
	219	*/
4dde4492 BZ	220	if (use_dma_info && drive->id[ATA_ID_EIDE_DMA_TIME] > cycle_time)
4dde4492 BZ	221	cycle_time = drive->id[ATA_ID_EIDE_DMA_TIME];
1da177e4	222
5bfb151f	223	ide_set_drivedata(drive, (void *)cycle_time);
1da177e4	224
1da177e4	225	printk("%s: %s selected (peak %dMB/s)\n", drive->name,
5bfb151f JR	226	ide_xfer_verbose(xfer_mode),
5bfb151f JR	227	2000 / (unsigned long)ide_get_drivedata(drive));
1da177e4 LT	228	}
1da177e4 LT	229
ac95beed BZ	230	static const struct ide_port_ops icside_v6_port_ops = {
ac95beed BZ	231	.set_dma_mode = icside_set_dma_mode,
ac95beed BZ	232	};
ac95beed BZ	233
15ce926a	234	static void icside_dma_host_set(ide_drive_t *drive, int on)
1da177e4	235	{
1da177e4 LT	236	}
1da177e4 LT	237
1da177e4 LT	238	static int icside_dma_end(ide_drive_t *drive)
1da177e4 LT	239	{
898ec223	240	ide_hwif_t *hwif = drive->hwif;
f8341c1c	241	struct expansion_card *ec = ECARD_DEV(hwif->dev);
1da177e4	242
f8341c1c	243	disable_dma(ec->dma);
1da177e4	244
f8341c1c	245	return get_dma_residue(ec->dma) != 0;
1da177e4 LT	246	}
	247
	248	static void icside_dma_start(ide_drive_t *drive)
	249	{
898ec223	250	ide_hwif_t *hwif = drive->hwif;
f8341c1c	251	struct expansion_card *ec = ECARD_DEV(hwif->dev);
1da177e4 LT	252
1da177e4 LT	253	/* We can not enable DMA on both channels simultaneously. */
f8341c1c BZ	254	BUG_ON(dma_channel_active(ec->dma));
f8341c1c BZ	255	enable_dma(ec->dma);
1da177e4 LT	256	}
1da177e4 LT	257
22981694	258	static int icside_dma_setup(ide_drive_t drive, struct ide_cmd cmd)
1da177e4	259	{
898ec223	260	ide_hwif_t *hwif = drive->hwif;
f8341c1c	261	struct expansion_card *ec = ECARD_DEV(hwif->dev);
26839f09	262	struct icside_state *state = ecard_get_drvdata(ec);
1da177e4 LT	263	unsigned int dma_mode;
1da177e4 LT	264
22981694	265	if (cmd->tf_flags & IDE_TFLAG_WRITE)
1da177e4 LT	266	dma_mode = DMA_MODE_WRITE;
	267	else
	268	dma_mode = DMA_MODE_READ;
	269
	270	/*
	271	* We can not enable DMA on both channels.
	272	*/
f8341c1c	273	BUG_ON(dma_channel_active(ec->dma));
1da177e4	274
1da177e4 LT	275	/*
	276	* Route the DMA signals to the correct interface.
	277	*/
26839f09	278	writeb(state->sel \| hwif->channel, state->ioc_base);
1da177e4 LT	279
	280	/*
	281	* Select the correct timing for this drive.
	282	*/
5bfb151f	283	set_dma_speed(ec->dma, (unsigned long)ide_get_drivedata(drive));
1da177e4 LT	284
	285	/*
	286	* Tell the DMA engine about the SG table and
	287	* data direction.
	288	*/
22981694	289	set_dma_sg(ec->dma, hwif->sg_table, cmd->sg_nents);
f8341c1c	290	set_dma_mode(ec->dma, dma_mode);
1da177e4	291
1da177e4 LT	292	return 0;
	293	}
	294
1da177e4 LT	295	static int icside_dma_test_irq(ide_drive_t *drive)
1da177e4 LT	296	{
898ec223	297	ide_hwif_t *hwif = drive->hwif;
26839f09 BZ	298	struct expansion_card *ec = ECARD_DEV(hwif->dev);
26839f09 BZ	299	struct icside_state *state = ecard_get_drvdata(ec);
1da177e4 LT	300
	301	return readb(state->irq_port +
	302	(hwif->channel ?
	303	ICS_ARCIN_V6_INTRSTAT_2 :
	304	ICS_ARCIN_V6_INTRSTAT_1)) & 1;
	305	}
	306
91432f48	307	static int icside_dma_init(ide_hwif_t hwif, const struct ide_port_info d)
1da177e4	308	{
1da177e4 LT	309	hwif->dmatable_cpu = NULL;
1da177e4 LT	310	hwif->dmatable_dma = 0;
1da177e4	311
91432f48	312	return 0;
1da177e4	313	}
5e37bdc0	314
f37afdac	315	static const struct ide_dma_ops icside_v6_dma_ops = {
5e37bdc0 BZ	316	.dma_host_set = icside_dma_host_set,
5e37bdc0 BZ	317	.dma_setup = icside_dma_setup,
5e37bdc0 BZ	318	.dma_start = icside_dma_start,
	319	.dma_end = icside_dma_end,
	320	.dma_test_irq = icside_dma_test_irq,
de23ec9c	321	.dma_lost_irq = ide_dma_lost_irq,
5e37bdc0 BZ	322	};
	323	#else
	324	#define icside_v6_dma_ops NULL
1da177e4 LT	325	#endif
1da177e4 LT	326
91432f48 BZ	327	static int icside_dma_off_init(ide_hwif_t hwif, const struct ide_port_info d)
	328	{
	329	return -EOPNOTSUPP;
	330	}
	331
9f36d314	332	static void icside_setup_ports(struct ide_hw hw, void __iomem base,
b25afdf1	333	struct cardinfo info, struct expansion_card ec)
1da177e4 LT	334	{
1da177e4 LT	335	unsigned long port = (unsigned long)base + info->dataoffset;
1da177e4	336
b25afdf1 BZ	337	hw->io_ports.data_addr = port;
	338	hw->io_ports.error_addr = port + (1 << info->stepping);
	339	hw->io_ports.nsect_addr = port + (2 << info->stepping);
	340	hw->io_ports.lbal_addr = port + (3 << info->stepping);
	341	hw->io_ports.lbam_addr = port + (4 << info->stepping);
	342	hw->io_ports.lbah_addr = port + (5 << info->stepping);
	343	hw->io_ports.device_addr = port + (6 << info->stepping);
	344	hw->io_ports.status_addr = port + (7 << info->stepping);
	345	hw->io_ports.ctl_addr = (unsigned long)base + info->ctrloffset;
	346
	347	hw->irq = ec->irq;
	348	hw->dev = &ec->dev;
1da177e4 LT	349	}
1da177e4 LT	350
33050ec7 BZ	351	static const struct ide_port_info icside_v5_port_info = {
33050ec7 BZ	352	.host_flags = IDE_HFLAG_NO_DMA,
29e52cf7	353	.chipset = ide_acorn,
33050ec7 BZ	354	};
33050ec7 BZ	355
d16d7667	356	static int __devinit
1da177e4 LT	357	icside_register_v5(struct icside_state state, struct expansion_card ec)
1da177e4 LT	358	{
1da177e4	359	void __iomem *base;
48c3c107	360	struct ide_host *host;
9f36d314	361	struct ide_hw hw, *hws[] = { &hw };
8a69580e	362	int ret;
1da177e4	363
10bdaaa0	364	base = ecardm_iomap(ec, ECARD_RES_MEMC, 0, 0);
1da177e4 LT	365	if (!base)
	366	return -ENOMEM;
	367
	368	state->irq_port = base;
	369
	370	ec->irqaddr = base + ICS_ARCIN_V5_INTRSTAT;
	371	ec->irqmask = 1;
c7b87f3d RK	372
c7b87f3d RK	373	ecard_setirq(ec, &icside_ops_arcin_v5, state);
1da177e4 LT	374
	375	/*
	376	* Be on the safe side - disable interrupts
	377	*/
	378	icside_irqdisable_arcin_v5(ec, 0);
	379
b25afdf1 BZ	380	icside_setup_ports(&hw, base, &icside_cardinfo_v5, ec);
b25afdf1 BZ	381
dca39830	382	host = ide_host_alloc(&icside_v5_port_info, hws, 1);
48c3c107	383	if (host == NULL)
1da177e4	384	return -ENODEV;
1da177e4	385
48c3c107	386	state->host = host;
1da177e4	387
26839f09 BZ	388	ecard_set_drvdata(ec, state);
26839f09 BZ	389
33050ec7	390	ret = ide_host_register(host, &icside_v5_port_info, hws);
8a69580e BZ	391	if (ret)
8a69580e BZ	392	goto err_free;
1da177e4 LT	393
1da177e4 LT	394	return 0;
8a69580e BZ	395	err_free:
	396	ide_host_free(host);
	397	ecard_set_drvdata(ec, NULL);
	398	return ret;
1da177e4 LT	399	}
1da177e4 LT	400
c413b9b9	401	static const struct ide_port_info icside_v6_port_info __initdata = {
91432f48	402	.init_dma = icside_dma_off_init,
5e37bdc0	403	.dma_ops = &icside_v6_dma_ops,
c5dd43ec	404	.host_flags = IDE_HFLAG_SERIALIZE \| IDE_HFLAG_MMIO,
c413b9b9 BZ	405	.mwdma_mask = ATA_MWDMA2,
c413b9b9 BZ	406	.swdma_mask = ATA_SWDMA2,
29e52cf7	407	.chipset = ide_acorn,
c413b9b9 BZ	408	};
c413b9b9 BZ	409
d16d7667	410	static int __devinit
1da177e4 LT	411	icside_register_v6(struct icside_state state, struct expansion_card ec)
1da177e4 LT	412	{
1da177e4	413	void __iomem ioc_base, easi_base;
48c3c107	414	struct ide_host *host;
1da177e4 LT	415	unsigned int sel = 0;
1da177e4 LT	416	int ret;
9f36d314	417	struct ide_hw hw[2], *hws[] = { &hw[0], &hw[1] };
c413b9b9	418	struct ide_port_info d = icside_v6_port_info;
1da177e4	419
10bdaaa0	420	ioc_base = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);
1da177e4 LT	421	if (!ioc_base) {
	422	ret = -ENOMEM;
	423	goto out;
	424	}
	425
	426	easi_base = ioc_base;
	427
	428	if (ecard_resource_flags(ec, ECARD_RES_EASI)) {
10bdaaa0	429	easi_base = ecardm_iomap(ec, ECARD_RES_EASI, 0, 0);
1da177e4 LT	430	if (!easi_base) {
1da177e4 LT	431	ret = -ENOMEM;
10bdaaa0	432	goto out;
1da177e4 LT	433	}
	434
	435	/*
	436	* Enable access to the EASI region.
	437	*/
	438	sel = 1 << 5;
	439	}
	440
	441	writeb(sel, ioc_base);
	442
c7b87f3d	443	ecard_setirq(ec, &icside_ops_arcin_v6, state);
1da177e4 LT	444
	445	state->irq_port = easi_base;
	446	state->ioc_base = ioc_base;
26839f09	447	state->sel = sel;
1da177e4 LT	448
	449	/*
	450	* Be on the safe side - disable interrupts
	451	*/
	452	icside_irqdisable_arcin_v6(ec, 0);
	453
b25afdf1 BZ	454	icside_setup_ports(&hw[0], easi_base, &icside_cardinfo_v6_1, ec);
	455	icside_setup_ports(&hw[1], easi_base, &icside_cardinfo_v6_2, ec);
	456
dca39830	457	host = ide_host_alloc(&d, hws, 2);
48c3c107	458	if (host == NULL)
b25afdf1	459	return -ENODEV;
1da177e4	460
48c3c107	461	state->host = host;
1da177e4	462
26839f09	463	ecard_set_drvdata(ec, state);
1da177e4	464
67717e22	465	if (ec->dma != NO_DMA && !request_dma(ec->dma, DRV_NAME)) {
91432f48	466	d.init_dma = icside_dma_init;
9c391bae	467	d.port_ops = &icside_v6_port_ops;
5e37bdc0	468	d.dma_ops = NULL;
91432f48	469	}
1da177e4	470
d224b626	471	ret = ide_host_register(host, &d, hws);
8a69580e BZ	472	if (ret)
8a69580e BZ	473	goto err_free;
1da177e4 LT	474
1da177e4 LT	475	return 0;
8a69580e BZ	476	err_free:
	477	ide_host_free(host);
	478	if (d.dma_ops)
	479	free_dma(ec->dma);
	480	ecard_set_drvdata(ec, NULL);
	481	out:
1da177e4 LT	482	return ret;
	483	}
	484
	485	static int __devinit
	486	icside_probe(struct expansion_card ec, const struct ecard_id id)
	487	{
	488	struct icside_state *state;
	489	void __iomem *idmem;
	490	int ret;
	491
	492	ret = ecard_request_resources(ec);
	493	if (ret)
	494	goto out;
	495
cc60d8ba	496	state = kzalloc(sizeof(struct icside_state), GFP_KERNEL);
1da177e4 LT	497	if (!state) {
	498	ret = -ENOMEM;
	499	goto release;
	500	}
	501
1da177e4	502	state->type = ICS_TYPE_NOTYPE;
1da177e4	503
10bdaaa0	504	idmem = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);
1da177e4 LT	505	if (idmem) {
	506	unsigned int type;
	507
	508	type = readb(idmem + ICS_IDENT_OFFSET) & 1;
	509	type \|= (readb(idmem + ICS_IDENT_OFFSET + 4) & 1) << 1;
	510	type \|= (readb(idmem + ICS_IDENT_OFFSET + 8) & 1) << 2;
	511	type \|= (readb(idmem + ICS_IDENT_OFFSET + 12) & 1) << 3;
10bdaaa0	512	ecardm_iounmap(ec, idmem);
1da177e4 LT	513
	514	state->type = type;
	515	}
	516
	517	switch (state->type) {
	518	case ICS_TYPE_A3IN:
	519	dev_warn(&ec->dev, "A3IN unsupported\n");
	520	ret = -ENODEV;
	521	break;
	522
	523	case ICS_TYPE_A3USER:
	524	dev_warn(&ec->dev, "A3USER unsupported\n");
	525	ret = -ENODEV;
	526	break;
	527
	528	case ICS_TYPE_V5:
	529	ret = icside_register_v5(state, ec);
	530	break;
	531
	532	case ICS_TYPE_V6:
	533	ret = icside_register_v6(state, ec);
	534	break;
	535
	536	default:
	537	dev_warn(&ec->dev, "unknown interface type\n");
	538	ret = -ENODEV;
	539	break;
	540	}
	541
26839f09	542	if (ret == 0)
1da177e4	543	goto out;
1da177e4 LT	544
	545	kfree(state);
	546	release:
	547	ecard_release_resources(ec);
	548	out:
	549	return ret;
	550	}
	551
	552	static void __devexit icside_remove(struct expansion_card *ec)
	553	{
	554	struct icside_state *state = ecard_get_drvdata(ec);
	555
	556	switch (state->type) {
	557	case ICS_TYPE_V5:
	558	/* FIXME: tell IDE to stop using the interface */
	559
	560	/* Disable interrupts */
	561	icside_irqdisable_arcin_v5(ec, 0);
	562	break;
	563
	564	case ICS_TYPE_V6:
	565	/* FIXME: tell IDE to stop using the interface */
	566	if (ec->dma != NO_DMA)
	567	free_dma(ec->dma);
	568
	569	/* Disable interrupts */
	570	icside_irqdisable_arcin_v6(ec, 0);
	571
	572	/* Reset the ROM pointer/EASI selection */
	573	writeb(0, state->ioc_base);
	574	break;
	575	}
	576
	577	ecard_set_drvdata(ec, NULL);
1da177e4	578
1da177e4 LT	579	kfree(state);
	580	ecard_release_resources(ec);
	581	}
	582
	583	static void icside_shutdown(struct expansion_card *ec)
	584	{
	585	struct icside_state *state = ecard_get_drvdata(ec);
	586	unsigned long flags;
	587
	588	/*
	589	* Disable interrupts from this card. We need to do
	590	* this before disabling EASI since we may be accessing
	591	* this register via that region.
	592	*/
	593	local_irq_save(flags);
	594	ec->ops->irqdisable(ec, 0);
	595	local_irq_restore(flags);
	596
	597	/*
	598	* Reset the ROM pointer so that we can read the ROM
	599	* after a soft reboot. This also disables access to
	600	* the IDE taskfile via the EASI region.
	601	*/
	602	if (state->ioc_base)
	603	writeb(0, state->ioc_base);
	604	}
	605
	606	static const struct ecard_id icside_ids[] = {
	607	{ MANU_ICS, PROD_ICS_IDE },
	608	{ MANU_ICS2, PROD_ICS2_IDE },
	609	{ 0xffff, 0xffff }
	610	};
	611
	612	static struct ecard_driver icside_driver = {
	613	.probe = icside_probe,
	614	.remove = __devexit_p(icside_remove),
	615	.shutdown = icside_shutdown,
	616	.id_table = icside_ids,
	617	.drv = {
	618	.name = "icside",
	619	},
	620	};
	621
	622	static int __init icside_init(void)
	623	{
	624	return ecard_register_driver(&icside_driver);
	625	}
	626
1137fb67	627	static void __exit icside_exit(void)
8e27cb11	628	{
1137fb67	629	ecard_remove_driver(&icside_driver);
8e27cb11 BZ	630	}
8e27cb11 BZ	631
1da177e4 LT	632	MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>");
	633	MODULE_LICENSE("GPL");
	634	MODULE_DESCRIPTION("ICS IDE driver");
	635
	636	module_init(icside_init);
8e27cb11	637	module_exit(icside_exit);