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IDE: sg chaining support
[deliverable/linux.git] / drivers / ide / ide-dma.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/drivers/ide/ide-dma.c Version 4.10 June 9, 2000
3 *
4 * Copyright (c) 1999-2000 Andre Hedrick <andre@linux-ide.org>
5 * May be copied or modified under the terms of the GNU General Public License
6 */
7
8/*
9 * Special Thanks to Mark for his Six years of work.
10 *
11 * Copyright (c) 1995-1998 Mark Lord
12 * May be copied or modified under the terms of the GNU General Public License
13 */
14
15/*
16 * This module provides support for the bus-master IDE DMA functions
17 * of various PCI chipsets, including the Intel PIIX (i82371FB for
18 * the 430 FX chipset), the PIIX3 (i82371SB for the 430 HX/VX and
19 * 440 chipsets), and the PIIX4 (i82371AB for the 430 TX chipset)
20 * ("PIIX" stands for "PCI ISA IDE Xcellerator").
21 *
22 * Pretty much the same code works for other IDE PCI bus-mastering chipsets.
23 *
24 * DMA is supported for all IDE devices (disk drives, cdroms, tapes, floppies).
25 *
26 * By default, DMA support is prepared for use, but is currently enabled only
27 * for drives which already have DMA enabled (UltraDMA or mode 2 multi/single),
28 * or which are recognized as "good" (see table below). Drives with only mode0
29 * or mode1 (multi/single) DMA should also work with this chipset/driver
30 * (eg. MC2112A) but are not enabled by default.
31 *
32 * Use "hdparm -i" to view modes supported by a given drive.
33 *
34 * The hdparm-3.5 (or later) utility can be used for manually enabling/disabling
35 * DMA support, but must be (re-)compiled against this kernel version or later.
36 *
37 * To enable DMA, use "hdparm -d1 /dev/hd?" on a per-drive basis after booting.
38 * If problems arise, ide.c will disable DMA operation after a few retries.
39 * This error recovery mechanism works and has been extremely well exercised.
40 *
41 * IDE drives, depending on their vintage, may support several different modes
42 * of DMA operation. The boot-time modes are indicated with a "*" in
43 * the "hdparm -i" listing, and can be changed with *knowledgeable* use of
44 * the "hdparm -X" feature. There is seldom a need to do this, as drives
45 * normally power-up with their "best" PIO/DMA modes enabled.
46 *
47 * Testing has been done with a rather extensive number of drives,
48 * with Quantum & Western Digital models generally outperforming the pack,
49 * and Fujitsu & Conner (and some Seagate which are really Conner) drives
50 * showing more lackluster throughput.
51 *
52 * Keep an eye on /var/adm/messages for "DMA disabled" messages.
53 *
54 * Some people have reported trouble with Intel Zappa motherboards.
55 * This can be fixed by upgrading the AMI BIOS to version 1.00.04.BS0,
56 * available from ftp://ftp.intel.com/pub/bios/10004bs0.exe
57 * (thanks to Glen Morrell <glen@spin.Stanford.edu> for researching this).
58 *
59 * Thanks to "Christopher J. Reimer" <reimer@doe.carleton.ca> for
60 * fixing the problem with the BIOS on some Acer motherboards.
61 *
62 * Thanks to "Benoit Poulot-Cazajous" <poulot@chorus.fr> for testing
63 * "TX" chipset compatibility and for providing patches for the "TX" chipset.
64 *
65 * Thanks to Christian Brunner <chb@muc.de> for taking a good first crack
66 * at generic DMA -- his patches were referred to when preparing this code.
67 *
68 * Most importantly, thanks to Robert Bringman <rob@mars.trion.com>
69 * for supplying a Promise UDMA board & WD UDMA drive for this work!
70 *
71 * And, yes, Intel Zappa boards really *do* use both PIIX IDE ports.
72 *
73 * ATA-66/100 and recovery functions, I forgot the rest......
74 *
75 */
76
1da177e4
LT		 77#include <linux/module.h>
78#include <linux/types.h>
79#include <linux/kernel.h>
80#include <linux/timer.h>
81#include <linux/mm.h>
82#include <linux/interrupt.h>
83#include <linux/pci.h>
84#include <linux/init.h>
85#include <linux/ide.h>
86#include <linux/delay.h>
87#include <linux/scatterlist.h>
88
89#include <asm/io.h>
90#include <asm/irq.h>
91
1da177e4
LT		 92static const struct drive_list_entry drive_whitelist [] = {
93
c2d3ce8c
JH		 94 { "Micropolis 2112A" , NULL },
95 { "CONNER CTMA 4000" , NULL },
96 { "CONNER CTT8000-A" , NULL },
97 { "ST34342A" , NULL },
1da177e4
LT		 98 { NULL , NULL }
99};
100
101static const struct drive_list_entry drive_blacklist [] = {
102
c2d3ce8c
JH		 103 { "WDC AC11000H" , NULL },
104 { "WDC AC22100H" , NULL },
105 { "WDC AC32500H" , NULL },
106 { "WDC AC33100H" , NULL },
107 { "WDC AC31600H" , NULL },
1da177e4
LT		 108 { "WDC AC32100H" , "24.09P07" },
109 { "WDC AC23200L" , "21.10N21" },
c2d3ce8c
JH		 110 { "Compaq CRD-8241B" , NULL },
111 { "CRD-8400B" , NULL },
112 { "CRD-8480B", NULL },
113 { "CRD-8482B", NULL },
114 { "CRD-84" , NULL },
115 { "SanDisk SDP3B" , NULL },
116 { "SanDisk SDP3B-64" , NULL },
117 { "SANYO CD-ROM CRD" , NULL },
118 { "HITACHI CDR-8" , NULL },
119 { "HITACHI CDR-8335" , NULL },
120 { "HITACHI CDR-8435" , NULL },
121 { "Toshiba CD-ROM XM-6202B" , NULL },
122 { "TOSHIBA CD-ROM XM-1702BC", NULL },
123 { "CD-532E-A" , NULL },
124 { "E-IDE CD-ROM CR-840", NULL },
125 { "CD-ROM Drive/F5A", NULL },
126 { "WPI CDD-820", NULL },
127 { "SAMSUNG CD-ROM SC-148C", NULL },
128 { "SAMSUNG CD-ROM SC", NULL },
129 { "ATAPI CD-ROM DRIVE 40X MAXIMUM", NULL },
130 { "_NEC DV5800A", NULL },
5a6248ca 131 { "SAMSUNG CD-ROM SN-124", "N001" },
c2d3ce8c 132 { "Seagate STT20000A", NULL },
1da177e4
LT		 133 { NULL , NULL }
134
135};
136
1da177e4
LT		 137/**
138 * ide_dma_intr - IDE DMA interrupt handler
139 * @drive: the drive the interrupt is for
140 *
141 * Handle an interrupt completing a read/write DMA transfer on an
142 * IDE device
143 */
144
145ide_startstop_t ide_dma_intr (ide_drive_t *drive)
146{
147 u8 stat = 0, dma_stat = 0;
148
149 dma_stat = HWIF(drive)->ide_dma_end(drive);
150 stat = HWIF(drive)->INB(IDE_STATUS_REG); /* get drive status */
151 if (OK_STAT(stat,DRIVE_READY,drive->bad_wstat|DRQ_STAT)) {
152 if (!dma_stat) {
153 struct request *rq = HWGROUP(drive)->rq;
154
155 if (rq->rq_disk) {
156 ide_driver_t *drv;
157
53b3531b 158 drv = *(ide_driver_t **)rq->rq_disk->private_data;
1da177e4
LT		 159 drv->end_request(drive, 1, rq->nr_sectors);
160 } else
161 ide_end_request(drive, 1, rq->nr_sectors);
162 return ide_stopped;
163 }
164 printk(KERN_ERR "%s: dma_intr: bad DMA status (dma_stat=%x)\n",
165 drive->name, dma_stat);
166 }
167 return ide_error(drive, "dma_intr", stat);
168}
169
170EXPORT_SYMBOL_GPL(ide_dma_intr);
171
75d7d963
BZ		 172static int ide_dma_good_drive(ide_drive_t *drive)
173{
174 return ide_in_drive_list(drive->id, drive_whitelist);
175}
176
1da177e4
LT		 177#ifdef CONFIG_BLK_DEV_IDEDMA_PCI
178/**
179 * ide_build_sglist - map IDE scatter gather for DMA I/O
180 * @drive: the drive to build the DMA table for
181 * @rq: the request holding the sg list
182 *
183 * Perform the PCI mapping magic necessary to access the source or
184 * target buffers of a request via PCI DMA. The lower layers of the
185 * kernel provide the necessary cache management so that we can
186 * operate in a portable fashion
187 */
188
189int ide_build_sglist(ide_drive_t *drive, struct request *rq)
190{
191 ide_hwif_t *hwif = HWIF(drive);
192 struct scatterlist *sg = hwif->sg_table;
193
4aff5e23 194 BUG_ON((rq->cmd_type == REQ_TYPE_ATA_TASKFILE) && rq->nr_sectors > 256);
1da177e4
LT		 195
196 ide_map_sg(drive, rq);
197
198 if (rq_data_dir(rq) == READ)
199 hwif->sg_dma_direction = PCI_DMA_FROMDEVICE;
200 else
201 hwif->sg_dma_direction = PCI_DMA_TODEVICE;
202
203 return pci_map_sg(hwif->pci_dev, sg, hwif->sg_nents, hwif->sg_dma_direction);
204}
205
206EXPORT_SYMBOL_GPL(ide_build_sglist);
207
208/**
209 * ide_build_dmatable - build IDE DMA table
210 *
211 * ide_build_dmatable() prepares a dma request. We map the command
212 * to get the pci bus addresses of the buffers and then build up
213 * the PRD table that the IDE layer wants to be fed. The code
214 * knows about the 64K wrap bug in the CS5530.
215 *
216 * Returns the number of built PRD entries if all went okay,
217 * returns 0 otherwise.
218 *
219 * May also be invoked from trm290.c
220 */
221
222int ide_build_dmatable (ide_drive_t *drive, struct request *rq)
223{
224 ide_hwif_t *hwif = HWIF(drive);
225 unsigned int *table = hwif->dmatable_cpu;
226 unsigned int is_trm290 = (hwif->chipset == ide_trm290) ? 1 : 0;
227 unsigned int count = 0;
228 int i;
229 struct scatterlist *sg;
230
231 hwif->sg_nents = i = ide_build_sglist(drive, rq);
232
233 if (!i)
234 return 0;
235
236 sg = hwif->sg_table;
237 while (i) {
238 u32 cur_addr;
239 u32 cur_len;
240
241 cur_addr = sg_dma_address(sg);
242 cur_len = sg_dma_len(sg);
243
244 /*
245 * Fill in the dma table, without crossing any 64kB boundaries.
246 * Most hardware requires 16-bit alignment of all blocks,
247 * but the trm290 requires 32-bit alignment.
248 */
249
250 while (cur_len) {
251 if (count++ >= PRD_ENTRIES) {
252 printk(KERN_ERR "%s: DMA table too small\n", drive->name);
253 goto use_pio_instead;
254 } else {
255 u32 xcount, bcount = 0x10000 - (cur_addr & 0xffff);
256
257 if (bcount > cur_len)
258 bcount = cur_len;
259 *table++ = cpu_to_le32(cur_addr);
260 xcount = bcount & 0xffff;
261 if (is_trm290)
262 xcount = ((xcount >> 2) - 1) << 16;
263 if (xcount == 0x0000) {
264 /*
265 * Most chipsets correctly interpret a length of 0x0000 as 64KB,
266 * but at least one (e.g. CS5530) misinterprets it as zero (!).
267 * So here we break the 64KB entry into two 32KB entries instead.
268 */
269 if (count++ >= PRD_ENTRIES) {
270 printk(KERN_ERR "%s: DMA table too small\n", drive->name);
271 goto use_pio_instead;
272 }
273 *table++ = cpu_to_le32(0x8000);
274 *table++ = cpu_to_le32(cur_addr + 0x8000);
275 xcount = 0x8000;
276 }
277 *table++ = cpu_to_le32(xcount);
278 cur_addr += bcount;
279 cur_len -= bcount;
280 }
281 }
282
55c16a70 283 sg = sg_next(sg);
1da177e4
LT		 284 i--;
285 }
286
287 if (count) {
288 if (!is_trm290)
289 *--table |= cpu_to_le32(0x80000000);
290 return count;
291 }
292 printk(KERN_ERR "%s: empty DMA table?\n", drive->name);
293use_pio_instead:
294 pci_unmap_sg(hwif->pci_dev,
295 hwif->sg_table,
296 hwif->sg_nents,
297 hwif->sg_dma_direction);
298 return 0; /* revert to PIO for this request */
299}
300
301EXPORT_SYMBOL_GPL(ide_build_dmatable);
302
303/**
304 * ide_destroy_dmatable - clean up DMA mapping
305 * @drive: The drive to unmap
306 *
307 * Teardown mappings after DMA has completed. This must be called
308 * after the completion of each use of ide_build_dmatable and before
309 * the next use of ide_build_dmatable. Failure to do so will cause
310 * an oops as only one mapping can be live for each target at a given
311 * time.
312 */
313
314void ide_destroy_dmatable (ide_drive_t *drive)
315{
316 struct pci_dev *dev = HWIF(drive)->pci_dev;
317 struct scatterlist *sg = HWIF(drive)->sg_table;
318 int nents = HWIF(drive)->sg_nents;
319
320 pci_unmap_sg(dev, sg, nents, HWIF(drive)->sg_dma_direction);
321}
322
323EXPORT_SYMBOL_GPL(ide_destroy_dmatable);
324
325/**
326 * config_drive_for_dma - attempt to activate IDE DMA
327 * @drive: the drive to place in DMA mode
328 *
329 * If the drive supports at least mode 2 DMA or UDMA of any kind
330 * then attempt to place it into DMA mode. Drives that are known to
331 * support DMA but predate the DMA properties or that are known
332 * to have DMA handling bugs are also set up appropriately based
333 * on the good/bad drive lists.
334 */
335
336static int config_drive_for_dma (ide_drive_t *drive)
337{
1116fae5 338 ide_hwif_t *hwif = drive->hwif;
1da177e4 339 struct hd_driveid *id = drive->id;
1da177e4 340
1116fae5
BZ		 341 /* consult the list of known "bad" drives */
342 if (__ide_dma_bad_drive(drive))
343 return -1;
344
345 if (drive->media != ide_disk && hwif->atapi_dma == 0)
346 return -1;
347
348 if ((id->capability & 1) && drive->autodma) {
1da177e4
LT		 349 /*
350 * Enable DMA on any drive that has
351 * UltraDMA (mode 0/1/2/3/4/5/6) enabled
352 */
353 if ((id->field_valid & 4) && ((id->dma_ultra >> 8) & 0x7f))
3608b5d7 354 return 0;
1da177e4
LT		 355 /*
356 * Enable DMA on any drive that has mode2 DMA
357 * (multi or single) enabled
358 */
359 if (id->field_valid & 2) /* regular DMA */
360 if ((id->dma_mword & 0x404) == 0x404 ||
361 (id->dma_1word & 0x404) == 0x404)
3608b5d7 362 return 0;
1da177e4
LT		 363
364 /* Consult the list of known "good" drives */
75d7d963 365 if (ide_dma_good_drive(drive))
3608b5d7 366 return 0;
1da177e4 367 }
3608b5d7
BZ		 368
369 return -1;
1da177e4
LT		 370}
371
372/**
373 * dma_timer_expiry - handle a DMA timeout
374 * @drive: Drive that timed out
375 *
376 * An IDE DMA transfer timed out. In the event of an error we ask
377 * the driver to resolve the problem, if a DMA transfer is still
378 * in progress we continue to wait (arguably we need to add a
379 * secondary 'I don't care what the drive thinks' timeout here)
380 * Finally if we have an interrupt we let it complete the I/O.
381 * But only one time - we clear expiry and if it's still not
382 * completed after WAIT_CMD, we error and retry in PIO.
383 * This can occur if an interrupt is lost or due to hang or bugs.
384 */
385
386static int dma_timer_expiry (ide_drive_t *drive)
387{
388 ide_hwif_t *hwif = HWIF(drive);
389 u8 dma_stat = hwif->INB(hwif->dma_status);
390
391 printk(KERN_WARNING "%s: dma_timer_expiry: dma status == 0x%02x\n",
392 drive->name, dma_stat);
393
394 if ((dma_stat & 0x18) == 0x18) /* BUSY Stupid Early Timer !! */
395 return WAIT_CMD;
396
397 HWGROUP(drive)->expiry = NULL; /* one free ride for now */
398
399 /* 1 dmaing, 2 error, 4 intr */
400 if (dma_stat & 2) /* ERROR */
401 return -1;
402
403 if (dma_stat & 1) /* DMAing */
404 return WAIT_CMD;
405
406 if (dma_stat & 4) /* Got an Interrupt */
407 return WAIT_CMD;
408
409 return 0; /* Status is unknown -- reset the bus */
410}
411
412/**
7469aaf6 413 * ide_dma_host_off - Generic DMA kill
1da177e4
LT		 414 * @drive: drive to control
415 *
416 * Perform the generic IDE controller DMA off operation. This
417 * works for most IDE bus mastering controllers
418 */
419
7469aaf6 420void ide_dma_host_off(ide_drive_t *drive)
1da177e4
LT		 421{
422 ide_hwif_t *hwif = HWIF(drive);
423 u8 unit = (drive->select.b.unit & 0x01);
424 u8 dma_stat = hwif->INB(hwif->dma_status);
425
426 hwif->OUTB((dma_stat & ~(1<<(5+unit))), hwif->dma_status);
1da177e4
LT		 427}
428
7469aaf6 429EXPORT_SYMBOL(ide_dma_host_off);
1da177e4
LT		 430
431/**
7469aaf6 432 * ide_dma_off_quietly - Generic DMA kill
1da177e4
LT		 433 * @drive: drive to control
434 *
435 * Turn off the current DMA on this IDE controller.
436 */
437
7469aaf6 438void ide_dma_off_quietly(ide_drive_t *drive)
1da177e4
LT		 439{
440 drive->using_dma = 0;
441 ide_toggle_bounce(drive, 0);
442
7469aaf6 443 drive->hwif->dma_host_off(drive);
1da177e4
LT		 444}
445
7469aaf6 446EXPORT_SYMBOL(ide_dma_off_quietly);
1da177e4
LT		 447#endif /* CONFIG_BLK_DEV_IDEDMA_PCI */
448
449/**
7469aaf6 450 * ide_dma_off - disable DMA on a device
1da177e4
LT		 451 * @drive: drive to disable DMA on
452 *
453 * Disable IDE DMA for a device on this IDE controller.
454 * Inform the user that DMA has been disabled.
455 */
456
7469aaf6 457void ide_dma_off(ide_drive_t *drive)
1da177e4
LT		 458{
459 printk(KERN_INFO "%s: DMA disabled\n", drive->name);
7469aaf6 460 drive->hwif->dma_off_quietly(drive);
1da177e4
LT		 461}
462
7469aaf6 463EXPORT_SYMBOL(ide_dma_off);
1da177e4
LT		 464
465#ifdef CONFIG_BLK_DEV_IDEDMA_PCI
466/**
ccf35289 467 * ide_dma_host_on - Enable DMA on a host
1da177e4
LT		 468 * @drive: drive to enable for DMA
469 *
470 * Enable DMA on an IDE controller following generic bus mastering
471 * IDE controller behaviour
472 */
ccf35289
BZ		 473
474void ide_dma_host_on(ide_drive_t *drive)
1da177e4
LT		 475{
476 if (drive->using_dma) {
477 ide_hwif_t *hwif = HWIF(drive);
478 u8 unit = (drive->select.b.unit & 0x01);
479 u8 dma_stat = hwif->INB(hwif->dma_status);
480
481 hwif->OUTB((dma_stat|(1<<(5+unit))), hwif->dma_status);
1da177e4 482 }
1da177e4
LT		 483}
484
ccf35289 485EXPORT_SYMBOL(ide_dma_host_on);
1da177e4
LT		 486
487/**
488 * __ide_dma_on - Enable DMA on a device
489 * @drive: drive to enable DMA on
490 *
491 * Enable IDE DMA for a device on this IDE controller.
492 */
493
494int __ide_dma_on (ide_drive_t *drive)
495{
496 /* consult the list of known "bad" drives */
497 if (__ide_dma_bad_drive(drive))
498 return 1;
499
500 drive->using_dma = 1;
501 ide_toggle_bounce(drive, 1);
502
ccf35289 503 drive->hwif->dma_host_on(drive);
1da177e4
LT		 504
505 return 0;
506}
507
508EXPORT_SYMBOL(__ide_dma_on);
509
1da177e4
LT		 510/**
511 * ide_dma_setup - begin a DMA phase
512 * @drive: target device
513 *
514 * Build an IDE DMA PRD (IDE speak for scatter gather table)
515 * and then set up the DMA transfer registers for a device
516 * that follows generic IDE PCI DMA behaviour. Controllers can
517 * override this function if they need to
518 *
519 * Returns 0 on success. If a PIO fallback is required then 1
520 * is returned.
521 */
522
523int ide_dma_setup(ide_drive_t *drive)
524{
525 ide_hwif_t *hwif = drive->hwif;
526 struct request *rq = HWGROUP(drive)->rq;
527 unsigned int reading;
528 u8 dma_stat;
529
530 if (rq_data_dir(rq))
531 reading = 0;
532 else
533 reading = 1 << 3;
534
535 /* fall back to pio! */
536 if (!ide_build_dmatable(drive, rq)) {
537 ide_map_sg(drive, rq);
538 return 1;
539 }
540
541 /* PRD table */
2ad1e558 542 if (hwif->mmio)
0ecdca26
BZ		 543 writel(hwif->dmatable_dma, (void __iomem *)hwif->dma_prdtable);
544 else
545 outl(hwif->dmatable_dma, hwif->dma_prdtable);
1da177e4
LT		 546
547 /* specify r/w */
548 hwif->OUTB(reading, hwif->dma_command);
549
550 /* read dma_status for INTR & ERROR flags */
551 dma_stat = hwif->INB(hwif->dma_status);
552
553 /* clear INTR & ERROR flags */
554 hwif->OUTB(dma_stat|6, hwif->dma_status);
555 drive->waiting_for_dma = 1;
556 return 0;
557}
558
559EXPORT_SYMBOL_GPL(ide_dma_setup);
560
561static void ide_dma_exec_cmd(ide_drive_t *drive, u8 command)
562{
563 /* issue cmd to drive */
564 ide_execute_command(drive, command, &ide_dma_intr, 2*WAIT_CMD, dma_timer_expiry);
565}
566
567void ide_dma_start(ide_drive_t *drive)
568{
569 ide_hwif_t *hwif = HWIF(drive);
570 u8 dma_cmd = hwif->INB(hwif->dma_command);
571
572 /* Note that this is done *after* the cmd has
573 * been issued to the drive, as per the BM-IDE spec.
574 * The Promise Ultra33 doesn't work correctly when
575 * we do this part before issuing the drive cmd.
576 */
577 /* start DMA */
578 hwif->OUTB(dma_cmd|1, hwif->dma_command);
579 hwif->dma = 1;
580 wmb();
581}
582
583EXPORT_SYMBOL_GPL(ide_dma_start);
584
585/* returns 1 on error, 0 otherwise */
586int __ide_dma_end (ide_drive_t *drive)
587{
588 ide_hwif_t *hwif = HWIF(drive);
589 u8 dma_stat = 0, dma_cmd = 0;
590
591 drive->waiting_for_dma = 0;
592 /* get dma_command mode */
593 dma_cmd = hwif->INB(hwif->dma_command);
594 /* stop DMA */
595 hwif->OUTB(dma_cmd&~1, hwif->dma_command);
596 /* get DMA status */
597 dma_stat = hwif->INB(hwif->dma_status);
598 /* clear the INTR & ERROR bits */
599 hwif->OUTB(dma_stat|6, hwif->dma_status);
600 /* purge DMA mappings */
601 ide_destroy_dmatable(drive);
602 /* verify good DMA status */
603 hwif->dma = 0;
604 wmb();
605 return (dma_stat & 7) != 4 ? (0x10 | dma_stat) : 0;
606}
607
608EXPORT_SYMBOL(__ide_dma_end);
609
610/* returns 1 if dma irq issued, 0 otherwise */
611static int __ide_dma_test_irq(ide_drive_t *drive)
612{
613 ide_hwif_t *hwif = HWIF(drive);
614 u8 dma_stat = hwif->INB(hwif->dma_status);
615
616#if 0 /* do not set unless you know what you are doing */
617 if (dma_stat & 4) {
618 u8 stat = hwif->INB(IDE_STATUS_REG);
619 hwif->OUTB(hwif->dma_status, dma_stat & 0xE4);
620 }
621#endif
622 /* return 1 if INTR asserted */
623 if ((dma_stat & 4) == 4)
624 return 1;
625 if (!drive->waiting_for_dma)
626 printk(KERN_WARNING "%s: (%s) called while not waiting\n",
627 drive->name, __FUNCTION__);
628 return 0;
629}
630#endif /* CONFIG_BLK_DEV_IDEDMA_PCI */
631
632int __ide_dma_bad_drive (ide_drive_t *drive)
633{
634 struct hd_driveid *id = drive->id;
635
65e5f2e3 636 int blacklist = ide_in_drive_list(id, drive_blacklist);
1da177e4
LT		 637 if (blacklist) {
638 printk(KERN_WARNING "%s: Disabling (U)DMA for %s (blacklisted)\n",
639 drive->name, id->model);
640 return blacklist;
641 }
642 return 0;
643}
644
645EXPORT_SYMBOL(__ide_dma_bad_drive);
646
2d5eaa6d
BZ		 647static const u8 xfer_mode_bases[] = {
648 XFER_UDMA_0,
649 XFER_MW_DMA_0,
650 XFER_SW_DMA_0,
651};
652
7670df73 653static unsigned int ide_get_mode_mask(ide_drive_t *drive, u8 base, u8 req_mode)
2d5eaa6d
BZ		 654{
655 struct hd_driveid *id = drive->id;
656 ide_hwif_t *hwif = drive->hwif;
657 unsigned int mask = 0;
658
659 switch(base) {
660 case XFER_UDMA_0:
661 if ((id->field_valid & 4) == 0)
662 break;
663
2d5eaa6d 664 if (hwif->udma_filter)
851dd33b
SS		 665 mask = hwif->udma_filter(drive);
666 else
667 mask = hwif->ultra_mask;
668 mask &= id->dma_ultra;
2d5eaa6d 669
7670df73
BZ		 670 /*
671 * avoid false cable warning from eighty_ninty_three()
672 */
673 if (req_mode > XFER_UDMA_2) {
674 if ((mask & 0x78) && (eighty_ninty_three(drive) == 0))
675 mask &= 0x07;
676 }
2d5eaa6d
BZ		 677 break;
678 case XFER_MW_DMA_0:
b4e44369
SS		 679 if ((id->field_valid & 2) == 0)
680 break;
681 if (hwif->mdma_filter)
682 mask = hwif->mdma_filter(drive);
683 else
684 mask = hwif->mwdma_mask;
685 mask &= id->dma_mword;
2d5eaa6d
BZ		 686 break;
687 case XFER_SW_DMA_0:
15a4f943 688 if (id->field_valid & 2) {
3649c06e 689 mask = id->dma_1word & hwif->swdma_mask;
15a4f943
BZ		 690 } else if (id->tDMA) {
691 /*
692 * ide_fix_driveid() doesn't convert ->tDMA to the
693 * CPU endianness so we need to do it here
694 */
695 u8 mode = le16_to_cpu(id->tDMA);
696
697 /*
698 * if the mode is valid convert it to the mask
699 * (the maximum allowed mode is XFER_SW_DMA_2)
700 */
701 if (mode <= 2)
702 mask = ((2 << mode) - 1) & hwif->swdma_mask;
703 }
2d5eaa6d
BZ		 704 break;
705 default:
706 BUG();
707 break;
708 }
709
710 return mask;
711}
712
713/**
7670df73 714 * ide_find_dma_mode - compute DMA speed
2d5eaa6d 715 * @drive: IDE device
7670df73
BZ		 716 * @req_mode: requested mode
717 *
718 * Checks the drive/host capabilities and finds the speed to use for
719 * the DMA transfer. The speed is then limited by the requested mode.
2d5eaa6d 720 *
7670df73
BZ		 721 * Returns 0 if the drive/host combination is incapable of DMA transfers
722 * or if the requested mode is not a DMA mode.
2d5eaa6d
BZ		 723 */
724
7670df73 725u8 ide_find_dma_mode(ide_drive_t *drive, u8 req_mode)
2d5eaa6d
BZ		 726{
727 ide_hwif_t *hwif = drive->hwif;
728 unsigned int mask;
729 int x, i;
730 u8 mode = 0;
731
732 if (drive->media != ide_disk && hwif->atapi_dma == 0)
733 return 0;
734
735 for (i = 0; i < ARRAY_SIZE(xfer_mode_bases); i++) {
7670df73
BZ		 736 if (req_mode < xfer_mode_bases[i])
737 continue;
738 mask = ide_get_mode_mask(drive, xfer_mode_bases[i], req_mode);
2d5eaa6d
BZ		 739 x = fls(mask) - 1;
740 if (x >= 0) {
741 mode = xfer_mode_bases[i] + x;
742 break;
743 }
744 }
745
75d7d963
BZ		 746 if (hwif->chipset == ide_acorn && mode == 0) {
747 /*
748 * is this correct?
749 */
750 if (ide_dma_good_drive(drive) && drive->id->eide_dma_time < 150)
751 mode = XFER_MW_DMA_1;
752 }
753
2d5eaa6d
BZ		 754 printk(KERN_DEBUG "%s: selected mode 0x%x\n", drive->name, mode);
755
7670df73 756 return min(mode, req_mode);
2d5eaa6d
BZ		 757}
758
7670df73 759EXPORT_SYMBOL_GPL(ide_find_dma_mode);
2d5eaa6d 760
29e744d0
BZ		 761int ide_tune_dma(ide_drive_t *drive)
762{
763 u8 speed;
764
122ab088
BZ		 765 if ((drive->id->capability & 1) == 0 || drive->autodma == 0)
766 return 0;
767
768 /* consult the list of known "bad" drives */
769 if (__ide_dma_bad_drive(drive))
29e744d0
BZ		 770 return 0;
771
772 speed = ide_max_dma_mode(drive);
773
774 if (!speed)
775 return 0;
776
88b2b32b
BZ		 777 if (drive->hwif->host_flags & IDE_HFLAG_NO_SET_MODE)
778 return 0;
779
780 if (ide_set_dma_mode(drive, speed))
4728d546 781 return 0;
29e744d0 782
4728d546 783 return 1;
29e744d0
BZ		 784}
785
786EXPORT_SYMBOL_GPL(ide_tune_dma);
787
1da177e4
LT		 788void ide_dma_verbose(ide_drive_t *drive)
789{
790 struct hd_driveid *id = drive->id;
791 ide_hwif_t *hwif = HWIF(drive);
792
793 if (id->field_valid & 4) {
794 if ((id->dma_ultra >> 8) && (id->dma_mword >> 8))
795 goto bug_dma_off;
796 if (id->dma_ultra & ((id->dma_ultra >> 8) & hwif->ultra_mask)) {
797 if (((id->dma_ultra >> 11) & 0x1F) &&
798 eighty_ninty_three(drive)) {
799 if ((id->dma_ultra >> 15) & 1) {
800 printk(", UDMA(mode 7)");
801 } else if ((id->dma_ultra >> 14) & 1) {
802 printk(", UDMA(133)");
803 } else if ((id->dma_ultra >> 13) & 1) {
804 printk(", UDMA(100)");
805 } else if ((id->dma_ultra >> 12) & 1) {
806 printk(", UDMA(66)");
807 } else if ((id->dma_ultra >> 11) & 1) {
808 printk(", UDMA(44)");
809 } else
810 goto mode_two;
811 } else {
812 mode_two:
813 if ((id->dma_ultra >> 10) & 1) {
814 printk(", UDMA(33)");
815 } else if ((id->dma_ultra >> 9) & 1) {
816 printk(", UDMA(25)");
817 } else if ((id->dma_ultra >> 8) & 1) {
818 printk(", UDMA(16)");
819 }
820 }
821 } else {
822 printk(", (U)DMA"); /* Can be BIOS-enabled! */
823 }
824 } else if (id->field_valid & 2) {
825 if ((id->dma_mword >> 8) && (id->dma_1word >> 8))
826 goto bug_dma_off;
827 printk(", DMA");
828 } else if (id->field_valid & 1) {
0a8348d0 829 goto bug_dma_off;
1da177e4
LT		 830 }
831 return;
832bug_dma_off:
833 printk(", BUG DMA OFF");
7469aaf6 834 hwif->dma_off_quietly(drive);
1da177e4
LT		 835 return;
836}
837
838EXPORT_SYMBOL(ide_dma_verbose);
839
3608b5d7
BZ		 840int ide_set_dma(ide_drive_t *drive)
841{
842 ide_hwif_t *hwif = drive->hwif;
843 int rc;
844
845 rc = hwif->ide_dma_check(drive);
846
847 switch(rc) {
848 case -1: /* DMA needs to be disabled */
7469aaf6 849 hwif->dma_off_quietly(drive);
6f5050a9 850 return -1;
3608b5d7
BZ		 851 case 0: /* DMA needs to be enabled */
852 return hwif->ide_dma_on(drive);
853 case 1: /* DMA setting cannot be changed */
854 break;
855 default:
856 BUG();
857 break;
858 }
859
860 return rc;
861}
862
1da177e4 863#ifdef CONFIG_BLK_DEV_IDEDMA_PCI
841d2a9b 864void ide_dma_lost_irq (ide_drive_t *drive)
1da177e4
LT		 865{
866 printk("%s: DMA interrupt recovery\n", drive->name);
1da177e4
LT		 867}
868
841d2a9b 869EXPORT_SYMBOL(ide_dma_lost_irq);
1da177e4 870
c283f5db 871void ide_dma_timeout (ide_drive_t *drive)
1da177e4 872{
c283f5db
SS		 873 ide_hwif_t *hwif = HWIF(drive);
874
1da177e4 875 printk(KERN_ERR "%s: timeout waiting for DMA\n", drive->name);
1da177e4 876
c283f5db
SS		 877 if (hwif->ide_dma_test_irq(drive))
878 return;
879
880 hwif->ide_dma_end(drive);
1da177e4
LT		 881}
882
c283f5db 883EXPORT_SYMBOL(ide_dma_timeout);
1da177e4
LT		 884
885/*
886 * Needed for allowing full modular support of ide-driver
887 */
888static int ide_release_dma_engine(ide_hwif_t *hwif)
889{
890 if (hwif->dmatable_cpu) {
891 pci_free_consistent(hwif->pci_dev,
892 PRD_ENTRIES * PRD_BYTES,
893 hwif->dmatable_cpu,
894 hwif->dmatable_dma);
895 hwif->dmatable_cpu = NULL;
896 }
897 return 1;
898}
899
900static int ide_release_iomio_dma(ide_hwif_t *hwif)
901{
1da177e4 902 release_region(hwif->dma_base, 8);
020e322d
SS		 903 if (hwif->extra_ports)
904 release_region(hwif->extra_base, hwif->extra_ports);
1da177e4
LT		 905 return 1;
906}
907
908/*
909 * Needed for allowing full modular support of ide-driver
910 */
dc844e05 911int ide_release_dma(ide_hwif_t *hwif)
1da177e4 912{
dc844e05
SS		 913 ide_release_dma_engine(hwif);
914
2ad1e558 915 if (hwif->mmio)
1da177e4 916 return 1;
dc844e05
SS		 917 else
918 return ide_release_iomio_dma(hwif);
1da177e4
LT		 919}
920
921static int ide_allocate_dma_engine(ide_hwif_t *hwif)
922{
923 hwif->dmatable_cpu = pci_alloc_consistent(hwif->pci_dev,
924 PRD_ENTRIES * PRD_BYTES,
925 &hwif->dmatable_dma);
926
927 if (hwif->dmatable_cpu)
928 return 0;
929
dc844e05
SS		 930 printk(KERN_ERR "%s: -- Error, unable to allocate DMA table.\n",
931 hwif->cds->name);
1da177e4 932
1da177e4
LT		 933 return 1;
934}
935
936static int ide_mapped_mmio_dma(ide_hwif_t *hwif, unsigned long base, unsigned int ports)
937{
938 printk(KERN_INFO " %s: MMIO-DMA ", hwif->name);
939
020e322d 940 hwif->dma_base = base;
1da177e4
LT		 941
942 if(hwif->mate)
943 hwif->dma_master = (hwif->channel) ? hwif->mate->dma_base : base;
944 else
945 hwif->dma_master = base;
946 return 0;
947}
948
949static int ide_iomio_dma(ide_hwif_t *hwif, unsigned long base, unsigned int ports)
950{
951 printk(KERN_INFO " %s: BM-DMA at 0x%04lx-0x%04lx",
020e322d
SS		 952 hwif->name, base, base + ports - 1);
953
1da177e4
LT		 954 if (!request_region(base, ports, hwif->name)) {
955 printk(" -- Error, ports in use.\n");
956 return 1;
957 }
020e322d 958
1da177e4 959 hwif->dma_base = base;
020e322d
SS		 960
961 if (hwif->cds->extra) {
962 hwif->extra_base = base + (hwif->channel ? 8 : 16);
963
964 if (!hwif->mate || !hwif->mate->extra_ports) {
965 if (!request_region(hwif->extra_base,
966 hwif->cds->extra, hwif->cds->name)) {
967 printk(" -- Error, extra ports in use.\n");
968 release_region(base, ports);
969 return 1;
970 }
971 hwif->extra_ports = hwif->cds->extra;
972 }
1da177e4 973 }
020e322d 974
1da177e4 975 if(hwif->mate)
3f63c5e8 976 hwif->dma_master = (hwif->channel) ? hwif->mate->dma_base:base;
1da177e4
LT		 977 else
978 hwif->dma_master = base;
1da177e4
LT		 979 return 0;
980}
981
982static int ide_dma_iobase(ide_hwif_t *hwif, unsigned long base, unsigned int ports)
983{
2ad1e558 984 if (hwif->mmio)
1da177e4 985 return ide_mapped_mmio_dma(hwif, base,ports);
2ad1e558 986
1da177e4
LT		 987 return ide_iomio_dma(hwif, base, ports);
988}
989
990/*
991 * This can be called for a dynamically installed interface. Don't __init it
992 */
993void ide_setup_dma (ide_hwif_t *hwif, unsigned long dma_base, unsigned int num_ports)
994{
995 if (ide_dma_iobase(hwif, dma_base, num_ports))
996 return;
997
998 if (ide_allocate_dma_engine(hwif)) {
999 ide_release_dma(hwif);
1000 return;
1001 }
1002
1003 if (!(hwif->dma_command))
1004 hwif->dma_command = hwif->dma_base;
1005 if (!(hwif->dma_vendor1))
1006 hwif->dma_vendor1 = (hwif->dma_base + 1);
1007 if (!(hwif->dma_status))
1008 hwif->dma_status = (hwif->dma_base + 2);
1009 if (!(hwif->dma_vendor3))
1010 hwif->dma_vendor3 = (hwif->dma_base + 3);
1011 if (!(hwif->dma_prdtable))
1012 hwif->dma_prdtable = (hwif->dma_base + 4);
1013
7469aaf6
BZ		 1014 if (!hwif->dma_off_quietly)
1015 hwif->dma_off_quietly = &ide_dma_off_quietly;
1016 if (!hwif->dma_host_off)
1017 hwif->dma_host_off = &ide_dma_host_off;
1da177e4
LT		 1018 if (!hwif->ide_dma_on)
1019 hwif->ide_dma_on = &__ide_dma_on;
ccf35289
BZ		 1020 if (!hwif->dma_host_on)
1021 hwif->dma_host_on = &ide_dma_host_on;
1da177e4 1022 if (!hwif->ide_dma_check)
1116fae5 1023 hwif->ide_dma_check = &config_drive_for_dma;
1da177e4
LT		 1024 if (!hwif->dma_setup)
1025 hwif->dma_setup = &ide_dma_setup;
1026 if (!hwif->dma_exec_cmd)
1027 hwif->dma_exec_cmd = &ide_dma_exec_cmd;
1028 if (!hwif->dma_start)
1029 hwif->dma_start = &ide_dma_start;
1030 if (!hwif->ide_dma_end)
1031 hwif->ide_dma_end = &__ide_dma_end;
1032 if (!hwif->ide_dma_test_irq)
1033 hwif->ide_dma_test_irq = &__ide_dma_test_irq;
c283f5db
SS		 1034 if (!hwif->dma_timeout)
1035 hwif->dma_timeout = &ide_dma_timeout;
841d2a9b
SS		 1036 if (!hwif->dma_lost_irq)
1037 hwif->dma_lost_irq = &ide_dma_lost_irq;
1da177e4
LT		 1038
1039 if (hwif->chipset != ide_trm290) {
1040 u8 dma_stat = hwif->INB(hwif->dma_status);
1041 printk(", BIOS settings: %s:%s, %s:%s",
1042 hwif->drives[0].name, (dma_stat & 0x20) ? "DMA" : "pio",
1043 hwif->drives[1].name, (dma_stat & 0x40) ? "DMA" : "pio");
1044 }
1045 printk("\n");
1046
125e1874 1047 BUG_ON(!hwif->dma_master);
1da177e4
LT		 1048}
1049
1050EXPORT_SYMBOL_GPL(ide_setup_dma);
1051#endif /* CONFIG_BLK_DEV_IDEDMA_PCI */
Linux kernel - Deliverables
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