Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
204f47c5 BZ |
2 | * IDE DMA support (including IDE PCI BM-DMA). |
3 | * | |
59bca8cc BZ |
4 | * Copyright (C) 1995-1998 Mark Lord |
5 | * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org> | |
6 | * Copyright (C) 2004, 2007 Bartlomiej Zolnierkiewicz | |
58f189fc | 7 | * |
1da177e4 | 8 | * May be copied or modified under the terms of the GNU General Public License |
204f47c5 BZ |
9 | * |
10 | * DMA is supported for all IDE devices (disk drives, cdroms, tapes, floppies). | |
1da177e4 LT |
11 | */ |
12 | ||
13 | /* | |
14 | * Special Thanks to Mark for his Six years of work. | |
1da177e4 LT |
15 | */ |
16 | ||
17 | /* | |
1da177e4 LT |
18 | * Thanks to "Christopher J. Reimer" <reimer@doe.carleton.ca> for |
19 | * fixing the problem with the BIOS on some Acer motherboards. | |
20 | * | |
21 | * Thanks to "Benoit Poulot-Cazajous" <poulot@chorus.fr> for testing | |
22 | * "TX" chipset compatibility and for providing patches for the "TX" chipset. | |
23 | * | |
24 | * Thanks to Christian Brunner <chb@muc.de> for taking a good first crack | |
25 | * at generic DMA -- his patches were referred to when preparing this code. | |
26 | * | |
27 | * Most importantly, thanks to Robert Bringman <rob@mars.trion.com> | |
28 | * for supplying a Promise UDMA board & WD UDMA drive for this work! | |
1da177e4 LT |
29 | */ |
30 | ||
1da177e4 LT |
31 | #include <linux/module.h> |
32 | #include <linux/types.h> | |
33 | #include <linux/kernel.h> | |
34 | #include <linux/timer.h> | |
35 | #include <linux/mm.h> | |
36 | #include <linux/interrupt.h> | |
37 | #include <linux/pci.h> | |
38 | #include <linux/init.h> | |
39 | #include <linux/ide.h> | |
40 | #include <linux/delay.h> | |
41 | #include <linux/scatterlist.h> | |
5c05ff68 | 42 | #include <linux/dma-mapping.h> |
1da177e4 LT |
43 | |
44 | #include <asm/io.h> | |
45 | #include <asm/irq.h> | |
46 | ||
1da177e4 LT |
47 | static const struct drive_list_entry drive_whitelist [] = { |
48 | ||
c2d3ce8c JH |
49 | { "Micropolis 2112A" , NULL }, |
50 | { "CONNER CTMA 4000" , NULL }, | |
51 | { "CONNER CTT8000-A" , NULL }, | |
52 | { "ST34342A" , NULL }, | |
1da177e4 LT |
53 | { NULL , NULL } |
54 | }; | |
55 | ||
56 | static const struct drive_list_entry drive_blacklist [] = { | |
57 | ||
c2d3ce8c JH |
58 | { "WDC AC11000H" , NULL }, |
59 | { "WDC AC22100H" , NULL }, | |
60 | { "WDC AC32500H" , NULL }, | |
61 | { "WDC AC33100H" , NULL }, | |
62 | { "WDC AC31600H" , NULL }, | |
1da177e4 LT |
63 | { "WDC AC32100H" , "24.09P07" }, |
64 | { "WDC AC23200L" , "21.10N21" }, | |
c2d3ce8c JH |
65 | { "Compaq CRD-8241B" , NULL }, |
66 | { "CRD-8400B" , NULL }, | |
67 | { "CRD-8480B", NULL }, | |
68 | { "CRD-8482B", NULL }, | |
69 | { "CRD-84" , NULL }, | |
70 | { "SanDisk SDP3B" , NULL }, | |
71 | { "SanDisk SDP3B-64" , NULL }, | |
72 | { "SANYO CD-ROM CRD" , NULL }, | |
73 | { "HITACHI CDR-8" , NULL }, | |
74 | { "HITACHI CDR-8335" , NULL }, | |
75 | { "HITACHI CDR-8435" , NULL }, | |
76 | { "Toshiba CD-ROM XM-6202B" , NULL }, | |
77 | { "TOSHIBA CD-ROM XM-1702BC", NULL }, | |
78 | { "CD-532E-A" , NULL }, | |
79 | { "E-IDE CD-ROM CR-840", NULL }, | |
80 | { "CD-ROM Drive/F5A", NULL }, | |
81 | { "WPI CDD-820", NULL }, | |
82 | { "SAMSUNG CD-ROM SC-148C", NULL }, | |
83 | { "SAMSUNG CD-ROM SC", NULL }, | |
84 | { "ATAPI CD-ROM DRIVE 40X MAXIMUM", NULL }, | |
85 | { "_NEC DV5800A", NULL }, | |
5a6248ca | 86 | { "SAMSUNG CD-ROM SN-124", "N001" }, |
c2d3ce8c | 87 | { "Seagate STT20000A", NULL }, |
b0bc65b9 | 88 | { "CD-ROM CDR_U200", "1.09" }, |
1da177e4 LT |
89 | { NULL , NULL } |
90 | ||
91 | }; | |
92 | ||
1da177e4 LT |
93 | /** |
94 | * ide_dma_intr - IDE DMA interrupt handler | |
95 | * @drive: the drive the interrupt is for | |
96 | * | |
97 | * Handle an interrupt completing a read/write DMA transfer on an | |
98 | * IDE device | |
99 | */ | |
100 | ||
101 | ide_startstop_t ide_dma_intr (ide_drive_t *drive) | |
102 | { | |
103 | u8 stat = 0, dma_stat = 0; | |
104 | ||
105 | dma_stat = HWIF(drive)->ide_dma_end(drive); | |
c47137a9 BZ |
106 | stat = ide_read_status(drive); |
107 | ||
1da177e4 LT |
108 | if (OK_STAT(stat,DRIVE_READY,drive->bad_wstat|DRQ_STAT)) { |
109 | if (!dma_stat) { | |
110 | struct request *rq = HWGROUP(drive)->rq; | |
111 | ||
4d7a984b | 112 | task_end_request(drive, rq, stat); |
1da177e4 LT |
113 | return ide_stopped; |
114 | } | |
115 | printk(KERN_ERR "%s: dma_intr: bad DMA status (dma_stat=%x)\n", | |
116 | drive->name, dma_stat); | |
117 | } | |
118 | return ide_error(drive, "dma_intr", stat); | |
119 | } | |
120 | ||
121 | EXPORT_SYMBOL_GPL(ide_dma_intr); | |
122 | ||
75d7d963 BZ |
123 | static int ide_dma_good_drive(ide_drive_t *drive) |
124 | { | |
125 | return ide_in_drive_list(drive->id, drive_whitelist); | |
126 | } | |
127 | ||
1da177e4 LT |
128 | /** |
129 | * ide_build_sglist - map IDE scatter gather for DMA I/O | |
130 | * @drive: the drive to build the DMA table for | |
131 | * @rq: the request holding the sg list | |
132 | * | |
5c05ff68 BZ |
133 | * Perform the DMA mapping magic necessary to access the source or |
134 | * target buffers of a request via DMA. The lower layers of the | |
1da177e4 | 135 | * kernel provide the necessary cache management so that we can |
5c05ff68 | 136 | * operate in a portable fashion. |
1da177e4 LT |
137 | */ |
138 | ||
139 | int ide_build_sglist(ide_drive_t *drive, struct request *rq) | |
140 | { | |
141 | ide_hwif_t *hwif = HWIF(drive); | |
142 | struct scatterlist *sg = hwif->sg_table; | |
143 | ||
1da177e4 LT |
144 | ide_map_sg(drive, rq); |
145 | ||
146 | if (rq_data_dir(rq) == READ) | |
5c05ff68 | 147 | hwif->sg_dma_direction = DMA_FROM_DEVICE; |
1da177e4 | 148 | else |
5c05ff68 | 149 | hwif->sg_dma_direction = DMA_TO_DEVICE; |
1da177e4 | 150 | |
5c05ff68 BZ |
151 | return dma_map_sg(hwif->dev, sg, hwif->sg_nents, |
152 | hwif->sg_dma_direction); | |
1da177e4 LT |
153 | } |
154 | ||
155 | EXPORT_SYMBOL_GPL(ide_build_sglist); | |
156 | ||
8e882ba1 | 157 | #ifdef CONFIG_BLK_DEV_IDEDMA_SFF |
1da177e4 LT |
158 | /** |
159 | * ide_build_dmatable - build IDE DMA table | |
160 | * | |
161 | * ide_build_dmatable() prepares a dma request. We map the command | |
162 | * to get the pci bus addresses of the buffers and then build up | |
163 | * the PRD table that the IDE layer wants to be fed. The code | |
164 | * knows about the 64K wrap bug in the CS5530. | |
165 | * | |
166 | * Returns the number of built PRD entries if all went okay, | |
167 | * returns 0 otherwise. | |
168 | * | |
169 | * May also be invoked from trm290.c | |
170 | */ | |
171 | ||
172 | int ide_build_dmatable (ide_drive_t *drive, struct request *rq) | |
173 | { | |
174 | ide_hwif_t *hwif = HWIF(drive); | |
175 | unsigned int *table = hwif->dmatable_cpu; | |
176 | unsigned int is_trm290 = (hwif->chipset == ide_trm290) ? 1 : 0; | |
177 | unsigned int count = 0; | |
178 | int i; | |
179 | struct scatterlist *sg; | |
180 | ||
181 | hwif->sg_nents = i = ide_build_sglist(drive, rq); | |
182 | ||
183 | if (!i) | |
184 | return 0; | |
185 | ||
186 | sg = hwif->sg_table; | |
187 | while (i) { | |
188 | u32 cur_addr; | |
189 | u32 cur_len; | |
190 | ||
191 | cur_addr = sg_dma_address(sg); | |
192 | cur_len = sg_dma_len(sg); | |
193 | ||
194 | /* | |
195 | * Fill in the dma table, without crossing any 64kB boundaries. | |
196 | * Most hardware requires 16-bit alignment of all blocks, | |
197 | * but the trm290 requires 32-bit alignment. | |
198 | */ | |
199 | ||
200 | while (cur_len) { | |
201 | if (count++ >= PRD_ENTRIES) { | |
202 | printk(KERN_ERR "%s: DMA table too small\n", drive->name); | |
203 | goto use_pio_instead; | |
204 | } else { | |
205 | u32 xcount, bcount = 0x10000 - (cur_addr & 0xffff); | |
206 | ||
207 | if (bcount > cur_len) | |
208 | bcount = cur_len; | |
209 | *table++ = cpu_to_le32(cur_addr); | |
210 | xcount = bcount & 0xffff; | |
211 | if (is_trm290) | |
212 | xcount = ((xcount >> 2) - 1) << 16; | |
213 | if (xcount == 0x0000) { | |
214 | /* | |
215 | * Most chipsets correctly interpret a length of 0x0000 as 64KB, | |
216 | * but at least one (e.g. CS5530) misinterprets it as zero (!). | |
217 | * So here we break the 64KB entry into two 32KB entries instead. | |
218 | */ | |
219 | if (count++ >= PRD_ENTRIES) { | |
220 | printk(KERN_ERR "%s: DMA table too small\n", drive->name); | |
221 | goto use_pio_instead; | |
222 | } | |
223 | *table++ = cpu_to_le32(0x8000); | |
224 | *table++ = cpu_to_le32(cur_addr + 0x8000); | |
225 | xcount = 0x8000; | |
226 | } | |
227 | *table++ = cpu_to_le32(xcount); | |
228 | cur_addr += bcount; | |
229 | cur_len -= bcount; | |
230 | } | |
231 | } | |
232 | ||
55c16a70 | 233 | sg = sg_next(sg); |
1da177e4 LT |
234 | i--; |
235 | } | |
236 | ||
237 | if (count) { | |
238 | if (!is_trm290) | |
239 | *--table |= cpu_to_le32(0x80000000); | |
240 | return count; | |
241 | } | |
f6fb786d | 242 | |
1da177e4 | 243 | printk(KERN_ERR "%s: empty DMA table?\n", drive->name); |
f6fb786d | 244 | |
1da177e4 | 245 | use_pio_instead: |
f6fb786d BZ |
246 | ide_destroy_dmatable(drive); |
247 | ||
1da177e4 LT |
248 | return 0; /* revert to PIO for this request */ |
249 | } | |
250 | ||
251 | EXPORT_SYMBOL_GPL(ide_build_dmatable); | |
062f9f02 | 252 | #endif |
1da177e4 LT |
253 | |
254 | /** | |
255 | * ide_destroy_dmatable - clean up DMA mapping | |
256 | * @drive: The drive to unmap | |
257 | * | |
258 | * Teardown mappings after DMA has completed. This must be called | |
259 | * after the completion of each use of ide_build_dmatable and before | |
260 | * the next use of ide_build_dmatable. Failure to do so will cause | |
261 | * an oops as only one mapping can be live for each target at a given | |
262 | * time. | |
263 | */ | |
264 | ||
265 | void ide_destroy_dmatable (ide_drive_t *drive) | |
266 | { | |
36501650 | 267 | ide_hwif_t *hwif = drive->hwif; |
1da177e4 | 268 | |
5c05ff68 | 269 | dma_unmap_sg(hwif->dev, hwif->sg_table, hwif->sg_nents, |
36501650 | 270 | hwif->sg_dma_direction); |
1da177e4 LT |
271 | } |
272 | ||
273 | EXPORT_SYMBOL_GPL(ide_destroy_dmatable); | |
274 | ||
8e882ba1 | 275 | #ifdef CONFIG_BLK_DEV_IDEDMA_SFF |
1da177e4 LT |
276 | /** |
277 | * config_drive_for_dma - attempt to activate IDE DMA | |
278 | * @drive: the drive to place in DMA mode | |
279 | * | |
280 | * If the drive supports at least mode 2 DMA or UDMA of any kind | |
281 | * then attempt to place it into DMA mode. Drives that are known to | |
282 | * support DMA but predate the DMA properties or that are known | |
283 | * to have DMA handling bugs are also set up appropriately based | |
284 | * on the good/bad drive lists. | |
285 | */ | |
286 | ||
287 | static int config_drive_for_dma (ide_drive_t *drive) | |
288 | { | |
1116fae5 | 289 | ide_hwif_t *hwif = drive->hwif; |
1da177e4 | 290 | struct hd_driveid *id = drive->id; |
1da177e4 | 291 | |
33c1002e BZ |
292 | if (drive->media != ide_disk) { |
293 | if (hwif->host_flags & IDE_HFLAG_NO_ATAPI_DMA) | |
bcbf6ee3 | 294 | return 0; |
33c1002e | 295 | } |
1116fae5 | 296 | |
0ae2e178 BZ |
297 | /* |
298 | * Enable DMA on any drive that has | |
299 | * UltraDMA (mode 0/1/2/3/4/5/6) enabled | |
300 | */ | |
301 | if ((id->field_valid & 4) && ((id->dma_ultra >> 8) & 0x7f)) | |
302 | return 1; | |
303 | ||
304 | /* | |
305 | * Enable DMA on any drive that has mode2 DMA | |
306 | * (multi or single) enabled | |
307 | */ | |
308 | if (id->field_valid & 2) /* regular DMA */ | |
309 | if ((id->dma_mword & 0x404) == 0x404 || | |
310 | (id->dma_1word & 0x404) == 0x404) | |
311 | return 1; | |
3608b5d7 | 312 | |
0ae2e178 BZ |
313 | /* Consult the list of known "good" drives */ |
314 | if (ide_dma_good_drive(drive)) | |
315 | return 1; | |
316 | ||
317 | return 0; | |
1da177e4 LT |
318 | } |
319 | ||
320 | /** | |
321 | * dma_timer_expiry - handle a DMA timeout | |
322 | * @drive: Drive that timed out | |
323 | * | |
324 | * An IDE DMA transfer timed out. In the event of an error we ask | |
325 | * the driver to resolve the problem, if a DMA transfer is still | |
326 | * in progress we continue to wait (arguably we need to add a | |
327 | * secondary 'I don't care what the drive thinks' timeout here) | |
328 | * Finally if we have an interrupt we let it complete the I/O. | |
329 | * But only one time - we clear expiry and if it's still not | |
330 | * completed after WAIT_CMD, we error and retry in PIO. | |
331 | * This can occur if an interrupt is lost or due to hang or bugs. | |
332 | */ | |
333 | ||
334 | static int dma_timer_expiry (ide_drive_t *drive) | |
335 | { | |
336 | ide_hwif_t *hwif = HWIF(drive); | |
337 | u8 dma_stat = hwif->INB(hwif->dma_status); | |
338 | ||
339 | printk(KERN_WARNING "%s: dma_timer_expiry: dma status == 0x%02x\n", | |
340 | drive->name, dma_stat); | |
341 | ||
342 | if ((dma_stat & 0x18) == 0x18) /* BUSY Stupid Early Timer !! */ | |
343 | return WAIT_CMD; | |
344 | ||
345 | HWGROUP(drive)->expiry = NULL; /* one free ride for now */ | |
346 | ||
347 | /* 1 dmaing, 2 error, 4 intr */ | |
348 | if (dma_stat & 2) /* ERROR */ | |
349 | return -1; | |
350 | ||
351 | if (dma_stat & 1) /* DMAing */ | |
352 | return WAIT_CMD; | |
353 | ||
354 | if (dma_stat & 4) /* Got an Interrupt */ | |
355 | return WAIT_CMD; | |
356 | ||
357 | return 0; /* Status is unknown -- reset the bus */ | |
358 | } | |
359 | ||
360 | /** | |
15ce926a | 361 | * ide_dma_host_set - Enable/disable DMA on a host |
1da177e4 LT |
362 | * @drive: drive to control |
363 | * | |
15ce926a BZ |
364 | * Enable/disable DMA on an IDE controller following generic |
365 | * bus-mastering IDE controller behaviour. | |
1da177e4 LT |
366 | */ |
367 | ||
15ce926a | 368 | void ide_dma_host_set(ide_drive_t *drive, int on) |
1da177e4 LT |
369 | { |
370 | ide_hwif_t *hwif = HWIF(drive); | |
371 | u8 unit = (drive->select.b.unit & 0x01); | |
372 | u8 dma_stat = hwif->INB(hwif->dma_status); | |
373 | ||
15ce926a BZ |
374 | if (on) |
375 | dma_stat |= (1 << (5 + unit)); | |
376 | else | |
377 | dma_stat &= ~(1 << (5 + unit)); | |
378 | ||
379 | hwif->OUTB(dma_stat, hwif->dma_status); | |
1da177e4 LT |
380 | } |
381 | ||
15ce926a | 382 | EXPORT_SYMBOL_GPL(ide_dma_host_set); |
8e882ba1 | 383 | #endif /* CONFIG_BLK_DEV_IDEDMA_SFF */ |
1da177e4 LT |
384 | |
385 | /** | |
7469aaf6 | 386 | * ide_dma_off_quietly - Generic DMA kill |
1da177e4 LT |
387 | * @drive: drive to control |
388 | * | |
389 | * Turn off the current DMA on this IDE controller. | |
390 | */ | |
391 | ||
7469aaf6 | 392 | void ide_dma_off_quietly(ide_drive_t *drive) |
1da177e4 LT |
393 | { |
394 | drive->using_dma = 0; | |
395 | ide_toggle_bounce(drive, 0); | |
396 | ||
15ce926a | 397 | drive->hwif->dma_host_set(drive, 0); |
1da177e4 LT |
398 | } |
399 | ||
7469aaf6 | 400 | EXPORT_SYMBOL(ide_dma_off_quietly); |
1da177e4 LT |
401 | |
402 | /** | |
7469aaf6 | 403 | * ide_dma_off - disable DMA on a device |
1da177e4 LT |
404 | * @drive: drive to disable DMA on |
405 | * | |
406 | * Disable IDE DMA for a device on this IDE controller. | |
407 | * Inform the user that DMA has been disabled. | |
408 | */ | |
409 | ||
7469aaf6 | 410 | void ide_dma_off(ide_drive_t *drive) |
1da177e4 LT |
411 | { |
412 | printk(KERN_INFO "%s: DMA disabled\n", drive->name); | |
4a546e04 | 413 | ide_dma_off_quietly(drive); |
1da177e4 LT |
414 | } |
415 | ||
7469aaf6 | 416 | EXPORT_SYMBOL(ide_dma_off); |
1da177e4 | 417 | |
1da177e4 | 418 | /** |
4a546e04 | 419 | * ide_dma_on - Enable DMA on a device |
1da177e4 LT |
420 | * @drive: drive to enable DMA on |
421 | * | |
422 | * Enable IDE DMA for a device on this IDE controller. | |
423 | */ | |
4a546e04 BZ |
424 | |
425 | void ide_dma_on(ide_drive_t *drive) | |
1da177e4 | 426 | { |
1da177e4 LT |
427 | drive->using_dma = 1; |
428 | ide_toggle_bounce(drive, 1); | |
429 | ||
15ce926a | 430 | drive->hwif->dma_host_set(drive, 1); |
1da177e4 LT |
431 | } |
432 | ||
8e882ba1 | 433 | #ifdef CONFIG_BLK_DEV_IDEDMA_SFF |
1da177e4 LT |
434 | /** |
435 | * ide_dma_setup - begin a DMA phase | |
436 | * @drive: target device | |
437 | * | |
438 | * Build an IDE DMA PRD (IDE speak for scatter gather table) | |
439 | * and then set up the DMA transfer registers for a device | |
440 | * that follows generic IDE PCI DMA behaviour. Controllers can | |
441 | * override this function if they need to | |
442 | * | |
443 | * Returns 0 on success. If a PIO fallback is required then 1 | |
444 | * is returned. | |
445 | */ | |
446 | ||
447 | int ide_dma_setup(ide_drive_t *drive) | |
448 | { | |
449 | ide_hwif_t *hwif = drive->hwif; | |
450 | struct request *rq = HWGROUP(drive)->rq; | |
451 | unsigned int reading; | |
452 | u8 dma_stat; | |
453 | ||
454 | if (rq_data_dir(rq)) | |
455 | reading = 0; | |
456 | else | |
457 | reading = 1 << 3; | |
458 | ||
459 | /* fall back to pio! */ | |
460 | if (!ide_build_dmatable(drive, rq)) { | |
461 | ide_map_sg(drive, rq); | |
462 | return 1; | |
463 | } | |
464 | ||
465 | /* PRD table */ | |
2ad1e558 | 466 | if (hwif->mmio) |
0ecdca26 BZ |
467 | writel(hwif->dmatable_dma, (void __iomem *)hwif->dma_prdtable); |
468 | else | |
469 | outl(hwif->dmatable_dma, hwif->dma_prdtable); | |
1da177e4 LT |
470 | |
471 | /* specify r/w */ | |
472 | hwif->OUTB(reading, hwif->dma_command); | |
473 | ||
474 | /* read dma_status for INTR & ERROR flags */ | |
475 | dma_stat = hwif->INB(hwif->dma_status); | |
476 | ||
477 | /* clear INTR & ERROR flags */ | |
478 | hwif->OUTB(dma_stat|6, hwif->dma_status); | |
479 | drive->waiting_for_dma = 1; | |
480 | return 0; | |
481 | } | |
482 | ||
483 | EXPORT_SYMBOL_GPL(ide_dma_setup); | |
484 | ||
485 | static void ide_dma_exec_cmd(ide_drive_t *drive, u8 command) | |
486 | { | |
487 | /* issue cmd to drive */ | |
488 | ide_execute_command(drive, command, &ide_dma_intr, 2*WAIT_CMD, dma_timer_expiry); | |
489 | } | |
490 | ||
491 | void ide_dma_start(ide_drive_t *drive) | |
492 | { | |
493 | ide_hwif_t *hwif = HWIF(drive); | |
494 | u8 dma_cmd = hwif->INB(hwif->dma_command); | |
495 | ||
496 | /* Note that this is done *after* the cmd has | |
497 | * been issued to the drive, as per the BM-IDE spec. | |
498 | * The Promise Ultra33 doesn't work correctly when | |
499 | * we do this part before issuing the drive cmd. | |
500 | */ | |
501 | /* start DMA */ | |
502 | hwif->OUTB(dma_cmd|1, hwif->dma_command); | |
503 | hwif->dma = 1; | |
504 | wmb(); | |
505 | } | |
506 | ||
507 | EXPORT_SYMBOL_GPL(ide_dma_start); | |
508 | ||
509 | /* returns 1 on error, 0 otherwise */ | |
510 | int __ide_dma_end (ide_drive_t *drive) | |
511 | { | |
512 | ide_hwif_t *hwif = HWIF(drive); | |
513 | u8 dma_stat = 0, dma_cmd = 0; | |
514 | ||
515 | drive->waiting_for_dma = 0; | |
516 | /* get dma_command mode */ | |
517 | dma_cmd = hwif->INB(hwif->dma_command); | |
518 | /* stop DMA */ | |
519 | hwif->OUTB(dma_cmd&~1, hwif->dma_command); | |
520 | /* get DMA status */ | |
521 | dma_stat = hwif->INB(hwif->dma_status); | |
522 | /* clear the INTR & ERROR bits */ | |
523 | hwif->OUTB(dma_stat|6, hwif->dma_status); | |
524 | /* purge DMA mappings */ | |
525 | ide_destroy_dmatable(drive); | |
526 | /* verify good DMA status */ | |
527 | hwif->dma = 0; | |
528 | wmb(); | |
529 | return (dma_stat & 7) != 4 ? (0x10 | dma_stat) : 0; | |
530 | } | |
531 | ||
532 | EXPORT_SYMBOL(__ide_dma_end); | |
533 | ||
534 | /* returns 1 if dma irq issued, 0 otherwise */ | |
535 | static int __ide_dma_test_irq(ide_drive_t *drive) | |
536 | { | |
537 | ide_hwif_t *hwif = HWIF(drive); | |
538 | u8 dma_stat = hwif->INB(hwif->dma_status); | |
539 | ||
1da177e4 LT |
540 | /* return 1 if INTR asserted */ |
541 | if ((dma_stat & 4) == 4) | |
542 | return 1; | |
543 | if (!drive->waiting_for_dma) | |
544 | printk(KERN_WARNING "%s: (%s) called while not waiting\n", | |
545 | drive->name, __FUNCTION__); | |
546 | return 0; | |
547 | } | |
0ae2e178 BZ |
548 | #else |
549 | static inline int config_drive_for_dma(ide_drive_t *drive) { return 0; } | |
8e882ba1 | 550 | #endif /* CONFIG_BLK_DEV_IDEDMA_SFF */ |
1da177e4 LT |
551 | |
552 | int __ide_dma_bad_drive (ide_drive_t *drive) | |
553 | { | |
554 | struct hd_driveid *id = drive->id; | |
555 | ||
65e5f2e3 | 556 | int blacklist = ide_in_drive_list(id, drive_blacklist); |
1da177e4 LT |
557 | if (blacklist) { |
558 | printk(KERN_WARNING "%s: Disabling (U)DMA for %s (blacklisted)\n", | |
559 | drive->name, id->model); | |
560 | return blacklist; | |
561 | } | |
562 | return 0; | |
563 | } | |
564 | ||
565 | EXPORT_SYMBOL(__ide_dma_bad_drive); | |
566 | ||
2d5eaa6d BZ |
567 | static const u8 xfer_mode_bases[] = { |
568 | XFER_UDMA_0, | |
569 | XFER_MW_DMA_0, | |
570 | XFER_SW_DMA_0, | |
571 | }; | |
572 | ||
7670df73 | 573 | static unsigned int ide_get_mode_mask(ide_drive_t *drive, u8 base, u8 req_mode) |
2d5eaa6d BZ |
574 | { |
575 | struct hd_driveid *id = drive->id; | |
576 | ide_hwif_t *hwif = drive->hwif; | |
ac95beed | 577 | const struct ide_port_ops *port_ops = hwif->port_ops; |
2d5eaa6d BZ |
578 | unsigned int mask = 0; |
579 | ||
580 | switch(base) { | |
581 | case XFER_UDMA_0: | |
582 | if ((id->field_valid & 4) == 0) | |
583 | break; | |
584 | ||
ac95beed BZ |
585 | if (port_ops && port_ops->udma_filter) |
586 | mask = port_ops->udma_filter(drive); | |
851dd33b SS |
587 | else |
588 | mask = hwif->ultra_mask; | |
589 | mask &= id->dma_ultra; | |
2d5eaa6d | 590 | |
7670df73 BZ |
591 | /* |
592 | * avoid false cable warning from eighty_ninty_three() | |
593 | */ | |
594 | if (req_mode > XFER_UDMA_2) { | |
595 | if ((mask & 0x78) && (eighty_ninty_three(drive) == 0)) | |
596 | mask &= 0x07; | |
597 | } | |
2d5eaa6d BZ |
598 | break; |
599 | case XFER_MW_DMA_0: | |
b4e44369 SS |
600 | if ((id->field_valid & 2) == 0) |
601 | break; | |
ac95beed BZ |
602 | if (port_ops && port_ops->mdma_filter) |
603 | mask = port_ops->mdma_filter(drive); | |
b4e44369 SS |
604 | else |
605 | mask = hwif->mwdma_mask; | |
606 | mask &= id->dma_mword; | |
2d5eaa6d BZ |
607 | break; |
608 | case XFER_SW_DMA_0: | |
15a4f943 | 609 | if (id->field_valid & 2) { |
3649c06e | 610 | mask = id->dma_1word & hwif->swdma_mask; |
15a4f943 BZ |
611 | } else if (id->tDMA) { |
612 | /* | |
613 | * ide_fix_driveid() doesn't convert ->tDMA to the | |
614 | * CPU endianness so we need to do it here | |
615 | */ | |
616 | u8 mode = le16_to_cpu(id->tDMA); | |
617 | ||
618 | /* | |
619 | * if the mode is valid convert it to the mask | |
620 | * (the maximum allowed mode is XFER_SW_DMA_2) | |
621 | */ | |
622 | if (mode <= 2) | |
623 | mask = ((2 << mode) - 1) & hwif->swdma_mask; | |
624 | } | |
2d5eaa6d BZ |
625 | break; |
626 | default: | |
627 | BUG(); | |
628 | break; | |
629 | } | |
630 | ||
631 | return mask; | |
632 | } | |
633 | ||
634 | /** | |
7670df73 | 635 | * ide_find_dma_mode - compute DMA speed |
2d5eaa6d | 636 | * @drive: IDE device |
7670df73 BZ |
637 | * @req_mode: requested mode |
638 | * | |
639 | * Checks the drive/host capabilities and finds the speed to use for | |
640 | * the DMA transfer. The speed is then limited by the requested mode. | |
2d5eaa6d | 641 | * |
7670df73 BZ |
642 | * Returns 0 if the drive/host combination is incapable of DMA transfers |
643 | * or if the requested mode is not a DMA mode. | |
2d5eaa6d BZ |
644 | */ |
645 | ||
7670df73 | 646 | u8 ide_find_dma_mode(ide_drive_t *drive, u8 req_mode) |
2d5eaa6d BZ |
647 | { |
648 | ide_hwif_t *hwif = drive->hwif; | |
649 | unsigned int mask; | |
650 | int x, i; | |
651 | u8 mode = 0; | |
652 | ||
33c1002e BZ |
653 | if (drive->media != ide_disk) { |
654 | if (hwif->host_flags & IDE_HFLAG_NO_ATAPI_DMA) | |
655 | return 0; | |
656 | } | |
2d5eaa6d BZ |
657 | |
658 | for (i = 0; i < ARRAY_SIZE(xfer_mode_bases); i++) { | |
7670df73 BZ |
659 | if (req_mode < xfer_mode_bases[i]) |
660 | continue; | |
661 | mask = ide_get_mode_mask(drive, xfer_mode_bases[i], req_mode); | |
2d5eaa6d BZ |
662 | x = fls(mask) - 1; |
663 | if (x >= 0) { | |
664 | mode = xfer_mode_bases[i] + x; | |
665 | break; | |
666 | } | |
667 | } | |
668 | ||
75d7d963 BZ |
669 | if (hwif->chipset == ide_acorn && mode == 0) { |
670 | /* | |
671 | * is this correct? | |
672 | */ | |
673 | if (ide_dma_good_drive(drive) && drive->id->eide_dma_time < 150) | |
674 | mode = XFER_MW_DMA_1; | |
675 | } | |
676 | ||
3ab7efe8 BZ |
677 | mode = min(mode, req_mode); |
678 | ||
679 | printk(KERN_INFO "%s: %s mode selected\n", drive->name, | |
d34887da | 680 | mode ? ide_xfer_verbose(mode) : "no DMA"); |
2d5eaa6d | 681 | |
3ab7efe8 | 682 | return mode; |
2d5eaa6d BZ |
683 | } |
684 | ||
7670df73 | 685 | EXPORT_SYMBOL_GPL(ide_find_dma_mode); |
2d5eaa6d | 686 | |
0ae2e178 | 687 | static int ide_tune_dma(ide_drive_t *drive) |
29e744d0 | 688 | { |
8704de8f | 689 | ide_hwif_t *hwif = drive->hwif; |
29e744d0 BZ |
690 | u8 speed; |
691 | ||
c223701c | 692 | if (noautodma || drive->nodma || (drive->id->capability & 1) == 0) |
122ab088 BZ |
693 | return 0; |
694 | ||
695 | /* consult the list of known "bad" drives */ | |
696 | if (__ide_dma_bad_drive(drive)) | |
29e744d0 BZ |
697 | return 0; |
698 | ||
3ab7efe8 BZ |
699 | if (ide_id_dma_bug(drive)) |
700 | return 0; | |
701 | ||
8704de8f | 702 | if (hwif->host_flags & IDE_HFLAG_TRUST_BIOS_FOR_DMA) |
0ae2e178 BZ |
703 | return config_drive_for_dma(drive); |
704 | ||
29e744d0 BZ |
705 | speed = ide_max_dma_mode(drive); |
706 | ||
951784b6 BZ |
707 | if (!speed) |
708 | return 0; | |
29e744d0 | 709 | |
88b2b32b | 710 | if (ide_set_dma_mode(drive, speed)) |
4728d546 | 711 | return 0; |
29e744d0 | 712 | |
4728d546 | 713 | return 1; |
29e744d0 BZ |
714 | } |
715 | ||
0ae2e178 BZ |
716 | static int ide_dma_check(ide_drive_t *drive) |
717 | { | |
718 | ide_hwif_t *hwif = drive->hwif; | |
719 | int vdma = (hwif->host_flags & IDE_HFLAG_VDMA)? 1 : 0; | |
720 | ||
721 | if (!vdma && ide_tune_dma(drive)) | |
722 | return 0; | |
723 | ||
724 | /* TODO: always do PIO fallback */ | |
725 | if (hwif->host_flags & IDE_HFLAG_TRUST_BIOS_FOR_DMA) | |
726 | return -1; | |
727 | ||
728 | ide_set_max_pio(drive); | |
729 | ||
730 | return vdma ? 0 : -1; | |
731 | } | |
732 | ||
3ab7efe8 | 733 | int ide_id_dma_bug(ide_drive_t *drive) |
1da177e4 | 734 | { |
3ab7efe8 | 735 | struct hd_driveid *id = drive->id; |
1da177e4 LT |
736 | |
737 | if (id->field_valid & 4) { | |
738 | if ((id->dma_ultra >> 8) && (id->dma_mword >> 8)) | |
3ab7efe8 | 739 | goto err_out; |
1da177e4 LT |
740 | } else if (id->field_valid & 2) { |
741 | if ((id->dma_mword >> 8) && (id->dma_1word >> 8)) | |
3ab7efe8 | 742 | goto err_out; |
1da177e4 | 743 | } |
3ab7efe8 BZ |
744 | return 0; |
745 | err_out: | |
746 | printk(KERN_ERR "%s: bad DMA info in identify block\n", drive->name); | |
747 | return 1; | |
1da177e4 LT |
748 | } |
749 | ||
3608b5d7 BZ |
750 | int ide_set_dma(ide_drive_t *drive) |
751 | { | |
3608b5d7 BZ |
752 | int rc; |
753 | ||
7b905994 BZ |
754 | /* |
755 | * Force DMAing for the beginning of the check. | |
756 | * Some chipsets appear to do interesting | |
757 | * things, if not checked and cleared. | |
758 | * PARANOIA!!! | |
759 | */ | |
4a546e04 | 760 | ide_dma_off_quietly(drive); |
3608b5d7 | 761 | |
7b905994 BZ |
762 | rc = ide_dma_check(drive); |
763 | if (rc) | |
764 | return rc; | |
3608b5d7 | 765 | |
4a546e04 BZ |
766 | ide_dma_on(drive); |
767 | ||
768 | return 0; | |
3608b5d7 BZ |
769 | } |
770 | ||
578cfa0d BZ |
771 | void ide_check_dma_crc(ide_drive_t *drive) |
772 | { | |
773 | u8 mode; | |
774 | ||
775 | ide_dma_off_quietly(drive); | |
776 | drive->crc_count = 0; | |
777 | mode = drive->current_speed; | |
778 | /* | |
779 | * Don't try non Ultra-DMA modes without iCRC's. Force the | |
780 | * device to PIO and make the user enable SWDMA/MWDMA modes. | |
781 | */ | |
782 | if (mode > XFER_UDMA_0 && mode <= XFER_UDMA_7) | |
783 | mode--; | |
784 | else | |
785 | mode = XFER_PIO_4; | |
786 | ide_set_xfer_rate(drive, mode); | |
787 | if (drive->current_speed >= XFER_SW_DMA_0) | |
788 | ide_dma_on(drive); | |
789 | } | |
790 | ||
8e882ba1 | 791 | #ifdef CONFIG_BLK_DEV_IDEDMA_SFF |
841d2a9b | 792 | void ide_dma_lost_irq (ide_drive_t *drive) |
1da177e4 LT |
793 | { |
794 | printk("%s: DMA interrupt recovery\n", drive->name); | |
1da177e4 LT |
795 | } |
796 | ||
841d2a9b | 797 | EXPORT_SYMBOL(ide_dma_lost_irq); |
1da177e4 | 798 | |
c283f5db | 799 | void ide_dma_timeout (ide_drive_t *drive) |
1da177e4 | 800 | { |
c283f5db SS |
801 | ide_hwif_t *hwif = HWIF(drive); |
802 | ||
1da177e4 | 803 | printk(KERN_ERR "%s: timeout waiting for DMA\n", drive->name); |
1da177e4 | 804 | |
c283f5db SS |
805 | if (hwif->ide_dma_test_irq(drive)) |
806 | return; | |
807 | ||
808 | hwif->ide_dma_end(drive); | |
1da177e4 LT |
809 | } |
810 | ||
c283f5db | 811 | EXPORT_SYMBOL(ide_dma_timeout); |
1da177e4 | 812 | |
0d1bad21 | 813 | void ide_release_dma_engine(ide_hwif_t *hwif) |
1da177e4 LT |
814 | { |
815 | if (hwif->dmatable_cpu) { | |
36501650 BZ |
816 | struct pci_dev *pdev = to_pci_dev(hwif->dev); |
817 | ||
818 | pci_free_consistent(pdev, PRD_ENTRIES * PRD_BYTES, | |
819 | hwif->dmatable_cpu, hwif->dmatable_dma); | |
1da177e4 LT |
820 | hwif->dmatable_cpu = NULL; |
821 | } | |
1da177e4 LT |
822 | } |
823 | ||
1da177e4 LT |
824 | static int ide_allocate_dma_engine(ide_hwif_t *hwif) |
825 | { | |
36501650 BZ |
826 | struct pci_dev *pdev = to_pci_dev(hwif->dev); |
827 | ||
828 | hwif->dmatable_cpu = pci_alloc_consistent(pdev, | |
1da177e4 LT |
829 | PRD_ENTRIES * PRD_BYTES, |
830 | &hwif->dmatable_dma); | |
831 | ||
832 | if (hwif->dmatable_cpu) | |
833 | return 0; | |
834 | ||
dc844e05 SS |
835 | printk(KERN_ERR "%s: -- Error, unable to allocate DMA table.\n", |
836 | hwif->cds->name); | |
1da177e4 | 837 | |
1da177e4 LT |
838 | return 1; |
839 | } | |
840 | ||
ecf32796 | 841 | static int ide_mapped_mmio_dma(ide_hwif_t *hwif, unsigned long base) |
1da177e4 LT |
842 | { |
843 | printk(KERN_INFO " %s: MMIO-DMA ", hwif->name); | |
844 | ||
1da177e4 LT |
845 | return 0; |
846 | } | |
847 | ||
ecf32796 | 848 | static int ide_iomio_dma(ide_hwif_t *hwif, unsigned long base) |
1da177e4 LT |
849 | { |
850 | printk(KERN_INFO " %s: BM-DMA at 0x%04lx-0x%04lx", | |
ecf32796 | 851 | hwif->name, base, base + 7); |
020e322d | 852 | |
0d1bad21 | 853 | if (hwif->cds->extra) |
020e322d SS |
854 | hwif->extra_base = base + (hwif->channel ? 8 : 16); |
855 | ||
1da177e4 LT |
856 | return 0; |
857 | } | |
858 | ||
ecf32796 | 859 | static int ide_dma_iobase(ide_hwif_t *hwif, unsigned long base) |
1da177e4 | 860 | { |
2ad1e558 | 861 | if (hwif->mmio) |
ecf32796 | 862 | return ide_mapped_mmio_dma(hwif, base); |
2ad1e558 | 863 | |
ecf32796 | 864 | return ide_iomio_dma(hwif, base); |
1da177e4 LT |
865 | } |
866 | ||
ecf32796 | 867 | void ide_setup_dma(ide_hwif_t *hwif, unsigned long base) |
1da177e4 | 868 | { |
4e5a68ae SS |
869 | u8 dma_stat; |
870 | ||
ecf32796 | 871 | if (ide_dma_iobase(hwif, base)) |
1da177e4 LT |
872 | return; |
873 | ||
874 | if (ide_allocate_dma_engine(hwif)) { | |
0d1bad21 | 875 | ide_release_dma_engine(hwif); |
1da177e4 LT |
876 | return; |
877 | } | |
878 | ||
a02bfd3c BZ |
879 | hwif->dma_base = base; |
880 | ||
ecf32796 SS |
881 | if (!hwif->dma_command) |
882 | hwif->dma_command = hwif->dma_base + 0; | |
883 | if (!hwif->dma_vendor1) | |
884 | hwif->dma_vendor1 = hwif->dma_base + 1; | |
885 | if (!hwif->dma_status) | |
886 | hwif->dma_status = hwif->dma_base + 2; | |
887 | if (!hwif->dma_vendor3) | |
888 | hwif->dma_vendor3 = hwif->dma_base + 3; | |
889 | if (!hwif->dma_prdtable) | |
890 | hwif->dma_prdtable = hwif->dma_base + 4; | |
1da177e4 | 891 | |
15ce926a BZ |
892 | if (!hwif->dma_host_set) |
893 | hwif->dma_host_set = &ide_dma_host_set; | |
1da177e4 LT |
894 | if (!hwif->dma_setup) |
895 | hwif->dma_setup = &ide_dma_setup; | |
896 | if (!hwif->dma_exec_cmd) | |
897 | hwif->dma_exec_cmd = &ide_dma_exec_cmd; | |
898 | if (!hwif->dma_start) | |
899 | hwif->dma_start = &ide_dma_start; | |
900 | if (!hwif->ide_dma_end) | |
901 | hwif->ide_dma_end = &__ide_dma_end; | |
902 | if (!hwif->ide_dma_test_irq) | |
903 | hwif->ide_dma_test_irq = &__ide_dma_test_irq; | |
c283f5db SS |
904 | if (!hwif->dma_timeout) |
905 | hwif->dma_timeout = &ide_dma_timeout; | |
841d2a9b SS |
906 | if (!hwif->dma_lost_irq) |
907 | hwif->dma_lost_irq = &ide_dma_lost_irq; | |
1da177e4 | 908 | |
4e5a68ae SS |
909 | dma_stat = hwif->INB(hwif->dma_status); |
910 | printk(KERN_CONT ", BIOS settings: %s:%s, %s:%s\n", | |
911 | hwif->drives[0].name, (dma_stat & 0x20) ? "DMA" : "PIO", | |
912 | hwif->drives[1].name, (dma_stat & 0x40) ? "DMA" : "PIO"); | |
1da177e4 LT |
913 | } |
914 | ||
915 | EXPORT_SYMBOL_GPL(ide_setup_dma); | |
8e882ba1 | 916 | #endif /* CONFIG_BLK_DEV_IDEDMA_SFF */ |