[deliverable/linux.git] / drivers / ide / mips / au1xxx-ide.c

/*
 * BRIEF MODULE DESCRIPTION
 * AMD Alchemy Au1xxx IDE interface routines over the Static Bus
 *
 * Copyright (c) 2003-2005 AMD, Personal Connectivity Solutions
 *
 * This program is free software; you can redistribute it and/or modify it under
 * the terms of the GNU General Public License as published by the Free Software
 * Foundation; either version 2 of the License, or (at your option) any later
 * version.
 *
 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
 * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR
 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc.,
 * 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 * Note: for more information, please refer "AMD Alchemy Au1200/Au1550 IDE
 *       Interface and Linux Device Driver" Application Note.
 */
#include <linux/types.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/init.h>
#include <linux/ide.h>
#include <linux/scatterlist.h>

#include <asm/mach-au1x00/au1xxx.h>
#include <asm/mach-au1x00/au1xxx_dbdma.h>
#include <asm/mach-au1x00/au1xxx_ide.h>

#define DRV_NAME	"au1200-ide"
#define DRV_AUTHOR	"Enrico Walther <enrico.walther@amd.com> / Pete Popov <ppopov@embeddedalley.com>"

/* enable the burstmode in the dbdma */
#define IDE_AU1XXX_BURSTMODE	1

static _auide_hwif auide_hwif;

#if defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA)

void auide_insw(unsigned long port, void *addr, u32 count)
{
	_auide_hwif *ahwif = &auide_hwif;
	chan_tab_t *ctp;
	au1x_ddma_desc_t *dp;

	if(!put_dest_flags(ahwif->rx_chan, (void*)addr, count << 1, 
			   DDMA_FLAGS_NOIE)) {
		printk(KERN_ERR "%s failed %d\n", __func__, __LINE__);
		return;
	}
	ctp = *((chan_tab_t **)ahwif->rx_chan);
	dp = ctp->cur_ptr;
	while (dp->dscr_cmd0 & DSCR_CMD0_V)
		;
	ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp);
}

void auide_outsw(unsigned long port, void *addr, u32 count)
{
	_auide_hwif *ahwif = &auide_hwif;
	chan_tab_t *ctp;
	au1x_ddma_desc_t *dp;

	if(!put_source_flags(ahwif->tx_chan, (void*)addr,
			     count << 1, DDMA_FLAGS_NOIE)) {
		printk(KERN_ERR "%s failed %d\n", __func__, __LINE__);
		return;
	}
	ctp = *((chan_tab_t **)ahwif->tx_chan);
	dp = ctp->cur_ptr;
	while (dp->dscr_cmd0 & DSCR_CMD0_V)
		;
	ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp);
}

static void au1xxx_input_data(ide_drive_t *drive, struct request *rq,
			      void *buf, unsigned int len)
{
	auide_insw(drive->hwif->io_ports.data_addr, buf, (len + 1) / 2);
}

static void au1xxx_output_data(ide_drive_t *drive, struct request *rq,
			       void *buf, unsigned int len)
{
	auide_outsw(drive->hwif->io_ports.data_addr, buf, (len + 1) / 2);
}
#endif

static void au1xxx_set_pio_mode(ide_drive_t *drive, const u8 pio)
{
	int mem_sttime = 0, mem_stcfg = au_readl(MEM_STCFG2);

	/* set pio mode! */
	switch(pio) {
	case 0:
		mem_sttime = SBC_IDE_TIMING(PIO0);

		/* set configuration for RCS2# */
		mem_stcfg |= TS_MASK;
		mem_stcfg &= ~TCSOE_MASK;
		mem_stcfg &= ~TOECS_MASK;
		mem_stcfg |= SBC_IDE_PIO0_TCSOE | SBC_IDE_PIO0_TOECS;
		break;

	case 1:
		mem_sttime = SBC_IDE_TIMING(PIO1);

		/* set configuration for RCS2# */
		mem_stcfg |= TS_MASK;
		mem_stcfg &= ~TCSOE_MASK;
		mem_stcfg &= ~TOECS_MASK;
		mem_stcfg |= SBC_IDE_PIO1_TCSOE | SBC_IDE_PIO1_TOECS;
		break;

	case 2:
		mem_sttime = SBC_IDE_TIMING(PIO2);

		/* set configuration for RCS2# */
		mem_stcfg &= ~TS_MASK;
		mem_stcfg &= ~TCSOE_MASK;
		mem_stcfg &= ~TOECS_MASK;
		mem_stcfg |= SBC_IDE_PIO2_TCSOE | SBC_IDE_PIO2_TOECS;
		break;

	case 3:
		mem_sttime = SBC_IDE_TIMING(PIO3);

		/* set configuration for RCS2# */
		mem_stcfg &= ~TS_MASK;
		mem_stcfg &= ~TCSOE_MASK;
		mem_stcfg &= ~TOECS_MASK;
		mem_stcfg |= SBC_IDE_PIO3_TCSOE | SBC_IDE_PIO3_TOECS;

		break;

	case 4:
		mem_sttime = SBC_IDE_TIMING(PIO4);

		/* set configuration for RCS2# */
		mem_stcfg &= ~TS_MASK;
		mem_stcfg &= ~TCSOE_MASK;
		mem_stcfg &= ~TOECS_MASK;
		mem_stcfg |= SBC_IDE_PIO4_TCSOE | SBC_IDE_PIO4_TOECS;
		break;
	}

	au_writel(mem_sttime,MEM_STTIME2);
	au_writel(mem_stcfg,MEM_STCFG2);
}

static void auide_set_dma_mode(ide_drive_t *drive, const u8 speed)
{
	int mem_sttime = 0, mem_stcfg = au_readl(MEM_STCFG2);

	switch(speed) {
#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
	case XFER_MW_DMA_2:
		mem_sttime = SBC_IDE_TIMING(MDMA2);

		/* set configuration for RCS2# */
		mem_stcfg &= ~TS_MASK;
		mem_stcfg &= ~TCSOE_MASK;
		mem_stcfg &= ~TOECS_MASK;
		mem_stcfg |= SBC_IDE_MDMA2_TCSOE | SBC_IDE_MDMA2_TOECS;

		break;
	case XFER_MW_DMA_1:
		mem_sttime = SBC_IDE_TIMING(MDMA1);

		/* set configuration for RCS2# */
		mem_stcfg &= ~TS_MASK;
		mem_stcfg &= ~TCSOE_MASK;
		mem_stcfg &= ~TOECS_MASK;
		mem_stcfg |= SBC_IDE_MDMA1_TCSOE | SBC_IDE_MDMA1_TOECS;

		break;
	case XFER_MW_DMA_0:
		mem_sttime = SBC_IDE_TIMING(MDMA0);

		/* set configuration for RCS2# */
		mem_stcfg |= TS_MASK;
		mem_stcfg &= ~TCSOE_MASK;
		mem_stcfg &= ~TOECS_MASK;
		mem_stcfg |= SBC_IDE_MDMA0_TCSOE | SBC_IDE_MDMA0_TOECS;

		break;
#endif
	}

	au_writel(mem_sttime,MEM_STTIME2);
	au_writel(mem_stcfg,MEM_STCFG2);
}

/*
 * Multi-Word DMA + DbDMA functions
 */

#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
static int auide_build_dmatable(ide_drive_t *drive)
{
	int i, iswrite, count = 0;
	ide_hwif_t *hwif = HWIF(drive);
	struct request *rq = HWGROUP(drive)->rq;
	_auide_hwif *ahwif = &auide_hwif;
	struct scatterlist *sg;

	iswrite = (rq_data_dir(rq) == WRITE);
	/* Save for interrupt context */
	ahwif->drive = drive;

	hwif->sg_nents = i = ide_build_sglist(drive, rq);

	if (!i)
		return 0;

	/* fill the descriptors */
	sg = hwif->sg_table;
	while (i && sg_dma_len(sg)) {
		u32 cur_addr;
		u32 cur_len;

		cur_addr = sg_dma_address(sg);
		cur_len = sg_dma_len(sg);

		while (cur_len) {
			u32 flags = DDMA_FLAGS_NOIE;
			unsigned int tc = (cur_len < 0xfe00)? cur_len: 0xfe00;

			if (++count >= PRD_ENTRIES) {
				printk(KERN_WARNING "%s: DMA table too small\n",
				       drive->name);
				goto use_pio_instead;
			}

			/* Lets enable intr for the last descriptor only */
			if (1==i)
				flags = DDMA_FLAGS_IE;
			else
				flags = DDMA_FLAGS_NOIE;

			if (iswrite) {
				if(!put_source_flags(ahwif->tx_chan, 
						     (void*) sg_virt(sg),
						     tc, flags)) { 
					printk(KERN_ERR "%s failed %d\n", 
					       __func__, __LINE__);
				}
			} else 
			{
				if(!put_dest_flags(ahwif->rx_chan, 
						   (void*) sg_virt(sg),
						   tc, flags)) { 
					printk(KERN_ERR "%s failed %d\n", 
					       __func__, __LINE__);
				}
			}

			cur_addr += tc;
			cur_len -= tc;
		}
		sg = sg_next(sg);
		i--;
	}

	if (count)
		return 1;

 use_pio_instead:
	ide_destroy_dmatable(drive);

	return 0; /* revert to PIO for this request */
}

static int auide_dma_end(ide_drive_t *drive)
{
	ide_hwif_t *hwif = HWIF(drive);

	if (hwif->sg_nents) {
		ide_destroy_dmatable(drive);
		hwif->sg_nents = 0;
	}

	return 0;
}

static void auide_dma_start(ide_drive_t *drive )
{
}


static void auide_dma_exec_cmd(ide_drive_t *drive, u8 command)
{
	/* issue cmd to drive */
	ide_execute_command(drive, command, &ide_dma_intr,
			    (2*WAIT_CMD), NULL);
}

static int auide_dma_setup(ide_drive_t *drive)
{       	
	struct request *rq = HWGROUP(drive)->rq;

	if (!auide_build_dmatable(drive)) {
		ide_map_sg(drive, rq);
		return 1;
	}

	drive->waiting_for_dma = 1;
	return 0;
}

static int auide_dma_test_irq(ide_drive_t *drive)
{
	/* If dbdma didn't execute the STOP command yet, the
	 * active bit is still set
	 */
	drive->waiting_for_dma++;
	if (drive->waiting_for_dma >= DMA_WAIT_TIMEOUT) {
		printk(KERN_WARNING "%s: timeout waiting for ddma to \
                                     complete\n", drive->name);
		return 1;
	}
	udelay(10);
	return 0;
}

static void auide_dma_host_set(ide_drive_t *drive, int on)
{
}

static void auide_dma_lost_irq(ide_drive_t *drive)
{
	printk(KERN_ERR "%s: IRQ lost\n", drive->name);
}

static void auide_ddma_tx_callback(int irq, void *param)
{
	_auide_hwif *ahwif = (_auide_hwif*)param;
	ahwif->drive->waiting_for_dma = 0;
}

static void auide_ddma_rx_callback(int irq, void *param)
{
	_auide_hwif *ahwif = (_auide_hwif*)param;
	ahwif->drive->waiting_for_dma = 0;
}

#endif /* end CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA */

static void auide_init_dbdma_dev(dbdev_tab_t *dev, u32 dev_id, u32 tsize, u32 devwidth, u32 flags)
{
	dev->dev_id          = dev_id;
	dev->dev_physaddr    = (u32)IDE_PHYS_ADDR;
	dev->dev_intlevel    = 0;
	dev->dev_intpolarity = 0;
	dev->dev_tsize       = tsize;
	dev->dev_devwidth    = devwidth;
	dev->dev_flags       = flags;
}

#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
static void auide_dma_timeout(ide_drive_t *drive)
{
	ide_hwif_t *hwif = HWIF(drive);

	printk(KERN_ERR "%s: DMA timeout occurred: ", drive->name);

	if (auide_dma_test_irq(drive))
		return;

	auide_dma_end(drive);
}

static const struct ide_dma_ops au1xxx_dma_ops = {
	.dma_host_set		= auide_dma_host_set,
	.dma_setup		= auide_dma_setup,
	.dma_exec_cmd		= auide_dma_exec_cmd,
	.dma_start		= auide_dma_start,
	.dma_end		= auide_dma_end,
	.dma_test_irq		= auide_dma_test_irq,
	.dma_lost_irq		= auide_dma_lost_irq,
	.dma_timeout		= auide_dma_timeout,
};

static int auide_ddma_init(ide_hwif_t *hwif, const struct ide_port_info *d)
{
	_auide_hwif *auide = &auide_hwif;
	dbdev_tab_t source_dev_tab, target_dev_tab;
	u32 dev_id, tsize, devwidth, flags;

	dev_id	 = IDE_DDMA_REQ;

	tsize    =  8; /*  1 */
	devwidth = 32; /* 16 */

#ifdef IDE_AU1XXX_BURSTMODE 
	flags = DEV_FLAGS_SYNC | DEV_FLAGS_BURSTABLE;
#else
	flags = DEV_FLAGS_SYNC;
#endif

	/* setup dev_tab for tx channel */
	auide_init_dbdma_dev( &source_dev_tab,
			      dev_id,
			      tsize, devwidth, DEV_FLAGS_OUT | flags);
 	auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );

	auide_init_dbdma_dev( &source_dev_tab,
			      dev_id,
			      tsize, devwidth, DEV_FLAGS_IN | flags);
 	auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
	
	/* We also need to add a target device for the DMA */
	auide_init_dbdma_dev( &target_dev_tab,
			      (u32)DSCR_CMD0_ALWAYS,
			      tsize, devwidth, DEV_FLAGS_ANYUSE);
	auide->target_dev_id = au1xxx_ddma_add_device(&target_dev_tab);	
 
	/* Get a channel for TX */
	auide->tx_chan = au1xxx_dbdma_chan_alloc(auide->target_dev_id,
						 auide->tx_dev_id,
						 auide_ddma_tx_callback,
						 (void*)auide);
 
	/* Get a channel for RX */
	auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id,
						 auide->target_dev_id,
						 auide_ddma_rx_callback,
						 (void*)auide);

	auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan,
							     NUM_DESCRIPTORS);
	auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan,
							     NUM_DESCRIPTORS);
 
	hwif->dmatable_cpu = dma_alloc_coherent(hwif->dev,
						PRD_ENTRIES * PRD_BYTES,        /* 1 Page */
						&hwif->dmatable_dma, GFP_KERNEL);
	
	au1xxx_dbdma_start( auide->tx_chan );
	au1xxx_dbdma_start( auide->rx_chan );
 
	return 0;
} 
#else
static int auide_ddma_init(ide_hwif_t *hwif, const struct ide_port_info *d)
{
	_auide_hwif *auide = &auide_hwif;
	dbdev_tab_t source_dev_tab;
	int flags;

#ifdef IDE_AU1XXX_BURSTMODE 
	flags = DEV_FLAGS_SYNC | DEV_FLAGS_BURSTABLE;
#else
	flags = DEV_FLAGS_SYNC;
#endif

	/* setup dev_tab for tx channel */
	auide_init_dbdma_dev( &source_dev_tab,
			      (u32)DSCR_CMD0_ALWAYS,
			      8, 32, DEV_FLAGS_OUT | flags);
 	auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );

	auide_init_dbdma_dev( &source_dev_tab,
			      (u32)DSCR_CMD0_ALWAYS,
			      8, 32, DEV_FLAGS_IN | flags);
 	auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
	
	/* Get a channel for TX */
	auide->tx_chan = au1xxx_dbdma_chan_alloc(DSCR_CMD0_ALWAYS,
						 auide->tx_dev_id,
						 NULL,
						 (void*)auide);
 
	/* Get a channel for RX */
	auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id,
						 DSCR_CMD0_ALWAYS,
						 NULL,
						 (void*)auide);
 
	auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan,
							     NUM_DESCRIPTORS);
	auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan,
							     NUM_DESCRIPTORS);
 
	au1xxx_dbdma_start( auide->tx_chan );
	au1xxx_dbdma_start( auide->rx_chan );
 	
	return 0;
}
#endif

static void auide_setup_ports(hw_regs_t *hw, _auide_hwif *ahwif)
{
	int i;
	unsigned long *ata_regs = hw->io_ports_array;

	/* FIXME? */
	for (i = 0; i < 8; i++)
		*ata_regs++ = ahwif->regbase + (i << IDE_REG_SHIFT);

	/* set the Alternative Status register */
	*ata_regs = ahwif->regbase + (14 << IDE_REG_SHIFT);
}

#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA
static const struct ide_tp_ops au1xxx_tp_ops = {
	.exec_command		= ide_exec_command,
	.read_status		= ide_read_status,
	.read_altstatus		= ide_read_altstatus,
	.read_sff_dma_status	= ide_read_sff_dma_status,

	.set_irq		= ide_set_irq,

	.tf_load		= ide_tf_load,
	.tf_read		= ide_tf_read,

	.input_data		= au1xxx_input_data,
	.output_data		= au1xxx_output_data,
};
#endif

static const struct ide_port_ops au1xxx_port_ops = {
	.set_pio_mode		= au1xxx_set_pio_mode,
	.set_dma_mode		= auide_set_dma_mode,
};

static const struct ide_port_info au1xxx_port_info = {
	.init_dma		= auide_ddma_init,
#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA
	.tp_ops			= &au1xxx_tp_ops,
#endif
	.port_ops		= &au1xxx_port_ops,
#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
	.dma_ops		= &au1xxx_dma_ops,
#endif
	.host_flags		= IDE_HFLAG_POST_SET_MODE |
				  IDE_HFLAG_NO_IO_32BIT |
				  IDE_HFLAG_UNMASK_IRQS,
	.pio_mask		= ATA_PIO4,
#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
	.mwdma_mask		= ATA_MWDMA2,
#endif
};

static int au_ide_probe(struct device *dev)
{
	struct platform_device *pdev = to_platform_device(dev);
	_auide_hwif *ahwif = &auide_hwif;
	struct resource *res;
	struct ide_host *host;
	int ret = 0;
	hw_regs_t hw, *hws[] = { &hw, NULL, NULL, NULL };

#if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA)
	char *mode = "MWDMA2";
#elif defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA)
	char *mode = "PIO+DDMA(offload)";
#endif

	memset(&auide_hwif, 0, sizeof(_auide_hwif));
	ahwif->irq = platform_get_irq(pdev, 0);

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);

	if (res == NULL) {
		pr_debug("%s %d: no base address\n", DRV_NAME, pdev->id);
		ret = -ENODEV;
		goto out;
	}
	if (ahwif->irq < 0) {
		pr_debug("%s %d: no IRQ\n", DRV_NAME, pdev->id);
		ret = -ENODEV;
		goto out;
	}

	if (!request_mem_region(res->start, res->end - res->start + 1,
				pdev->name)) {
		pr_debug("%s: request_mem_region failed\n", DRV_NAME);
		ret =  -EBUSY;
		goto out;
	}

	ahwif->regbase = (u32)ioremap(res->start, res->end - res->start + 1);
	if (ahwif->regbase == 0) {
		ret = -ENOMEM;
		goto out;
	}

	memset(&hw, 0, sizeof(hw));
	auide_setup_ports(&hw, ahwif);
	hw.irq = ahwif->irq;
	hw.dev = dev;
	hw.chipset = ide_au1xxx;

	ret = ide_host_add(&au1xxx_port_info, hws, &host);
	if (ret)
		goto out;

	auide_hwif.hwif = host->ports[0];

	dev_set_drvdata(dev, host);

	printk(KERN_INFO "Au1xxx IDE(builtin) configured for %s\n", mode );

 out:
	return ret;
}

static int au_ide_remove(struct device *dev)
{
	struct platform_device *pdev = to_platform_device(dev);
	struct resource *res;
	struct ide_host *host = dev_get_drvdata(dev);
	_auide_hwif *ahwif = &auide_hwif;

	ide_host_remove(host);

	iounmap((void *)ahwif->regbase);

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	release_mem_region(res->start, res->end - res->start + 1);

	return 0;
}

static struct device_driver au1200_ide_driver = {
	.name		= "au1200-ide",
	.bus		= &platform_bus_type,
	.probe 		= au_ide_probe,
	.remove		= au_ide_remove,
};

static int __init au_ide_init(void)
{
	return driver_register(&au1200_ide_driver);
}

static void __exit au_ide_exit(void)
{
	driver_unregister(&au1200_ide_driver);
}

MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("AU1200 IDE driver");

module_init(au_ide_init);
module_exit(au_ide_exit);
Commit	Line	Data
26a940e2	1	/*
26a940e2 PP	2	* BRIEF MODULE DESCRIPTION
	3	* AMD Alchemy Au1xxx IDE interface routines over the Static Bus
	4	*
	5	* Copyright (c) 2003-2005 AMD, Personal Connectivity Solutions
	6	*
	7	* This program is free software; you can redistribute it and/or modify it under
	8	* the terms of the GNU General Public License as published by the Free Software
	9	* Foundation; either version 2 of the License, or (at your option) any later
	10	* version.
	11	*
	12	* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
	13	* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
	14	* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR
	15	* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
	16	* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
	17	* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
	18	* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
	19	* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
	20	* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
	21	* POSSIBILITY OF SUCH DAMAGE.
	22	*
	23	* You should have received a copy of the GNU General Public License along with
	24	* this program; if not, write to the Free Software Foundation, Inc.,
	25	* 675 Mass Ave, Cambridge, MA 02139, USA.
	26	*
	27	* Note: for more information, please refer "AMD Alchemy Au1200/Au1550 IDE
	28	* Interface and Linux Device Driver" Application Note.
	29	*/
26a940e2 PP	30	#include <linux/types.h>
	31	#include <linux/module.h>
	32	#include <linux/kernel.h>
	33	#include <linux/delay.h>
8f29e650	34	#include <linux/platform_device.h>
26a940e2 PP	35	#include <linux/init.h>
26a940e2 PP	36	#include <linux/ide.h>
fabd3a22	37	#include <linux/scatterlist.h>
26a940e2	38
26a940e2 PP	39	#include <asm/mach-au1x00/au1xxx.h>
26a940e2 PP	40	#include <asm/mach-au1x00/au1xxx_dbdma.h>
26a940e2 PP	41	#include <asm/mach-au1x00/au1xxx_ide.h>
	42
	43	#define DRV_NAME "au1200-ide"
8f29e650	44	#define DRV_AUTHOR "Enrico Walther <enrico.walther@amd.com> / Pete Popov <ppopov@embeddedalley.com>"
26a940e2	45
8f29e650 JC	46	/* enable the burstmode in the dbdma */
8f29e650 JC	47	#define IDE_AU1XXX_BURSTMODE 1
26a940e2	48
8f29e650	49	static _auide_hwif auide_hwif;
26a940e2	50
26a940e2 PP	51	#if defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA)
26a940e2 PP	52
8f29e650	53	void auide_insw(unsigned long port, void *addr, u32 count)
26a940e2	54	{
8f29e650 JC	55	_auide_hwif *ahwif = &auide_hwif;
	56	chan_tab_t *ctp;
	57	au1x_ddma_desc_t *dp;
26a940e2	58
8f29e650 JC	59	if(!put_dest_flags(ahwif->rx_chan, (void*)addr, count << 1,
8f29e650 JC	60	DDMA_FLAGS_NOIE)) {
eb63963a	61	printk(KERN_ERR "%s failed %d\n", __func__, __LINE__);
8f29e650 JC	62	return;
	63	}
	64	ctp = ((chan_tab_t *)ahwif->rx_chan);
	65	dp = ctp->cur_ptr;
	66	while (dp->dscr_cmd0 & DSCR_CMD0_V)
	67	;
	68	ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp);
26a940e2 PP	69	}
26a940e2 PP	70
8f29e650	71	void auide_outsw(unsigned long port, void *addr, u32 count)
26a940e2	72	{
8f29e650 JC	73	_auide_hwif *ahwif = &auide_hwif;
	74	chan_tab_t *ctp;
	75	au1x_ddma_desc_t *dp;
26a940e2	76
8f29e650 JC	77	if(!put_source_flags(ahwif->tx_chan, (void*)addr,
8f29e650 JC	78	count << 1, DDMA_FLAGS_NOIE)) {
eb63963a	79	printk(KERN_ERR "%s failed %d\n", __func__, __LINE__);
8f29e650 JC	80	return;
	81	}
	82	ctp = ((chan_tab_t *)ahwif->tx_chan);
	83	dp = ctp->cur_ptr;
	84	while (dp->dscr_cmd0 & DSCR_CMD0_V)
	85	;
	86	ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp);
26a940e2 PP	87	}
26a940e2 PP	88
70f91e0d BZ	89	static void au1xxx_input_data(ide_drive_t drive, struct request rq,
	90	void *buf, unsigned int len)
	91	{
	92	auide_insw(drive->hwif->io_ports.data_addr, buf, (len + 1) / 2);
	93	}
	94
	95	static void au1xxx_output_data(ide_drive_t drive, struct request rq,
	96	void *buf, unsigned int len)
	97	{
	98	auide_outsw(drive->hwif->io_ports.data_addr, buf, (len + 1) / 2);
	99	}
26a940e2	100	#endif
26a940e2	101
26bcb879	102	static void au1xxx_set_pio_mode(ide_drive_t *drive, const u8 pio)
26a940e2	103	{
88b2b32b	104	int mem_sttime = 0, mem_stcfg = au_readl(MEM_STCFG2);
8f29e650 JC	105
	106	/* set pio mode! */
	107	switch(pio) {
	108	case 0:
	109	mem_sttime = SBC_IDE_TIMING(PIO0);
	110
	111	/* set configuration for RCS2# */
	112	mem_stcfg \|= TS_MASK;
	113	mem_stcfg &= ~TCSOE_MASK;
	114	mem_stcfg &= ~TOECS_MASK;
	115	mem_stcfg \|= SBC_IDE_PIO0_TCSOE \| SBC_IDE_PIO0_TOECS;
	116	break;
	117
	118	case 1:
	119	mem_sttime = SBC_IDE_TIMING(PIO1);
	120
	121	/* set configuration for RCS2# */
	122	mem_stcfg \|= TS_MASK;
	123	mem_stcfg &= ~TCSOE_MASK;
	124	mem_stcfg &= ~TOECS_MASK;
	125	mem_stcfg \|= SBC_IDE_PIO1_TCSOE \| SBC_IDE_PIO1_TOECS;
	126	break;
	127
	128	case 2:
	129	mem_sttime = SBC_IDE_TIMING(PIO2);
	130
	131	/* set configuration for RCS2# */
	132	mem_stcfg &= ~TS_MASK;
	133	mem_stcfg &= ~TCSOE_MASK;
	134	mem_stcfg &= ~TOECS_MASK;
	135	mem_stcfg \|= SBC_IDE_PIO2_TCSOE \| SBC_IDE_PIO2_TOECS;
	136	break;
	137
	138	case 3:
	139	mem_sttime = SBC_IDE_TIMING(PIO3);
	140
	141	/* set configuration for RCS2# */
	142	mem_stcfg &= ~TS_MASK;
	143	mem_stcfg &= ~TCSOE_MASK;
	144	mem_stcfg &= ~TOECS_MASK;
	145	mem_stcfg \|= SBC_IDE_PIO3_TCSOE \| SBC_IDE_PIO3_TOECS;
	146
	147	break;
	148
	149	case 4:
	150	mem_sttime = SBC_IDE_TIMING(PIO4);
	151
	152	/* set configuration for RCS2# */
	153	mem_stcfg &= ~TS_MASK;
	154	mem_stcfg &= ~TCSOE_MASK;
	155	mem_stcfg &= ~TOECS_MASK;
	156	mem_stcfg \|= SBC_IDE_PIO4_TCSOE \| SBC_IDE_PIO4_TOECS;
	157	break;
	158	}
	159
	160	au_writel(mem_sttime,MEM_STTIME2);
	161	au_writel(mem_stcfg,MEM_STCFG2);
26a940e2 PP	162	}
26a940e2 PP	163
88b2b32b	164	static void auide_set_dma_mode(ide_drive_t *drive, const u8 speed)
26a940e2	165	{
88b2b32b	166	int mem_sttime = 0, mem_stcfg = au_readl(MEM_STCFG2);
26a940e2	167
8f29e650	168	switch(speed) {
26a940e2	169	#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
8f29e650 JC	170	case XFER_MW_DMA_2:
	171	mem_sttime = SBC_IDE_TIMING(MDMA2);
	172
	173	/* set configuration for RCS2# */
	174	mem_stcfg &= ~TS_MASK;
	175	mem_stcfg &= ~TCSOE_MASK;
	176	mem_stcfg &= ~TOECS_MASK;
	177	mem_stcfg \|= SBC_IDE_MDMA2_TCSOE \| SBC_IDE_MDMA2_TOECS;
	178
8f29e650 JC	179	break;
	180	case XFER_MW_DMA_1:
	181	mem_sttime = SBC_IDE_TIMING(MDMA1);
	182
	183	/* set configuration for RCS2# */
	184	mem_stcfg &= ~TS_MASK;
	185	mem_stcfg &= ~TCSOE_MASK;
	186	mem_stcfg &= ~TOECS_MASK;
	187	mem_stcfg \|= SBC_IDE_MDMA1_TCSOE \| SBC_IDE_MDMA1_TOECS;
	188
8f29e650 JC	189	break;
	190	case XFER_MW_DMA_0:
	191	mem_sttime = SBC_IDE_TIMING(MDMA0);
	192
	193	/* set configuration for RCS2# */
	194	mem_stcfg \|= TS_MASK;
	195	mem_stcfg &= ~TCSOE_MASK;
	196	mem_stcfg &= ~TOECS_MASK;
	197	mem_stcfg \|= SBC_IDE_MDMA0_TCSOE \| SBC_IDE_MDMA0_TOECS;
	198
8f29e650	199	break;
26a940e2	200	#endif
8f29e650	201	}
a523a175	202
8f29e650 JC	203	au_writel(mem_sttime,MEM_STTIME2);
8f29e650 JC	204	au_writel(mem_stcfg,MEM_STCFG2);
26a940e2 PP	205	}
	206
	207	/*
	208	* Multi-Word DMA + DbDMA functions
	209	*/
26a940e2	210
8f29e650	211	#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
26a940e2 PP	212	static int auide_build_dmatable(ide_drive_t *drive)
26a940e2 PP	213	{
8f29e650 JC	214	int i, iswrite, count = 0;
8f29e650 JC	215	ide_hwif_t *hwif = HWIF(drive);
8f29e650	216	struct request *rq = HWGROUP(drive)->rq;
a536f326	217	_auide_hwif *ahwif = &auide_hwif;
8f29e650 JC	218	struct scatterlist *sg;
	219
	220	iswrite = (rq_data_dir(rq) == WRITE);
	221	/* Save for interrupt context */
	222	ahwif->drive = drive;
	223
062f9f02	224	hwif->sg_nents = i = ide_build_sglist(drive, rq);
8f29e650 JC	225
	226	if (!i)
	227	return 0;
	228
	229	/* fill the descriptors */
	230	sg = hwif->sg_table;
	231	while (i && sg_dma_len(sg)) {
	232	u32 cur_addr;
	233	u32 cur_len;
	234
	235	cur_addr = sg_dma_address(sg);
	236	cur_len = sg_dma_len(sg);
	237
	238	while (cur_len) {
	239	u32 flags = DDMA_FLAGS_NOIE;
	240	unsigned int tc = (cur_len < 0xfe00)? cur_len: 0xfe00;
	241
	242	if (++count >= PRD_ENTRIES) {
	243	printk(KERN_WARNING "%s: DMA table too small\n",
	244	drive->name);
	245	goto use_pio_instead;
	246	}
	247
	248	/* Lets enable intr for the last descriptor only */
	249	if (1==i)
	250	flags = DDMA_FLAGS_IE;
	251	else
	252	flags = DDMA_FLAGS_NOIE;
	253
	254	if (iswrite) {
	255	if(!put_source_flags(ahwif->tx_chan,
45711f1a	256	(void*) sg_virt(sg),
8f29e650 JC	257	tc, flags)) {
8f29e650 JC	258	printk(KERN_ERR "%s failed %d\n",
eb63963a	259	__func__, __LINE__);
26a940e2	260	}
8f29e650	261	} else
26a940e2	262	{
8f29e650	263	if(!put_dest_flags(ahwif->rx_chan,
45711f1a	264	(void*) sg_virt(sg),
8f29e650 JC	265	tc, flags)) {
8f29e650 JC	266	printk(KERN_ERR "%s failed %d\n",
eb63963a	267	__func__, __LINE__);
26a940e2	268	}
8f29e650	269	}
26a940e2	270
8f29e650 JC	271	cur_addr += tc;
	272	cur_len -= tc;
	273	}
55c16a70	274	sg = sg_next(sg);
8f29e650 JC	275	i--;
8f29e650 JC	276	}
26a940e2	277
8f29e650 JC	278	if (count)
8f29e650 JC	279	return 1;
26a940e2	280
8f29e650	281	use_pio_instead:
062f9f02	282	ide_destroy_dmatable(drive);
26a940e2	283
8f29e650	284	return 0; /* revert to PIO for this request */
26a940e2 PP	285	}
	286
	287	static int auide_dma_end(ide_drive_t *drive)
	288	{
8f29e650	289	ide_hwif_t *hwif = HWIF(drive);
26a940e2	290
8f29e650	291	if (hwif->sg_nents) {
062f9f02	292	ide_destroy_dmatable(drive);
8f29e650 JC	293	hwif->sg_nents = 0;
8f29e650 JC	294	}
26a940e2	295
8f29e650	296	return 0;
26a940e2 PP	297	}
	298
	299	static void auide_dma_start(ide_drive_t *drive )
	300	{
26a940e2 PP	301	}
26a940e2 PP	302
26a940e2 PP	303
	304	static void auide_dma_exec_cmd(ide_drive_t *drive, u8 command)
	305	{
8f29e650 JC	306	/* issue cmd to drive */
	307	ide_execute_command(drive, command, &ide_dma_intr,
	308	(2*WAIT_CMD), NULL);
26a940e2 PP	309	}
	310
	311	static int auide_dma_setup(ide_drive_t *drive)
8f29e650 JC	312	{
8f29e650 JC	313	struct request *rq = HWGROUP(drive)->rq;
26a940e2	314
8f29e650 JC	315	if (!auide_build_dmatable(drive)) {
	316	ide_map_sg(drive, rq);
	317	return 1;
	318	}
26a940e2	319
8f29e650 JC	320	drive->waiting_for_dma = 1;
8f29e650 JC	321	return 0;
26a940e2 PP	322	}
26a940e2 PP	323
26a940e2	324	static int auide_dma_test_irq(ide_drive_t *drive)
c67c216d	325	{
8f29e650 JC	326	/* If dbdma didn't execute the STOP command yet, the
8f29e650 JC	327	* active bit is still set
26a940e2	328	*/
8f29e650 JC	329	drive->waiting_for_dma++;
	330	if (drive->waiting_for_dma >= DMA_WAIT_TIMEOUT) {
	331	printk(KERN_WARNING "%s: timeout waiting for ddma to \
26a940e2	332	complete\n", drive->name);
8f29e650 JC	333	return 1;
	334	}
	335	udelay(10);
	336	return 0;
26a940e2 PP	337	}
26a940e2 PP	338
15ce926a	339	static void auide_dma_host_set(ide_drive_t *drive, int on)
26a940e2	340	{
26a940e2 PP	341	}
26a940e2 PP	342
841d2a9b	343	static void auide_dma_lost_irq(ide_drive_t *drive)
26a940e2	344	{
8f29e650	345	printk(KERN_ERR "%s: IRQ lost\n", drive->name);
26a940e2 PP	346	}
26a940e2 PP	347
53e62d3a	348	static void auide_ddma_tx_callback(int irq, void *param)
26a940e2	349	{
8f29e650 JC	350	_auide_hwif ahwif = (_auide_hwif)param;
8f29e650 JC	351	ahwif->drive->waiting_for_dma = 0;
26a940e2 PP	352	}
26a940e2 PP	353
53e62d3a	354	static void auide_ddma_rx_callback(int irq, void *param)
26a940e2	355	{
8f29e650 JC	356	_auide_hwif ahwif = (_auide_hwif)param;
	357	ahwif->drive->waiting_for_dma = 0;
	358	}
	359
	360	#endif /* end CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA */
26a940e2	361
8f29e650 JC	362	static void auide_init_dbdma_dev(dbdev_tab_t *dev, u32 dev_id, u32 tsize, u32 devwidth, u32 flags)
	363	{
	364	dev->dev_id = dev_id;
fcbd3b4b	365	dev->dev_physaddr = (u32)IDE_PHYS_ADDR;
8f29e650 JC	366	dev->dev_intlevel = 0;
	367	dev->dev_intpolarity = 0;
	368	dev->dev_tsize = tsize;
	369	dev->dev_devwidth = devwidth;
	370	dev->dev_flags = flags;
26a940e2 PP	371	}
26a940e2 PP	372
5e37bdc0	373	#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
c283f5db	374	static void auide_dma_timeout(ide_drive_t *drive)
26a940e2	375	{
c283f5db	376	ide_hwif_t *hwif = HWIF(drive);
26a940e2	377
8f29e650	378	printk(KERN_ERR "%s: DMA timeout occurred: ", drive->name);
26a940e2	379
5e37bdc0	380	if (auide_dma_test_irq(drive))
c283f5db	381	return;
26a940e2	382
5e37bdc0	383	auide_dma_end(drive);
26a940e2	384	}
26a940e2	385
f37afdac	386	static const struct ide_dma_ops au1xxx_dma_ops = {
5e37bdc0 BZ	387	.dma_host_set = auide_dma_host_set,
	388	.dma_setup = auide_dma_setup,
	389	.dma_exec_cmd = auide_dma_exec_cmd,
	390	.dma_start = auide_dma_start,
	391	.dma_end = auide_dma_end,
	392	.dma_test_irq = auide_dma_test_irq,
	393	.dma_lost_irq = auide_dma_lost_irq,
	394	.dma_timeout = auide_dma_timeout,
	395	};
	396
85528659 BZ	397	static int auide_ddma_init(ide_hwif_t hwif, const struct ide_port_info d)
85528659 BZ	398	{
a536f326	399	_auide_hwif *auide = &auide_hwif;
8f29e650 JC	400	dbdev_tab_t source_dev_tab, target_dev_tab;
8f29e650 JC	401	u32 dev_id, tsize, devwidth, flags;
26a940e2	402
fcbd3b4b	403	dev_id = IDE_DDMA_REQ;
26a940e2	404
f629b38b BZ	405	tsize = 8; /* 1 */
f629b38b BZ	406	devwidth = 32; /* 16 */
26a940e2	407
8f29e650 JC	408	#ifdef IDE_AU1XXX_BURSTMODE
8f29e650 JC	409	flags = DEV_FLAGS_SYNC \| DEV_FLAGS_BURSTABLE;
26a940e2	410	#else
8f29e650	411	flags = DEV_FLAGS_SYNC;
26a940e2 PP	412	#endif
26a940e2 PP	413
8f29e650 JC	414	/* setup dev_tab for tx channel */
	415	auide_init_dbdma_dev( &source_dev_tab,
	416	dev_id,
	417	tsize, devwidth, DEV_FLAGS_OUT \| flags);
	418	auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
	419
	420	auide_init_dbdma_dev( &source_dev_tab,
	421	dev_id,
	422	tsize, devwidth, DEV_FLAGS_IN \| flags);
	423	auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
	424
	425	/* We also need to add a target device for the DMA */
	426	auide_init_dbdma_dev( &target_dev_tab,
	427	(u32)DSCR_CMD0_ALWAYS,
	428	tsize, devwidth, DEV_FLAGS_ANYUSE);
	429	auide->target_dev_id = au1xxx_ddma_add_device(&target_dev_tab);
	430
	431	/* Get a channel for TX */
	432	auide->tx_chan = au1xxx_dbdma_chan_alloc(auide->target_dev_id,
	433	auide->tx_dev_id,
	434	auide_ddma_tx_callback,
	435	(void*)auide);
	436
	437	/* Get a channel for RX */
	438	auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id,
	439	auide->target_dev_id,
	440	auide_ddma_rx_callback,
	441	(void*)auide);
	442
	443	auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan,
	444	NUM_DESCRIPTORS);
	445	auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan,
	446	NUM_DESCRIPTORS);
	447
5df37c34	448	hwif->dmatable_cpu = dma_alloc_coherent(hwif->dev,
8f29e650 JC	449	PRD_ENTRIES * PRD_BYTES, /* 1 Page */
	450	&hwif->dmatable_dma, GFP_KERNEL);
	451
	452	au1xxx_dbdma_start( auide->tx_chan );
	453	au1xxx_dbdma_start( auide->rx_chan );
	454
	455	return 0;
	456	}
26a940e2	457	#else
85528659	458	static int auide_ddma_init(ide_hwif_t hwif, const struct ide_port_info d)
8f29e650	459	{
a536f326	460	_auide_hwif *auide = &auide_hwif;
8f29e650 JC	461	dbdev_tab_t source_dev_tab;
8f29e650 JC	462	int flags;
26a940e2	463
8f29e650 JC	464	#ifdef IDE_AU1XXX_BURSTMODE
	465	flags = DEV_FLAGS_SYNC \| DEV_FLAGS_BURSTABLE;
	466	#else
	467	flags = DEV_FLAGS_SYNC;
26a940e2	468	#endif
26a940e2	469
8f29e650 JC	470	/* setup dev_tab for tx channel */
	471	auide_init_dbdma_dev( &source_dev_tab,
	472	(u32)DSCR_CMD0_ALWAYS,
	473	8, 32, DEV_FLAGS_OUT \| flags);
	474	auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
	475
	476	auide_init_dbdma_dev( &source_dev_tab,
	477	(u32)DSCR_CMD0_ALWAYS,
	478	8, 32, DEV_FLAGS_IN \| flags);
	479	auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
	480
	481	/* Get a channel for TX */
	482	auide->tx_chan = au1xxx_dbdma_chan_alloc(DSCR_CMD0_ALWAYS,
	483	auide->tx_dev_id,
	484	NULL,
	485	(void*)auide);
	486
	487	/* Get a channel for RX */
	488	auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id,
	489	DSCR_CMD0_ALWAYS,
	490	NULL,
	491	(void*)auide);
	492
	493	auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan,
	494	NUM_DESCRIPTORS);
	495	auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan,
	496	NUM_DESCRIPTORS);
	497
	498	au1xxx_dbdma_start( auide->tx_chan );
	499	au1xxx_dbdma_start( auide->rx_chan );
	500
	501	return 0;
26a940e2	502	}
8f29e650	503	#endif
26a940e2 PP	504
	505	static void auide_setup_ports(hw_regs_t hw, _auide_hwif ahwif)
	506	{
8f29e650	507	int i;
4c3032d8	508	unsigned long *ata_regs = hw->io_ports_array;
8f29e650 JC	509
8f29e650 JC	510	/* FIXME? */
4c3032d8	511	for (i = 0; i < 8; i++)
fcbd3b4b	512	*ata_regs++ = ahwif->regbase + (i << IDE_REG_SHIFT);
8f29e650 JC	513
8f29e650 JC	514	/* set the Alternative Status register */
fcbd3b4b	515	*ata_regs = ahwif->regbase + (14 << IDE_REG_SHIFT);
26a940e2 PP	516	}
26a940e2 PP	517
374e042c BZ	518	#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA
	519	static const struct ide_tp_ops au1xxx_tp_ops = {
	520	.exec_command = ide_exec_command,
	521	.read_status = ide_read_status,
	522	.read_altstatus = ide_read_altstatus,
	523	.read_sff_dma_status = ide_read_sff_dma_status,
	524
	525	.set_irq = ide_set_irq,
	526
	527	.tf_load = ide_tf_load,
	528	.tf_read = ide_tf_read,
	529
	530	.input_data = au1xxx_input_data,
	531	.output_data = au1xxx_output_data,
	532	};
	533	#endif
	534
ac95beed BZ	535	static const struct ide_port_ops au1xxx_port_ops = {
	536	.set_pio_mode = au1xxx_set_pio_mode,
	537	.set_dma_mode = auide_set_dma_mode,
ac95beed BZ	538	};
ac95beed BZ	539
c413b9b9	540	static const struct ide_port_info au1xxx_port_info = {
85528659	541	.init_dma = auide_ddma_init,
374e042c BZ	542	#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA
	543	.tp_ops = &au1xxx_tp_ops,
	544	#endif
ac95beed	545	.port_ops = &au1xxx_port_ops,
5e37bdc0 BZ	546	#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
	547	.dma_ops = &au1xxx_dma_ops,
	548	#endif
c413b9b9	549	.host_flags = IDE_HFLAG_POST_SET_MODE \|
807b90d0	550	IDE_HFLAG_NO_IO_32BIT \|
c413b9b9 BZ	551	IDE_HFLAG_UNMASK_IRQS,
	552	.pio_mask = ATA_PIO4,
	553	#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
	554	.mwdma_mask = ATA_MWDMA2,
	555	#endif
	556	};
	557
26a940e2 PP	558	static int au_ide_probe(struct device *dev)
	559	{
	560	struct platform_device *pdev = to_platform_device(dev);
8f29e650	561	_auide_hwif *ahwif = &auide_hwif;
26a940e2	562	struct resource *res;
48c3c107	563	struct ide_host *host;
26a940e2	564	int ret = 0;
c97c6aca	565	hw_regs_t hw, *hws[] = { &hw, NULL, NULL, NULL };
26a940e2 PP	566
26a940e2 PP	567	#if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA)
8f29e650	568	char *mode = "MWDMA2";
26a940e2	569	#elif defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA)
8f29e650	570	char *mode = "PIO+DDMA(offload)";
26a940e2 PP	571	#endif
26a940e2 PP	572
8f29e650	573	memset(&auide_hwif, 0, sizeof(_auide_hwif));
26a940e2 PP	574	ahwif->irq = platform_get_irq(pdev, 0);
	575
	576	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	577
	578	if (res == NULL) {
	579	pr_debug("%s %d: no base address\n", DRV_NAME, pdev->id);
	580	ret = -ENODEV;
48944738 DV	581	goto out;
	582	}
	583	if (ahwif->irq < 0) {
	584	pr_debug("%s %d: no IRQ\n", DRV_NAME, pdev->id);
	585	ret = -ENODEV;
26a940e2 PP	586	goto out;
	587	}
	588
b4dcaea3 SS	589	if (!request_mem_region(res->start, res->end - res->start + 1,
b4dcaea3 SS	590	pdev->name)) {
26a940e2	591	pr_debug("%s: request_mem_region failed\n", DRV_NAME);
8f29e650	592	ret = -EBUSY;
26a940e2	593	goto out;
8f29e650	594	}
26a940e2	595
b4dcaea3	596	ahwif->regbase = (u32)ioremap(res->start, res->end - res->start + 1);
26a940e2 PP	597	if (ahwif->regbase == 0) {
	598	ret = -ENOMEM;
	599	goto out;
	600	}
	601
9239b333 BZ	602	memset(&hw, 0, sizeof(hw));
9239b333 BZ	603	auide_setup_ports(&hw, ahwif);
aa79a2fa	604	hw.irq = ahwif->irq;
ed1f7889	605	hw.dev = dev;
aa79a2fa BZ	606	hw.chipset = ide_au1xxx;
aa79a2fa BZ	607
6f904d01 BZ	608	ret = ide_host_add(&au1xxx_port_info, hws, &host);
6f904d01 BZ	609	if (ret)
48c3c107	610	goto out;
5cbf79cd	611
48c3c107	612	auide_hwif.hwif = host->ports[0];
5cbf79cd	613
48c3c107	614	dev_set_drvdata(dev, host);
26a940e2	615
8f29e650	616	printk(KERN_INFO "Au1xxx IDE(builtin) configured for %s\n", mode );
26a940e2	617
8f29e650 JC	618	out:
8f29e650 JC	619	return ret;
26a940e2 PP	620	}
	621
	622	static int au_ide_remove(struct device *dev)
	623	{
	624	struct platform_device *pdev = to_platform_device(dev);
	625	struct resource *res;
48c3c107	626	struct ide_host *host = dev_get_drvdata(dev);
8f29e650	627	_auide_hwif *ahwif = &auide_hwif;
26a940e2	628
48c3c107	629	ide_host_remove(host);
26a940e2 PP	630
	631	iounmap((void *)ahwif->regbase);
	632
	633	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
b4dcaea3	634	release_mem_region(res->start, res->end - res->start + 1);
26a940e2 PP	635
	636	return 0;
	637	}
	638
	639	static struct device_driver au1200_ide_driver = {
	640	.name = "au1200-ide",
	641	.bus = &platform_bus_type,
	642	.probe = au_ide_probe,
	643	.remove = au_ide_remove,
	644	};
	645
	646	static int __init au_ide_init(void)
	647	{
	648	return driver_register(&au1200_ide_driver);
	649	}
	650
8f29e650	651	static void __exit au_ide_exit(void)
26a940e2 PP	652	{
	653	driver_unregister(&au1200_ide_driver);
	654	}
	655
26a940e2 PP	656	MODULE_LICENSE("GPL");
	657	MODULE_DESCRIPTION("AU1200 IDE driver");
	658
	659	module_init(au_ide_init);
	660	module_exit(au_ide_exit);