[deliverable/linux.git] / drivers / ide / pci / aec62xx.c

/*
 * linux/drivers/ide/pci/aec62xx.c		Version 0.24	May 24, 2007
 *
 * Copyright (C) 1999-2002	Andre Hedrick <andre@linux-ide.org>
 * Copyright (C) 2007		MontaVista Software, Inc. <source@mvista.com>
 *
 */

#include <linux/module.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/delay.h>
#include <linux/hdreg.h>
#include <linux/ide.h>
#include <linux/init.h>

#include <asm/io.h>

struct chipset_bus_clock_list_entry {
	u8 xfer_speed;
	u8 chipset_settings;
	u8 ultra_settings;
};

static const struct chipset_bus_clock_list_entry aec6xxx_33_base [] = {
	{	XFER_UDMA_6,	0x31,	0x07	},
	{	XFER_UDMA_5,	0x31,	0x06	},
	{	XFER_UDMA_4,	0x31,	0x05	},
	{	XFER_UDMA_3,	0x31,	0x04	},
	{	XFER_UDMA_2,	0x31,	0x03	},
	{	XFER_UDMA_1,	0x31,	0x02	},
	{	XFER_UDMA_0,	0x31,	0x01	},

	{	XFER_MW_DMA_2,	0x31,	0x00	},
	{	XFER_MW_DMA_1,	0x31,	0x00	},
	{	XFER_MW_DMA_0,	0x0a,	0x00	},
	{	XFER_PIO_4,	0x31,	0x00	},
	{	XFER_PIO_3,	0x33,	0x00	},
	{	XFER_PIO_2,	0x08,	0x00	},
	{	XFER_PIO_1,	0x0a,	0x00	},
	{	XFER_PIO_0,	0x00,	0x00	},
	{	0,		0x00,	0x00	}
};

static const struct chipset_bus_clock_list_entry aec6xxx_34_base [] = {
	{	XFER_UDMA_6,	0x41,	0x06	},
	{	XFER_UDMA_5,	0x41,	0x05	},
	{	XFER_UDMA_4,	0x41,	0x04	},
	{	XFER_UDMA_3,	0x41,	0x03	},
	{	XFER_UDMA_2,	0x41,	0x02	},
	{	XFER_UDMA_1,	0x41,	0x01	},
	{	XFER_UDMA_0,	0x41,	0x01	},

	{	XFER_MW_DMA_2,	0x41,	0x00	},
	{	XFER_MW_DMA_1,	0x42,	0x00	},
	{	XFER_MW_DMA_0,	0x7a,	0x00	},
	{	XFER_PIO_4,	0x41,	0x00	},
	{	XFER_PIO_3,	0x43,	0x00	},
	{	XFER_PIO_2,	0x78,	0x00	},
	{	XFER_PIO_1,	0x7a,	0x00	},
	{	XFER_PIO_0,	0x70,	0x00	},
	{	0,		0x00,	0x00	}
};

#define BUSCLOCK(D)	\
	((struct chipset_bus_clock_list_entry *) pci_get_drvdata((D)))


/*
 * TO DO: active tuning and correction of cards without a bios.
 */
static u8 pci_bus_clock_list (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
{
	for ( ; chipset_table->xfer_speed ; chipset_table++)
		if (chipset_table->xfer_speed == speed) {
			return chipset_table->chipset_settings;
		}
	return chipset_table->chipset_settings;
}

static u8 pci_bus_clock_list_ultra (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
{
	for ( ; chipset_table->xfer_speed ; chipset_table++)
		if (chipset_table->xfer_speed == speed) {
			return chipset_table->ultra_settings;
		}
	return chipset_table->ultra_settings;
}

static int aec6210_tune_chipset(ide_drive_t *drive, const u8 speed)
{
	ide_hwif_t *hwif	= HWIF(drive);
	struct pci_dev *dev	= hwif->pci_dev;
	u16 d_conf		= 0;
	u8 ultra = 0, ultra_conf = 0;
	u8 tmp0 = 0, tmp1 = 0, tmp2 = 0;
	unsigned long flags;

	local_irq_save(flags);
	/* 0x40|(2*drive->dn): Active, 0x41|(2*drive->dn): Recovery */
	pci_read_config_word(dev, 0x40|(2*drive->dn), &d_conf);
	tmp0 = pci_bus_clock_list(speed, BUSCLOCK(dev));
	d_conf = ((tmp0 & 0xf0) << 4) | (tmp0 & 0xf);
	pci_write_config_word(dev, 0x40|(2*drive->dn), d_conf);

	tmp1 = 0x00;
	tmp2 = 0x00;
	pci_read_config_byte(dev, 0x54, &ultra);
	tmp1 = ((0x00 << (2*drive->dn)) | (ultra & ~(3 << (2*drive->dn))));
	ultra_conf = pci_bus_clock_list_ultra(speed, BUSCLOCK(dev));
	tmp2 = ((ultra_conf << (2*drive->dn)) | (tmp1 & ~(3 << (2*drive->dn))));
	pci_write_config_byte(dev, 0x54, tmp2);
	local_irq_restore(flags);
	return(ide_config_drive_speed(drive, speed));
}

static int aec6260_tune_chipset(ide_drive_t *drive, const u8 speed)
{
	ide_hwif_t *hwif	= HWIF(drive);
	struct pci_dev *dev	= hwif->pci_dev;
	u8 unit		= (drive->select.b.unit & 0x01);
	u8 tmp1 = 0, tmp2 = 0;
	u8 ultra = 0, drive_conf = 0, ultra_conf = 0;
	unsigned long flags;

	local_irq_save(flags);
	/* high 4-bits: Active, low 4-bits: Recovery */
	pci_read_config_byte(dev, 0x40|drive->dn, &drive_conf);
	drive_conf = pci_bus_clock_list(speed, BUSCLOCK(dev));
	pci_write_config_byte(dev, 0x40|drive->dn, drive_conf);

	pci_read_config_byte(dev, (0x44|hwif->channel), &ultra);
	tmp1 = ((0x00 << (4*unit)) | (ultra & ~(7 << (4*unit))));
	ultra_conf = pci_bus_clock_list_ultra(speed, BUSCLOCK(dev));
	tmp2 = ((ultra_conf << (4*unit)) | (tmp1 & ~(7 << (4*unit))));
	pci_write_config_byte(dev, (0x44|hwif->channel), tmp2);
	local_irq_restore(flags);
	return(ide_config_drive_speed(drive, speed));
}

static void aec_set_pio_mode(ide_drive_t *drive, const u8 pio)
{
	(void) HWIF(drive)->speedproc(drive, pio + XFER_PIO_0);
}

static int aec62xx_config_drive_xfer_rate (ide_drive_t *drive)
{
	if (ide_tune_dma(drive))
		return 0;

	if (ide_use_fast_pio(drive))
		ide_set_max_pio(drive);

	return -1;
}

static void aec62xx_dma_lost_irq (ide_drive_t *drive)
{
	switch (HWIF(drive)->pci_dev->device) {
		case PCI_DEVICE_ID_ARTOP_ATP860:
		case PCI_DEVICE_ID_ARTOP_ATP860R:
		case PCI_DEVICE_ID_ARTOP_ATP865:
		case PCI_DEVICE_ID_ARTOP_ATP865R:
			printk(" AEC62XX time out ");
		default:
			break;
	}
}

static unsigned int __devinit init_chipset_aec62xx(struct pci_dev *dev, const char *name)
{
	int bus_speed = system_bus_clock();

	if (bus_speed <= 33)
		pci_set_drvdata(dev, (void *) aec6xxx_33_base);
	else
		pci_set_drvdata(dev, (void *) aec6xxx_34_base);

	/* These are necessary to get AEC6280 Macintosh cards to work */
	if ((dev->device == PCI_DEVICE_ID_ARTOP_ATP865) ||
	    (dev->device == PCI_DEVICE_ID_ARTOP_ATP865R)) {
		u8 reg49h = 0, reg4ah = 0;
		/* Clear reset and test bits.  */
		pci_read_config_byte(dev, 0x49, &reg49h);
		pci_write_config_byte(dev, 0x49, reg49h & ~0x30);
		/* Enable chip interrupt output.  */
		pci_read_config_byte(dev, 0x4a, &reg4ah);
		pci_write_config_byte(dev, 0x4a, reg4ah & ~0x01);
		/* Enable burst mode. */
		pci_read_config_byte(dev, 0x4a, &reg4ah);
		pci_write_config_byte(dev, 0x4a, reg4ah | 0x80);
	}

	return dev->irq;
}

static void __devinit init_hwif_aec62xx(ide_hwif_t *hwif)
{
	struct pci_dev *dev	= hwif->pci_dev;
	u8 reg54 = 0,  mask	= hwif->channel ? 0xf0 : 0x0f;
	unsigned long flags;

	hwif->set_pio_mode = &aec_set_pio_mode;

	if (dev->device == PCI_DEVICE_ID_ARTOP_ATP850UF) {
		if(hwif->mate)
			hwif->mate->serialized = hwif->serialized = 1;
		hwif->speedproc = &aec6210_tune_chipset;
	} else
		hwif->speedproc = &aec6260_tune_chipset;

	if (!hwif->dma_base) {
		hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
		return;
	}

	hwif->ultra_mask = hwif->cds->udma_mask;
	hwif->mwdma_mask = 0x07;

	hwif->ide_dma_check	= &aec62xx_config_drive_xfer_rate;
	hwif->dma_lost_irq	= &aec62xx_dma_lost_irq;

	if (dev->device == PCI_DEVICE_ID_ARTOP_ATP850UF) {
		spin_lock_irqsave(&ide_lock, flags);
		pci_read_config_byte (dev, 0x54, &reg54);
		pci_write_config_byte(dev, 0x54, (reg54 & ~mask));
		spin_unlock_irqrestore(&ide_lock, flags);
	} else if (hwif->cbl != ATA_CBL_PATA40_SHORT) {
		u8 ata66 = 0, mask = hwif->channel ? 0x02 : 0x01;

		pci_read_config_byte(hwif->pci_dev, 0x49, &ata66);

		hwif->cbl = (ata66 & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
	}

	if (!noautodma)
		hwif->autodma = 1;
	hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
}

static int __devinit init_setup_aec62xx(struct pci_dev *dev, ide_pci_device_t *d)
{
	return ide_setup_pci_device(dev, d);
}

static int __devinit init_setup_aec6x80(struct pci_dev *dev, ide_pci_device_t *d)
{
	unsigned long dma_base = pci_resource_start(dev, 4);

	if (inb(dma_base + 2) & 0x10) {
		d->name = (dev->device == PCI_DEVICE_ID_ARTOP_ATP865R) ?
			  "AEC6880R" : "AEC6880";
		d->udma_mask = 0x7f; /* udma0-6 */
	}

	return ide_setup_pci_device(dev, d);
}

static ide_pci_device_t aec62xx_chipsets[] __devinitdata = {
	{	/* 0 */
		.name		= "AEC6210",
		.init_setup	= init_setup_aec62xx,
		.init_chipset	= init_chipset_aec62xx,
		.init_hwif	= init_hwif_aec62xx,
		.autodma	= AUTODMA,
		.enablebits	= {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
		.bootable	= OFF_BOARD,
		.pio_mask	= ATA_PIO4,
		.udma_mask	= 0x07, /* udma0-2 */
	},{	/* 1 */
		.name		= "AEC6260",
		.init_setup	= init_setup_aec62xx,
		.init_chipset	= init_chipset_aec62xx,
		.init_hwif	= init_hwif_aec62xx,
		.autodma	= NOAUTODMA,
		.bootable	= OFF_BOARD,
		.pio_mask	= ATA_PIO4,
		.udma_mask	= 0x1f, /* udma0-4 */
	},{	/* 2 */
		.name		= "AEC6260R",
		.init_setup	= init_setup_aec62xx,
		.init_chipset	= init_chipset_aec62xx,
		.init_hwif	= init_hwif_aec62xx,
		.autodma	= AUTODMA,
		.enablebits	= {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
		.bootable	= NEVER_BOARD,
		.pio_mask	= ATA_PIO4,
		.udma_mask	= 0x1f, /* udma0-4 */
	},{	/* 3 */
		.name		= "AEC6280",
		.init_setup	= init_setup_aec6x80,
		.init_chipset	= init_chipset_aec62xx,
		.init_hwif	= init_hwif_aec62xx,
		.autodma	= AUTODMA,
		.bootable	= OFF_BOARD,
		.pio_mask	= ATA_PIO4,
		.udma_mask	= 0x3f, /* udma0-5 */
	},{	/* 4 */
		.name		= "AEC6280R",
		.init_setup	= init_setup_aec6x80,
		.init_chipset	= init_chipset_aec62xx,
		.init_hwif	= init_hwif_aec62xx,
		.autodma	= AUTODMA,
		.enablebits	= {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
		.bootable	= OFF_BOARD,
		.pio_mask	= ATA_PIO4,
		.udma_mask	= 0x3f, /* udma0-5 */
	}
};

/**
 *	aec62xx_init_one	-	called when a AEC is found
 *	@dev: the aec62xx device
 *	@id: the matching pci id
 *
 *	Called when the PCI registration layer (or the IDE initialization)
 *	finds a device matching our IDE device tables.
 *
 *	NOTE: since we're going to modify the 'name' field for AEC-6[26]80[R]
 *	chips, pass a local copy of 'struct pci_device_id' down the call chain.
 */
 
static int __devinit aec62xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	ide_pci_device_t d = aec62xx_chipsets[id->driver_data];

	return d.init_setup(dev, &d);
}

static struct pci_device_id aec62xx_pci_tbl[] = {
	{ PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP850UF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
	{ PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP860,   PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
	{ PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP860R,  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 },
	{ PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP865,   PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3 },
	{ PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP865R,  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, aec62xx_pci_tbl);

static struct pci_driver driver = {
	.name		= "AEC62xx_IDE",
	.id_table	= aec62xx_pci_tbl,
	.probe		= aec62xx_init_one,
};

static int __init aec62xx_ide_init(void)
{
	return ide_pci_register_driver(&driver);
}

module_init(aec62xx_ide_init);

MODULE_AUTHOR("Andre Hedrick");
MODULE_DESCRIPTION("PCI driver module for ARTOP AEC62xx IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4	1	/*
6d78013b	2	* linux/drivers/ide/pci/aec62xx.c Version 0.24 May 24, 2007
1da177e4 LT	3	*
1da177e4 LT	4	* Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
826a1b65	5	* Copyright (C) 2007 MontaVista Software, Inc. <source@mvista.com>
1da177e4 LT	6	*
	7	*/
	8
	9	#include <linux/module.h>
1da177e4 LT	10	#include <linux/types.h>
	11	#include <linux/pci.h>
	12	#include <linux/delay.h>
	13	#include <linux/hdreg.h>
	14	#include <linux/ide.h>
	15	#include <linux/init.h>
	16
	17	#include <asm/io.h>
	18
	19	struct chipset_bus_clock_list_entry {
	20	u8 xfer_speed;
	21	u8 chipset_settings;
	22	u8 ultra_settings;
	23	};
	24
f201f504	25	static const struct chipset_bus_clock_list_entry aec6xxx_33_base [] = {
1da177e4 LT	26	{ XFER_UDMA_6, 0x31, 0x07 },
	27	{ XFER_UDMA_5, 0x31, 0x06 },
	28	{ XFER_UDMA_4, 0x31, 0x05 },
	29	{ XFER_UDMA_3, 0x31, 0x04 },
	30	{ XFER_UDMA_2, 0x31, 0x03 },
	31	{ XFER_UDMA_1, 0x31, 0x02 },
	32	{ XFER_UDMA_0, 0x31, 0x01 },
	33
	34	{ XFER_MW_DMA_2, 0x31, 0x00 },
	35	{ XFER_MW_DMA_1, 0x31, 0x00 },
	36	{ XFER_MW_DMA_0, 0x0a, 0x00 },
	37	{ XFER_PIO_4, 0x31, 0x00 },
	38	{ XFER_PIO_3, 0x33, 0x00 },
	39	{ XFER_PIO_2, 0x08, 0x00 },
	40	{ XFER_PIO_1, 0x0a, 0x00 },
	41	{ XFER_PIO_0, 0x00, 0x00 },
	42	{ 0, 0x00, 0x00 }
	43	};
	44
f201f504	45	static const struct chipset_bus_clock_list_entry aec6xxx_34_base [] = {
1da177e4 LT	46	{ XFER_UDMA_6, 0x41, 0x06 },
	47	{ XFER_UDMA_5, 0x41, 0x05 },
	48	{ XFER_UDMA_4, 0x41, 0x04 },
	49	{ XFER_UDMA_3, 0x41, 0x03 },
	50	{ XFER_UDMA_2, 0x41, 0x02 },
	51	{ XFER_UDMA_1, 0x41, 0x01 },
	52	{ XFER_UDMA_0, 0x41, 0x01 },
	53
	54	{ XFER_MW_DMA_2, 0x41, 0x00 },
	55	{ XFER_MW_DMA_1, 0x42, 0x00 },
	56	{ XFER_MW_DMA_0, 0x7a, 0x00 },
	57	{ XFER_PIO_4, 0x41, 0x00 },
	58	{ XFER_PIO_3, 0x43, 0x00 },
	59	{ XFER_PIO_2, 0x78, 0x00 },
	60	{ XFER_PIO_1, 0x7a, 0x00 },
	61	{ XFER_PIO_0, 0x70, 0x00 },
	62	{ 0, 0x00, 0x00 }
	63	};
	64
	65	#define BUSCLOCK(D) \
	66	((struct chipset_bus_clock_list_entry *) pci_get_drvdata((D)))
	67
1da177e4 LT	68
	69	/*
	70	* TO DO: active tuning and correction of cards without a bios.
	71	*/
	72	static u8 pci_bus_clock_list (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
	73	{
	74	for ( ; chipset_table->xfer_speed ; chipset_table++)
	75	if (chipset_table->xfer_speed == speed) {
	76	return chipset_table->chipset_settings;
	77	}
	78	return chipset_table->chipset_settings;
	79	}
	80
	81	static u8 pci_bus_clock_list_ultra (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
	82	{
	83	for ( ; chipset_table->xfer_speed ; chipset_table++)
	84	if (chipset_table->xfer_speed == speed) {
	85	return chipset_table->ultra_settings;
	86	}
	87	return chipset_table->ultra_settings;
	88	}
	89
f212ff28	90	static int aec6210_tune_chipset(ide_drive_t *drive, const u8 speed)
1da177e4 LT	91	{
	92	ide_hwif_t *hwif = HWIF(drive);
	93	struct pci_dev *dev = hwif->pci_dev;
	94	u16 d_conf = 0;
1da177e4 LT	95	u8 ultra = 0, ultra_conf = 0;
	96	u8 tmp0 = 0, tmp1 = 0, tmp2 = 0;
	97	unsigned long flags;
	98
	99	local_irq_save(flags);
	100	/* 0x40\|(2drive->dn): Active, 0x41\|(2drive->dn): Recovery */
	101	pci_read_config_word(dev, 0x40\|(2*drive->dn), &d_conf);
	102	tmp0 = pci_bus_clock_list(speed, BUSCLOCK(dev));
	103	d_conf = ((tmp0 & 0xf0) << 4) \| (tmp0 & 0xf);
	104	pci_write_config_word(dev, 0x40\|(2*drive->dn), d_conf);
	105
	106	tmp1 = 0x00;
	107	tmp2 = 0x00;
	108	pci_read_config_byte(dev, 0x54, &ultra);
	109	tmp1 = ((0x00 << (2drive->dn)) \| (ultra & ~(3 << (2drive->dn))));
	110	ultra_conf = pci_bus_clock_list_ultra(speed, BUSCLOCK(dev));
	111	tmp2 = ((ultra_conf << (2drive->dn)) \| (tmp1 & ~(3 << (2drive->dn))));
	112	pci_write_config_byte(dev, 0x54, tmp2);
	113	local_irq_restore(flags);
	114	return(ide_config_drive_speed(drive, speed));
	115	}
	116
f212ff28	117	static int aec6260_tune_chipset(ide_drive_t *drive, const u8 speed)
1da177e4 LT	118	{
	119	ide_hwif_t *hwif = HWIF(drive);
	120	struct pci_dev *dev = hwif->pci_dev;
1da177e4 LT	121	u8 unit = (drive->select.b.unit & 0x01);
	122	u8 tmp1 = 0, tmp2 = 0;
	123	u8 ultra = 0, drive_conf = 0, ultra_conf = 0;
	124	unsigned long flags;
	125
	126	local_irq_save(flags);
	127	/* high 4-bits: Active, low 4-bits: Recovery */
	128	pci_read_config_byte(dev, 0x40\|drive->dn, &drive_conf);
	129	drive_conf = pci_bus_clock_list(speed, BUSCLOCK(dev));
	130	pci_write_config_byte(dev, 0x40\|drive->dn, drive_conf);
	131
	132	pci_read_config_byte(dev, (0x44\|hwif->channel), &ultra);
	133	tmp1 = ((0x00 << (4unit)) \| (ultra & ~(7 << (4unit))));
	134	ultra_conf = pci_bus_clock_list_ultra(speed, BUSCLOCK(dev));
	135	tmp2 = ((ultra_conf << (4unit)) \| (tmp1 & ~(7 << (4unit))));
	136	pci_write_config_byte(dev, (0x44\|hwif->channel), tmp2);
	137	local_irq_restore(flags);
	138	return(ide_config_drive_speed(drive, speed));
	139	}
	140
26bcb879	141	static void aec_set_pio_mode(ide_drive_t *drive, const u8 pio)
1da177e4	142	{
6d78013b	143	(void) HWIF(drive)->speedproc(drive, pio + XFER_PIO_0);
1da177e4 LT	144	}
	145
	146	static int aec62xx_config_drive_xfer_rate (ide_drive_t *drive)
	147	{
29e744d0	148	if (ide_tune_dma(drive))
3608b5d7	149	return 0;
1da177e4	150
d8f4469d	151	if (ide_use_fast_pio(drive))
26bcb879	152	ide_set_max_pio(drive);
d8f4469d	153
3608b5d7	154	return -1;
1da177e4 LT	155	}
1da177e4 LT	156
841d2a9b	157	static void aec62xx_dma_lost_irq (ide_drive_t *drive)
1da177e4	158	{
841d2a9b	159	switch (HWIF(drive)->pci_dev->device) {
1da177e4 LT	160	case PCI_DEVICE_ID_ARTOP_ATP860:
	161	case PCI_DEVICE_ID_ARTOP_ATP860R:
	162	case PCI_DEVICE_ID_ARTOP_ATP865:
	163	case PCI_DEVICE_ID_ARTOP_ATP865R:
	164	printk(" AEC62XX time out ");
1da177e4 LT	165	default:
	166	break;
	167	}
1da177e4 LT	168	}
	169
	170	static unsigned int __devinit init_chipset_aec62xx(struct pci_dev dev, const char name)
	171	{
	172	int bus_speed = system_bus_clock();
	173
1da177e4 LT	174	if (bus_speed <= 33)
	175	pci_set_drvdata(dev, (void *) aec6xxx_33_base);
	176	else
	177	pci_set_drvdata(dev, (void *) aec6xxx_34_base);
	178
d237bf49 TV	179	/* These are necessary to get AEC6280 Macintosh cards to work */
	180	if ((dev->device == PCI_DEVICE_ID_ARTOP_ATP865) \|\|
	181	(dev->device == PCI_DEVICE_ID_ARTOP_ATP865R)) {
	182	u8 reg49h = 0, reg4ah = 0;
	183	/* Clear reset and test bits. */
	184	pci_read_config_byte(dev, 0x49, &reg49h);
	185	pci_write_config_byte(dev, 0x49, reg49h & ~0x30);
	186	/* Enable chip interrupt output. */
	187	pci_read_config_byte(dev, 0x4a, &reg4ah);
	188	pci_write_config_byte(dev, 0x4a, reg4ah & ~0x01);
	189	/* Enable burst mode. */
	190	pci_read_config_byte(dev, 0x4a, &reg4ah);
	191	pci_write_config_byte(dev, 0x4a, reg4ah \| 0x80);
	192	}
	193
1da177e4 LT	194	return dev->irq;
	195	}
	196
	197	static void __devinit init_hwif_aec62xx(ide_hwif_t *hwif)
	198	{
1b9da32a SS	199	struct pci_dev *dev = hwif->pci_dev;
	200	u8 reg54 = 0, mask = hwif->channel ? 0xf0 : 0x0f;
	201	unsigned long flags;
18137207	202
26bcb879	203	hwif->set_pio_mode = &aec_set_pio_mode;
1da177e4	204
6d78013b SS	205	if (dev->device == PCI_DEVICE_ID_ARTOP_ATP850UF) {
	206	if(hwif->mate)
	207	hwif->mate->serialized = hwif->serialized = 1;
	208	hwif->speedproc = &aec6210_tune_chipset;
	209	} else
	210	hwif->speedproc = &aec6260_tune_chipset;
1da177e4 LT	211
1da177e4 LT	212	if (!hwif->dma_base) {
1b9da32a	213	hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
1da177e4 LT	214	return;
	215	}
	216
18137207	217	hwif->ultra_mask = hwif->cds->udma_mask;
1da177e4	218	hwif->mwdma_mask = 0x07;
1da177e4 LT	219
1da177e4 LT	220	hwif->ide_dma_check = &aec62xx_config_drive_xfer_rate;
841d2a9b	221	hwif->dma_lost_irq = &aec62xx_dma_lost_irq;
826a1b65	222
1da177e4	223	if (dev->device == PCI_DEVICE_ID_ARTOP_ATP850UF) {
1da177e4	224	spin_lock_irqsave(&ide_lock, flags);
1b9da32a SS	225	pci_read_config_byte (dev, 0x54, &reg54);
1b9da32a SS	226	pci_write_config_byte(dev, 0x54, (reg54 & ~mask));
1da177e4	227	spin_unlock_irqrestore(&ide_lock, flags);
49521f97	228	} else if (hwif->cbl != ATA_CBL_PATA40_SHORT) {
1b9da32a SS	229	u8 ata66 = 0, mask = hwif->channel ? 0x02 : 0x01;
1b9da32a SS	230
1da177e4	231	pci_read_config_byte(hwif->pci_dev, 0x49, &ata66);
49521f97 BZ	232
49521f97 BZ	233	hwif->cbl = (ata66 & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
1da177e4 LT	234	}
1da177e4 LT	235
1b9da32a SS	236	if (!noautodma)
	237	hwif->autodma = 1;
	238	hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
1da177e4 LT	239	}
	240
	241	static int __devinit init_setup_aec62xx(struct pci_dev dev, ide_pci_device_t d)
	242	{
	243	return ide_setup_pci_device(dev, d);
	244	}
	245
	246	static int __devinit init_setup_aec6x80(struct pci_dev dev, ide_pci_device_t d)
	247	{
b1d19db4	248	unsigned long dma_base = pci_resource_start(dev, 4);
1da177e4	249
b1d19db4 SS	250	if (inb(dma_base + 2) & 0x10) {
	251	d->name = (dev->device == PCI_DEVICE_ID_ARTOP_ATP865R) ?
	252	"AEC6880R" : "AEC6880";
	253	d->udma_mask = 0x7f; /* udma0-6 */
1da177e4 LT	254	}
	255
	256	return ide_setup_pci_device(dev, d);
	257	}
	258
	259	static ide_pci_device_t aec62xx_chipsets[] __devinitdata = {
	260	{ /* 0 */
	261	.name = "AEC6210",
	262	.init_setup = init_setup_aec62xx,
	263	.init_chipset = init_chipset_aec62xx,
	264	.init_hwif = init_hwif_aec62xx,
1da177e4 LT	265	.autodma = AUTODMA,
	266	.enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
	267	.bootable = OFF_BOARD,
4099d143	268	.pio_mask = ATA_PIO4,
18137207	269	.udma_mask = 0x07, /* udma0-2 */
1da177e4 LT	270	},{ /* 1 */
	271	.name = "AEC6260",
	272	.init_setup = init_setup_aec62xx,
	273	.init_chipset = init_chipset_aec62xx,
	274	.init_hwif = init_hwif_aec62xx,
1da177e4 LT	275	.autodma = NOAUTODMA,
1da177e4 LT	276	.bootable = OFF_BOARD,
4099d143	277	.pio_mask = ATA_PIO4,
18137207	278	.udma_mask = 0x1f, /* udma0-4 */
1da177e4 LT	279	},{ /* 2 */
	280	.name = "AEC6260R",
	281	.init_setup = init_setup_aec62xx,
	282	.init_chipset = init_chipset_aec62xx,
	283	.init_hwif = init_hwif_aec62xx,
1da177e4 LT	284	.autodma = AUTODMA,
	285	.enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
	286	.bootable = NEVER_BOARD,
4099d143	287	.pio_mask = ATA_PIO4,
18137207	288	.udma_mask = 0x1f, /* udma0-4 */
1da177e4	289	},{ /* 3 */
b1d19db4	290	.name = "AEC6280",
1da177e4 LT	291	.init_setup = init_setup_aec6x80,
	292	.init_chipset = init_chipset_aec62xx,
	293	.init_hwif = init_hwif_aec62xx,
1da177e4 LT	294	.autodma = AUTODMA,
1da177e4 LT	295	.bootable = OFF_BOARD,
4099d143	296	.pio_mask = ATA_PIO4,
18137207	297	.udma_mask = 0x3f, /* udma0-5 */
1da177e4	298	},{ /* 4 */
b1d19db4	299	.name = "AEC6280R",
1da177e4 LT	300	.init_setup = init_setup_aec6x80,
	301	.init_chipset = init_chipset_aec62xx,
	302	.init_hwif = init_hwif_aec62xx,
1da177e4 LT	303	.autodma = AUTODMA,
	304	.enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
	305	.bootable = OFF_BOARD,
4099d143	306	.pio_mask = ATA_PIO4,
18137207	307	.udma_mask = 0x3f, /* udma0-5 */
1da177e4 LT	308	}
	309	};
	310
	311	/**
	312	* aec62xx_init_one - called when a AEC is found
	313	* @dev: the aec62xx device
	314	* @id: the matching pci id
	315	*
	316	* Called when the PCI registration layer (or the IDE initialization)
	317	* finds a device matching our IDE device tables.
b1d19db4 SS	318	*
	319	* NOTE: since we're going to modify the 'name' field for AEC-6[26]80[R]
	320	* chips, pass a local copy of 'struct pci_device_id' down the call chain.
1da177e4 LT	321	*/
	322
	323	static int __devinit aec62xx_init_one(struct pci_dev dev, const struct pci_device_id id)
	324	{
b1d19db4	325	ide_pci_device_t d = aec62xx_chipsets[id->driver_data];
1da177e4	326
b1d19db4	327	return d.init_setup(dev, &d);
1da177e4 LT	328	}
1da177e4 LT	329
28a2a3f5 AC	330	static struct pci_device_id aec62xx_pci_tbl[] = {
	331	{ PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP850UF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
	332	{ PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
	333	{ PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP860R, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 },
	334	{ PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP865, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3 },
	335	{ PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP865R, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
1da177e4 LT	336	{ 0, },
	337	};
	338	MODULE_DEVICE_TABLE(pci, aec62xx_pci_tbl);
	339
	340	static struct pci_driver driver = {
	341	.name = "AEC62xx_IDE",
	342	.id_table = aec62xx_pci_tbl,
	343	.probe = aec62xx_init_one,
	344	};
	345
82ab1eec	346	static int __init aec62xx_ide_init(void)
1da177e4 LT	347	{
	348	return ide_pci_register_driver(&driver);
	349	}
	350
	351	module_init(aec62xx_ide_init);
	352
	353	MODULE_AUTHOR("Andre Hedrick");
	354	MODULE_DESCRIPTION("PCI driver module for ARTOP AEC62xx IDE");
	355	MODULE_LICENSE("GPL");