[deliverable/linux.git] / drivers / ide / pci / atiixp.c

/*
 *  linux/drivers/ide/pci/atiixp.c	Version 0.02	Jun 16 2007
 *
 *  Copyright (C) 2003 ATI Inc. <hyu@ati.com>
 *  Copyright (C) 2004,2007 Bartlomiej Zolnierkiewicz
 */

#include <linux/types.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/ioport.h>
#include <linux/pci.h>
#include <linux/hdreg.h>
#include <linux/ide.h>
#include <linux/delay.h>
#include <linux/init.h>

#include <asm/io.h>

#define ATIIXP_IDE_PIO_TIMING		0x40
#define ATIIXP_IDE_MDMA_TIMING		0x44
#define ATIIXP_IDE_PIO_CONTROL		0x48
#define ATIIXP_IDE_PIO_MODE		0x4a
#define ATIIXP_IDE_UDMA_CONTROL		0x54
#define ATIIXP_IDE_UDMA_MODE		0x56

typedef struct {
	u8 command_width;
	u8 recover_width;
} atiixp_ide_timing;

static atiixp_ide_timing pio_timing[] = {
	{ 0x05, 0x0d },
	{ 0x04, 0x07 },
	{ 0x03, 0x04 },
	{ 0x02, 0x02 },
	{ 0x02, 0x00 },
};

static atiixp_ide_timing mdma_timing[] = {
	{ 0x07, 0x07 },
	{ 0x02, 0x01 },
	{ 0x02, 0x00 },
};

static int save_mdma_mode[4];

static DEFINE_SPINLOCK(atiixp_lock);

/**
 *	atiixp_dma_2_pio		-	return the PIO mode matching DMA
 *	@xfer_rate: transfer speed
 *
 *	Returns the nearest equivalent PIO timing for the PIO or DMA
 *	mode requested by the controller.
 */

static u8 atiixp_dma_2_pio(u8 xfer_rate) {
	switch(xfer_rate) {
		case XFER_UDMA_6:
		case XFER_UDMA_5:
		case XFER_UDMA_4:
		case XFER_UDMA_3:
		case XFER_UDMA_2:
		case XFER_UDMA_1:
		case XFER_UDMA_0:
		case XFER_MW_DMA_2:
		case XFER_PIO_4:
			return 4;
		case XFER_MW_DMA_1:
		case XFER_PIO_3:
			return 3;
		case XFER_SW_DMA_2:
		case XFER_PIO_2:
			return 2;
		case XFER_MW_DMA_0:
		case XFER_SW_DMA_1:
		case XFER_SW_DMA_0:
		case XFER_PIO_1:
		case XFER_PIO_0:
		case XFER_PIO_SLOW:
		default:
			return 0;
	}
}

static void atiixp_dma_host_on(ide_drive_t *drive)
{
	struct pci_dev *dev = drive->hwif->pci_dev;
	unsigned long flags;
	u16 tmp16;

	spin_lock_irqsave(&atiixp_lock, flags);

	pci_read_config_word(dev, ATIIXP_IDE_UDMA_CONTROL, &tmp16);
	if (save_mdma_mode[drive->dn])
		tmp16 &= ~(1 << drive->dn);
	else
		tmp16 |= (1 << drive->dn);
	pci_write_config_word(dev, ATIIXP_IDE_UDMA_CONTROL, tmp16);

	spin_unlock_irqrestore(&atiixp_lock, flags);

	ide_dma_host_on(drive);
}

static void atiixp_dma_host_off(ide_drive_t *drive)
{
	struct pci_dev *dev = drive->hwif->pci_dev;
	unsigned long flags;
	u16 tmp16;

	spin_lock_irqsave(&atiixp_lock, flags);

	pci_read_config_word(dev, ATIIXP_IDE_UDMA_CONTROL, &tmp16);
	tmp16 &= ~(1 << drive->dn);
	pci_write_config_word(dev, ATIIXP_IDE_UDMA_CONTROL, tmp16);

	spin_unlock_irqrestore(&atiixp_lock, flags);

	ide_dma_host_off(drive);
}

/**
 *	atiixp_tune_pio	-	tune a drive attached to a ATIIXP
 *	@drive: drive to tune
 *	@pio: desired PIO mode
 *
 *	Set the interface PIO mode.
 */

static void atiixp_tune_pio(ide_drive_t *drive, u8 pio)
{
	struct pci_dev *dev = drive->hwif->pci_dev;
	unsigned long flags;
	int timing_shift = (drive->dn & 2) ? 16 : 0 + (drive->dn & 1) ? 0 : 8;
	u32 pio_timing_data;
	u16 pio_mode_data;

	spin_lock_irqsave(&atiixp_lock, flags);

	pci_read_config_word(dev, ATIIXP_IDE_PIO_MODE, &pio_mode_data);
	pio_mode_data &= ~(0x07 << (drive->dn * 4));
	pio_mode_data |= (pio << (drive->dn * 4));
	pci_write_config_word(dev, ATIIXP_IDE_PIO_MODE, pio_mode_data);

	pci_read_config_dword(dev, ATIIXP_IDE_PIO_TIMING, &pio_timing_data);
	pio_timing_data &= ~(0xff << timing_shift);
	pio_timing_data |= (pio_timing[pio].recover_width << timing_shift) |
		 (pio_timing[pio].command_width << (timing_shift + 4));
	pci_write_config_dword(dev, ATIIXP_IDE_PIO_TIMING, pio_timing_data);

	spin_unlock_irqrestore(&atiixp_lock, flags);
}

static void atiixp_set_pio_mode(ide_drive_t *drive, const u8 pio)
{
	atiixp_tune_pio(drive, pio);
	(void)ide_config_drive_speed(drive, XFER_PIO_0 + pio);
}

/**
 *	atiixp_tune_chipset	-	tune a ATIIXP interface
 *	@drive: IDE drive to tune
 *	@speed: speed to configure
 *
 *	Set a ATIIXP interface channel to the desired speeds. This involves
 *	requires the right timing data into the ATIIXP configuration space
 *	then setting the drive parameters appropriately
 */

static int atiixp_speedproc(ide_drive_t *drive, const u8 speed)
{
	struct pci_dev *dev = drive->hwif->pci_dev;
	unsigned long flags;
	int timing_shift = (drive->dn & 2) ? 16 : 0 + (drive->dn & 1) ? 0 : 8;
	u32 tmp32;
	u16 tmp16;
	u8 pio;

	spin_lock_irqsave(&atiixp_lock, flags);

	save_mdma_mode[drive->dn] = 0;
	if (speed >= XFER_UDMA_0) {
		pci_read_config_word(dev, ATIIXP_IDE_UDMA_MODE, &tmp16);
		tmp16 &= ~(0x07 << (drive->dn * 4));
		tmp16 |= ((speed & 0x07) << (drive->dn * 4));
		pci_write_config_word(dev, ATIIXP_IDE_UDMA_MODE, tmp16);
	} else {
		if ((speed >= XFER_MW_DMA_0) && (speed <= XFER_MW_DMA_2)) {
			save_mdma_mode[drive->dn] = speed;
			pci_read_config_dword(dev, ATIIXP_IDE_MDMA_TIMING, &tmp32);
			tmp32 &= ~(0xff << timing_shift);
			tmp32 |= (mdma_timing[speed & 0x03].recover_width << timing_shift) |
				(mdma_timing[speed & 0x03].command_width << (timing_shift + 4));
			pci_write_config_dword(dev, ATIIXP_IDE_MDMA_TIMING, tmp32);
		}
	}

	spin_unlock_irqrestore(&atiixp_lock, flags);

	if (speed >= XFER_SW_DMA_0)
		pio = atiixp_dma_2_pio(speed);
	else
		pio = speed - XFER_PIO_0;

	atiixp_tune_pio(drive, pio);

	return ide_config_drive_speed(drive, speed);
}

/**
 *	atiixp_dma_check	-	set up an IDE device
 *	@drive: IDE drive to configure
 *
 *	Set up the ATIIXP interface for the best available speed on this
 *	interface, preferring DMA to PIO.
 */

static int atiixp_dma_check(ide_drive_t *drive)
{
	drive->init_speed = 0;

	if (ide_tune_dma(drive))
		return 0;

	if (ide_use_fast_pio(drive))
		ide_set_max_pio(drive);

	return -1;
}

/**
 *	init_hwif_atiixp		-	fill in the hwif for the ATIIXP
 *	@hwif: IDE interface
 *
 *	Set up the ide_hwif_t for the ATIIXP interface according to the
 *	capabilities of the hardware.
 */

static void __devinit init_hwif_atiixp(ide_hwif_t *hwif)
{
	u8 udma_mode = 0;
	u8 ch = hwif->channel;
	struct pci_dev *pdev = hwif->pci_dev;

	if (!hwif->irq)
		hwif->irq = ch ? 15 : 14;

	hwif->autodma = 0;
	hwif->set_pio_mode = &atiixp_set_pio_mode;
	hwif->speedproc = &atiixp_speedproc;
	hwif->drives[0].autotune = 1;
	hwif->drives[1].autotune = 1;

	if (!hwif->dma_base)
		return;

	hwif->atapi_dma = 1;
	hwif->ultra_mask = 0x3f;
	hwif->mwdma_mask = 0x06;
	hwif->swdma_mask = 0x04;

	pci_read_config_byte(pdev, ATIIXP_IDE_UDMA_MODE + ch, &udma_mode);

	if ((udma_mode & 0x07) >= 0x04 || (udma_mode & 0x70) >= 0x40)
		hwif->cbl = ATA_CBL_PATA80;
	else
		hwif->cbl = ATA_CBL_PATA40;

	hwif->dma_host_on = &atiixp_dma_host_on;
	hwif->dma_host_off = &atiixp_dma_host_off;
	hwif->ide_dma_check = &atiixp_dma_check;
	if (!noautodma)
		hwif->autodma = 1;

	hwif->drives[1].autodma = hwif->autodma;
	hwif->drives[0].autodma = hwif->autodma;
}


static ide_pci_device_t atiixp_pci_info[] __devinitdata = {
	{	/* 0 */
		.name		= "ATIIXP",
		.init_hwif	= init_hwif_atiixp,
		.autodma	= AUTODMA,
		.enablebits	= {{0x48,0x01,0x00}, {0x48,0x08,0x00}},
		.bootable	= ON_BOARD,
		.pio_mask	= ATA_PIO4,
	},{	/* 1 */
		.name		= "SB600_PATA",
		.init_hwif	= init_hwif_atiixp,
		.autodma	= AUTODMA,
		.enablebits	= {{0x48,0x01,0x00}, {0x00,0x00,0x00}},
 		.bootable	= ON_BOARD,
 		.host_flags	= IDE_HFLAG_SINGLE,
		.pio_mask	= ATA_PIO4,
 	},
};

/**
 *	atiixp_init_one	-	called when a ATIIXP is found
 *	@dev: the atiixp device
 *	@id: the matching pci id
 *
 *	Called when the PCI registration layer (or the IDE initialization)
 *	finds a device matching our IDE device tables.
 */

static int __devinit atiixp_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	return ide_setup_pci_device(dev, &atiixp_pci_info[id->driver_data]);
}

static struct pci_device_id atiixp_pci_tbl[] = {
	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP200_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP300_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, atiixp_pci_tbl);

static struct pci_driver driver = {
	.name		= "ATIIXP_IDE",
	.id_table	= atiixp_pci_tbl,
	.probe		= atiixp_init_one,
};

static int __init atiixp_ide_init(void)
{
	return ide_pci_register_driver(&driver);
}

module_init(atiixp_ide_init);

MODULE_AUTHOR("HUI YU");
MODULE_DESCRIPTION("PCI driver module for ATI IXP IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4	1	/*
485efc6c	2	* linux/drivers/ide/pci/atiixp.c Version 0.02 Jun 16 2007
1da177e4 LT	3	*
1da177e4 LT	4	* Copyright (C) 2003 ATI Inc. <hyu@ati.com>
485efc6c	5	* Copyright (C) 2004,2007 Bartlomiej Zolnierkiewicz
1da177e4 LT	6	*/
1da177e4 LT	7
1da177e4 LT	8	#include <linux/types.h>
	9	#include <linux/module.h>
	10	#include <linux/kernel.h>
	11	#include <linux/ioport.h>
	12	#include <linux/pci.h>
	13	#include <linux/hdreg.h>
	14	#include <linux/ide.h>
	15	#include <linux/delay.h>
	16	#include <linux/init.h>
	17
	18	#include <asm/io.h>
	19
	20	#define ATIIXP_IDE_PIO_TIMING 0x40
	21	#define ATIIXP_IDE_MDMA_TIMING 0x44
	22	#define ATIIXP_IDE_PIO_CONTROL 0x48
	23	#define ATIIXP_IDE_PIO_MODE 0x4a
	24	#define ATIIXP_IDE_UDMA_CONTROL 0x54
	25	#define ATIIXP_IDE_UDMA_MODE 0x56
	26
	27	typedef struct {
	28	u8 command_width;
	29	u8 recover_width;
	30	} atiixp_ide_timing;
	31
	32	static atiixp_ide_timing pio_timing[] = {
	33	{ 0x05, 0x0d },
	34	{ 0x04, 0x07 },
	35	{ 0x03, 0x04 },
	36	{ 0x02, 0x02 },
	37	{ 0x02, 0x00 },
	38	};
	39
	40	static atiixp_ide_timing mdma_timing[] = {
	41	{ 0x07, 0x07 },
	42	{ 0x02, 0x01 },
	43	{ 0x02, 0x00 },
	44	};
	45
	46	static int save_mdma_mode[4];
	47
6c5f8cc3 A	48	static DEFINE_SPINLOCK(atiixp_lock);
6c5f8cc3 A	49
1da177e4 LT	50	/**
	51	* atiixp_dma_2_pio - return the PIO mode matching DMA
	52	* @xfer_rate: transfer speed
	53	*
	54	* Returns the nearest equivalent PIO timing for the PIO or DMA
	55	* mode requested by the controller.
	56	*/
	57
	58	static u8 atiixp_dma_2_pio(u8 xfer_rate) {
	59	switch(xfer_rate) {
	60	case XFER_UDMA_6:
	61	case XFER_UDMA_5:
	62	case XFER_UDMA_4:
	63	case XFER_UDMA_3:
	64	case XFER_UDMA_2:
	65	case XFER_UDMA_1:
	66	case XFER_UDMA_0:
	67	case XFER_MW_DMA_2:
	68	case XFER_PIO_4:
	69	return 4;
	70	case XFER_MW_DMA_1:
	71	case XFER_PIO_3:
	72	return 3;
	73	case XFER_SW_DMA_2:
	74	case XFER_PIO_2:
	75	return 2;
	76	case XFER_MW_DMA_0:
	77	case XFER_SW_DMA_1:
	78	case XFER_SW_DMA_0:
	79	case XFER_PIO_1:
	80	case XFER_PIO_0:
	81	case XFER_PIO_SLOW:
	82	default:
	83	return 0;
	84	}
	85	}
	86
ccf35289	87	static void atiixp_dma_host_on(ide_drive_t *drive)
1da177e4 LT	88	{
	89	struct pci_dev *dev = drive->hwif->pci_dev;
	90	unsigned long flags;
	91	u16 tmp16;
	92
6c5f8cc3	93	spin_lock_irqsave(&atiixp_lock, flags);
1da177e4 LT	94
	95	pci_read_config_word(dev, ATIIXP_IDE_UDMA_CONTROL, &tmp16);
	96	if (save_mdma_mode[drive->dn])
	97	tmp16 &= ~(1 << drive->dn);
	98	else
	99	tmp16 \|= (1 << drive->dn);
	100	pci_write_config_word(dev, ATIIXP_IDE_UDMA_CONTROL, tmp16);
	101
6c5f8cc3	102	spin_unlock_irqrestore(&atiixp_lock, flags);
1da177e4	103
ccf35289	104	ide_dma_host_on(drive);
1da177e4 LT	105	}
1da177e4 LT	106
7469aaf6	107	static void atiixp_dma_host_off(ide_drive_t *drive)
1da177e4 LT	108	{
	109	struct pci_dev *dev = drive->hwif->pci_dev;
	110	unsigned long flags;
	111	u16 tmp16;
	112
6c5f8cc3	113	spin_lock_irqsave(&atiixp_lock, flags);
1da177e4 LT	114
	115	pci_read_config_word(dev, ATIIXP_IDE_UDMA_CONTROL, &tmp16);
	116	tmp16 &= ~(1 << drive->dn);
	117	pci_write_config_word(dev, ATIIXP_IDE_UDMA_CONTROL, tmp16);
	118
6c5f8cc3	119	spin_unlock_irqrestore(&atiixp_lock, flags);
1da177e4	120
7469aaf6	121	ide_dma_host_off(drive);
1da177e4 LT	122	}
	123
	124	/**
485efc6c	125	* atiixp_tune_pio - tune a drive attached to a ATIIXP
1da177e4 LT	126	* @drive: drive to tune
	127	* @pio: desired PIO mode
	128	*
	129	* Set the interface PIO mode.
	130	*/
	131
485efc6c	132	static void atiixp_tune_pio(ide_drive_t *drive, u8 pio)
1da177e4 LT	133	{
	134	struct pci_dev *dev = drive->hwif->pci_dev;
	135	unsigned long flags;
	136	int timing_shift = (drive->dn & 2) ? 16 : 0 + (drive->dn & 1) ? 0 : 8;
	137	u32 pio_timing_data;
	138	u16 pio_mode_data;
	139
6c5f8cc3	140	spin_lock_irqsave(&atiixp_lock, flags);
1da177e4 LT	141
	142	pci_read_config_word(dev, ATIIXP_IDE_PIO_MODE, &pio_mode_data);
	143	pio_mode_data &= ~(0x07 << (drive->dn * 4));
	144	pio_mode_data \|= (pio << (drive->dn * 4));
	145	pci_write_config_word(dev, ATIIXP_IDE_PIO_MODE, pio_mode_data);
	146
	147	pci_read_config_dword(dev, ATIIXP_IDE_PIO_TIMING, &pio_timing_data);
	148	pio_timing_data &= ~(0xff << timing_shift);
	149	pio_timing_data \|= (pio_timing[pio].recover_width << timing_shift) \|
	150	(pio_timing[pio].command_width << (timing_shift + 4));
	151	pci_write_config_dword(dev, ATIIXP_IDE_PIO_TIMING, pio_timing_data);
	152
6c5f8cc3	153	spin_unlock_irqrestore(&atiixp_lock, flags);
1da177e4 LT	154	}
1da177e4 LT	155
26bcb879	156	static void atiixp_set_pio_mode(ide_drive_t *drive, const u8 pio)
485efc6c	157	{
485efc6c BZ	158	atiixp_tune_pio(drive, pio);
	159	(void)ide_config_drive_speed(drive, XFER_PIO_0 + pio);
	160	}
	161
1da177e4 LT	162	/**
	163	* atiixp_tune_chipset - tune a ATIIXP interface
	164	* @drive: IDE drive to tune
f212ff28	165	* @speed: speed to configure
1da177e4 LT	166	*
	167	* Set a ATIIXP interface channel to the desired speeds. This involves
	168	* requires the right timing data into the ATIIXP configuration space
	169	* then setting the drive parameters appropriately
	170	*/
	171
f212ff28	172	static int atiixp_speedproc(ide_drive_t *drive, const u8 speed)
1da177e4 LT	173	{
	174	struct pci_dev *dev = drive->hwif->pci_dev;
	175	unsigned long flags;
	176	int timing_shift = (drive->dn & 2) ? 16 : 0 + (drive->dn & 1) ? 0 : 8;
	177	u32 tmp32;
	178	u16 tmp16;
f212ff28	179	u8 pio;
1da177e4	180
6c5f8cc3	181	spin_lock_irqsave(&atiixp_lock, flags);
1da177e4 LT	182
	183	save_mdma_mode[drive->dn] = 0;
	184	if (speed >= XFER_UDMA_0) {
	185	pci_read_config_word(dev, ATIIXP_IDE_UDMA_MODE, &tmp16);
	186	tmp16 &= ~(0x07 << (drive->dn * 4));
	187	tmp16 \|= ((speed & 0x07) << (drive->dn * 4));
	188	pci_write_config_word(dev, ATIIXP_IDE_UDMA_MODE, tmp16);
	189	} else {
	190	if ((speed >= XFER_MW_DMA_0) && (speed <= XFER_MW_DMA_2)) {
	191	save_mdma_mode[drive->dn] = speed;
	192	pci_read_config_dword(dev, ATIIXP_IDE_MDMA_TIMING, &tmp32);
	193	tmp32 &= ~(0xff << timing_shift);
	194	tmp32 \|= (mdma_timing[speed & 0x03].recover_width << timing_shift) \|
	195	(mdma_timing[speed & 0x03].command_width << (timing_shift + 4));
	196	pci_write_config_dword(dev, ATIIXP_IDE_MDMA_TIMING, tmp32);
	197	}
	198	}
	199
6c5f8cc3	200	spin_unlock_irqrestore(&atiixp_lock, flags);
1da177e4 LT	201
	202	if (speed >= XFER_SW_DMA_0)
	203	pio = atiixp_dma_2_pio(speed);
	204	else
	205	pio = speed - XFER_PIO_0;
	206
485efc6c	207	atiixp_tune_pio(drive, pio);
1da177e4 LT	208
	209	return ide_config_drive_speed(drive, speed);
	210	}
	211
1da177e4 LT	212	/**
	213	* atiixp_dma_check - set up an IDE device
	214	* @drive: IDE drive to configure
	215	*
	216	* Set up the ATIIXP interface for the best available speed on this
	217	* interface, preferring DMA to PIO.
	218	*/
	219
	220	static int atiixp_dma_check(ide_drive_t *drive)
	221	{
1da177e4 LT	222	drive->init_speed = 0;
1da177e4 LT	223
29e744d0	224	if (ide_tune_dma(drive))
3608b5d7	225	return 0;
1da177e4	226
485efc6c	227	if (ide_use_fast_pio(drive))
26bcb879	228	ide_set_max_pio(drive);
d8f4469d	229
3608b5d7	230	return -1;
1da177e4 LT	231	}
	232
	233	/**
	234	* init_hwif_atiixp - fill in the hwif for the ATIIXP
	235	* @hwif: IDE interface
	236	*
	237	* Set up the ide_hwif_t for the ATIIXP interface according to the
	238	* capabilities of the hardware.
	239	*/
	240
	241	static void __devinit init_hwif_atiixp(ide_hwif_t *hwif)
	242	{
e5c073ff CH	243	u8 udma_mode = 0;
	244	u8 ch = hwif->channel;
	245	struct pci_dev *pdev = hwif->pci_dev;
	246
1da177e4	247	if (!hwif->irq)
e5c073ff	248	hwif->irq = ch ? 15 : 14;
1da177e4 LT	249
1da177e4 LT	250	hwif->autodma = 0;
26bcb879	251	hwif->set_pio_mode = &atiixp_set_pio_mode;
1da177e4 LT	252	hwif->speedproc = &atiixp_speedproc;
	253	hwif->drives[0].autotune = 1;
	254	hwif->drives[1].autotune = 1;
	255
	256	if (!hwif->dma_base)
	257	return;
	258
	259	hwif->atapi_dma = 1;
	260	hwif->ultra_mask = 0x3f;
	261	hwif->mwdma_mask = 0x06;
	262	hwif->swdma_mask = 0x04;
	263
e5c073ff	264	pci_read_config_byte(pdev, ATIIXP_IDE_UDMA_MODE + ch, &udma_mode);
49521f97	265
e5c073ff	266	if ((udma_mode & 0x07) >= 0x04 \|\| (udma_mode & 0x70) >= 0x40)
49521f97	267	hwif->cbl = ATA_CBL_PATA80;
e5c073ff	268	else
49521f97	269	hwif->cbl = ATA_CBL_PATA40;
e5c073ff	270
ccf35289	271	hwif->dma_host_on = &atiixp_dma_host_on;
7469aaf6	272	hwif->dma_host_off = &atiixp_dma_host_off;
1da177e4 LT	273	hwif->ide_dma_check = &atiixp_dma_check;
	274	if (!noautodma)
	275	hwif->autodma = 1;
	276
	277	hwif->drives[1].autodma = hwif->autodma;
	278	hwif->drives[0].autodma = hwif->autodma;
	279	}
	280
2b33b4dc	281
1da177e4 LT	282	static ide_pci_device_t atiixp_pci_info[] __devinitdata = {
	283	{ /* 0 */
	284	.name = "ATIIXP",
	285	.init_hwif = init_hwif_atiixp,
1da177e4 LT	286	.autodma = AUTODMA,
	287	.enablebits = {{0x48,0x01,0x00}, {0x48,0x08,0x00}},
	288	.bootable = ON_BOARD,
4099d143	289	.pio_mask = ATA_PIO4,
b25168df CH	290	},{ /* 1 */
	291	.name = "SB600_PATA",
	292	.init_hwif = init_hwif_atiixp,
b25168df CH	293	.autodma = AUTODMA,
	294	.enablebits = {{0x48,0x01,0x00}, {0x00,0x00,0x00}},
	295	.bootable = ON_BOARD,
a5d8c5c8	296	.host_flags = IDE_HFLAG_SINGLE,
4099d143	297	.pio_mask = ATA_PIO4,
b25168df	298	},
1da177e4 LT	299	};
	300
	301	/**
	302	* atiixp_init_one - called when a ATIIXP is found
	303	* @dev: the atiixp device
	304	* @id: the matching pci id
	305	*
	306	* Called when the PCI registration layer (or the IDE initialization)
	307	* finds a device matching our IDE device tables.
	308	*/
	309
	310	static int __devinit atiixp_init_one(struct pci_dev dev, const struct pci_device_id id)
	311	{
	312	return ide_setup_pci_device(dev, &atiixp_pci_info[id->driver_data]);
	313	}
	314
	315	static struct pci_device_id atiixp_pci_tbl[] = {
	316	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP200_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
	317	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP300_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
	318	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
b25168df	319	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
7cfa7168	320	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1da177e4 LT	321	{ 0, },
	322	};
	323	MODULE_DEVICE_TABLE(pci, atiixp_pci_tbl);
	324
	325	static struct pci_driver driver = {
	326	.name = "ATIIXP_IDE",
	327	.id_table = atiixp_pci_tbl,
	328	.probe = atiixp_init_one,
	329	};
	330
82ab1eec	331	static int __init atiixp_ide_init(void)
1da177e4 LT	332	{
	333	return ide_pci_register_driver(&driver);
	334	}
	335
	336	module_init(atiixp_ide_init);
	337
	338	MODULE_AUTHOR("HUI YU");
	339	MODULE_DESCRIPTION("PCI driver module for ATI IXP IDE");
	340	MODULE_LICENSE("GPL");